/**
  ******************************************************************************
  * @file    stm32u385xx.h
  * @author  MCD Application Team
  * @brief   CMSIS STM32U385xx Device Peripheral Access Layer Header File.
  *
  *          This file contains:
  *           - Data structures and the address mapping for all peripherals
  *           - Peripheral's registers declarations and bits definition
  *           - Macros to access peripheral's registers hardware
  *
  ******************************************************************************
  * @attention
  *
  * Copyright (c) 2023 STMicroelectronics.
  * All rights reserved.
  *
  * This software is licensed under terms that can be found in the LICENSE file
  * in the root directory of this software component.
  * If no LICENSE file comes with this software, it is provided AS-IS.
  *
  ******************************************************************************
  */

#ifndef STM32U385xx_H
#define STM32U385xx_H

#ifdef __cplusplus
extern "C" {
#endif

/** @addtogroup ST
  * @{
  */

/** @addtogroup STM32U385xx
  * @{
  */

/** @addtogroup Configuration_of_CMSIS
  * @{
  */
#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
#define CPU_IN_SECURE_STATE
#endif

/* ================================================================================================================== */
/* ================                     Interrupt Number Definition                                  ================ */
/* ================================================================================================================== */
typedef enum
{
  /* ================================== ARM Cortex-M33 Specific Interrupt Numbers =================================== */
  NonMaskableInt_IRQn         = -14,    /*!< -14 Non maskable Interrupt, cannot be stopped or preempted               */
  HardFault_IRQn              = -13,    /*!< -13 Hard Fault, all classes of Fault                                     */
  MemoryManagement_IRQn       = -12,    /*!< -12 Memory Management, MPU mismatch, including Access Violation and No
                                                 No Match                                                             */
  BusFault_IRQn               = -11,    /*!< -11 Bus Fault, Pre-Fetch, Memory Access Fault, other address/memory
                                                 related Fault                                                        */
  UsageFault_IRQn             = -10,    /*!< -10 Usage Fault, i.e. Undef Instruction, Illegal State Transition        */
  SecureFault_IRQn            = -9,     /*!< -9  Secure Fault                                                         */
  SVCall_IRQn                 = -5,     /*!< -5  System Service Call via SVC instruction                              */
  DebugMonitor_IRQn           = -4,     /*!< -4  Debug Monitor                                                        */
  PendSV_IRQn                 = -2,     /*!< -2  Pendable request for system service                                  */
  SysTick_IRQn                = -1,     /*!< -1  System Tick Timer                                                    */

  /* ================================== STM32U385xx Specific Interrupt Numbers ================================= */
  WWDG_IRQn                   = 0,      /*!< Window WatchDog interrupt                                                */
  PVD_PVM_IRQn                = 1,      /*!< PVD and PVM through EXTI Line detection Interrupt                        */
  RTC_IRQn                    = 2,      /*!< RTC non-secure interrupt                                                 */
  RTC_S_IRQn                  = 3,      /*!< RTC secure interrupt                                                     */
  TAMP_IRQn                   = 4,      /*!< Tamper global interrupt                                                  */
  RAMCFG_IRQn                 = 5,      /*!< RAMCFG global interrupt                                                  */
  FLASH_IRQn                  = 6,      /*!< FLASH non-secure global interrupt                                        */
  FLASH_S_IRQn                = 7,      /*!< FLASH secure global interrupt                                            */
  GTZC_IRQn                   = 8,      /*!< Global TrustZone Controller interrupt                                    */
  RCC_IRQn                    = 9,      /*!< RCC non secure global interrupt                                          */
  RCC_S_IRQn                  = 10,     /*!< RCC secure global interrupt                                              */
  EXTI0_IRQn                  = 11,     /*!< EXTI Line 0 interrupt                                                    */
  EXTI1_IRQn                  = 12,     /*!< EXTI Line 1 interrupt                                                    */
  EXTI2_IRQn                  = 13,     /*!< EXTI Line 2 interrupt                                                    */
  EXTI3_IRQn                  = 14,     /*!< EXTI Line 3 interrupt                                                    */
  EXTI4_IRQn                  = 15,     /*!< EXTI Line 4 interrupt                                                    */
  EXTI5_IRQn                  = 16,     /*!< EXTI Line 5 interrupt                                                    */
  EXTI6_IRQn                  = 17,     /*!< EXTI Line 6 interrupt                                                    */
  EXTI7_IRQn                  = 18,     /*!< EXTI Line 7 interrupt                                                    */
  EXTI8_IRQn                  = 19,     /*!< EXTI Line 8 interrupt                                                    */
  EXTI9_IRQn                  = 20,     /*!< EXTI Line 9 interrupt                                                    */
  EXTI10_IRQn                 = 21,     /*!< EXTI Line 10 interrupt                                                   */
  EXTI11_IRQn                 = 22,     /*!< EXTI Line 11 interrupt                                                   */
  EXTI12_IRQn                 = 23,     /*!< EXTI Line 12 interrupt                                                   */
  EXTI13_IRQn                 = 24,     /*!< EXTI Line 13 interrupt                                                   */
  EXTI14_IRQn                 = 25,     /*!< EXTI Line 14 interrupt                                                   */
  EXTI15_IRQn                 = 26,     /*!< EXTI Line 15 interrupt                                                   */
  IWDG_IRQn                   = 27,     /*!< IWDG global interrupt                                                    */
  SAES_IRQn                   = 28,     /*!< Secure AES global interrupt                                              */
  GPDMA1_Channel0_IRQn        = 29,     /*!< GPDMA1 Channel 0 global interrupt                                        */
  GPDMA1_Channel1_IRQn        = 30,     /*!< GPDMA1 Channel 1 global interrupt                                        */
  GPDMA1_Channel2_IRQn        = 31,     /*!< GPDMA1 Channel 2 global interrupt                                        */
  GPDMA1_Channel3_IRQn        = 32,     /*!< GPDMA1 Channel 3 global interrupt                                        */
  GPDMA1_Channel4_IRQn        = 33,     /*!< GPDMA1 Channel 4 global interrupt                                        */
  GPDMA1_Channel5_IRQn        = 34,     /*!< GPDMA1 Channel 5 global interrupt                                        */
  GPDMA1_Channel6_IRQn        = 35,     /*!< GPDMA1 Channel 6 global interrupt                                        */
  GPDMA1_Channel7_IRQn        = 36,     /*!< GPDMA1 Channel 7 global interrupt                                        */
  ADC1_IRQn                   = 37,     /*!< ADC1 global interrupt                                                    */
  DAC1_IRQn                   = 38,     /*!< DAC1 global interrupt                                                    */
  FDCAN1_IT0_IRQn             = 39,     /*!< FDCAN1 interrupt 0                                                       */
  FDCAN1_IT1_IRQn             = 40,     /*!< FDCAN1 interrupt 1                                                       */
  TIM1_BRK_TERR_IERR_IRQn     = 41,     /*!< TIM1 Break, Transition error and Index error interrupt                   */
  TIM1_UP_IRQn                = 42,     /*!< TIM1 Update interrupt                                                    */
  TIM1_TRG_COM_DIR_IDX_IRQn   = 43,     /*!< TIM1 Trigger, Commutation, Direction change and Index interrupt          */
  TIM1_CC_IRQn                = 44,     /*!< TIM1 Capture Compare interrupt                                           */
  TIM2_IRQn                   = 45,     /*!< TIM2 global interrupt                                                    */
  TIM3_IRQn                   = 46,     /*!< TIM3 global interrupt                                                    */
  TIM4_IRQn                   = 47,     /*!< TIM4 global interrupt                                                    */
  TIM6_IRQn                   = 49,     /*!< TIM6 global interrupt                                                    */
  TIM7_IRQn                   = 50,     /*!< TIM7 global interrupt                                                    */
  I3C1_EV_IRQn                = 53,     /*!< I3C1 event interrupt                                                     */
  I3C1_ER_IRQn                = 54,     /*!< I3C1 error interrupt                                                     */
  I2C1_EV_IRQn                = 55,     /*!< I2C1 Event interrupt                                                     */
  I2C1_ER_IRQn                = 56,     /*!< I2C1 Error interrupt                                                     */
  I2C2_EV_IRQn                = 57,     /*!< I2C2 Event interrupt                                                     */
  I2C2_ER_IRQn                = 58,     /*!< I2C2 Error interrupt                                                     */
  SPI1_IRQn                   = 59,     /*!< SPI1 global interrupt                                                    */
  SPI2_IRQn                   = 60,     /*!< SPI2 global interrupt                                                    */
  USART1_IRQn                 = 61,     /*!< USART1 global interrupt                                                  */
  USART3_IRQn                 = 63,     /*!< USART3 global interrupt                                                  */
  UART4_IRQn                  = 64,     /*!< UART4 global interrupt                                                   */
  UART5_IRQn                  = 65,     /*!< UART5 global interrupt                                                   */
  LPUART1_IRQn                = 66,     /*!< LPUART1 global interrupt                                                 */
  LPTIM1_IRQn                 = 67,     /*!< LPTIM1 global interrupt                                                  */
  LPTIM2_IRQn                 = 68,     /*!< LPTIM2 global interrupt                                                  */
  TIM15_IRQn                  = 69,     /*!< TIM15 global interrupt                                                   */
  TIM16_IRQn                  = 70,     /*!< TIM16 global interrupt                                                   */
  TIM17_IRQn                  = 71,     /*!< TIM17 global interrupt                                                   */
  COMP_IRQn                   = 72,     /*!< COMP1 and COMP2 through EXTI Lines interrupts                            */
  USB_FS_IRQn                 = 73,     /*!< USB FS global interrupt                                                  */
  CRS_IRQn                    = 74,     /*!< CRS global interrupt                                                     */
  OCTOSPI1_IRQn               = 76,     /*!< OctoSPI1 global interrupt                                                */
  SDMMC1_IRQn                 = 78,     /*!< SDMMC1 global interrupt                                                  */
  GPDMA1_Channel8_IRQn        = 80,     /*!< GPDMA1 Channel 8 global interrupt                                        */
  GPDMA1_Channel9_IRQn        = 81,     /*!< GPDMA1 Channel 9 global interrupt                                        */
  GPDMA1_Channel10_IRQn       = 82,     /*!< GPDMA1 Channel 10 global interrupt                                       */
  GPDMA1_Channel11_IRQn       = 83,     /*!< GPDMA1 Channel 11 global interrupt                                       */
  I2C3_EV_IRQn                = 88,     /*!< I2C3 event interrupt                                                     */
  I2C3_ER_IRQn                = 89,     /*!< I2C3 error interrupt                                                     */
  SAI1_IRQn                   = 90,     /*!< Serial Audio Interface 1 global interrupt                                */
  TSC_IRQn                    = 92,     /*!< Touch Sense Controller global interrupt                                  */
  AES_IRQn                    = 93,     /*!< AES global interrupt                                                     */
  RNG_IRQn                    = 94,     /*!< RNG global interrupt                                                     */
  FPU_IRQn                    = 95,     /*!< FPU global interrupt                                                     */
  HASH_IRQn                   = 96,     /*!< HASH global interrupt                                                    */
  PKA_IRQn                    = 97,     /*!< PKA global interrupt                                                     */
  LPTIM3_IRQn                 = 98,     /*!< LPTIM3 global interrupt                                                  */
  SPI3_IRQn                   = 99,     /*!< SPI3 global interrupt                                                    */
  I3C2_EV_IRQn                = 100,    /*!< I3C2 Event interrupt                                                     */
  I3C2_ER_IRQn                = 101,    /*!< I3C2 Error interrupt                                                     */
  ICACHE_IRQn                 = 107,    /*!< Instruction cache global interrupt                                       */
  LPTIM4_IRQn                 = 110,    /*!< LPTIM4 global interrupt                                                  */
  ADF1_IRQn                   = 112,    /*!< ADF1 interrupt                                                           */
  ADC2_IRQn                   = 113,    /*!< ADC2 (12bits) global interrupt                                           */
  PWR_IRQn                    = 123,    /*!< PWR non-secure interrupt                                                 */
  PWR_S_IRQn                  = 124     /*!< PWR secure interrupt                                                     */
} IRQn_Type;

/* ================================================================================================================== */
/* ================                     Processor and Core Peripheral Section                        ================ */
/* ================================================================================================================== */
/* -------  Start of section using anonymous unions and disabling warnings  ------- */
#if   defined (__CC_ARM)
  #pragma push
  #pragma anon_unions
#elif defined (__ICCARM__)
  #pragma language=extended
#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
  #pragma clang diagnostic push
  #pragma clang diagnostic ignored "-Wc11-extensions"
  #pragma clang diagnostic ignored "-Wreserved-id-macro"
#elif defined (__GNUC__)
  /* anonymous unions are enabled by default */
#elif defined (__TMS470__)
  /* anonymous unions are enabled by default */
#elif defined (__TASKING__)
  #pragma warning 586
#elif defined (__CSMC__)
  /* anonymous unions are enabled by default */
#else
  #warning Not supported compiler type
#endif

/* --------  Configuration of the Cortex-M33 Processor and Core Peripherals  ------ */
#define __CM33_REV                      0x0000U   /* Core revision r0p4 */
#define __SAUREGION_PRESENT             1U        /* SAU regions present */
#define __MPU_PRESENT                   1U        /* MPU present */
#define __VTOR_PRESENT                  1U        /* VTOR present */
#define __NVIC_PRIO_BITS                4U        /* Number of Bits used for Priority Levels */
#define __Vendor_SysTickConfig          0U        /* Set to 1 if different SysTick Config is used */
#define __FPU_PRESENT                   1U        /* FPU present */
#define __DSP_PRESENT                   1U        /* DSP extension present */

/** @} */ /* End of group Configuration_of_CMSIS */

#include "core_cm33.h"                            /*!< ARM Cortex-M33 processor and core peripherals */
#include "system_stm32u3xx.h"                     /*!< STM32U3xx System */


/* ================================================================================================================== */
/* ================                     Device Specific Peripheral Section                           ================ */
/* ================================================================================================================== */
/** @addtogroup STM32U3xx_peripherals
  * @{
  */

/**
  * @brief ADC Analog to Digital Converter
  */
typedef struct
{
  __IO uint32_t ISR;              /*!< ADC interrupt and status register,                        Address offset: 0x00 */
  __IO uint32_t IER;              /*!< ADC interrupt enable register,                            Address offset: 0x04 */
  __IO uint32_t CR;               /*!< ADC control register,                                     Address offset: 0x08 */
  __IO uint32_t CFGR1;            /*!< ADC configuration register 1,                             Address offset: 0x0C */
  __IO uint32_t CFGR2;            /*!< ADC configuration register 2,                             Address offset: 0x10 */
  __IO uint32_t SMPR1;            /*!< ADC sample time register 1,                               Address offset: 0x14 */
  __IO uint32_t SMPR2;            /*!< ADC sample time register 2,                               Address offset: 0x18 */
  __IO uint32_t PCSEL;            /*!< ADC channel preselection register,                        Address offset: 0x1C */
  uint32_t      RESERVED1[4];     /*!< Reserved,                                                 Address offset: 0x20 */
  __IO uint32_t SQR1;             /*!< ADC regular sequence register 1,                          Address offset: 0x30 */
  __IO uint32_t SQR2;             /*!< ADC regular sequence register 2,                          Address offset: 0x34 */
  __IO uint32_t SQR3;             /*!< ADC regular sequence register 3,                          Address offset: 0x38 */
  __IO uint32_t SQR4;             /*!< ADC regular sequence register 4,                          Address offset: 0x3C */
  __IO uint32_t DR;               /*!< ADC regular data register,                                Address offset: 0x40 */
  uint32_t      RESERVED2[2];     /*!< Reserved,                                                 Address offset: 0x44 */
  __IO uint32_t JSQR;             /*!< ADC injected sequence register,                           Address offset: 0x4C */
  __IO uint32_t OFCFGR1;          /*!< ADC offset configuration register 1,                      Address offset: 0x50 */
  __IO uint32_t OFCFGR2;          /*!< ADC offset configuration register 2,                      Address offset: 0x54 */
  __IO uint32_t OFCFGR3;          /*!< ADC offset configuration register 3,                      Address offset: 0x58 */
  __IO uint32_t OFCFGR4;          /*!< ADC offset configuration register 4,                      Address offset: 0x5C */
  __IO uint32_t OFR1;             /*!< ADC offset register 1,                                    Address offset: 0x60 */
  __IO uint32_t OFR2;             /*!< ADC offset register 2,                                    Address offset: 0x64 */
  __IO uint32_t OFR3;             /*!< ADC offset register 3,                                    Address offset: 0x68 */
  __IO uint32_t OFR4;             /*!< ADC offset register 4,                                    Address offset: 0x6C */
  __IO uint32_t GCOMP;            /*!< ADC gain compensation register,                           Address offset: 0x70 */
  uint32_t      RESERVED3[3];     /*!< Reserved,                                                 Address offset: 0x74 */
  __IO uint32_t JDR1;             /*!< ADC injected data register 1,                             Address offset: 0x80 */
  __IO uint32_t JDR2;             /*!< ADC injected data register 2,                             Address offset: 0x84 */
  __IO uint32_t JDR3;             /*!< ADC injected data register 3,                             Address offset: 0x88 */
  __IO uint32_t JDR4;             /*!< ADC injected data register 4,                             Address offset: 0x8C */
  uint32_t      RESERVED4[4];     /*!< Reserved,                                                 Address offset: 0x90 */
  __IO uint32_t AWD2CR;           /*!< ADC analog watchdog 2 configuration register,             Address offset: 0xA0 */
  __IO uint32_t AWD3CR;           /*!< ADC analog watchdog 3 configuration register,             Address offset: 0xA4 */
  __IO uint32_t AWD1LTR;          /*!< ADC analog watchdog 1 low threshold register,             Address offset: 0xA8 */
  __IO uint32_t AWD1HTR;          /*!< ADC analog watchdog 1 high threshold register,            Address offset: 0xAC */
  __IO uint32_t AWD2LTR;          /*!< ADC analog watchdog 2 low threshold register,             Address offset: 0xB0 */
  __IO uint32_t AWD2HTR;          /*!< ADC analog watchdog 2 high threshold register,            Address offset: 0xB4 */
  __IO uint32_t AWD3LTR;          /*!< ADC analog watchdog 3 low threshold register,             Address offset: 0xB8 */
  __IO uint32_t AWD3HTR;          /*!< ADC analog watchdog 3 high threshold register,            Address offset: 0xBC */
  __IO uint32_t DIFSEL;           /*!< ADC differential mode selection register,                 Address offset: 0xC0 */
  __IO uint32_t CALFACT;          /*!< ADC calibration factors,                                  Address offset: 0xC4 */
  uint32_t      RESERVED5[2];     /*!< Reserved,                                                 Address offset: 0xC8 */
  __IO uint32_t OR;               /*!< ADC option register,                                      Address offset: 0xD0 */
} ADC_TypeDef;

typedef struct
{
  __IO uint32_t CSR;              /*!< ADC common status register,                              Address offset: 0x300 */
  uint32_t RESERVED;              /*!< Reserved,                                                Address offset: 0x304 */
  __IO uint32_t CCR;              /*!< ADC common control register,                             Address offset: 0x308 */
  __IO uint32_t CDR;              /*!< ADC common regular data register for dual mode,          Address offset: 0x30C */
  __IO uint32_t CDR2;             /*!< ADC common regular data register for dual mode 32-bit,   Address offset: 0x310 */
} ADC_Common_TypeDef;

/**
  * @brief AES hardware accelerator
  */
typedef struct
{
  __IO uint32_t CR;               /*!< AES control register,                              Address offset: 0x00 */
  __IO uint32_t SR;               /*!< AES status register,                               Address offset: 0x04 */
  __IO uint32_t DINR;             /*!< AES data input register,                           Address offset: 0x08 */
  __IO uint32_t DOUTR;            /*!< AES data output register,                          Address offset: 0x0C */
  __IO uint32_t KEYR0;            /*!< AES key register 0,                                Address offset: 0x10 */
  __IO uint32_t KEYR1;            /*!< AES key register 1,                                Address offset: 0x14 */
  __IO uint32_t KEYR2;            /*!< AES key register 2,                                Address offset: 0x18 */
  __IO uint32_t KEYR3;            /*!< AES key register 3,                                Address offset: 0x1C */
  __IO uint32_t IVR0;             /*!< AES initialization vector register 0,              Address offset: 0x20 */
  __IO uint32_t IVR1;             /*!< AES initialization vector register 1,              Address offset: 0x24 */
  __IO uint32_t IVR2;             /*!< AES initialization vector register 2,              Address offset: 0x28 */
  __IO uint32_t IVR3;             /*!< AES initialization vector register 3,              Address offset: 0x2C */
  __IO uint32_t KEYR4;            /*!< AES key register 4,                                Address offset: 0x30 */
  __IO uint32_t KEYR5;            /*!< AES key register 5,                                Address offset: 0x34 */
  __IO uint32_t KEYR6;            /*!< AES key register 6,                                Address offset: 0x38 */
  __IO uint32_t KEYR7;            /*!< AES key register 7,                                Address offset: 0x3C */
  __IO uint32_t SUSP0R;           /*!< AES Suspend register 0,                            Address offset: 0x40 */
  __IO uint32_t SUSP1R;           /*!< AES Suspend register 1,                            Address offset: 0x44 */
  __IO uint32_t SUSP2R;           /*!< AES Suspend register 2,                            Address offset: 0x48 */
  __IO uint32_t SUSP3R;           /*!< AES Suspend register 3,                            Address offset: 0x4C */
  __IO uint32_t SUSP4R;           /*!< AES Suspend register 4,                            Address offset: 0x50 */
  __IO uint32_t SUSP5R;           /*!< AES Suspend register 5,                            Address offset: 0x54 */
  __IO uint32_t SUSP6R;           /*!< AES Suspend register 6,                            Address offset: 0x58 */
  __IO uint32_t SUSP7R;           /*!< AES Suspend register 7,                            Address offset: 0x5C */
       uint32_t RESERVED1[168];   /*!< Reserved,                                                 0x60 -- 0x2FC */
  __IO uint32_t IER;              /*!< AES Interrupt Enable Register,                    Address offset: 0x300 */
  __IO uint32_t ISR;              /*!< AES Interrupt Status Register,                    Address offset: 0x304 */
  __IO uint32_t ICR;              /*!< AES Interrupt Clear Register,                     Address offset: 0x308 */
} AES_TypeDef;

/**
  * @brief  Coupling and chaining bridge (CCB)
  */
typedef struct
{
  __IO uint32_t CR;               /*!< CCB ccontrol register,                                   Address offset: 0x00 */
  __IO uint32_t SR;               /*!< CCB status register,                                     Address offset: 0x04 */
       uint32_t RESERVED1[2];     /*!< Reserved,                                                Address offset: 0x08 */
  __IO uint32_t REFTAGR[4];       /*!< CCB reference tag register,                              Address offset: 0x10 */
} CCB_TypeDef;

/**
  * @brief Comparator
  */
typedef struct
{
  __IO uint32_t CSR;              /*!< Comparator control/status register  ,             Address offset: 0x00 */
} COMP_TypeDef;

typedef struct
{
  __IO uint32_t CSR_ODD;          /*!< COMP control and status register located in register of comparator instance odd, used for bits common to several COMP instances, Address offset: 0x00 */
  __IO uint32_t CSR_EVEN;         /*!< COMP control and status register located in register of comparator instance even, used for bits common to several COMP instances, Address offset: 0x04 */
} COMP_Common_TypeDef;

/**
  * @brief CRC calculation unit
  */
typedef struct
{
  __IO uint32_t DR;               /*!< CRC Data register,                                   Address offset: 0x00 */
  __IO uint32_t IDR;              /*!< CRC Independent data register,                       Address offset: 0x04 */
  __IO uint32_t CR;               /*!< CRC Control register,                                Address offset: 0x08 */
       uint32_t RESERVED2;        /*!< Reserved,                                                            0x0C */
  __IO uint32_t INIT;             /*!< Initial CRC value register,                          Address offset: 0x10 */
  __IO uint32_t POL;              /*!< CRC polynomial register,                             Address offset: 0x14 */
} CRC_TypeDef;

/**
  * @brief Clock Recovery System
  */
typedef struct
{
__IO uint32_t CR;                 /*!< CRS ccontrol register,              Address offset: 0x00 */
__IO uint32_t CFGR;               /*!< CRS configuration register,         Address offset: 0x04 */
__IO uint32_t ISR;                /*!< CRS interrupt and status register,  Address offset: 0x08 */
__IO uint32_t ICR;                /*!< CRS interrupt flag clear register,  Address offset: 0x0C */
} CRS_TypeDef;

/**
  * @brief DAC
  */
typedef struct
{
  __IO uint32_t CR;               /*!< DAC control register,                                    Address offset: 0x00 */
  __IO uint32_t SWTRIGR;          /*!< DAC software trigger register,                           Address offset: 0x04 */
  __IO uint32_t DHR12R1;          /*!< DAC channel1 12-bit right-aligned data holding register, Address offset: 0x08 */
  __IO uint32_t DHR12L1;          /*!< DAC channel1 12-bit left aligned data holding register,  Address offset: 0x0C */
  __IO uint32_t DHR8R1;           /*!< DAC channel1 8-bit right aligned data holding register,  Address offset: 0x10 */
  __IO uint32_t DHR12R2;          /*!< DAC channel2 12-bit right aligned data holding register, Address offset: 0x14 */
  __IO uint32_t DHR12L2;          /*!< DAC channel2 12-bit left aligned data holding register,  Address offset: 0x18 */
  __IO uint32_t DHR8R2;           /*!< DAC channel2 8-bit right-aligned data holding register,  Address offset: 0x1C */
  __IO uint32_t DHR12RD;          /*!< Dual DAC 12-bit right-aligned data holding register,     Address offset: 0x20 */
  __IO uint32_t DHR12LD;          /*!< DUAL DAC 12-bit left aligned data holding register,      Address offset: 0x24 */
  __IO uint32_t DHR8RD;           /*!< DUAL DAC 8-bit right aligned data holding register,      Address offset: 0x28 */
  __IO uint32_t DOR1;             /*!< DAC channel1 data output register,                       Address offset: 0x2C */
  __IO uint32_t DOR2;             /*!< DAC channel2 data output register,                       Address offset: 0x30 */
  __IO uint32_t SR;               /*!< DAC status register,                                     Address offset: 0x34 */
  __IO uint32_t CCR;              /*!< DAC calibration control register,                        Address offset: 0x38 */
  __IO uint32_t MCR;              /*!< DAC mode control register,                               Address offset: 0x3C */
  __IO uint32_t SHSR1;            /*!< DAC Sample and Hold sample time register 1,              Address offset: 0x40 */
  __IO uint32_t SHSR2;            /*!< DAC Sample and Hold sample time register 2,              Address offset: 0x44 */
  __IO uint32_t SHHR;             /*!< DAC Sample and Hold hold time register,                  Address offset: 0x48 */
  __IO uint32_t SHRR;             /*!< DAC Sample and Hold refresh time register,               Address offset: 0x4C */
  __IO uint32_t RESERVED[1];
  __IO uint32_t AUTOCR;           /*!< DAC Autonomous mode register,                         Address offset: 0x54 */
} DAC_TypeDef;

/**
  * @brief Debug MCU
  */
typedef struct
{
  __IO uint32_t IDCODE;           /*!< MCU device ID code,                 Address offset: 0x00 */
  __IO uint32_t CR;               /*!< Debug MCU configuration register,   Address offset: 0x04 */
  __IO uint32_t APB1FZR1;         /*!< Debug MCU APB1 freeze register 1,   Address offset: 0x08 */
  __IO uint32_t APB1FZR2;         /*!< Debug MCU APB1 freeze register 2,   Address offset: 0x0C */
  __IO uint32_t APB2FZR;          /*!< Debug MCU APB2 freeze register,     Address offset: 0x10 */
  __IO uint32_t APB3FZR;          /*!< Debug MCU APB3 freeze register,     Address offset: 0x14 */
       uint32_t RESERVED1[2];     /*!< Reserved,                                    0x18 - 0x1C */
  __IO uint32_t AHB1FZR;          /*!< Debug MCU AHB1 freeze register,     Address offset: 0x20 */
       uint32_t RESERVED2;        /*!< Reserved,                                           0x24 */
  __IO uint32_t AHB3FZR;          /*!< Debug MCU AHB3 freeze register,     Address offset: 0x28 */
} DBGMCU_TypeDef;

/**
  * @ brief Delay Block
  */
typedef struct
{
  __IO uint32_t CR;   /*!< Delay Block Control Register,       Address offset: 0x00 */
  __IO uint32_t CFGR; /*!< Delay Block Configuration Register, Address offset: 0x04 */
} DLYB_TypeDef;

/**
  * @brief DMA Controller
  */
typedef struct
{
  __IO uint32_t SECCFGR;          /*!< DMA secure configuration register,               Address offset: 0x00  */
  __IO uint32_t PRIVCFGR;         /*!< DMA privileged configuration register,           Address offset: 0x04  */
  __IO uint32_t RCFGLOCKR;        /*!< DMA lock configuration register,                 Address offset: 0x08  */
  __IO uint32_t MISR;             /*!< DMA non secure masked interrupt status register, Address offset: 0x0C  */
  __IO uint32_t SMISR;            /*!< DMA secure masked interrupt status register,     Address offset: 0x10  */
} DMA_TypeDef;

typedef struct
{
  __IO uint32_t CLBAR;            /*!< DMA channel x linked-list base address register, Address offset: 0x50 + (x * 0x80) */
       uint32_t RESERVED1[2];     /*!< Reserved 1,                                      Address offset: 0x54 -- 0x58      */
  __IO uint32_t CFCR;             /*!< DMA channel x flag clear register,               Address offset: 0x5C + (x * 0x80) */
  __IO uint32_t CSR;              /*!< DMA channel x flag status register,              Address offset: 0x60 + (x * 0x80) */
  __IO uint32_t CCR;              /*!< DMA channel x control register,                  Address offset: 0x64 + (x * 0x80) */
       uint32_t RESERVED2[10];    /*!< Reserved 2,                                      Address offset: 0x68 -- 0x8C      */
  __IO uint32_t CTR1;             /*!< DMA channel x transfer register 1,               Address offset: 0x90 + (x * 0x80) */
  __IO uint32_t CTR2;             /*!< DMA channel x transfer register 2,               Address offset: 0x94 + (x * 0x80) */
  __IO uint32_t CBR1;             /*!< DMA channel x block register 1,                  Address offset: 0x98 + (x * 0x80) */
  __IO uint32_t CSAR;             /*!< DMA channel x source address register,           Address offset: 0x9C + (x * 0x80) */
  __IO uint32_t CDAR;             /*!< DMA channel x destination address register,      Address offset: 0xA0 + (x * 0x80) */
  __IO uint32_t CTR3;             /*!< DMA channel x transfer register 3,               Address offset: 0xA4 + (x * 0x80) */
  __IO uint32_t CBR2;             /*!< DMA channel x block register 2,                  Address offset: 0xA8 + (x * 0x80) */
       uint32_t RESERVED3[8];     /*!< Reserved 3,                                      Address offset: 0xAC -- 0xC8      */
  __IO uint32_t CLLR;             /*!< DMA channel x linked-list address register,      Address offset: 0xCC + (x * 0x80) */
} DMA_Channel_TypeDef;

/**
  * @brief Asynch Interrupt/Event Controller (EXTI)
  */
typedef struct
{
  __IO uint32_t RTSR1;            /*!< EXTI Rising Trigger Selection Register 1,        Address offset:   0x00 */
  __IO uint32_t FTSR1;            /*!< EXTI Falling Trigger Selection Register 1,       Address offset:   0x04 */
  __IO uint32_t SWIER1;           /*!< EXTI Software Interrupt event Register 1,        Address offset:   0x08 */
  __IO uint32_t RPR1;             /*!< EXTI Rising Pending Register 1,                  Address offset:   0x0C */
  __IO uint32_t FPR1;             /*!< EXTI Falling Pending Register 1,                 Address offset:   0x10 */
  __IO uint32_t SECCFGR1;         /*!< EXTI Security Configuration Register 1,          Address offset:   0x14 */
  __IO uint32_t PRIVCFGR1;        /*!< EXTI Privilege Configuration Register 1,         Address offset:   0x18 */
       uint32_t RESERVED1[17];    /*!< Reserved 1,                                                0x1C -- 0x5C */
  __IO uint32_t EXTICR[4];        /*!< EXIT External Interrupt Configuration Register,            0x60 -- 0x6C */
  __IO uint32_t LOCKR;            /*!< EXTI Lock Register,                              Address offset:   0x70 */
       uint32_t RESERVED2[3];     /*!< Reserved 2,                                                0x74 -- 0x7C */
  __IO uint32_t IMR1;             /*!< EXTI Interrupt Mask Register 1,                  Address offset:   0x80 */
  __IO uint32_t EMR1;             /*!< EXTI Event Mask Register 1,                      Address offset:   0x84 */
} EXTI_TypeDef;

/**
  * @brief FD Controller Area Network
  */
typedef struct
{
  __IO uint32_t CREL;             /*!< FDCAN Core Release register,                                     Address offset: 0x000 */
  __IO uint32_t ENDN;             /*!< FDCAN Endian register,                                           Address offset: 0x004 */
       uint32_t RESERVED1;        /*!< Reserved,                                                                        0x008 */
  __IO uint32_t DBTP;             /*!< FDCAN Data Bit Timing & Prescaler register,                      Address offset: 0x00C */
  __IO uint32_t TEST;             /*!< FDCAN Test register,                                             Address offset: 0x010 */
  __IO uint32_t RWD;              /*!< FDCAN RAM Watchdog register,                                     Address offset: 0x014 */
  __IO uint32_t CCCR;             /*!< FDCAN CC Control register,                                       Address offset: 0x018 */
  __IO uint32_t NBTP;             /*!< FDCAN Nominal Bit Timing & Prescaler register,                   Address offset: 0x01C */
  __IO uint32_t TSCC;             /*!< FDCAN Timestamp Counter Configuration register,                  Address offset: 0x020 */
  __IO uint32_t TSCV;             /*!< FDCAN Timestamp Counter Value register,                          Address offset: 0x024 */
  __IO uint32_t TOCC;             /*!< FDCAN Timeout Counter Configuration register,                    Address offset: 0x028 */
  __IO uint32_t TOCV;             /*!< FDCAN Timeout Counter Value register,                            Address offset: 0x02C */
       uint32_t RESERVED2[4];     /*!< Reserved,                                                                0x030 - 0x03C */
  __IO uint32_t ECR;              /*!< FDCAN Error Counter register,                                    Address offset: 0x040 */
  __IO uint32_t PSR;              /*!< FDCAN Protocol Status register,                                  Address offset: 0x044 */
  __IO uint32_t TDCR;             /*!< FDCAN Transmitter Delay Compensation register,                   Address offset: 0x048 */
       uint32_t RESERVED3;        /*!< Reserved,                                                                        0x04C */
  __IO uint32_t IR;               /*!< FDCAN Interrupt register,                                        Address offset: 0x050 */
  __IO uint32_t IE;               /*!< FDCAN Interrupt Enable register,                                 Address offset: 0x054 */
  __IO uint32_t ILS;              /*!< FDCAN Interrupt Line Select register,                            Address offset: 0x058 */
  __IO uint32_t ILE;              /*!< FDCAN Interrupt Line Enable register,                            Address offset: 0x05C */
       uint32_t RESERVED4[8];     /*!< Reserved,                                                                0x060 - 0x07C */
  __IO uint32_t RXGFC;            /*!< FDCAN Global Filter Configuration register,                      Address offset: 0x080 */
  __IO uint32_t XIDAM;            /*!< FDCAN Extended ID AND Mask register,                             Address offset: 0x084 */
  __IO uint32_t HPMS;             /*!< FDCAN High Priority Message Status register,                     Address offset: 0x088 */
       uint32_t RESERVED5;        /*!< Reserved,                                                                        0x08C */
  __IO uint32_t RXF0S;            /*!< FDCAN Rx FIFO 0 Status register,                                 Address offset: 0x090 */
  __IO uint32_t RXF0A;            /*!< FDCAN Rx FIFO 0 Acknowledge register,                            Address offset: 0x094 */
  __IO uint32_t RXF1S;            /*!< FDCAN Rx FIFO 1 Status register,                                 Address offset: 0x098 */
  __IO uint32_t RXF1A;            /*!< FDCAN Rx FIFO 1 Acknowledge register,                            Address offset: 0x09C */
       uint32_t RESERVED6[8];     /*!< Reserved,                                                                0x0A0 - 0x0BC */
  __IO uint32_t TXBC;             /*!< FDCAN Tx Buffer Configuration register,                          Address offset: 0x0C0 */
  __IO uint32_t TXFQS;            /*!< FDCAN Tx FIFO/Queue Status register,                             Address offset: 0x0C4 */
  __IO uint32_t TXBRP;            /*!< FDCAN Tx Buffer Request Pending register,                        Address offset: 0x0C8 */
  __IO uint32_t TXBAR;            /*!< FDCAN Tx Buffer Add Request register,                            Address offset: 0x0CC */
  __IO uint32_t TXBCR;            /*!< FDCAN Tx Buffer Cancellation Request register,                   Address offset: 0x0D0 */
  __IO uint32_t TXBTO;            /*!< FDCAN Tx Buffer Transmission Occurred register,                  Address offset: 0x0D4 */
  __IO uint32_t TXBCF;            /*!< FDCAN Tx Buffer Cancellation Finished register,                  Address offset: 0x0D8 */
  __IO uint32_t TXBTIE;           /*!< FDCAN Tx Buffer Transmission Interrupt Enable register,          Address offset: 0x0DC */
  __IO uint32_t TXBCIE;           /*!< FDCAN Tx Buffer Cancellation Finished Interrupt Enable register, Address offset: 0x0E0 */
  __IO uint32_t TXEFS;            /*!< FDCAN Tx Event FIFO Status register,                             Address offset: 0x0E4 */
  __IO uint32_t TXEFA;            /*!< FDCAN Tx Event FIFO Acknowledge register,                        Address offset: 0x0E8 */
} FDCAN_GlobalTypeDef;

/**
  * @brief FD Controller Area Network Configuration
  */
typedef struct
{
  __IO uint32_t CKDIV;            /*!< FDCAN clock divider register,                            Address offset: 0x100 + 0x000 */
       uint32_t RESERVED1[128];   /*!< Reserved,                                                0x100 + 0x004 - 0x100 + 0x200 */
  __IO uint32_t OPTR;             /*!< FDCAN option register,                                   Address offset: 0x100 + 0x204 */
       uint32_t RESERVED2[58];    /*!< Reserved,                                                0x100 + 0x208 - 0x100 + 0x2EC */
  __IO uint32_t HWCFG;            /*!< FDCAN hardware configuration register,                   Address offset: 0x100 + 0x2F0 */
  __IO uint32_t VERR;             /*!< FDCAN IP version register,                               Address offset: 0x100 + 0x2F4 */
  __IO uint32_t IPIDR;            /*!< FDCAN IP ID register,                                    Address offset: 0x100 + 0x2F8 */
  __IO uint32_t SIDR;             /*!< FDCAN size ID register,                                  Address offset: 0x100 + 0x2FC */
} FDCAN_Config_TypeDef;

/**
  * @brief FLASH Registers
  */
typedef struct
{
  __IO uint32_t ACR;              /*!< FLASH access control register,                  Address offset: 0x00 */
       uint32_t RESERVED1;        /*!< Reserved,                                       Address offset: 0x04 */
  __IO uint32_t KEYR;             /*!< FLASH non-secure key register,                  Address offset: 0x08 */
  __IO uint32_t SKEYR;            /*!< FLASH secure key register,                      Address offset: 0x0C */
  __IO uint32_t OPTKEYR;          /*!< FLASH option key register,                      Address offset: 0x10 */
       uint32_t RESERVED2;        /*!< Reserved,                                       Address offset: 0x14 */
  __IO uint32_t PDKEY1R;          /*!< FLASH bank 1 power-down key register,           Address offset: 0x18 */
  __IO uint32_t PDKEY2R;          /*!< FLASH bank 2 power-down key register,           Address offset: 0x1C */
  __IO uint32_t SR;               /*!< FLASH non-secure status register,               Address offset: 0x20 */
  __IO uint32_t SSR;              /*!< FLASH secure status register,                   Address offset: 0x24 */
  __IO uint32_t CR;               /*!< FLASH non-secure control register,              Address offset: 0x28 */
  __IO uint32_t SCR;              /*!< FLASH secure control register,                  Address offset: 0x2C */
  __IO uint32_t ECCCR;            /*!< FLASH ECC correction register,                  Address offset: 0x30 */
  __IO uint32_t ECCDR;            /*!< FLASH ECC detection register,                   Address offset: 0x34 */
  __IO uint32_t OPSR;             /*!< FLASH OPSR register,                            Address offset: 0x38 */
       uint32_t RESERVED3;        /*!< Reserved,                                       Address offset: 0x3C */
  __IO uint32_t OPTR;             /*!< FLASH option control register,                  Address offset: 0x40 */
  __IO uint32_t BOOT0R;           /*!< FLASH non-secure boot address 0 register,       Address offset: 0x44 */
  __IO uint32_t BOOT1R;           /*!< FLASH non-secure boot address 1 register,       Address offset: 0x48 */
  __IO uint32_t SBOOT0R;          /*!< FLASH secure boot address 0 register,           Address offset: 0x4C */
  __IO uint32_t SECWM1R1;         /*!< FLASH secure watermark1 register 1,             Address offset: 0x50 */
  __IO uint32_t SECWM1R2;         /*!< FLASH secure watermark1 register 2,             Address offset: 0x54 */
  __IO uint32_t WRP1AR;           /*!< FLASH WRP1 area A address register,             Address offset: 0x58 */
  __IO uint32_t WRP1BR;           /*!< FLASH WRP1 area B address register,             Address offset: 0x5C */
  __IO uint32_t SECWM2R1;         /*!< FLASH secure watermark2 register 1,             Address offset: 0x60 */
  __IO uint32_t SECWM2R2;         /*!< FLASH secure watermark2 register 2,             Address offset: 0x64 */
  __IO uint32_t WRP2AR;           /*!< FLASH WRP2 area A address register,             Address offset: 0x68 */
  __IO uint32_t WRP2BR;           /*!< FLASH WRP2 area B address register,             Address offset: 0x6C */
       uint32_t RESERVED4[4];     /*!< Reserved,                                       Address offset: 0x70-0x7C */
  __IO uint32_t SECBB1R1;         /*!< FLASH secure block-based bank 1 register 1,     Address offset: 0x80 */
  __IO uint32_t SECBB1R2;         /*!< FLASH secure block-based bank 1 register 2,     Address offset: 0x84 */
  __IO uint32_t SECBB1R3;         /*!< FLASH secure block-based bank 1 register 3,     Address offset: 0x88 */
  __IO uint32_t SECBB1R4;         /*!< FLASH secure block-based bank 1 register 4,     Address offset: 0x8C */
       uint32_t RESERVED5[4];     /*!< Reserved,                                       Address offset: 0x90-0x9C */
  __IO uint32_t SECBB2R1;         /*!< FLASH secure block-based bank 2 register 1,     Address offset: 0xA0 */
  __IO uint32_t SECBB2R2;         /*!< FLASH secure block-based bank 2 register 2,     Address offset: 0xA4 */
  __IO uint32_t SECBB2R3;         /*!< FLASH secure block-based bank 2 register 3,     Address offset: 0xA8 */
  __IO uint32_t SECBB2R4;         /*!< FLASH secure block-based bank 2 register 4,     Address offset: 0xAC */
       uint32_t RESERVED6[4];     /*!< Reserved,                                       Address offset: 0xB0-0xBC */
  __IO uint32_t SECHDPCR;         /*!< FLASH secure HDP control register,              Address offset: 0xC0 */
  __IO uint32_t PRIVCFGR;         /*!< FLASH privilege configuration register,         Address offset: 0xC4 */
  __IO uint32_t SECHDPEXTR;       /*!< FLASH HDP extension register,                   Address offset: 0xC8 */
       uint32_t RESERVED7;        /*!< Reserved,                                       Address offset: 0xCC */
  __IO uint32_t PRIVBB1R1;        /*!< FLASH privilege block-based bank 1 register 1,  Address offset: 0xD0 */
  __IO uint32_t PRIVBB1R2;        /*!< FLASH privilege block-based bank 1 register 2,  Address offset: 0xD4 */
  __IO uint32_t PRIVBB1R3;        /*!< FLASH privilege block-based bank 1 register 3,  Address offset: 0xD8 */
  __IO uint32_t PRIVBB1R4;        /*!< FLASH privilege block-based bank 1 register 4,  Address offset: 0xDC */
       uint32_t RESERVED8[4];     /*!< Reserved,                                       Address offset: 0xE0-0xEC */
  __IO uint32_t PRIVBB2R1;        /*!< FLASH privilege block-based bank 2 register 1,  Address offset: 0xF0 */
  __IO uint32_t PRIVBB2R2;        /*!< FLASH privilege block-based bank 2 register 2,  Address offset: 0xF4 */
  __IO uint32_t PRIVBB2R3;        /*!< FLASH privilege block-based bank 2 register 3,  Address offset: 0xF8 */
  __IO uint32_t PRIVBB2R4;        /*!< FLASH privilege block-based bank 2 register 4,  Address offset: 0xFC */
       uint32_t RESERVED9[4];     /*!< Reserved,                                       Address offset: 0x100-0x10C */
  __IO uint32_t OEM1KEYR1;        /*!< FLASH OEM1 key register 1,                      Address offset: 0x110 */
  __IO uint32_t OEM1KEYR2;        /*!< FLASH OEM1 key register 2,                      Address offset: 0x114 */
  __IO uint32_t OEM1KEYR3;        /*!< FLASH OEM1 key register 3,                      Address offset: 0x118 */
  __IO uint32_t OEM1KEYR4;        /*!< FLASH OEM1 key register 4,                      Address offset: 0x11C */
  __IO uint32_t OEM2KEYR1;        /*!< FLASH OEM2 key register 1,                      Address offset: 0x120 */
  __IO uint32_t OEM2KEYR2;        /*!< FLASH OEM2 key register 2,                      Address offset: 0x124 */
  __IO uint32_t OEM2KEYR3;        /*!< FLASH OEM2 key register 3,                      Address offset: 0x128 */
  __IO uint32_t OEM2KEYR4;        /*!< FLASH OEM2 key register 4,                      Address offset: 0x12C */
  __IO uint32_t OEMKEYSR;         /*!< FLASH OEM key status register,                  Address offset: 0x130 */
} FLASH_TypeDef;

/**
  * @brief General Purpose I/O
  */
typedef struct
{
  __IO uint32_t MODER;            /*!< GPIO port mode register,               Address offset: 0x00      */
  __IO uint32_t OTYPER;           /*!< GPIO port output type register,        Address offset: 0x04      */
  __IO uint32_t OSPEEDR;          /*!< GPIO port output speed register,       Address offset: 0x08      */
  __IO uint32_t PUPDR;            /*!< GPIO port pull-up/pull-down register,  Address offset: 0x0C      */
  __IO uint32_t IDR;              /*!< GPIO port input data register,         Address offset: 0x10      */
  __IO uint32_t ODR;              /*!< GPIO port output data register,        Address offset: 0x14      */
  __IO uint32_t BSRR;             /*!< GPIO port bit set/reset  register,     Address offset: 0x18      */
  __IO uint32_t LCKR;             /*!< GPIO port configuration lock register, Address offset: 0x1C      */
  __IO uint32_t AFR[2];           /*!< GPIO alternate function registers,     Address offset: 0x20-0x24 */
  __IO uint32_t BRR;              /*!< GPIO Bit Reset register,               Address offset: 0x28      */
  __IO uint32_t HSLVR;            /*!< GPIO high-speed low voltage register,  Address offset: 0x2C      */
  __IO uint32_t SECCFGR;          /*!< GPIO secure configuration register,    Address offset: 0x30      */
} GPIO_TypeDef;

typedef struct
{
  __IO uint32_t IER1;             /*!< TZIC interrupt enable register 1, Address offset: 0x00 */
  __IO uint32_t IER2;             /*!< TZIC interrupt enable register 2, Address offset: 0x04 */
  __IO uint32_t IER3;             /*!< TZIC interrupt enable register 3, Address offset: 0x08 */
  __IO uint32_t IER4;             /*!< TZIC interrupt enable register 4, Address offset: 0x0C */
  __IO uint32_t SR1;              /*!< TZIC status register 1,           Address offset: 0x10 */
  __IO uint32_t SR2;              /*!< TZIC status register 2,           Address offset: 0x14 */
  __IO uint32_t SR3;              /*!< TZIC status register 3,           Address offset: 0x18 */
  __IO uint32_t SR4;              /*!< TZIC status register 4,           Address offset: 0x1C */
  __IO uint32_t FCR1;             /*!< TZIC flag clear register 1,       Address offset: 0x20 */
  __IO uint32_t FCR2;             /*!< TZIC flag clear register 2,       Address offset: 0x24 */
  __IO uint32_t FCR3;             /*!< TZIC flag clear register 3,       Address offset: 0x28 */
  __IO uint32_t FCR4;             /*!< TZIC flag clear register 3,       Address offset: 0x2C */
} GTZC_TZIC_TypeDef;

typedef struct
{
  __IO uint32_t CR;               /*!< MPCBBx control register,                  Address offset: 0x00        */
  uint32_t RESERVED1[3];          /*!< Reserved1,                                Address offset: 0x04-0x0C   */
  __IO uint32_t CFGLOCKR1;        /*!< MPCBBx Configuration lock register,       Address offset: 0x10        */
  uint32_t RESERVED2[59];         /*!< Reserved2,                                Address offset: 0x14-0xFC   */
  __IO uint32_t SECCFGR[12];      /*!< MPCBBx security configuration registers,  Address offset: 0x100-0x12C */
  uint32_t RESERVED3[52];         /*!< Reserved3,                                Address offset: 0x130-0x200 */
  __IO uint32_t PRIVCFGR[12];     /*!< MPCBBx privilege configuration registers, Address offset: 0x200-0x22C */
} GTZC_MPCBB_TypeDef;

/**
  * @brief Global TrustZone Controller
  */
typedef struct
{
  __IO uint32_t CR;               /*!< TZSC control register,                                                Address offset: 0x00      */
       uint32_t RESERVED1[3];     /*!< Reserved1,                                                            Address offset: 0x04-0x0C */
  __IO uint32_t SECCFGR1;         /*!< TZSC secure configuration register 1,                                 Address offset: 0x10      */
  __IO uint32_t SECCFGR2;         /*!< TZSC secure configuration register 2,                                 Address offset: 0x14      */
  __IO uint32_t SECCFGR3;         /*!< TZSC secure configuration register 3,                                 Address offset: 0x18      */
       uint32_t RESERVED2;        /*!< Reserved2,                                                            Address offset: 0x1C      */
  __IO uint32_t PRIVCFGR1;        /*!< TZSC privilege configuration register 1,                              Address offset: 0x20      */
  __IO uint32_t PRIVCFGR2;        /*!< TZSC privilege configuration register 2,                              Address offset: 0x24      */
  __IO uint32_t PRIVCFGR3;        /*!< TZSC privilege configuration register 3,                              Address offset: 0x28      */
} GTZC_TZSC_TypeDef;

/**
  * @brief HASH
  */
typedef struct
{
  __IO uint32_t CR;               /*!< HASH control register,          Address offset: 0x00        */
  __IO uint32_t DIN;              /*!< HASH data input register,       Address offset: 0x04        */
  __IO uint32_t STR;              /*!< HASH start register,            Address offset: 0x08        */
  __IO uint32_t HR[5];            /*!< HASH digest registers,          Address offset: 0x0C-0x1C   */
  __IO uint32_t IMR;              /*!< HASH interrupt enable register, Address offset: 0x20        */
  __IO uint32_t SR;               /*!< HASH status register,           Address offset: 0x24        */
  __IO uint32_t SHA3CFGR;         /*!< HASH SHA-3 configuration register,  Address offset: 0x28    */
       uint32_t RESERVED[51];     /*!< Reserved, 0x2C-0xF4                                         */
  __IO uint32_t CSR[103];         /*!< HASH context swap registers,    Address offset: 0x0F8-0x290 */
} HASH_TypeDef;

/**
  * @brief HASH_DIGEST
  */
typedef struct
{
  __IO uint32_t HR[50];           /*!< HASH digest registers,          Address offset: 0x310-0x3D4 */
} HASH_DIGEST_TypeDef;

/**
  * @brief Inter-integrated Circuit Interface
  */
typedef struct
{
  __IO uint32_t CR1;              /*!< I2C Control register 1,                  Address offset: 0x00 */
  __IO uint32_t CR2;              /*!< I2C Control register 2,                  Address offset: 0x04 */
  __IO uint32_t OAR1;             /*!< I2C Own address 1 register,              Address offset: 0x08 */
  __IO uint32_t OAR2;             /*!< I2C Own address 2 register,              Address offset: 0x0C */
  __IO uint32_t TIMINGR;          /*!< I2C Timing register,                     Address offset: 0x10 */
  __IO uint32_t TIMEOUTR;         /*!< I2C Timeout register,                    Address offset: 0x14 */
  __IO uint32_t ISR;              /*!< I2C Interrupt and status register,       Address offset: 0x18 */
  __IO uint32_t ICR;              /*!< I2C Interrupt clear register,            Address offset: 0x1C */
  __IO uint32_t PECR;             /*!< I2C PEC register,                        Address offset: 0x20 */
  __IO uint32_t RXDR;             /*!< I2C Receive data register,               Address offset: 0x24 */
  __IO uint32_t TXDR;             /*!< I2C Transmit data register,              Address offset: 0x28 */
  __IO uint32_t AUTOCR;           /*!< I2C Autonomous mode control register,    Address offset: 0x2C */
} I2C_TypeDef;

/**
  * @brief Improved Inter-integrated Circuit Interface
  */
typedef struct
{
  __IO uint32_t CR;             /*!< I3C Control register,                      Address offset: 0x00      */
  __IO uint32_t CFGR;           /*!< I3C Controller Configuration register,     Address offset: 0x04      */
  uint32_t      RESERVED1[2];   /*!< Reserved,                                  Address offset: 0x08-0x0C */
  __IO uint32_t RDR;            /*!< I3C Received Data register,                Address offset: 0x10      */
  __IO uint32_t RDWR;           /*!< I3C Received Data Word register,           Address offset: 0x14      */
  __IO uint32_t TDR;            /*!< I3C Transmit Data register,                Address offset: 0x18      */
  __IO uint32_t TDWR;           /*!< I3C Transmit Data Word register,           Address offset: 0x1C      */
  __IO uint32_t IBIDR;          /*!< I3C IBI payload Data register,             Address offset: 0x20      */
  __IO uint32_t TGTTDR;         /*!< I3C Target Transmit register,              Address offset: 0x24      */
  uint32_t      RESERVED2[2];   /*!< Reserved,                                  Address offset: 0x28-0x2C */
  __IO uint32_t SR;             /*!< I3C Status register,                       Address offset: 0x30      */
  __IO uint32_t SER;            /*!< I3C Status Error register,                 Address offset: 0x34      */
  uint32_t      RESERVED3[2];   /*!< Reserved,                                  Address offset: 0x38-0x3C */
  __IO uint32_t RMR;            /*!< I3C Received Message register,             Address offset: 0x40      */
  uint32_t      RESERVED4[3];   /*!< Reserved,                                  Address offset: 0x44-0x4C */
  __IO uint32_t EVR;            /*!< I3C Event register,                        Address offset: 0x50      */
  __IO uint32_t IER;            /*!< I3C Interrupt Enable register,             Address offset: 0x54      */
  __IO uint32_t CEVR;           /*!< I3C Clear Event register,                  Address offset: 0x58      */
  __IO uint32_t MISR;           /*!< I3C Masked Interrupt Status register,      Address offset: 0x5C      */
  __IO uint32_t DEVR0;          /*!< I3C own Target characteristics register,   Address offset: 0x60      */
  __IO uint32_t DEVRX[4];       /*!< I3C Target x (1<=x<=4) register,           Address offset: 0x64-0x70 */
  uint32_t      RESERVED6[7];   /*!< Reserved,                                  Address offset: 0x74-0x8C */
  __IO uint32_t MAXRLR;         /*!< I3C Maximum Read Length register,          Address offset: 0x90      */
  __IO uint32_t MAXWLR;         /*!< I3C Maximum Write Length register,         Address offset: 0x94      */
  uint32_t      RESERVED7[2];   /*!< Reserved,                                  Address offset: 0x98-0x9C */
  __IO uint32_t TIMINGR0;       /*!< I3C Timing 0 register,                     Address offset: 0xA0      */
  __IO uint32_t TIMINGR1;       /*!< I3C Timing 1 register,                     Address offset: 0xA4      */
  __IO uint32_t TIMINGR2;       /*!< I3C Timing 2 register,                     Address offset: 0xA8      */
  uint32_t      RESERVED9[5];   /*!< Reserved,                                  Address offset: 0xAC-0xBC */
  __IO uint32_t BCR;            /*!< I3C Bus Characteristics register,          Address offset: 0xC0      */
  __IO uint32_t DCR;            /*!< I3C Device Characteristics register,       Address offset: 0xC4      */
  __IO uint32_t GETCAPR;        /*!< I3C GET CAPabilities register,             Address offset: 0xC8      */
  __IO uint32_t CRCAPR;         /*!< I3C Controller CAPabilities register,      Address offset: 0xCC      */
  __IO uint32_t GETMXDSR;       /*!< I3C GET Max Data Speed register,           Address offset: 0xD0      */
  __IO uint32_t EPIDR;          /*!< I3C Extended Provisioned ID register,      Address offset: 0xD4      */
} I3C_TypeDef;

/**
  * @brief Instruction Cache
  */
typedef struct
{
  __IO uint32_t CR;               /*!< ICACHE control register,                Address offset: 0x00 */
  __IO uint32_t SR;               /*!< ICACHE status register,                 Address offset: 0x04 */
  __IO uint32_t IER;              /*!< ICACHE interrupt enable register,       Address offset: 0x08 */
  __IO uint32_t FCR;              /*!< ICACHE Flag clear register,             Address offset: 0x0C */
  __IO uint32_t HMONR;            /*!< ICACHE hit monitor register,            Address offset: 0x10 */
  __IO uint32_t MMONR;            /*!< ICACHE miss monitor register,           Address offset: 0x14 */
       uint32_t RESERVED1[2];     /*!< Reserved,                                        0x018-0x01C */
  __IO uint32_t CRR0;             /*!< ICACHE region 0 configuration register, Address offset: 0x20 */
  __IO uint32_t CRR1;             /*!< ICACHE region 1 configuration register, Address offset: 0x24 */
  __IO uint32_t CRR2;             /*!< ICACHE region 2 configuration register, Address offset: 0x28 */
  __IO uint32_t CRR3;             /*!< ICACHE region 3 configuration register, Address offset: 0x2C */
} ICACHE_TypeDef;

/**
  * @brief IWDG
  */
typedef struct
{
  __IO uint32_t KR;               /*!< IWDG Key register,          Address offset: 0x00 */
  __IO uint32_t PR;               /*!< IWDG Prescaler register,    Address offset: 0x04 */
  __IO uint32_t RLR;              /*!< IWDG Reload register,       Address offset: 0x08 */
  __IO uint32_t SR;               /*!< IWDG Status register,       Address offset: 0x0C */
  __IO uint32_t WINR;             /*!< IWDG Window register,       Address offset: 0x10 */
  __IO uint32_t EWCR;             /*!< IWDG Early Wakeup register, Address offset: 0x14 */
} IWDG_TypeDef;


/**
  * @brief LPTIMER
  */
typedef struct
{
  __IO uint32_t ISR;              /*!< LPTIM Interrupt and Status register,    Address offset: 0x00 */
  __IO uint32_t ICR;              /*!< LPTIM Interrupt Clear register,         Address offset: 0x04 */
  __IO uint32_t DIER;             /*!< LPTIM Interrupt Enable register,        Address offset: 0x08 */
  __IO uint32_t CFGR;             /*!< LPTIM Configuration register,           Address offset: 0x0C */
  __IO uint32_t CR;               /*!< LPTIM Control register,                 Address offset: 0x10 */
  __IO uint32_t CCR1;             /*!< LPTIM Capture/Compare register 1,       Address offset: 0x14 */
  __IO uint32_t ARR;              /*!< LPTIM Autoreload register,              Address offset: 0x18 */
  __IO uint32_t CNT;              /*!< LPTIM Counter register,                 Address offset: 0x1C */
  __IO uint32_t RESERVED0;        /*!< Reserved,                               Address offset: 0x20 */
  __IO uint32_t CFGR2;            /*!< LPTIM Configuration register 2,         Address offset: 0x24 */
  __IO uint32_t RCR;              /*!< LPTIM Repetition register,              Address offset: 0x28 */
  __IO uint32_t CCMR1;            /*!< LPTIM Capture/Compare mode register,    Address offset: 0x2C */
  __IO uint32_t RESERVED1;        /*!< Reserved,                               Address offset: 0x30 */
  __IO uint32_t CCR2;             /*!< LPTIM Capture/Compare register 2,       Address offset: 0x34 */
} LPTIM_TypeDef;

/**
  * @brief MDF/ADF
  */
typedef struct
{
  __IO uint32_t GCR;              /*!< MDF Global Control register,            Address offset: 0x00  */
  __IO uint32_t CKGCR;            /*!< MDF Clock Generator Control Register,   Address offset: 0x04  */
 uint32_t       RESERVED0[6];     /*!< Reserved, 0x08-0x1C                                           */
  __IO uint32_t TRGISELR;         /*!< MDF Trigger Input Selection Register,   Address offset: 0x20  */
} MDF_TypeDef;

/**
  * @brief MDF/ADF filter
  */
typedef struct
{
 __IO uint32_t SITFCR;            /*!< MDF Serial Interface Control Register,          Address offset: 0x80 */
 __IO uint32_t BSMXCR;            /*!< MDF Bitstream Matrix Control Register,          Address offset: 0x84 */
 __IO uint32_t DFLTCR;            /*!< MDF Digital Filter Control Register,            Address offset: 0x88 */
 __IO uint32_t DFLTCICR;          /*!< MDF MCIC Configuration Register,                Address offset: 0x8C */
 __IO uint32_t DFLTRSFR;          /*!< MDF Reshape Filter Configuration Register,      Address offset: 0x90 */
 uint32_t      RESERVED0[4];      /*!< Reserved, 0x94-0xA0                                                  */
 __IO uint32_t DLYCR;             /*!< MDF Delay control Register,                     Address offset: 0xA4 */
 uint32_t      RESERVED1[1];      /*!< Reserved, 0xA8                                                       */
 __IO uint32_t DFLTIER;           /*!< MDF DFLT Interrupt enable Register,             Address offset: 0xAC */
 __IO uint32_t DFLTISR;           /*!< MDF DFLT Interrupt status Register,             Address offset: 0xB0 */
 uint32_t      RESERVED2[1];      /*!< Reserved, 0xB4                                                       */
 __IO uint32_t SADCR;             /*!< MDF SAD Control Register,                       Address offset: 0xB8 */
 __IO uint32_t SADCFGR;           /*!< MDF SAD configuration register,                 Address offset: 0xBC */
 __IO uint32_t SADSDLVR;          /*!< MDF SAD Sound level Register,                   Address offset: 0xC0 */
 __IO uint32_t SADANLVR;          /*!< MDF SAD Ambient Noise level Register,           Address offset: 0xC4 */
 uint32_t      RESERVED3[10];     /*!< Reserved, 0xC8-0xEC                                                  */
 __IO uint32_t DFLTDR;            /*!< MDF Digital Filter Data Register,               Address offset: 0xF0 */
} MDF_Filter_TypeDef;

/**
  * @brief Operational Amplifier (OPAMP)
  */
typedef struct
{
  __IO uint32_t CSR;              /*!< OPAMP control/status register,                     Address offset: 0x00 */
  __IO uint32_t OTR;              /*!< OPAMP offset trimming register for normal mode,    Address offset: 0x04 */
  __IO uint32_t LPOTR;            /*!< OPAMP offset trimming register for low power mode, Address offset: 0x08 */
} OPAMP_TypeDef;

typedef struct
{
  __IO uint32_t CSR;              /*!< OPAMP control/status register, used for bits common to
                                    several OPAMP instances, Address offset: 0x00         */
} OPAMP_Common_TypeDef;

/**
  * @brief PKA
  */
typedef struct
{
  __IO uint32_t CR;               /*!< PKA control register,             Address offset: 0x00 */
  __IO uint32_t SR;               /*!< PKA status register,              Address offset: 0x04 */
  __IO uint32_t CLRFR;            /*!< PKA clear flag register,          Address offset: 0x08 */
  uint32_t Reserved[253];         /*!< Reserved memory area              Address offset: 0x0C  -> 0x03FC */
  __IO uint32_t RAM[1334];        /*!< PKA RAM                           Address offset: 0x400 -> 0x18D4 */
} PKA_TypeDef;

/**
  * @brief Power Control
  */
typedef struct
{
  __IO uint32_t CR1;              /*!< Power control register 1,                          Address offset: 0x00 */
  __IO uint32_t CR2;              /*!< Power control register 2,                          Address offset: 0x04 */
  __IO uint32_t CR3;              /*!< Power control register 3,                          Address offset: 0x08 */
  __IO uint32_t VOSR;             /*!< Power voltage scaling register,                    Address offset: 0x0C */
  __IO uint32_t SVMCR;            /*!< Power supply voltage monitoring control register,  Address offset: 0x10 */
  __IO uint32_t WUCR1;            /*!< Power wakeup control register 1,                   Address offset: 0x14 */
  __IO uint32_t WUCR2;            /*!< Power wakeup control register 2,                   Address offset: 0x18 */
  __IO uint32_t WUCR3;            /*!< Power wakeup control register 3,                   Address offset: 0x1C */
  uint32_t      RESERVED1;        /*!< Reserved,                                          Address offset: 0x20 */
  __IO uint32_t BDCR;             /*!< Power backup domain control register,              Address offset: 0x24 */
  __IO uint32_t DBPR;             /*!< Power disable backup domain register,              Address offset: 0x28 */
  uint32_t      RESERVED2;        /*!< Reserved,                                          Address offset: 0x2C */
  __IO uint32_t SECCFGR;          /*!< Power Security configuration register,             Address offset: 0x30 */
  __IO uint32_t PRIVCFGR;         /*!< Power privilege control register,                  Address offset: 0x34 */
  __IO uint32_t SR;               /*!< Power status register,                             Address offset: 0x38 */
  __IO uint32_t SVMSR;            /*!< Power supply voltage monitoring status register,   Address offset: 0x3C */
  uint32_t      RESERVED3;        /*!< Reserved,                                          Address offset: 0x20 */
  __IO uint32_t WUSR;             /*!< Power wakeup status register,                      Address offset: 0x44 */
  __IO uint32_t WUSCR;            /*!< Power wakeup status clear register,                Address offset: 0x48 */
  __IO uint32_t APCR;             /*!< Power apply pull configuration register,           Address offset: 0x4C */
  __IO uint32_t PUCRA;            /*!< Power Port A pull-up control register,             Address offset: 0x50 */
  __IO uint32_t PDCRA;            /*!< Power Port A pull-down control register,           Address offset: 0x54 */
  __IO uint32_t PUCRB;            /*!< Power Port B pull-up control register,             Address offset: 0x58 */
  __IO uint32_t PDCRB;            /*!< Power Port B pull-down control register,           Address offset: 0x5C */
  __IO uint32_t PUCRC;            /*!< Power Port C pull-up control register,             Address offset: 0x60 */
  __IO uint32_t PDCRC;            /*!< Power Port C pull-down control register,           Address offset: 0x64 */
  __IO uint32_t PUCRD;            /*!< Power Port D pull-up control register,             Address offset: 0x68 */
  __IO uint32_t PDCRD;            /*!< Power Port D pull-down control register,           Address offset: 0x6C */
  __IO uint32_t PUCRE;            /*!< Power Port E pull-up control register,             Address offset: 0x70 */
  __IO uint32_t PDCRE;            /*!< Power Port E pull-down control register,           Address offset: 0x74 */
  uint32_t      RESERVED4[2];     /*!< Reserved,                                          Address offset: 0x78 -> 0x7C */
  __IO uint32_t PUCRG;            /*!< Power Port G pull-up control register,             Address offset: 0x80 */
  __IO uint32_t PDCRG;            /*!< Power Port G pull-down control register,           Address offset: 0x84 */
  __IO uint32_t PUCRH;            /*!< Power Port H pull-up control register,             Address offset: 0x88 */
  __IO uint32_t PDCRH;            /*!< Power Port H pull-down control register,           Address offset: 0x8C */
  uint32_t      RESERVED5[8];     /*!< Reserved,                                          Address offset: 0x90 -> 0xAC */
  __IO uint32_t I3CPUCR1;         /*!< Power I3C pull-up control register 1,              Address offset: 0xB0 */
  __IO uint32_t I3CPUCR2;         /*!< Power I3C pull-up control register 2,              Address offset: 0xB4 */
} PWR_TypeDef;

/**
  * @brief SRAMs configuration controller
  */
typedef struct
{
  __IO uint32_t CR;           /*!< Control Register,                  Address offset: 0x00 */
  __IO uint32_t IER;          /*!< Interrupt enable register,         Address offset: 0x04 */
  __IO uint32_t ISR;          /*!< Interrupt status register,         Address offset: 0x08 */
  uint32_t      RESERVED0;    /*!< Reserved,                          Address offset: 0x0C */
  __IO uint32_t PEAR;         /*!< Parity error address register,     Address offset: 0x10 */
  __IO uint32_t ICR;          /*!< Interrupt clear register,          Address offset: 0x14 */
  __IO uint32_t WPR1;         /*!< Write protection register 1,       Address offset: 0x18 */
  __IO uint32_t WPR2;         /*!< Write protection register 2,       Address offset: 0x1C */
  uint32_t      RESERVED1;    /*!< Reserved,                          Address offset: 0x20 */
  __IO uint32_t PARKEYR;      /*!< Parity key register,               Address offset: 0x24 */
  __IO uint32_t ERKEYR;       /*!< Erase key register,                Address offset: 0x28 */
}RAMCFG_TypeDef;

/**
  * @brief Reset and Clock Control
  */
typedef struct
{
  __IO uint32_t CR;               /*!< RCC Clock Control Register                               Address offset: 0x000 */
  uint32_t      RESERVED0;        /*!< Reserved                                                 Address offset: 0x004 */
  __IO uint32_t ICSCR1;           /*!< RCC Internal Clock Sources Calibration Register 1        Address offset: 0x008 */
  __IO uint32_t ICSCR2;           /*!< RCC Internal Clock Sources Calibration Register 2        Address offset: 0x00C */
  __IO uint32_t ICSCR3;           /*!< RCC Internal Clock Sources Calibration Register 3        Address offset: 0x010 */
  __IO uint32_t CRRCR;            /*!< RCC Clock Recovery RC Register                           Address offset: 0x014 */
  uint32_t      RESERVED1;        /*!< Reserved                                                 Address offset: 0x018 */
  __IO uint32_t CFGR1;            /*!< RCC Clock Configuration Register 1                       Address offset: 0x01C */
  __IO uint32_t CFGR2;            /*!< RCC Clock Configuration Register 2                       Address offset: 0x020 */
  __IO uint32_t CFGR3;            /*!< RCC Clock Configuration Register 3                       Address offset: 0x024 */
  __IO uint32_t CFGR4;            /*!< RCC Clock Configuration Register 4                       Address offset: 0x028 */
  uint32_t      RESERVED2[9];     /*!< Reserved                                                 Address offset: 0x02C */
  __IO uint32_t CIER;             /*!< Clock Interrupt Enable Register                          Address offset: 0x050 */
  __IO uint32_t CIFR;             /*!< Clock Interrupt Flag Register                            Address offset: 0x054 */
  __IO uint32_t CICR;             /*!< Clock Interrupt Clear Register                           Address offset: 0x058 */
  uint32_t      RESERVED3;        /*!< Reserved                                                 Address offset: 0x05C */
  __IO uint32_t AHB1RSTR1;        /*!< AHB1 Peripherals Reset Register 1                        Address offset: 0x060 */
  __IO uint32_t AHB2RSTR1;        /*!< AHB2 Peripherals Reset Register 1                        Address offset: 0x064 */
  __IO uint32_t AHB2RSTR2;        /*!< AHB2 Peripherals Reset Register 2                        Address offset: 0x068 */
  uint32_t      RESERVED4[2];     /*!< Reserved                                                 Address offset: 0x06C */
  __IO uint32_t APB1RSTR1;        /*!< APB1 Peripherals Reset Register 1                        Address offset: 0x074 */
  __IO uint32_t APB1RSTR2;        /*!< APB1 Peripherals Reset Register 2                        Address offset: 0x078 */
  __IO uint32_t APB2RSTR;         /*!< APB2 Peripherals Reset Register                          Address offset: 0x07C */
  __IO uint32_t APB3RSTR;         /*!< APB3 Peripherals Reset Register                          Address offset: 0x080 */
  uint32_t      RESERVED5;        /*!< Reserved                                                 Address offset: 0x084 */
  __IO uint32_t AHB1ENR1;         /*!< AHB1 Peripherals Clock Enable Register 1                 Address offset: 0x088 */
  __IO uint32_t AHB2ENR1;         /*!< AHB2 Peripherals Clock Enable Register 1                 Address offset: 0x08C */
  __IO uint32_t AHB2ENR2;         /*!< AHB2 Peripherals Clock Enable Register 2                 Address offset: 0x090 */
  __IO uint32_t AHB1ENR2;         /*!< AHB1 Peripherals Clock Enable Register 2                 Address offset: 0x094 */
  uint32_t      RESERVED6;        /*!< Reserved                                                 Address offset: 0x098 */
  __IO uint32_t APB1ENR1;         /*!< APB1 Peripherals Clock Enable Register 1                 Address offset: 0x09C */
  __IO uint32_t APB1ENR2;         /*!< APB1 Peripherals Clock Enable Register 2                 Address offset: 0x0A0 */
  __IO uint32_t APB2ENR;          /*!< APB2 Peripherals Clock Enable Register                   Address offset: 0x0A4 */
  __IO uint32_t APB3ENR;          /*!< APB3 Peripherals Clock Enable Register                   Address offset: 0x0A8 */
  uint32_t      RESERVED7;        /*!< Reserved                                                 Address offset: 0x0AC */
  __IO uint32_t AHB1SLPENR1;      /*!< AHB1 Peripherals Clock Enable in Sleep Mode Register 1   Address offset: 0x0B0 */
  __IO uint32_t AHB2SLPENR1;      /*!< AHB2 Peripherals Clock Enable in Sleep Mode Register 1   Address offset: 0x0B4 */
  __IO uint32_t AHB2SLPENR2;      /*!< AHB2 Peripherals Clock Enable in Sleep Mode Register 2   Address offset: 0x0B8 */
  __IO uint32_t AHB1SLPENR2;      /*!< AHB1 Peripherals Clock Enable in Sleep Mode Register 2   Address offset: 0x0BC */
  uint32_t      RESERVED8;        /*!< Reserved                                                 Address offset: 0x0C0 */
  __IO uint32_t APB1SLPENR1;      /*!< APB1 Peripherals Clock Enable in Sleep Mode Register 1   Address offset: 0x0C4 */
  __IO uint32_t APB1SLPENR2;      /*!< APB1 Peripherals Clock Enable in Sleep Mode Register 2   Address offset: 0x0C8 */
  __IO uint32_t APB2SLPENR;       /*!< APB2 Peripherals Clock Enable in Sleep Mode Register     Address offset: 0x0CC */
  __IO uint32_t APB3SLPENR;       /*!< APB3 Peripherals Clock Enable in Sleep Mode Register     Address offset: 0x0D0 */
  uint32_t      RESERVED9;        /*!< Reserved                                                 Address offset: 0x0D4 */
  __IO uint32_t AHB1STPENR1;      /*!< AHB1 Peripherals Clock Enable in Stop Mode Register 1    Address offset: 0x0D8 */
  __IO uint32_t AHB2STPENR1;      /*!< AHB2 Peripherals Clock Enable in Stop Mode Register 1    Address offset: 0x0DC */
  uint32_t      RESERVED10[3];    /*!< Reserved                                                 Address offset: 0x0E0 */
  __IO uint32_t APB1STPENR1;      /*!< APB1 Peripherals Clock Enable in Stop Mode Register 1    Address offset: 0x0EC */
  __IO uint32_t APB1STPENR2;      /*!< APB1 Peripherals Clock Enable in Stop Mode Register 2    Address offset: 0x0F0 */
  __IO uint32_t APB2STPENR;       /*!< APB2 Peripherals Clock Enable in Stop Mode Register      Address offset: 0x0F4 */
  __IO uint32_t APB3STPENR;       /*!< APB3 Peripherals Clock Enable in Stop Mode Register      Address offset: 0x0F8 */
       uint32_t RESERVED11;       /*!< Reserved                                                 Address offset: 0x0FC */
  __IO uint32_t CCIPR1;           /*!< Peripherals Independent Clocks Configuration Register 1  Address offset: 0x100 */
  __IO uint32_t CCIPR2;           /*!< Peripherals Independent Clocks Configuration Register 2  Address offset: 0x104 */
  __IO uint32_t CCIPR3;           /*!< Peripherals Independent Clocks Configuration Register 3  Address offset: 0x108 */
  uint32_t      RESERVED12;       /*!< Reserved                                                 Address offset: 0x10C */
  __IO uint32_t BDCR;             /*!< Backup Domain Control Register                           Address offset: 0x110 */
  __IO uint32_t CSR;              /*!< Control & Status Register                                Address offset: 0x114 */
  uint32_t      RESERVED13[6];    /*!< Reserved                                                 Address offset: 0x118 */
  __IO uint32_t SECCFGR;          /*!< RCC Secure Configuration Register                        Address offset: 0x130 */
  __IO uint32_t PRIVCFGR;         /*!< RCC Privilege Configuration Register                     Address offset: 0x134 */
} RCC_TypeDef;

/**
  * @brief RNG
  */
typedef struct
{
  __IO uint32_t CR;               /*!< RNG control register,                     Address offset: 0x00 */
  __IO uint32_t SR;               /*!< RNG status register,                      Address offset: 0x04 */
  __IO uint32_t DR;               /*!< RNG data register,                        Address offset: 0x08 */
  __IO uint32_t NSCR;             /*!< RNG noise source control register,        Address offset: 0x0C */
  __IO uint32_t HTCR;             /*!< RNG health test configuration register,   Address offset: 0x10 */
} RNG_TypeDef;

/**
  * @brief Real-Time Clock
  */
typedef struct
{
  __IO uint32_t TR;               /*!< RTC time register,                              Address offset: 0x00 */
  __IO uint32_t DR;               /*!< RTC date register,                              Address offset: 0x04 */
  __IO uint32_t SSR;              /*!< RTC sub second register,                        Address offset: 0x08 */
  __IO uint32_t ICSR;             /*!< RTC initialization control and status register, Address offset: 0x0C */
  __IO uint32_t PRER;             /*!< RTC prescaler register,                         Address offset: 0x10 */
  __IO uint32_t WUTR;             /*!< RTC wakeup timer register,                      Address offset: 0x14 */
  __IO uint32_t CR;               /*!< RTC control register,                           Address offset: 0x18 */
  __IO uint32_t PRIVCFGR;         /*!< RTC privilege mode control register,            Address offset: 0x1C */
  __IO uint32_t SECCFGR;          /*!< RTC secure mode control register,               Address offset: 0x20 */
  __IO uint32_t WPR;              /*!< RTC write protection register,                  Address offset: 0x24 */
  __IO uint32_t CALR;             /*!< RTC calibration register,                       Address offset: 0x28 */
  __IO uint32_t SHIFTR;           /*!< RTC shift control register,                     Address offset: 0x2C */
  __IO uint32_t TSTR;             /*!< RTC time stamp time register,                   Address offset: 0x30 */
  __IO uint32_t TSDR;             /*!< RTC time stamp date register,                   Address offset: 0x34 */
  __IO uint32_t TSSSR;            /*!< RTC time-stamp sub second register,             Address offset: 0x38 */
       uint32_t RESERVED0;        /*!< Reserved,                                       Address offset: 0x3C */
  __IO uint32_t ALRMAR;           /*!< RTC alarm A register,                           Address offset: 0x40 */
  __IO uint32_t ALRMASSR;         /*!< RTC alarm A sub second register,                Address offset: 0x44 */
  __IO uint32_t ALRMBR;           /*!< RTC alarm B register,                           Address offset: 0x48 */
  __IO uint32_t ALRMBSSR;         /*!< RTC alarm B sub second register,                Address offset: 0x4C */
  __IO uint32_t SR;               /*!< RTC Status register,                            Address offset: 0x50 */
  __IO uint32_t MISR;             /*!< RTC masked interrupt status register,           Address offset: 0x54 */
  __IO uint32_t SMISR;            /*!< RTC secure masked interrupt status register,    Address offset: 0x58 */
  __IO uint32_t SCR;              /*!< RTC status Clear register,                      Address offset: 0x5C */
       uint32_t RESERVED1;        /*!< Reserved,                                       Address offset: 0x60 */
  __IO uint32_t TAMPTSCR;         /*!< RTC timestamp on tamper control register,       Address offset: 0x64 */
  __IO uint32_t TSIDR;            /*!< RTC timestamp status register,                  Address offset: 0x68 */
       uint32_t RESERVED2;        /*!< Reserved,                                       Address offset: 0x6C */
  __IO uint32_t ALRABINR;         /*!< RTC alarm A binary mode register,               Address offset: 0x70 */
  __IO uint32_t ALRBBINR;         /*!< RTC alarm B binary mode register,               Address offset: 0x74 */
} RTC_TypeDef;

/**
  * @brief Serial Audio Interface
  */
typedef struct
{
  uint32_t      RESERVED[17];     /*!< Reserved,                         Address offset: 0x00 to 0x40 */
  __IO uint32_t PDMCR;            /*!< SAI PDM control register,                 Address offset: 0x44 */
  __IO uint32_t PDMDLY;           /*!< SAI PDM delay register,                   Address offset: 0x48 */
} SAI_TypeDef;

typedef struct
{
  __IO uint32_t CR1;              /*!< SAI block x configuration register 1,     Address offset: 0x04 */
  __IO uint32_t CR2;              /*!< SAI block x configuration register 2,     Address offset: 0x08 */
  __IO uint32_t FRCR;             /*!< SAI block x frame configuration register, Address offset: 0x0C */
  __IO uint32_t SLOTR;            /*!< SAI block x slot register,                Address offset: 0x10 */
  __IO uint32_t IMR;              /*!< SAI block x interrupt mask register,      Address offset: 0x14 */
  __IO uint32_t SR;               /*!< SAI block x status register,              Address offset: 0x18 */
  __IO uint32_t CLRFR;            /*!< SAI block x clear flag register,          Address offset: 0x1C */
  __IO uint32_t DR;               /*!< SAI block x data register,                Address offset: 0x20 */
} SAI_Block_TypeDef;

/**
  * @brief Secure digital input/output Interface
  */
typedef struct
{
  __IO uint32_t POWER;            /*!< SDMMC power control register,                Address offset: 0x00 */
  __IO uint32_t CLKCR;            /*!< SDMMC clock control register,                Address offset: 0x04 */
  __IO uint32_t ARG;              /*!< SDMMC argument register,                     Address offset: 0x08 */
  __IO uint32_t CMD;              /*!< SDMMC command register,                      Address offset: 0x0C */
  __I uint32_t  RESPCMD;          /*!< SDMMC command response register,             Address offset: 0x10 */
  __I uint32_t  RESP1;            /*!< SDMMC response 1 register,                   Address offset: 0x14 */
  __I uint32_t  RESP2;            /*!< SDMMC response 2 register,                   Address offset: 0x18 */
  __I uint32_t  RESP3;            /*!< SDMMC response 3 register,                   Address offset: 0x1C */
  __I uint32_t  RESP4;            /*!< SDMMC response 4 register,                   Address offset: 0x20 */
  __IO uint32_t DTIMER;           /*!< SDMMC data timer register,                   Address offset: 0x24 */
  __IO uint32_t DLEN;             /*!< SDMMC data length register,                  Address offset: 0x28 */
  __IO uint32_t DCTRL;            /*!< SDMMC data control register,                 Address offset: 0x2C */
  __I uint32_t  DCOUNT;           /*!< SDMMC data counter register,                 Address offset: 0x30 */
  __I uint32_t  STA;              /*!< SDMMC status register,                       Address offset: 0x34 */
  __IO uint32_t ICR;              /*!< SDMMC interrupt clear register,              Address offset: 0x38 */
  __IO uint32_t MASK;             /*!< SDMMC mask register,                         Address offset: 0x3C */
  __IO uint32_t ACKTIME;          /*!< SDMMC Acknowledgement timer register,        Address offset: 0x40 */
  uint32_t      RESERVED0[3];     /*!< Reserved, 0x44 - 0x4C - 0x4C                                      */
  __IO uint32_t IDMACTRL;         /*!< SDMMC DMA control register,                  Address offset: 0x50 */
  __IO uint32_t IDMABSIZE;        /*!< SDMMC DMA buffer size register,              Address offset: 0x54 */
  __IO uint32_t IDMABASER;        /*!< SDMMC DMA buffer base address register,      Address offset: 0x58 */
  uint32_t      RESERVED1[2];     /*!< Reserved, 0x60                                                    */
  __IO uint32_t IDMALAR;          /*!< SDMMC DMA linked list address register,      Address offset: 0x64 */
  __IO uint32_t IDMABAR;          /*!< SDMMC DMA linked list memory base register,  Address offset: 0x68 */
  uint32_t      RESERVED2[5];     /*!< Reserved, 0x6C-0x7C                                               */
  __IO uint32_t FIFO;             /*!< SDMMC data FIFO register,                    Address offset: 0x80 */
} SDMMC_TypeDef;

/**
  * @brief SPI
  */
typedef struct
{
  __IO uint32_t CR1;              /*!< SPI/I2S Control register 1,                      Address offset: 0x00 */
  __IO uint32_t CR2;               /*!< SPI Control register 2,                          Address offset: 0x04 */
  __IO uint32_t CFG1;              /*!< SPI Configuration register 1,                    Address offset: 0x08 */
  __IO uint32_t CFG2;              /*!< SPI Configuration register 2,                    Address offset: 0x0C */
  __IO uint32_t IER;               /*!< SPI Interrupt Enable register,                   Address offset: 0x10 */
  __IO uint32_t SR;                /*!< SPI Status register,                             Address offset: 0x14 */
  __IO uint32_t IFCR;              /*!< SPI Interrupt/Status Flags Clear register,       Address offset: 0x18 */
  __IO uint32_t AUTOCR;            /*!< SPI Autonomous Mode Control register,            Address offset: 0x1C */
  __IO uint32_t TXDR;              /*!< SPI Transmit data register,                      Address offset: 0x20 */
  uint32_t      RESERVED1[3];      /*!< Reserved, 0x24-0x2C                                                   */
  __IO uint32_t RXDR;              /*!< SPI/I2S data register,                           Address offset: 0x30 */
  uint32_t      RESERVED2[3];      /*!< Reserved, 0x34-0x3C                                                   */
  __IO uint32_t CRCPOLY;           /*!< SPI CRC Polynomial register,                     Address offset: 0x40 */
  __IO uint32_t TXCRC;             /*!< SPI Transmitter CRC register,                    Address offset: 0x44 */
  __IO uint32_t RXCRC;             /*!< SPI Receiver CRC register,                       Address offset: 0x48 */
  __IO uint32_t UDRDR;             /*!< SPI Underrun data register,                      Address offset: 0x4C */
} SPI_TypeDef;

/**
  * @brief System configuration controller
  */
typedef struct
{
  __IO uint32_t SECCFGR;          /*!< SYSCFG secure configuration register,            Address offset: 0x00 */
  __IO uint32_t CFGR1;            /*!< SYSCFG configuration register 1,                 Address offset: 0x04 */
  __IO uint32_t FPUIMR;           /*!< SYSCFG FPU interrupt mask register,              Address offset: 0x08 */
  __IO uint32_t CNSLCKR;          /*!< SYSCFG CPU non-secure lock register,             Address offset: 0x0C */
  __IO uint32_t CSLCKR;           /*!< SYSCFG CPU secure lock register,                 Address offset: 0x10 */
  __IO uint32_t CFGR2;            /*!< SYSCFG configuration register 2,                 Address offset: 0x14 */
       uint32_t RESERVED1;        /*!< RESERVED1,                                       Address offset: 0x28 */
  __IO uint32_t CCCSR;            /*!< SYSCFG Conpensaion Cell Control&Status register, Address offset: 0x1C */
  __IO uint32_t CCVR;             /*!< SYSCFG Conpensaion Cell value register,          Address offset: 0x20 */
  __IO uint32_t CCCR;             /*!< SYSCFG Conpensaion Cell Code register,           Address offset: 0x24 */
       uint32_t RESERVED2;        /*!< RESERVED2,                                       Address offset: 0x28 */
  __IO uint32_t RSSCMDR;          /*!< SYSCFG RSS command mode register,                Address offset: 0x2C */
} SYSCFG_TypeDef;

/**
  * @brief Tamper and backup registers
  */
typedef struct
{
  __IO uint32_t CR1;              /*!< TAMP configuration register 1,                    Address offset: 0x00 */
  __IO uint32_t CR2;              /*!< TAMP configuration register 2,                    Address offset: 0x04 */
  __IO uint32_t CR3;              /*!< TAMP configuration register 3,                    Address offset: 0x08 */
  __IO uint32_t FLTCR;            /*!< TAMP filter control register,                     Address offset: 0x0C */
       uint32_t RESERVED1[4];     /*!< Reserved,                                                 0x10 -- 0x1C */
  __IO uint32_t SECCFGR;          /*!< TAMP secure mode control register,                Address offset: 0x20 */
  __IO uint32_t PRIVCFGR;         /*!< TAMP privilege mode control register,             Address offset: 0x24 */
       uint32_t RESERVED0;        /*!< Reserved,                                         Address offset: 0x28 */
  __IO uint32_t IER;              /*!< TAMP interrupt enable register,                   Address offset: 0x2C */
  __IO uint32_t SR;               /*!< TAMP status register,                             Address offset: 0x30 */
  __IO uint32_t MISR;             /*!< TAMP masked interrupt status register,            Address offset: 0x34 */
  __IO uint32_t SMISR;            /*!< TAMP secure masked interrupt status register,     Address offset: 0x38 */
  __IO uint32_t SCR;              /*!< TAMP status clear register,                       Address offset: 0x3C */
  __IO uint32_t COUNT1R;          /*!< TAMP monotonic counter register,                  Address offset: 0x40 */
       uint32_t RESERVED2[4];     /*!< Reserved,                                                 0x44 -- 0x50 */
  __IO uint32_t RPCFGR;           /*!< TAMP resources protection configuration register, Address offset: 0x54 */
       uint32_t RESERVED3[42];    /*!< Reserved,                                                 0x58 -- 0xFC */
  __IO uint32_t BKP0R;            /*!< TAMP backup register 0,                          Address offset: 0x100 */
  __IO uint32_t BKP1R;            /*!< TAMP backup register 1,                          Address offset: 0x104 */
  __IO uint32_t BKP2R;            /*!< TAMP backup register 2,                          Address offset: 0x108 */
  __IO uint32_t BKP3R;            /*!< TAMP backup register 3,                          Address offset: 0x10C */
  __IO uint32_t BKP4R;            /*!< TAMP backup register 4,                          Address offset: 0x110 */
  __IO uint32_t BKP5R;            /*!< TAMP backup register 5,                          Address offset: 0x114 */
  __IO uint32_t BKP6R;            /*!< TAMP backup register 6,                          Address offset: 0x118 */
  __IO uint32_t BKP7R;            /*!< TAMP backup register 7,                          Address offset: 0x11C */
  __IO uint32_t BKP8R;            /*!< TAMP backup register 8,                          Address offset: 0x120 */
  __IO uint32_t BKP9R;            /*!< TAMP backup register 9,                          Address offset: 0x124 */
  __IO uint32_t BKP10R;           /*!< TAMP backup register 10,                         Address offset: 0x128 */
  __IO uint32_t BKP11R;           /*!< TAMP backup register 11,                         Address offset: 0x12C */
  __IO uint32_t BKP12R;           /*!< TAMP backup register 12,                         Address offset: 0x130 */
  __IO uint32_t BKP13R;           /*!< TAMP backup register 13,                         Address offset: 0x134 */
  __IO uint32_t BKP14R;           /*!< TAMP backup register 14,                         Address offset: 0x138 */
  __IO uint32_t BKP15R;           /*!< TAMP backup register 15,                         Address offset: 0x13C */
  __IO uint32_t BKP16R;           /*!< TAMP backup register 16,                         Address offset: 0x140 */
  __IO uint32_t BKP17R;           /*!< TAMP backup register 17,                         Address offset: 0x144 */
  __IO uint32_t BKP18R;           /*!< TAMP backup register 18,                         Address offset: 0x148 */
  __IO uint32_t BKP19R;           /*!< TAMP backup register 19,                         Address offset: 0x14C */
  __IO uint32_t BKP20R;           /*!< TAMP backup register 20,                         Address offset: 0x150 */
  __IO uint32_t BKP21R;           /*!< TAMP backup register 21,                         Address offset: 0x154 */
  __IO uint32_t BKP22R;           /*!< TAMP backup register 22,                         Address offset: 0x158 */
  __IO uint32_t BKP23R;           /*!< TAMP backup register 23,                         Address offset: 0x15C */
  __IO uint32_t BKP24R;           /*!< TAMP backup register 24,                         Address offset: 0x160 */
  __IO uint32_t BKP25R;           /*!< TAMP backup register 25,                         Address offset: 0x164 */
  __IO uint32_t BKP26R;           /*!< TAMP backup register 26,                         Address offset: 0x168 */
  __IO uint32_t BKP27R;           /*!< TAMP backup register 27,                         Address offset: 0x16C */
  __IO uint32_t BKP28R;           /*!< TAMP backup register 28,                         Address offset: 0x170 */
  __IO uint32_t BKP29R;           /*!< TAMP backup register 29,                         Address offset: 0x174 */
  __IO uint32_t BKP30R;           /*!< TAMP backup register 30,                         Address offset: 0x178 */
  __IO uint32_t BKP31R;           /*!< TAMP backup register 31,                         Address offset: 0x17C */
} TAMP_TypeDef;

/**
  * @brief Touch Sensing Controller (TSC)
  */
typedef struct
{
  __IO uint32_t CR;               /*!< TSC control register,                           Address offset: 0x00 */
  __IO uint32_t IER;              /*!< TSC interrupt enable register,                  Address offset: 0x04 */
  __IO uint32_t ICR;              /*!< TSC interrupt clear register,                   Address offset: 0x08 */
  __IO uint32_t ISR;              /*!< TSC interrupt status register,                  Address offset: 0x0C */
  __IO uint32_t IOHCR;            /*!< TSC I/O hysteresis control register,            Address offset: 0x10 */
  uint32_t      RESERVED1;        /*!< Reserved,                                       Address offset: 0x14 */
  __IO uint32_t IOASCR;           /*!< TSC I/O analog switch control register,         Address offset: 0x18 */
  uint32_t      RESERVED2;        /*!< Reserved,                                       Address offset: 0x1C */
  __IO uint32_t IOSCR;            /*!< TSC I/O sampling control register,              Address offset: 0x20 */
  uint32_t      RESERVED3;        /*!< Reserved,                                       Address offset: 0x24 */
  __IO uint32_t IOCCR;            /*!< TSC I/O channel control register,               Address offset: 0x28 */
  uint32_t      RESERVED4;        /*!< Reserved,                                       Address offset: 0x2C */
  __IO uint32_t IOGCSR;           /*!< TSC I/O group control status register,          Address offset: 0x30 */
  __IO uint32_t IOGXCR[7];        /*!< TSC I/O group x counter register,                          0x34-0x4C */
} TSC_TypeDef;

/**
  * @brief TIM
  */
typedef struct
{
  __IO uint32_t CR1;              /*!< TIM control register 1,                   Address offset: 0x00 */
  __IO uint32_t CR2;              /*!< TIM control register 2,                   Address offset: 0x04 */
  __IO uint32_t SMCR;             /*!< TIM slave mode control register,          Address offset: 0x08 */
  __IO uint32_t DIER;             /*!< TIM DMA/interrupt enable register,        Address offset: 0x0C */
  __IO uint32_t SR;               /*!< TIM status register,                      Address offset: 0x10 */
  __IO uint32_t EGR;              /*!< TIM event generation register,            Address offset: 0x14 */
  __IO uint32_t CCMR1;            /*!< TIM capture/compare mode register 1,      Address offset: 0x18 */
  __IO uint32_t CCMR2;            /*!< TIM capture/compare mode register 2,      Address offset: 0x1C */
  __IO uint32_t CCER;             /*!< TIM capture/compare enable register,      Address offset: 0x20 */
  __IO uint32_t CNT;              /*!< TIM counter register,                     Address offset: 0x24 */
  __IO uint32_t PSC;              /*!< TIM prescaler,                            Address offset: 0x28 */
  __IO uint32_t ARR;              /*!< TIM auto-reload register,                 Address offset: 0x2C */
  __IO uint32_t RCR;              /*!< TIM repetition counter register,          Address offset: 0x30 */
  __IO uint32_t CCR1;             /*!< TIM capture/compare register 1,           Address offset: 0x34 */
  __IO uint32_t CCR2;             /*!< TIM capture/compare register 2,           Address offset: 0x38 */
  __IO uint32_t CCR3;             /*!< TIM capture/compare register 3,           Address offset: 0x3C */
  __IO uint32_t CCR4;             /*!< TIM capture/compare register 4,           Address offset: 0x40 */
  __IO uint32_t BDTR;             /*!< TIM break and dead-time register,         Address offset: 0x44 */
  __IO uint32_t CCR5;             /*!< TIM capture/compare register 5,           Address offset: 0x48 */
  __IO uint32_t CCR6;             /*!< TIM capture/compare register 6,           Address offset: 0x4C */
  __IO uint32_t CCMR3;            /*!< TIM capture/compare mode register 3,      Address offset: 0x50 */
  __IO uint32_t DTR2;             /*!< TIM deadtime register 2,                  Address offset: 0x54 */
  __IO uint32_t ECR;              /*!< TIM encoder control register,             Address offset: 0x58 */
  __IO uint32_t TISEL;            /*!< TIM Input Selection register,             Address offset: 0x5C */
  __IO uint32_t AF1;              /*!< TIM alternate function option register 1, Address offset: 0x60 */
  __IO uint32_t AF2;              /*!< TIM alternate function option register 2, Address offset: 0x64 */
  __IO uint32_t OR1 ;             /*!< TIM option register,                      Address offset: 0x68 */
       uint32_t RESERVED0[220];     /*!< Reserved,                               Address offset: 0x6C */
  __IO uint32_t DCR;              /*!< TIM DMA control register,                Address offset: 0x3DC */
  __IO uint32_t DMAR;             /*!< TIM DMA address for full transfer,       Address offset: 0x3E0 */
} TIM_TypeDef;

/**
  * @brief Universal Synchronous Asynchronous Receiver Transmitter
  */
typedef struct
{
  __IO uint32_t CR1;              /*!< USART Control register 1,                 Address offset: 0x00  */
  __IO uint32_t CR2;              /*!< USART Control register 2,                 Address offset: 0x04  */
  __IO uint32_t CR3;              /*!< USART Control register 3,                 Address offset: 0x08  */
  __IO uint32_t BRR;              /*!< USART Baud rate register,                 Address offset: 0x0C  */
  __IO uint32_t GTPR;             /*!< USART Guard time and prescaler register,  Address offset: 0x10  */
  __IO uint32_t RTOR;             /*!< USART Receiver Time Out register,         Address offset: 0x14  */
  __IO uint32_t RQR;              /*!< USART Request register,                   Address offset: 0x18  */
  __IO uint32_t ISR;              /*!< USART Interrupt and status register,      Address offset: 0x1C  */
  __IO uint32_t ICR;              /*!< USART Interrupt flag Clear register,      Address offset: 0x20  */
  __IO uint32_t RDR;              /*!< USART Receive Data register,              Address offset: 0x24  */
  __IO uint32_t TDR;              /*!< USART Transmit Data register,             Address offset: 0x28  */
  __IO uint32_t PRESC;            /*!< USART Prescaler register,                 Address offset: 0x2C  */
  __IO uint32_t AUTOCR;           /*!< USART Autonomous mode control register    Address offset: 0x30  */
} USART_TypeDef;

/**
  * @brief Universal Serial Bus Full Speed Dual Role Device
  */
typedef struct
{
  __IO uint32_t CHEP0R;          /*!< USB Channel/Endpoint 0 register,      Address offset: 0x00 */
  __IO uint32_t CHEP1R;          /*!< USB Channel/Endpoint 1 register,      Address offset: 0x04 */
  __IO uint32_t CHEP2R;          /*!< USB Channel/Endpoint 2 register,      Address offset: 0x08 */
  __IO uint32_t CHEP3R;          /*!< USB Channel/Endpoint 3 register,      Address offset: 0x0C */
  __IO uint32_t CHEP4R;          /*!< USB Channel/Endpoint 4 register,      Address offset: 0x10 */
  __IO uint32_t CHEP5R;          /*!< USB Channel/Endpoint 5 register,      Address offset: 0x14 */
  __IO uint32_t CHEP6R;          /*!< USB Channel/Endpoint 6 register,      Address offset: 0x18 */
  __IO uint32_t CHEP7R;          /*!< USB Channel/Endpoint 7 register,      Address offset: 0x1C */
  __IO uint32_t RESERVED0[8];    /*!< Reserved,                                                  */
  __IO uint32_t CNTR;            /*!< Control register,                     Address offset: 0x40 */
  __IO uint32_t ISTR;            /*!< Interrupt status register,            Address offset: 0x44 */
  __IO uint32_t FNR;             /*!< Frame number register,                Address offset: 0x48 */
  __IO uint32_t DADDR;           /*!< Device address register,              Address offset: 0x4C */
  __IO uint32_t RESERVED1;       /*!< Reserved */
  __IO uint32_t LPMCSR;          /*!< LPM Control and Status register,      Address offset: 0x54 */
  __IO uint32_t BCDR;            /*!< Battery Charging detector register,   Address offset: 0x58 */
} USB_DRD_TypeDef;

/**
  * @brief Universal Serial Bus PacketMemoryArea Buffer Descriptor Table
  */
typedef struct
{
  __IO uint32_t TXBD;             /*!<Transmission buffer address*/
  __IO uint32_t RXBD;             /*!<Reception buffer address */
} USB_DRD_PMABuffDescTypeDef;

/**
  * @brief VREFBUF
  */
typedef struct
{
  __IO uint32_t CSR;              /*!< VREFBUF control and status register,         Address offset: 0x00 */
  __IO uint32_t CCR;              /*!< VREFBUF calibration and control register,    Address offset: 0x04 */
} VREFBUF_TypeDef;

/**
  * @brief WWDG
  */
typedef struct
{
  __IO uint32_t CR;               /*!< WWDG Control register,       Address offset: 0x00 */
  __IO uint32_t CFR;              /*!< WWDG Configuration register, Address offset: 0x04 */
  __IO uint32_t SR;               /*!< WWDG Status register,        Address offset: 0x08 */
} WWDG_TypeDef;

/**
  * @brief OCTO Serial Peripheral Interface
  */
typedef struct
{
  __IO uint32_t CR;               /*!< XSPI Control register,                            Address offset: 0x000 */
  uint32_t RESERVED;              /*!< Reserved,                                         Address offset: 0x004 */
  __IO uint32_t DCR1;             /*!< XSPI Device Configuration register 1,             Address offset: 0x008 */
  __IO uint32_t DCR2;             /*!< XSPI Device Configuration register 2,             Address offset: 0x00C */
  __IO uint32_t DCR3;             /*!< XSPI Device Configuration register 3,             Address offset: 0x010 */
  __IO uint32_t DCR4;             /*!< XSPI Device Configuration register 4,             Address offset: 0x014 */
  uint32_t RESERVED1[2];          /*!< Reserved,                                         Address offset: 0x018-0x01C */
  __IO uint32_t SR;               /*!< XSPI Status register,                             Address offset: 0x020 */
  __IO uint32_t FCR;              /*!< XSPI Flag Clear register,                         Address offset: 0x024 */
  uint32_t RESERVED2[6];          /*!< Reserved,                                         Address offset: 0x028-0x03C */
  __IO uint32_t DLR;              /*!< XSPI Data Length register,                        Address offset: 0x040 */
  uint32_t RESERVED3;             /*!< Reserved,                                         Address offset: 0x044 */
  __IO uint32_t AR;               /*!< XSPI Address register,                            Address offset: 0x048 */
  uint32_t RESERVED4;             /*!< Reserved,                                         Address offset: 0x04C */
  __IO uint32_t DR;               /*!< XSPI Data register,                               Address offset: 0x050 */
  uint32_t RESERVED5[11];         /*!< Reserved,                                         Address offset: 0x054-0x07C */
  __IO uint32_t PSMKR;            /*!< XSPI Polling Status Mask register,                Address offset: 0x080 */
  uint32_t RESERVED6;             /*!< Reserved,                                         Address offset: 0x084 */
  __IO uint32_t PSMAR;            /*!< XSPI Polling Status Match register,               Address offset: 0x088 */
  uint32_t RESERVED7;             /*!< Reserved,                                         Address offset: 0x08C */
  __IO uint32_t PIR;              /*!< XSPI Polling Interval register,                   Address offset: 0x090 */
  uint32_t RESERVED8[27];         /*!< Reserved,                                         Address offset: 0x094-0x0FC */
  __IO uint32_t CCR;              /*!< XSPI Communication Configuration register,        Address offset: 0x100 */
  uint32_t RESERVED9;             /*!< Reserved,                                         Address offset: 0x104 */
  __IO uint32_t TCR;              /*!< XSPI Timing Configuration register,               Address offset: 0x108 */
  uint32_t RESERVED10;            /*!< Reserved,                                         Address offset: 0x10C */
  __IO uint32_t IR;               /*!< XSPI Instruction register,                        Address offset: 0x110 */
  uint32_t RESERVED11[3];         /*!< Reserved,                                         Address offset: 0x114-0x11C */
  __IO uint32_t ABR;              /*!< XSPI Alternate Bytes register,                    Address offset: 0x120 */
  uint32_t RESERVED12[3];         /*!< Reserved,                                         Address offset: 0x124-0x12C */
  __IO uint32_t LPTR;             /*!< XSPI Low Power Timeout register,                  Address offset: 0x130 */
  uint32_t RESERVED13[3];         /*!< Reserved,                                         Address offset: 0x134-0x13C */
  __IO uint32_t WPCCR;            /*!< XSPI Wrap Communication Configuration register,   Address offset: 0x140 */
  uint32_t RESERVED14;            /*!< Reserved,                                         Address offset: 0x144 */
  __IO uint32_t WPTCR;            /*!< XSPI Wrap Timing Configuration register,          Address offset: 0x148 */
  uint32_t RESERVED15;            /*!< Reserved,                                         Address offset: 0x14C */
  __IO uint32_t WPIR;             /*!< XSPI Wrap Instruction register,                   Address offset: 0x150 */
  uint32_t RESERVED16[3];         /*!< Reserved,                                         Address offset: 0x154-0x15C */
  __IO uint32_t WPABR;            /*!< XSPI Wrap Alternate Bytes register,               Address offset: 0x160 */
  uint32_t RESERVED17[7];         /*!< Reserved,                                         Address offset: 0x164-0x17C */
  __IO uint32_t WCCR;             /*!< XSPI Write Communication Configuration register,  Address offset: 0x180 */
  uint32_t RESERVED18;            /*!< Reserved,                                         Address offset: 0x184 */
  __IO uint32_t WTCR;             /*!< XSPI Write Timing Configuration register,         Address offset: 0x188 */
  uint32_t RESERVED19;            /*!< Reserved,                                         Address offset: 0x18C */
  __IO uint32_t WIR;              /*!< XSPI Write Instruction register,                  Address offset: 0x190 */
  uint32_t RESERVED20[3];         /*!< Reserved,                                         Address offset: 0x194-0x19C */
  __IO uint32_t WABR;             /*!< XSPI Write Alternate Bytes register,              Address offset: 0x1A0 */
  uint32_t RESERVED21[23];        /*!< Reserved,                                         Address offset: 0x1A4-0x1FC */
  __IO uint32_t HLCR;             /*!< XSPI Hyperbus Latency Configuration register,     Address offset: 0x200 */
} XSPI_TypeDef;

typedef  XSPI_TypeDef OCTOSPI_TypeDef;

/**
  * @brief Serial Peripheral Interface IO Manager
  */
typedef struct
{
  __IO uint32_t CR;               /*!< OCTOSPIM IO Manager Control register,                 Address offset: 0x00 */
  __IO uint32_t PCR[8];           /*!< OCTOSPIM IO Manager Port[1:8] Configuration register, Address offset: 0x04-0x20 */
} XSPIM_TypeDef;

typedef  XSPIM_TypeDef OCTOSPIM_TypeDef;

/*@}*/ /* end of group STM32U3xx_peripherals */

/* --------  End of section using anonymous unions and disabling warnings  -------- */
#if   defined (__CC_ARM)
  #pragma pop
#elif defined (__ICCARM__)
  /* leave anonymous unions enabled */
#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
  #pragma clang diagnostic pop
#elif defined (__GNUC__)
  /* anonymous unions are enabled by default */
#elif defined (__TMS470__)
  /* anonymous unions are enabled by default */
#elif defined (__TASKING__)
  #pragma warning restore
#elif defined (__CSMC__)
  /* anonymous unions are enabled by default */
#else
  #warning Not supported compiler type
#endif


/* ================================================================================================================== */
/* ================                     Device Specific Peripheral Address Map                       ================ */
/* ================================================================================================================== */
/** @addtogroup STM32U3xx_Peripheral_peripheralAddr
  * @{
  */

/*!< Flash, Peripheral and internal SRAMs base addresses - Non secure */
#define FLASH_BASE_NS                   0x08000000UL  /*!< FLASH non-secure base address        */
#define SYSTEM_FLASH_BASE_NS            0x0BF80000UL  /*!< System FLASH non-secure base address */
#define SRAM1_BASE_NS                   0x20000000UL  /*!< SRAM1 non-secure base address        */
#define SRAM2_BASE_NS                   0x20030000UL  /*!< SRAM2 non-secure base address        */

#define PERIPH_BASE_NS                  0x40000000UL  /*!< Peripheral non-secure base address   */
#define EXTRAM_BASE_NS                  0x90000000UL  /*!< External RAM base address            */
#define EPPB_BASE                       0xE0040000UL  /*!< External Private Peripheral Bus      */

/*!< OTP, Engineering bytes, Option bytes defines */
#define FLASH_OTP_BASE                  (SYSTEM_FLASH_BASE_NS + 0x00020000UL) /*!< FLASH OTP (one-time programmable) base address */
#define FLASH_OTP_SIZE                  0x00000200U                           /*!< 512 bytes OTP (one-time programmable)          */
#define FLASH_ENGY_BASE                 (SYSTEM_FLASH_BASE_NS + 0x00020500UL)
#define PACKAGE_BASE                    (FLASH_ENGY_BASE)                     /*!< Package data register base address     */
#define UID_BASE                        (FLASH_ENGY_BASE + 0x00000200UL)      /*!< Unique device ID register base address */
#define FLASHSIZE_BASE                  (FLASH_ENGY_BASE + 0x000002A0UL)      /*!< Flash size data register base address  */
#define UID64_BASE                      (FLASH_ENGY_BASE + 0x00000500UL)      /*!< 64-bit Unique device Identification    */

/*!< Memory sizes */
/* Internal Flash size */
#define FLASH_SIZE                      ((((*((uint16_t *)FLASHSIZE_BASE)) == 0xFFFFU)) ? 0x100000U : \
                                         ((((*((uint16_t *)FLASHSIZE_BASE)) == 0x0000U)) ? 0x100000U : \
                                           (((uint32_t)(*((uint16_t *)FLASHSIZE_BASE)) & (0xFFFFU)) << 10U)))

/*!< Internal SRAMs size */
#define SRAM1_SIZE                      0x00030000UL  /*!< SRAM1=192k */
#define SRAM2_SIZE                      0x00010000UL  /*!< SRAM2=64k  */

/*!< Peripheral memory map - Non secure */
#define APB1PERIPH_BASE_NS              PERIPH_BASE_NS
#define APB2PERIPH_BASE_NS              (PERIPH_BASE_NS + 0x00010000UL)
#define AHB1PERIPH_BASE_NS              (PERIPH_BASE_NS + 0x00020000UL)
#define APB3PERIPH_BASE_NS              (PERIPH_BASE_NS + 0x00040000UL)
#define AHB2PERIPH_BASE_NS              (PERIPH_BASE_NS + 0x02020000UL)

/*!< APB1 Non secure peripherals */
#define TIM2_BASE_NS                    (APB1PERIPH_BASE_NS + 0x00000000UL)
#define TIM3_BASE_NS                    (APB1PERIPH_BASE_NS + 0x00000400UL)
#define TIM4_BASE_NS                    (APB1PERIPH_BASE_NS + 0x00000800UL)
#define TIM6_BASE_NS                    (APB1PERIPH_BASE_NS + 0x00001000UL)
#define TIM7_BASE_NS                    (APB1PERIPH_BASE_NS + 0x00001400UL)
#define SPI3_BASE_NS                    (APB1PERIPH_BASE_NS + 0x00002000UL)
#define WWDG_BASE_NS                    (APB1PERIPH_BASE_NS + 0x00002C00UL)
#define IWDG_BASE_NS                    (APB1PERIPH_BASE_NS + 0x00003000UL)
#define SPI2_BASE_NS                    (APB1PERIPH_BASE_NS + 0x00003800UL)
#define USART3_BASE_NS                  (APB1PERIPH_BASE_NS + 0x00004800UL)
#define UART4_BASE_NS                   (APB1PERIPH_BASE_NS + 0x00004C00UL)
#define UART5_BASE_NS                   (APB1PERIPH_BASE_NS + 0x00005000UL)
#define I2C1_BASE_NS                    (APB1PERIPH_BASE_NS + 0x00005400UL)
#define I2C2_BASE_NS                    (APB1PERIPH_BASE_NS + 0x00005800UL)
#define I3C1_BASE_NS                    (APB1PERIPH_BASE_NS + 0x00005C00UL)
#define CRS_BASE_NS                     (APB1PERIPH_BASE_NS + 0x00006000UL)
#define OPAMP1_BASE_NS                  (APB1PERIPH_BASE_NS + 0x00007000UL)
#define OPAMP2_BASE_NS                  (OPAMP1_BASE_NS + 0x0000010UL)
#define VREFBUF_BASE_NS                 (APB1PERIPH_BASE_NS + 0x00007400UL)
#define RTC_BASE_NS                     (APB1PERIPH_BASE_NS + 0x00007800UL)
#define TAMP_BASE_NS                    (APB1PERIPH_BASE_NS + 0x00007C00UL)
#define LPTIM2_BASE_NS                  (APB1PERIPH_BASE_NS + 0x00009400UL)
#define FDCAN1_BASE_NS                  (APB1PERIPH_BASE_NS + 0x0000A400UL)
#define FDCAN_CONFIG_BASE_NS            (APB1PERIPH_BASE_NS + 0x0000A500UL)
#define SRAMCAN_BASE_NS                 (APB1PERIPH_BASE_NS + 0x0000AC00UL)

/*!< APB2 Non secure peripherals */
#define TIM1_BASE_NS                    (APB2PERIPH_BASE_NS + 0x00002C00UL)
#define SPI1_BASE_NS                    (APB2PERIPH_BASE_NS + 0x00003000UL)
#define USART1_BASE_NS                  (APB2PERIPH_BASE_NS + 0x00003800UL)
#define TIM15_BASE_NS                   (APB2PERIPH_BASE_NS + 0x00004000UL)
#define TIM16_BASE_NS                   (APB2PERIPH_BASE_NS + 0x00004400UL)
#define TIM17_BASE_NS                   (APB2PERIPH_BASE_NS + 0x00004800UL)
#define SAI1_BASE_NS                    (APB2PERIPH_BASE_NS + 0x00005400UL)
#define SAI1_Block_A_BASE_NS            (SAI1_BASE_NS + 0x0000004UL)
#define SAI1_Block_B_BASE_NS            (SAI1_BASE_NS + 0x0000024UL)
#define USB_DRD_BASE_NS                 (APB2PERIPH_BASE_NS + 0x00006000UL)
#define USB_DRD_PMAADDR_NS              (APB2PERIPH_BASE_NS + 0x00006400UL)
#define I3C2_BASE_NS                    (APB2PERIPH_BASE_NS + 0x00006C00UL)

/*!< AHB1 Non secure peripherals */
#define GPDMA1_BASE_NS                  (AHB1PERIPH_BASE_NS)
#define GPDMA1_Channel0_BASE_NS         (GPDMA1_BASE_NS + 0x00000050UL)
#define GPDMA1_Channel1_BASE_NS         (GPDMA1_BASE_NS + 0x000000D0UL)
#define GPDMA1_Channel2_BASE_NS         (GPDMA1_BASE_NS + 0x00000150UL)
#define GPDMA1_Channel3_BASE_NS         (GPDMA1_BASE_NS + 0x000001D0UL)
#define GPDMA1_Channel4_BASE_NS         (GPDMA1_BASE_NS + 0x00000250UL)
#define GPDMA1_Channel5_BASE_NS         (GPDMA1_BASE_NS + 0x000002D0UL)
#define GPDMA1_Channel6_BASE_NS         (GPDMA1_BASE_NS + 0x00000350UL)
#define GPDMA1_Channel7_BASE_NS         (GPDMA1_BASE_NS + 0x000003D0UL)
#define GPDMA1_Channel8_BASE_NS         (GPDMA1_BASE_NS + 0x00000450UL)
#define GPDMA1_Channel9_BASE_NS         (GPDMA1_BASE_NS + 0x000004D0UL)
#define GPDMA1_Channel10_BASE_NS        (GPDMA1_BASE_NS + 0x00000550UL)
#define GPDMA1_Channel11_BASE_NS        (GPDMA1_BASE_NS + 0x000005D0UL)
#define FLASH_R_BASE_NS                 (AHB1PERIPH_BASE_NS + 0x00002000UL)
#define CRC_BASE_NS                     (AHB1PERIPH_BASE_NS + 0x00003000UL)
#define TSC_BASE_NS                     (AHB1PERIPH_BASE_NS + 0x00004000UL)
#define RAMCFG_BASE_NS                  (AHB1PERIPH_BASE_NS + 0x00006000UL)
#define RAMCFG_SRAM1_BASE_NS            (RAMCFG_BASE_NS)
#define RAMCFG_SRAM2_BASE_NS            (RAMCFG_BASE_NS + 0x00000040UL)
#define ICACHE_BASE_NS                  (AHB1PERIPH_BASE_NS + 0x00010400UL)
#define PWR_BASE_NS                     (AHB1PERIPH_BASE_NS + 0x00010800UL)
#define RCC_BASE_NS                     (AHB1PERIPH_BASE_NS + 0x00010C00UL)
#define EXTI_BASE_NS                    (AHB1PERIPH_BASE_NS + 0x00012000UL)
#define GTZC_TZSC1_BASE_NS              (AHB1PERIPH_BASE_NS + 0x00012400UL)
#define GTZC_MPCBB1_BASE_NS             (AHB1PERIPH_BASE_NS + 0x00012C00UL)
#define GTZC_MPCBB2_BASE_NS             (AHB1PERIPH_BASE_NS + 0x00013000UL)
#define ADF1_BASE_NS                    (AHB1PERIPH_BASE_NS + 0x00014000UL)
#define ADF1_Filter0_BASE_NS            (ADF1_BASE_NS + 0x00000080UL)

/*!< APB3 Non secure peripherals */
#define SYSCFG_BASE_NS                  (APB3PERIPH_BASE_NS + 0x00000400UL)
#define LPUART1_BASE_NS                 (APB3PERIPH_BASE_NS + 0x00002400UL)
#define I2C3_BASE_NS                    (APB3PERIPH_BASE_NS + 0x00002800UL)
#define LPTIM1_BASE_NS                  (APB3PERIPH_BASE_NS + 0x00004400UL)
#define LPTIM3_BASE_NS                  (APB3PERIPH_BASE_NS + 0x00004800UL)
#define LPTIM4_BASE_NS                  (APB3PERIPH_BASE_NS + 0x00004C00UL)
#define COMP1_BASE_NS                   (APB3PERIPH_BASE_NS + 0x00005400UL)
#define COMP2_BASE_NS                   (COMP1_BASE_NS + 0x00000004UL)

/*!< AHB2 Non secure peripherals */
#define GPIOA_BASE_NS                   (AHB2PERIPH_BASE_NS + 0x00000000UL)
#define GPIOB_BASE_NS                   (AHB2PERIPH_BASE_NS + 0x00000400UL)
#define GPIOC_BASE_NS                   (AHB2PERIPH_BASE_NS + 0x00000800UL)
#define GPIOD_BASE_NS                   (AHB2PERIPH_BASE_NS + 0x00000C00UL)
#define GPIOE_BASE_NS                   (AHB2PERIPH_BASE_NS + 0x00001000UL)
#define GPIOG_BASE_NS                   (AHB2PERIPH_BASE_NS + 0x00001800UL)
#define GPIOH_BASE_NS                   (AHB2PERIPH_BASE_NS + 0x00001C00UL)
#define ADC1_BASE_NS                    (AHB2PERIPH_BASE_NS + 0x00008000UL)
#define ADC2_BASE_NS                    (AHB2PERIPH_BASE_NS + 0x00008100UL)
#define ADC12_COMMON_BASE_NS            (AHB2PERIPH_BASE_NS + 0x00008300UL)
#define DAC1_BASE_NS                    (AHB2PERIPH_BASE_NS + 0x00008400UL)
#define AES_BASE_NS                     (AHB2PERIPH_BASE_NS + 0x000A0000UL)
#define HASH_BASE_NS                    (AHB2PERIPH_BASE_NS + 0x000A0400UL)
#define HASH_DIGEST_BASE_NS             (AHB2PERIPH_BASE_NS + 0x000A0710UL)
#define RNG_BASE_NS                     (AHB2PERIPH_BASE_NS + 0x000A0800UL)
#define SAES_BASE_NS                    (AHB2PERIPH_BASE_NS + 0x000A0C00UL)
#define PKA_BASE_NS                     (AHB2PERIPH_BASE_NS + 0x000A2000UL)
#define PKA_RAM_BASE_NS                 (AHB2PERIPH_BASE_NS + 0x000A2400UL)
#define CCB_BASE_NS                     (AHB2PERIPH_BASE_NS + 0x000A7C00UL)
#define SDMMC1_BASE_NS                  (AHB2PERIPH_BASE_NS + 0x000A8000UL)
#define DLYB_SDMMC1_BASE_NS             (AHB2PERIPH_BASE_NS + 0x000A8400UL)
#define DLYB_OCTOSPI1_BASE_NS           (AHB2PERIPH_BASE_NS + 0x000AF000UL)
#define OCTOSPI1_R_BASE_NS              (AHB2PERIPH_BASE_NS + 0x000B1400UL)

#if defined(CPU_IN_SECURE_STATE)
/*!< Flash, Peripheral and internal SRAMs base addresses - secure */
#define FLASH_BASE_S                    0x0C000000UL  /*!< FLASH secure base address        */
#define SYSTEM_FLASH_BASE_S             0x0FF80000UL  /*!< System FLASH secure base address */
#define SRAM1_BASE_S                    0x30000000UL  /*!< SRAM1 secure base address        */
#define SRAM2_BASE_S                    0x30030000UL  /*!< SRAM2 secure base address        */
#define PERIPH_BASE_S                   0x50000000UL  /*!< Peripheral secure base address   */

/*!< Peripheral memory map - secure */
#define APB1PERIPH_BASE_S               PERIPH_BASE_S
#define APB2PERIPH_BASE_S               (PERIPH_BASE_S + 0x00010000UL)
#define AHB1PERIPH_BASE_S               (PERIPH_BASE_S + 0x00020000UL)
#define APB3PERIPH_BASE_S               (PERIPH_BASE_S + 0x00040000UL)
#define AHB2PERIPH_BASE_S               (PERIPH_BASE_S + 0x02020000UL)

/*!< APB1 secure peripherals */
#define TIM2_BASE_S                     (APB1PERIPH_BASE_S + 0x00000000UL)
#define TIM3_BASE_S                     (APB1PERIPH_BASE_S + 0x00000400UL)
#define TIM4_BASE_S                     (APB1PERIPH_BASE_S + 0x00000800UL)
#define TIM6_BASE_S                     (APB1PERIPH_BASE_S + 0x00001000UL)
#define TIM7_BASE_S                     (APB1PERIPH_BASE_S + 0x00001400UL)
#define SPI3_BASE_S                     (APB1PERIPH_BASE_S + 0x00002000UL)
#define WWDG_BASE_S                     (APB1PERIPH_BASE_S + 0x00002C00UL)
#define IWDG_BASE_S                     (APB1PERIPH_BASE_S + 0x00003000UL)
#define SPI2_BASE_S                     (APB1PERIPH_BASE_S + 0x00003800UL)
#define USART3_BASE_S                   (APB1PERIPH_BASE_S + 0x00004800UL)
#define UART4_BASE_S                    (APB1PERIPH_BASE_S + 0x00004C00UL)
#define UART5_BASE_S                    (APB1PERIPH_BASE_S + 0x00005000UL)
#define I2C1_BASE_S                     (APB1PERIPH_BASE_S + 0x00005400UL)
#define I2C2_BASE_S                     (APB1PERIPH_BASE_S + 0x00005800UL)
#define I3C1_BASE_S                     (APB1PERIPH_BASE_S + 0x00005C00UL)
#define CRS_BASE_S                      (APB1PERIPH_BASE_S + 0x00006000UL)
#define OPAMP1_BASE_S                   (APB1PERIPH_BASE_S + 0x00007000UL)
#define OPAMP2_BASE_S                   (OPAMP1_BASE_S + 0x0000010UL)
#define VREFBUF_BASE_S                  (APB1PERIPH_BASE_S + 0x00007400UL)
#define RTC_BASE_S                      (APB1PERIPH_BASE_S + 0x00007800UL)
#define TAMP_BASE_S                     (APB1PERIPH_BASE_S + 0x00007C00UL)
#define LPTIM2_BASE_S                   (APB1PERIPH_BASE_S + 0x00009400UL)
#define FDCAN1_BASE_S                   (APB1PERIPH_BASE_S + 0x0000A400UL)
#define FDCAN_CONFIG_BASE_S             (APB1PERIPH_BASE_S + 0x0000A500UL)
#define SRAMCAN_BASE_S                  (APB1PERIPH_BASE_S + 0x0000AC00UL)

/*!< APB2 secure peripherals */
#define TIM1_BASE_S                     (APB2PERIPH_BASE_S + 0x00002C00UL)
#define SPI1_BASE_S                     (APB2PERIPH_BASE_S + 0x00003000UL)
#define USART1_BASE_S                   (APB2PERIPH_BASE_S + 0x00003800UL)
#define TIM15_BASE_S                    (APB2PERIPH_BASE_S + 0x00004000UL)
#define TIM16_BASE_S                    (APB2PERIPH_BASE_S + 0x00004400UL)
#define TIM17_BASE_S                    (APB2PERIPH_BASE_S + 0x00004800UL)
#define SAI1_BASE_S                     (APB2PERIPH_BASE_S + 0x00005400UL)
#define SAI1_Block_A_BASE_S             (SAI1_BASE_S + 0x0000004UL)
#define SAI1_Block_B_BASE_S             (SAI1_BASE_S + 0x0000024UL)
#define USB_DRD_BASE_S                  (APB2PERIPH_BASE_S + 0x00006000UL)
#define USB_DRD_PMAADDR_S               (APB2PERIPH_BASE_S + 0x00006400UL)
#define I3C2_BASE_S                     (APB2PERIPH_BASE_S + 0x00006C00UL)

/*!< AHB1 secure peripherals */
#define GPDMA1_BASE_S                   (AHB1PERIPH_BASE_S)
#define GPDMA1_Channel0_BASE_S          (GPDMA1_BASE_S + 0x00000050UL)
#define GPDMA1_Channel1_BASE_S          (GPDMA1_BASE_S + 0x000000D0UL)
#define GPDMA1_Channel2_BASE_S          (GPDMA1_BASE_S + 0x00000150UL)
#define GPDMA1_Channel3_BASE_S          (GPDMA1_BASE_S + 0x000001D0UL)
#define GPDMA1_Channel4_BASE_S          (GPDMA1_BASE_S + 0x00000250UL)
#define GPDMA1_Channel5_BASE_S          (GPDMA1_BASE_S + 0x000002D0UL)
#define GPDMA1_Channel6_BASE_S          (GPDMA1_BASE_S + 0x00000350UL)
#define GPDMA1_Channel7_BASE_S          (GPDMA1_BASE_S + 0x000003D0UL)
#define GPDMA1_Channel8_BASE_S          (GPDMA1_BASE_S + 0x00000450UL)
#define GPDMA1_Channel9_BASE_S          (GPDMA1_BASE_S + 0x000004D0UL)
#define GPDMA1_Channel10_BASE_S         (GPDMA1_BASE_S + 0x00000550UL)
#define GPDMA1_Channel11_BASE_S         (GPDMA1_BASE_S + 0x000005D0UL)
#define FLASH_R_BASE_S                  (AHB1PERIPH_BASE_S + 0x00002000UL)
#define CRC_BASE_S                      (AHB1PERIPH_BASE_S + 0x00003000UL)
#define TSC_BASE_S                      (AHB1PERIPH_BASE_S + 0x00004000UL)
#define RAMCFG_BASE_S                   (AHB1PERIPH_BASE_S + 0x00006000UL)
#define RAMCFG_SRAM1_BASE_S             (RAMCFG_BASE_S)
#define RAMCFG_SRAM2_BASE_S             (RAMCFG_BASE_S + 0x00000040UL)
#define ICACHE_BASE_S                   (AHB1PERIPH_BASE_S + 0x00010400UL)
#define PWR_BASE_S                      (AHB1PERIPH_BASE_S + 0x00010800UL)
#define RCC_BASE_S                      (AHB1PERIPH_BASE_S + 0x00010C00UL)
#define EXTI_BASE_S                     (AHB1PERIPH_BASE_S + 0x00012000UL)
#define GTZC_TZSC1_BASE_S               (AHB1PERIPH_BASE_S + 0x00012400UL)
#define GTZC_TZIC1_BASE_S               (AHB1PERIPH_BASE_S + 0x00012800UL)
#define GTZC_MPCBB1_BASE_S              (AHB1PERIPH_BASE_S + 0x00012C00UL)
#define GTZC_MPCBB2_BASE_S              (AHB1PERIPH_BASE_S + 0x00013000UL)
#define ADF1_BASE_S                     (AHB1PERIPH_BASE_S + 0x00014000UL)
#define ADF1_Filter0_BASE_S             (ADF1_BASE_S + 0x00000080UL)

/*!< APB3 secure peripherals */
#define SYSCFG_BASE_S                   (APB3PERIPH_BASE_S + 0x00000400UL)
#define LPUART1_BASE_S                  (APB3PERIPH_BASE_S + 0x00002400UL)
#define I2C3_BASE_S                     (APB3PERIPH_BASE_S + 0x00002800UL)
#define LPTIM1_BASE_S                   (APB3PERIPH_BASE_S + 0x00004400UL)
#define LPTIM3_BASE_S                   (APB3PERIPH_BASE_S + 0x00004800UL)
#define LPTIM4_BASE_S                   (APB3PERIPH_BASE_S + 0x00004C00UL)
#define COMP1_BASE_S                    (APB3PERIPH_BASE_S + 0x00005400UL)
#define COMP2_BASE_S                    (COMP1_BASE_S + 0x00000004UL)

/*!< AHB2 secure peripherals */
#define GPIOA_BASE_S                    (AHB2PERIPH_BASE_S + 0x00000000UL)
#define GPIOB_BASE_S                    (AHB2PERIPH_BASE_S + 0x00000400UL)
#define GPIOC_BASE_S                    (AHB2PERIPH_BASE_S + 0x00000800UL)
#define GPIOD_BASE_S                    (AHB2PERIPH_BASE_S + 0x00000C00UL)
#define GPIOE_BASE_S                    (AHB2PERIPH_BASE_S + 0x00001000UL)
#define GPIOG_BASE_S                    (AHB2PERIPH_BASE_S + 0x00001800UL)
#define GPIOH_BASE_S                    (AHB2PERIPH_BASE_S + 0x00001C00UL)
#define ADC1_BASE_S                     (AHB2PERIPH_BASE_S + 0x00008000UL)
#define ADC2_BASE_S                     (AHB2PERIPH_BASE_S + 0x00008100UL)
#define ADC12_COMMON_BASE_S             (AHB2PERIPH_BASE_S + 0x00008300UL)
#define DAC1_BASE_S                     (AHB2PERIPH_BASE_S + 0x00008400UL)
#define AES_BASE_S                      (AHB2PERIPH_BASE_S + 0x000A0000UL)
#define HASH_BASE_S                     (AHB2PERIPH_BASE_S + 0x000A0400UL)
#define HASH_DIGEST_BASE_S              (AHB2PERIPH_BASE_S + 0x000A0710UL)
#define RNG_BASE_S                      (AHB2PERIPH_BASE_S + 0x000A0800UL)
#define SAES_BASE_S                     (AHB2PERIPH_BASE_S + 0x000A0C00UL)
#define PKA_BASE_S                      (AHB2PERIPH_BASE_S + 0x000A2000UL)
#define PKA_RAM_BASE_S                  (AHB2PERIPH_BASE_S + 0x000A2400UL)
#define CCB_BASE_S                      (AHB2PERIPH_BASE_S + 0x000A7C00UL)
#define SDMMC1_BASE_S                   (AHB2PERIPH_BASE_S + 0x000A8000UL)
#define DLYB_SDMMC1_BASE_S              (AHB2PERIPH_BASE_S + 0x000A8400UL)
#define DLYB_OCTOSPI1_BASE_S            (AHB2PERIPH_BASE_S + 0x000AF000UL)
#define OCTOSPI1_R_BASE_S               (AHB2PERIPH_BASE_S + 0x000B1400UL)
#endif /* CPU_IN_SECURE_STATE */

/*!< External memories base addresses - Not aliased */
#define OCTOSPI1_BASE                   EXTRAM_BASE_NS

/*!< DBGMCU base addresses - Not aliased */
#define DBGMCU_BASE                     (EPPB_BASE + 0x00004000UL)

/*!< USB PMA SIZE */
#define USB_DRD_PMA_SIZE        (2048U)         /*!< USB PMA Size 2Kbyte */

/*!< Root Secure Service Library */
/************ RSSLIB SAU system Flash region definition constants *************/
#define RSSLIB_SYS_FLASH_NS_PFUNC_START 0x0BF99040UL
#define RSSLIB_SYS_FLASH_NS_PFUNC_END   0x0BF990FFUL

/************ RSSLIB function return constants ********************************/
#define RSSLIB_ERROR                    0xF5F5F5F5UL
#define RSSLIB_SUCCESS                  0xEAEAEAEAUL

/*!< RSSLIB  pointer function structure address definition */
#define RSSLIB_PFUNC_BASE               RSSLIB_SYS_FLASH_NS_PFUNC_START
#define RSSLIB_PFUNC                    ((RSSLIB_pFunc_TypeDef *)RSSLIB_PFUNC_BASE)

/*!< HDP Area constant definition */
#define RSSLIB_HDP_AREA_Pos             0UL
#define RSSLIB_HDP_AREA_Msk             (0x3UL << RSSLIB_HDP_AREA_Pos )
#define RSSLIB_HDP_AREA1_Pos            0UL
#define RSSLIB_HDP_AREA1_Msk            (0x1UL << RSSLIB_HDP_AREA1_Pos )
#define RSSLIB_HDP_AREA2_Pos            1UL
#define RSSLIB_HDP_AREA2_Msk            (0x1UL << RSSLIB_HDP_AREA2_Pos )
#define RSSLIB_HDPEXT_CLOSE_BOUNDARY_OPEN 0xC9C9C9C9UL  /* Access to HDPx extension area and HDPx area denied but HDPx_EXT (in FLASH_HDPEXTR) increment allowed at any time */
#define RSSLIB_HDPEXT_CLOSE_BOUNDARY_LOCK 0xD6D6D6D6UL  /* Access to HDPx extension area and HDPx area denied. Update of HDPx_EXT size is not possible anymore */

/**
  * @brief  Prototype of RSSLIB Close and exit HDP Function
  * @detail This function close the requested hdp area passed in input
  *         parameter and jump to the reset handler present within the
  *         Vector table. The function does not return on successful execution.
  * @param  HdpArea notifies which hdp area to close, can be a combination of
  *         hdpa area 1 and hdp area 2
  * @param  VectorTableAddr pointer on the vector table containing the reset handler the function
  *         jumps to.
  * @retval RSSLIB_RSS_ERROR on error on input parameter, otherwise does not return.
  */
typedef uint32_t ( *RSSLIB_S_CloseExitHDP_TypeDef)( uint32_t HdpArea, uint32_t VectorTableAddr );

/**
  * @brief  Prototype of RSSLIB Close and exit HDP extension Function
  * @detail This function close the requested hdp extension area passed in input
  *         parameter and jump to the reset handler present within the
  *         Vector table. The function does not return on successful execution.
  * @param  HdpExtArea notifies which hdp extension area to close, can be a combination of
  *         hdp extension area 1 and hdp extension area 2
  * @param  VectorTableAddr pointer on the vector table containing the reset handler the function
  *         jumps to.
  * @param  CloseBound notifies if the HDP extension area should be closed with
  *         HDPx_EXT increment allowed or not
  * @retval RSSLIB_RSS_ERROR on error on input parameter, otherwise does not return.
  */
typedef uint32_t ( *RSSLIB_S_CloseExitHDPExt_TypeDef)( uint32_t HdpExtArea, uint32_t VectorTableAddr, uint32_t CloseBound );


/**
  * @brief RSSLib non-secure callable function pointer structure
  */
typedef struct
{
  __IM uint32_t Reserved[8];
}NSC_pFuncTypeDef;

/**
  * @brief RSSLib secure callable function pointer structure
  */
typedef struct
{
  __IM uint32_t Reserved2[2];
  __IM RSSLIB_S_CloseExitHDP_TypeDef CloseExitHDP;        /*!< RSSLIB Bootloader Close and exit HDP           Address offset: 0x28 */
  __IM RSSLIB_S_CloseExitHDPExt_TypeDef CloseExitHDPExt;  /*!< RSSLIB Bootloader Close and exit HDP extension Address offset: 0x2C */
}S_pFuncTypeDef;

/**
  * @brief RSSLib function pointer structure
  */
typedef struct
{
  NSC_pFuncTypeDef NSC;
  S_pFuncTypeDef S;
}RSSLIB_pFunc_TypeDef;

/*
 * Certificate address description
 */
#define CERT_CHIP_PACK1_ADDR (0x0BF9FE00U)
#define CERT_CHIP_PACK1_SIZE (0x200U)
#define CERT_CHIP_PACK2_ADDR (0x0BF9FC00U)
#define CERT_CHIP_PACK2_SIZE (0x200U)

#define CERT_CHIP_PACK_ADDR (CERT_CHIP_PACK2_ADDR)
#define CERT_CHIP_PACK_SIZE (CERT_CHIP_PACK1_SIZE + CERT_CHIP_PACK2_SIZE)

#define CERT_ST_DUA_USER_FU_PUB_KEY_OFFSET  (12U)
#define CERT_ST_DUA_USER_FU_PUB_KEY_ADDR    (CERT_CHIP_PACK2_ADDR + CERT_ST_DUA_USER_FU_PUB_KEY_OFFSET)
#define CERT_ST_DUA_USER_FU_SIGN_OFFSET     (76U)
#define CERT_ST_DUA_USER_FU_SIGN_ADDR       (CERT_CHIP_PACK2_ADDR + CERT_ST_DUA_USER_FU_SIGN_OFFSET)
#define CERT_ST_DUA_USER_FU_SERIAL_OFFSET   (140U)
#define CERT_ST_DUA_USER_FU_SERIAL_ADDR     (CERT_CHIP_PACK2_ADDR + CERT_ST_DUA_USER_FU_SERIAL_OFFSET)

#define CERT_ST_DUA_USER_LU_PUB_KEY_OFFSET  (162U)
#define CERT_ST_DUA_USER_LU_PUB_KEY_ADDR    (CERT_CHIP_PACK2_ADDR + CERT_ST_DUA_USER_LU_PUB_KEY_OFFSET)
#define CERT_ST_DUA_USER_LU_SIGN_OFFSET     (226U)
#define CERT_ST_DUA_USER_LU_SIGN_ADDR       (CERT_CHIP_PACK2_ADDR + CERT_ST_DUA_USER_LU_SIGN_OFFSET)
#define CERT_ST_DUA_USER_LU_SERIAL_OFFSET   (290U)
#define CERT_ST_DUA_USER_LU_SERIAL_ADDR     (CERT_CHIP_PACK2_ADDR + CERT_ST_DUA_USER_LU_SERIAL_OFFSET)
/** @} */ /* End of group STM32U3xx_Peripheral_peripheralAddr */


/* ================================================================================================================== */
/* ================                     Peripheral declaration                                       ================ */
/* ================================================================================================================== */
/** @addtogroup STM32U3xx_Peripheral_declaration
  * @{
  */
#define ADC12_COMMON_NS                 ((ADC_Common_TypeDef *) ADC12_COMMON_BASE_NS)
#define ADC1_NS                         ((ADC_TypeDef *) ADC1_BASE_NS)
#define ADC2_NS                         ((ADC_TypeDef *) ADC2_BASE_NS)
#define ADF1_NS                         ((MDF_TypeDef *) ADF1_BASE_NS)
#define ADF1_Filter0_NS                 ((MDF_Filter_TypeDef*) ADF1_Filter0_BASE_NS)
#define AES_NS                          ((AES_TypeDef *) AES_BASE_NS)
#define CCB_NS                          ((CCB_TypeDef *) CCB_BASE_NS)
#define COMP1_NS                        ((COMP_TypeDef *) COMP1_BASE_NS)
#define COMP2_NS                        ((COMP_TypeDef *) COMP2_BASE_NS)
#define COMP12_COMMON_NS                ((COMP_Common_TypeDef *) COMP1_BASE_NS)
#define CRC_NS                          ((CRC_TypeDef *) CRC_BASE_NS)
#define CRS_NS                          ((CRS_TypeDef *) CRS_BASE_NS)
#define DAC1_NS                         ((DAC_TypeDef *) DAC1_BASE_NS)
#define DLYB_SDMMC1_NS                  ((DLYB_TypeDef *) DLYB_SDMMC1_BASE_NS)
#define DLYB_OCTOSPI1_NS                ((DLYB_TypeDef *) DLYB_OCTOSPI1_BASE_NS)
#define EXTI_NS                         ((EXTI_TypeDef *) EXTI_BASE_NS)
#define FDCAN1_NS                       ((FDCAN_GlobalTypeDef *) FDCAN1_BASE_NS)
#define FDCAN_CONFIG_NS                 ((FDCAN_Config_TypeDef *) FDCAN_CONFIG_BASE_NS)
#define FLASH_NS                        ((FLASH_TypeDef *) FLASH_R_BASE_NS)
#define GPDMA1_NS                       ((DMA_TypeDef *) GPDMA1_BASE_NS)
#define GPDMA1_Channel0_NS              ((DMA_Channel_TypeDef *) GPDMA1_Channel0_BASE_NS)
#define GPDMA1_Channel1_NS              ((DMA_Channel_TypeDef *) GPDMA1_Channel1_BASE_NS)
#define GPDMA1_Channel2_NS              ((DMA_Channel_TypeDef *) GPDMA1_Channel2_BASE_NS)
#define GPDMA1_Channel3_NS              ((DMA_Channel_TypeDef *) GPDMA1_Channel3_BASE_NS)
#define GPDMA1_Channel4_NS              ((DMA_Channel_TypeDef *) GPDMA1_Channel4_BASE_NS)
#define GPDMA1_Channel5_NS              ((DMA_Channel_TypeDef *) GPDMA1_Channel5_BASE_NS)
#define GPDMA1_Channel6_NS              ((DMA_Channel_TypeDef *) GPDMA1_Channel6_BASE_NS)
#define GPDMA1_Channel7_NS              ((DMA_Channel_TypeDef *) GPDMA1_Channel7_BASE_NS)
#define GPDMA1_Channel8_NS              ((DMA_Channel_TypeDef *) GPDMA1_Channel8_BASE_NS)
#define GPDMA1_Channel9_NS              ((DMA_Channel_TypeDef *) GPDMA1_Channel9_BASE_NS)
#define GPDMA1_Channel10_NS             ((DMA_Channel_TypeDef *) GPDMA1_Channel10_BASE_NS)
#define GPDMA1_Channel11_NS             ((DMA_Channel_TypeDef *) GPDMA1_Channel11_BASE_NS)
#define GPIOA_NS                        ((GPIO_TypeDef *) GPIOA_BASE_NS)
#define GPIOB_NS                        ((GPIO_TypeDef *) GPIOB_BASE_NS)
#define GPIOC_NS                        ((GPIO_TypeDef *) GPIOC_BASE_NS)
#define GPIOD_NS                        ((GPIO_TypeDef *) GPIOD_BASE_NS)
#define GPIOE_NS                        ((GPIO_TypeDef *) GPIOE_BASE_NS)
#define GPIOG_NS                        ((GPIO_TypeDef *) GPIOG_BASE_NS)
#define GPIOH_NS                        ((GPIO_TypeDef *) GPIOH_BASE_NS)
#define GTZC_MPCBB1_NS                  ((GTZC_MPCBB_TypeDef *) GTZC_MPCBB1_BASE_NS)
#define GTZC_MPCBB2_NS                  ((GTZC_MPCBB_TypeDef *) GTZC_MPCBB2_BASE_NS)
#define GTZC_TZSC1_NS                   ((GTZC_TZSC_TypeDef *) GTZC_TZSC1_BASE_NS)
#define HASH_NS                         ((HASH_TypeDef *) HASH_BASE_NS)
#define HASH_DIGEST_NS                  ((HASH_DIGEST_TypeDef *) HASH_DIGEST_BASE_NS)
#define I2C1_NS                         ((I2C_TypeDef *) I2C1_BASE_NS)
#define I2C2_NS                         ((I2C_TypeDef *) I2C2_BASE_NS)
#define I2C3_NS                         ((I2C_TypeDef *) I2C3_BASE_NS)
#define I3C1_NS                         ((I3C_TypeDef *) I3C1_BASE_NS)
#define I3C2_NS                         ((I3C_TypeDef *) I3C2_BASE_NS)
#define ICACHE_NS                       ((ICACHE_TypeDef *) ICACHE_BASE_NS)
#define IWDG_NS                         ((IWDG_TypeDef *) IWDG_BASE_NS)
#define LPTIM1_NS                       ((LPTIM_TypeDef *) LPTIM1_BASE_NS)
#define LPTIM2_NS                       ((LPTIM_TypeDef *) LPTIM2_BASE_NS)
#define LPTIM3_NS                       ((LPTIM_TypeDef *) LPTIM3_BASE_NS)
#define LPTIM4_NS                       ((LPTIM_TypeDef *) LPTIM4_BASE_NS)
#define LPUART1_NS                      ((USART_TypeDef *) LPUART1_BASE_NS)
#define OCTOSPI1_NS                     ((OCTOSPI_TypeDef *) OCTOSPI1_R_BASE_NS)
#define OPAMP1_NS                       ((OPAMP_TypeDef *) OPAMP1_BASE_NS)
#define OPAMP2_NS                       ((OPAMP_TypeDef *) OPAMP2_BASE_NS)
#define OPAMP12_COMMON_NS               ((OPAMP_Common_TypeDef *) OPAMP1_BASE_NS)
#define PKA_NS                          ((PKA_TypeDef *) PKA_BASE_NS)
#define PWR_NS                          ((PWR_TypeDef *) PWR_BASE_NS)
#define RAMCFG_SRAM1_NS                 ((RAMCFG_TypeDef *) RAMCFG_SRAM1_BASE_NS)
#define RAMCFG_SRAM2_NS                 ((RAMCFG_TypeDef *) RAMCFG_SRAM2_BASE_NS)
#define RCC_NS                          ((RCC_TypeDef *) RCC_BASE_NS)
#define RNG_NS                          ((RNG_TypeDef *) RNG_BASE_NS)
#define RTC_NS                          ((RTC_TypeDef *) RTC_BASE_NS)
#define SAES_NS                         ((AES_TypeDef *) SAES_BASE_NS)
#define SAI1_NS                         ((SAI_TypeDef *) SAI1_BASE_NS)
#define SAI1_Block_A_NS                 ((SAI_Block_TypeDef *)SAI1_Block_A_BASE_NS)
#define SAI1_Block_B_NS                 ((SAI_Block_TypeDef *)SAI1_Block_B_BASE_NS)
#define SDMMC1_NS                       ((SDMMC_TypeDef *) SDMMC1_BASE_NS)
#define SPI1_NS                         ((SPI_TypeDef *) SPI1_BASE_NS)
#define SPI2_NS                         ((SPI_TypeDef *) SPI2_BASE_NS)
#define SPI3_NS                         ((SPI_TypeDef *) SPI3_BASE_NS)
#define SYSCFG_NS                       ((SYSCFG_TypeDef *) SYSCFG_BASE_NS)
#define TAMP_NS                         ((TAMP_TypeDef *) TAMP_BASE_NS)
#define TIM1_NS                         ((TIM_TypeDef *) TIM1_BASE_NS)
#define TIM2_NS                         ((TIM_TypeDef *) TIM2_BASE_NS)
#define TIM3_NS                         ((TIM_TypeDef *) TIM3_BASE_NS)
#define TIM4_NS                         ((TIM_TypeDef *) TIM4_BASE_NS)
#define TIM6_NS                         ((TIM_TypeDef *) TIM6_BASE_NS)
#define TIM7_NS                         ((TIM_TypeDef *) TIM7_BASE_NS)
#define TIM15_NS                        ((TIM_TypeDef *) TIM15_BASE_NS)
#define TIM16_NS                        ((TIM_TypeDef *) TIM16_BASE_NS)
#define TIM17_NS                        ((TIM_TypeDef *) TIM17_BASE_NS)
#define TSC_NS                          ((TSC_TypeDef *) TSC_BASE_NS)
#define UART4_NS                        ((USART_TypeDef *) UART4_BASE_NS)
#define UART5_NS                        ((USART_TypeDef *) UART5_BASE_NS)
#define USART1_NS                       ((USART_TypeDef *) USART1_BASE_NS)
#define USART3_NS                       ((USART_TypeDef *) USART3_BASE_NS)
#define USB_DRD_FS_NS                   ((USB_DRD_TypeDef *) USB_DRD_BASE_NS)
#define USB_DRD_PMA_BUFF_NS             ((USB_DRD_PMABuffDescTypeDef *) USB_DRD_PMAADDR_NS)
#define VREFBUF_NS                      ((VREFBUF_TypeDef *) VREFBUF_BASE_NS)
#define WWDG_NS                         ((WWDG_TypeDef *) WWDG_BASE_NS)

/*!< DBGMCU peripheral */
#define DBGMCU                          ((DBGMCU_TypeDef *) DBGMCU_BASE)

#if defined (CPU_IN_SECURE_STATE)
#define ADC12_COMMON_S                  ((ADC_Common_TypeDef *) ADC12_COMMON_BASE_S)
#define ADC1_S                          ((ADC_TypeDef *) ADC1_BASE_S)
#define ADC2_S                          ((ADC_TypeDef *) ADC2_BASE_S)
#define ADF1_S                          ((MDF_TypeDef *) ADF1_BASE_S)
#define ADF1_Filter0_S                  ((MDF_Filter_TypeDef*) ADF1_Filter0_BASE_S)
#define AES_S                           ((AES_TypeDef *) AES_BASE_S)
#define CCB_S                           ((CCB_TypeDef *) CCB_BASE_S)
#define COMP1_S                         ((COMP_TypeDef *) COMP1_BASE_S)
#define COMP2_S                         ((COMP_TypeDef *) COMP2_BASE_S)
#define COMP12_COMMON_S                 ((COMP_Common_TypeDef *) COMP1_BASE_S)
#define CRC_S                           ((CRC_TypeDef *) CRC_BASE_S)
#define CRS_S                           ((CRS_TypeDef *) CRS_BASE_S)
#define DAC1_S                          ((DAC_TypeDef *) DAC1_BASE_S)
#define DLYB_SDMMC1_S                   ((DLYB_TypeDef *) DLYB_SDMMC1_BASE_S)
#define DLYB_OCTOSPI1_S                 ((DLYB_TypeDef *) DLYB_OCTOSPI1_BASE_S)
#define EXTI_S                          ((EXTI_TypeDef *) EXTI_BASE_S)
#define FDCAN1_S                        ((FDCAN_GlobalTypeDef *) FDCAN1_BASE_S)
#define FDCAN_CONFIG_S                  ((FDCAN_Config_TypeDef *) FDCAN_CONFIG_BASE_S)
#define FLASH_S                         ((FLASH_TypeDef *) FLASH_R_BASE_S)
#define GPDMA1_S                        ((DMA_TypeDef *) GPDMA1_BASE_S)
#define GPDMA1_Channel0_S               ((DMA_Channel_TypeDef *) GPDMA1_Channel0_BASE_S)
#define GPDMA1_Channel1_S               ((DMA_Channel_TypeDef *) GPDMA1_Channel1_BASE_S)
#define GPDMA1_Channel2_S               ((DMA_Channel_TypeDef *) GPDMA1_Channel2_BASE_S)
#define GPDMA1_Channel3_S               ((DMA_Channel_TypeDef *) GPDMA1_Channel3_BASE_S)
#define GPDMA1_Channel4_S               ((DMA_Channel_TypeDef *) GPDMA1_Channel4_BASE_S)
#define GPDMA1_Channel5_S               ((DMA_Channel_TypeDef *) GPDMA1_Channel5_BASE_S)
#define GPDMA1_Channel6_S               ((DMA_Channel_TypeDef *) GPDMA1_Channel6_BASE_S)
#define GPDMA1_Channel7_S               ((DMA_Channel_TypeDef *) GPDMA1_Channel7_BASE_S)
#define GPDMA1_Channel8_S               ((DMA_Channel_TypeDef *) GPDMA1_Channel8_BASE_S)
#define GPDMA1_Channel9_S               ((DMA_Channel_TypeDef *) GPDMA1_Channel9_BASE_S)
#define GPDMA1_Channel10_S              ((DMA_Channel_TypeDef *) GPDMA1_Channel10_BASE_S)
#define GPDMA1_Channel11_S              ((DMA_Channel_TypeDef *) GPDMA1_Channel11_BASE_S)
#define GPIOA_S                         ((GPIO_TypeDef *) GPIOA_BASE_S)
#define GPIOB_S                         ((GPIO_TypeDef *) GPIOB_BASE_S)
#define GPIOC_S                         ((GPIO_TypeDef *) GPIOC_BASE_S)
#define GPIOD_S                         ((GPIO_TypeDef *) GPIOD_BASE_S)
#define GPIOE_S                         ((GPIO_TypeDef *) GPIOE_BASE_S)
#define GPIOG_S                         ((GPIO_TypeDef *) GPIOG_BASE_S)
#define GPIOH_S                         ((GPIO_TypeDef *) GPIOH_BASE_S)
#define GTZC_TZSC1_S                    ((GTZC_TZSC_TypeDef *) GTZC_TZSC1_BASE_S)
#define GTZC_TZIC1_S                    ((GTZC_TZIC_TypeDef *) GTZC_TZIC1_BASE_S)
#define GTZC_MPCBB1_S                   ((GTZC_MPCBB_TypeDef *) GTZC_MPCBB1_BASE_S)
#define GTZC_MPCBB2_S                   ((GTZC_MPCBB_TypeDef *) GTZC_MPCBB2_BASE_S)
#define HASH_S                          ((HASH_TypeDef *) HASH_BASE_S)
#define HASH_DIGEST_S                   ((HASH_DIGEST_TypeDef *) HASH_DIGEST_BASE_S)
#define I2C1_S                          ((I2C_TypeDef *) I2C1_BASE_S)
#define I2C2_S                          ((I2C_TypeDef *) I2C2_BASE_S)
#define I2C3_S                          ((I2C_TypeDef *) I2C3_BASE_S)
#define I3C1_S                          ((I3C_TypeDef *) I3C1_BASE_S)
#define I3C2_S                          ((I3C_TypeDef *) I3C2_BASE_S)
#define ICACHE_S                        ((ICACHE_TypeDef *) ICACHE_BASE_S)
#define IWDG_S                          ((IWDG_TypeDef *) IWDG_BASE_S)
#define LPTIM1_S                        ((LPTIM_TypeDef *) LPTIM1_BASE_S)
#define LPTIM2_S                        ((LPTIM_TypeDef *) LPTIM2_BASE_S)
#define LPTIM3_S                        ((LPTIM_TypeDef *) LPTIM3_BASE_S)
#define LPTIM4_S                        ((LPTIM_TypeDef *) LPTIM4_BASE_S)
#define LPUART1_S                       ((USART_TypeDef *) LPUART1_BASE_S)
#define OCTOSPI1_S                      ((OCTOSPI_TypeDef *) OCTOSPI1_R_BASE_S)
#define OPAMP1_S                        ((OPAMP_TypeDef *) OPAMP1_BASE_S)
#define OPAMP2_S                        ((OPAMP_TypeDef *) OPAMP2_BASE_S)
#define OPAMP12_COMMON_S                ((OPAMP_Common_TypeDef *) OPAMP1_BASE_S)
#define PKA_S                           ((PKA_TypeDef *) PKA_BASE_S)
#define PWR_S                           ((PWR_TypeDef *) PWR_BASE_S)
#define RAMCFG_SRAM1_S                  ((RAMCFG_TypeDef *) RAMCFG_SRAM1_BASE_S)
#define RAMCFG_SRAM2_S                  ((RAMCFG_TypeDef *) RAMCFG_SRAM2_BASE_S)
#define RCC_S                           ((RCC_TypeDef *) RCC_BASE_S)
#define RNG_S                           ((RNG_TypeDef *) RNG_BASE_S)
#define RTC_S                           ((RTC_TypeDef *) RTC_BASE_S)
#define SAES_S                          ((AES_TypeDef *) SAES_BASE_S)
#define SAI1_S                          ((SAI_TypeDef *) SAI1_BASE_S)
#define SAI1_Block_A_S                  ((SAI_Block_TypeDef *)SAI1_Block_A_BASE_S)
#define SAI1_Block_B_S                  ((SAI_Block_TypeDef *)SAI1_Block_B_BASE_S)
#define SDMMC1_S                        ((SDMMC_TypeDef *) SDMMC1_BASE_S)
#define SPI1_S                          ((SPI_TypeDef *) SPI1_BASE_S)
#define SPI2_S                          ((SPI_TypeDef *) SPI2_BASE_S)
#define SPI3_S                          ((SPI_TypeDef *) SPI3_BASE_S)
#define SYSCFG_S                        ((SYSCFG_TypeDef *) SYSCFG_BASE_S)
#define TAMP_S                          ((TAMP_TypeDef *) TAMP_BASE_S)
#define TIM1_S                          ((TIM_TypeDef *) TIM1_BASE_S)
#define TIM2_S                          ((TIM_TypeDef *) TIM2_BASE_S)
#define TIM3_S                          ((TIM_TypeDef *) TIM3_BASE_S)
#define TIM4_S                          ((TIM_TypeDef *) TIM4_BASE_S)
#define TIM6_S                          ((TIM_TypeDef *) TIM6_BASE_S)
#define TIM7_S                          ((TIM_TypeDef *) TIM7_BASE_S)
#define TIM15_S                         ((TIM_TypeDef *) TIM15_BASE_S)
#define TIM16_S                         ((TIM_TypeDef *) TIM16_BASE_S)
#define TIM17_S                         ((TIM_TypeDef *) TIM17_BASE_S)
#define TSC_S                           ((TSC_TypeDef *) TSC_BASE_S)
#define UART4_S                         ((USART_TypeDef *) UART4_BASE_S)
#define UART5_S                         ((USART_TypeDef *) UART5_BASE_S)
#define USART1_S                        ((USART_TypeDef *) USART1_BASE_S)
#define USART3_S                        ((USART_TypeDef *) USART3_BASE_S)
#define USB_DRD_FS_S                    ((USB_DRD_TypeDef *) USB_DRD_BASE_S)
#define USB_DRD_PMA_BUFF_S              ((USB_DRD_PMABuffDescTypeDef *) USB_DRD_PMAADDR_S)
#define VREFBUF_S                       ((VREFBUF_TypeDef *) VREFBUF_BASE_S)
#define WWDG_S                          ((WWDG_TypeDef *) WWDG_BASE_S)

/*!< Memory & Instance aliases and base addresses for Non-Secure/Secure peripherals */
/*!< Memory base addresses for Secure peripherals */
#define FLASH_BASE                      FLASH_BASE_S
#define SRAM1_BASE                      SRAM1_BASE_S
#define SRAM2_BASE                      SRAM2_BASE_S

/*!< Instance aliases and base addresses for Secure peripherals */
#define ADC12_COMMON                    ADC12_COMMON_S
#define ADC12_COMMON_BASE               ADC12_COMMON_BASE_S
#define ADC1                            ADC1_S
#define ADC1_BASE                       ADC1_BASE_S
#define ADC2                            ADC2_S
#define ADC2_BASE                       ADC2_BASE_S
#define ADF1                            ADF1_S
#define ADF1_BASE                       ADF1_BASE_S
#define ADF1_Filter0                    ADF1_Filter0_S
#define ADF1_Filter0_BASE               ADF1_Filter0_BASE_S
#define AES                             AES_S
#define AES_BASE                        AES_BASE_S
#define CCB                             CCB_S
#define CCB_BASE                        CCB_BASE_S
#define COMP1                           COMP1_S
#define COMP1_BASE                      COMP1_BASE_S
#define COMP2                           COMP2_S
#define COMP2_BASE                      COMP2_BASE_S
#define COMP12_COMMON                   COMP12_COMMON_S
#define COMP12_COMMON_BASE              COMP12_BASE_S
#define CRC                             CRC_S
#define CRC_BASE                        CRC_BASE_S
#define CRS                             CRS_S
#define CRS_BASE                        CRS_BASE_S
#define DAC1                            DAC1_S
#define DAC1_BASE                       DAC1_BASE_S
#define DLYB_SDMMC1                     DLYB_SDMMC1_S
#define DLYB_SDMMC1_BASE                DLYB_SDMMC1_BASE_S
#define DLYB_OCTOSPI1                   DLYB_OCTOSPI1_S
#define DLYB_OCTOSPI1_BASE              DLYB_OCTOSPI1_BASE_S
#define EXTI                            EXTI_S
#define EXTI_BASE                       EXTI_BASE_S
#define FDCAN1                          FDCAN1_S
#define FDCAN1_BASE                     FDCAN1_BASE_S
#define FDCAN_CONFIG                    FDCAN_CONFIG_S
#define FDCAN_CONFIG_BASE               FDCAN_CONFIG_BASE_S
#define FLASH                           FLASH_S
#define FLASH_R_BASE                    FLASH_R_BASE_S
#define GPDMA1                          GPDMA1_S
#define GPDMA1_BASE                     GPDMA1_BASE_S
#define GPDMA1_Channel0                 GPDMA1_Channel0_S
#define GPDMA1_Channel0_BASE            GPDMA1_Channel0_BASE_S
#define GPDMA1_Channel1                 GPDMA1_Channel1_S
#define GPDMA1_Channel1_BASE            GPDMA1_Channel1_BASE_S
#define GPDMA1_Channel2                 GPDMA1_Channel2_S
#define GPDMA1_Channel2_BASE            GPDMA1_Channel2_BASE_S
#define GPDMA1_Channel3                 GPDMA1_Channel3_S
#define GPDMA1_Channel3_BASE            GPDMA1_Channel3_BASE_S
#define GPDMA1_Channel4                 GPDMA1_Channel4_S
#define GPDMA1_Channel4_BASE            GPDMA1_Channel4_BASE_S
#define GPDMA1_Channel5                 GPDMA1_Channel5_S
#define GPDMA1_Channel5_BASE            GPDMA1_Channel5_BASE_S
#define GPDMA1_Channel6                 GPDMA1_Channel6_S
#define GPDMA1_Channel6_BASE            GPDMA1_Channel6_BASE_S
#define GPDMA1_Channel7                 GPDMA1_Channel7_S
#define GPDMA1_Channel7_BASE            GPDMA1_Channel7_BASE_S
#define GPDMA1_Channel8                 GPDMA1_Channel8_S
#define GPDMA1_Channel8_BASE            GPDMA1_Channel8_BASE_S
#define GPDMA1_Channel9                 GPDMA1_Channel9_S
#define GPDMA1_Channel9_BASE            GPDMA1_Channel9_BASE_S
#define GPDMA1_Channel10                GPDMA1_Channel10_S
#define GPDMA1_Channel10_BASE           GPDMA1_Channel10_BASE_S
#define GPDMA1_Channel11                GPDMA1_Channel11_S
#define GPDMA1_Channel11_BASE           GPDMA1_Channel11_BASE_S
#define GPIOA                           GPIOA_S
#define GPIOA_BASE                      GPIOA_BASE_S
#define GPIOB                           GPIOB_S
#define GPIOB_BASE                      GPIOB_BASE_S
#define GPIOC                           GPIOC_S
#define GPIOC_BASE                      GPIOC_BASE_S
#define GPIOD                           GPIOD_S
#define GPIOD_BASE                      GPIOD_BASE_S
#define GPIOE                           GPIOE_S
#define GPIOE_BASE                      GPIOE_BASE_S
#define GPIOG                           GPIOG_S
#define GPIOG_BASE                      GPIOG_BASE_S
#define GPIOH                           GPIOH_S
#define GPIOH_BASE                      GPIOH_BASE_S
#define GTZC_MPCBB1                     GTZC_MPCBB1_S
#define GTZC_MPCBB1_BASE                GTZC_MPCBB1_BASE_S
#define GTZC_MPCBB2                     GTZC_MPCBB2_S
#define GTZC_MPCBB2_BASE                GTZC_MPCBB2_BASE_S
#define GTZC_TZSC1                      GTZC_TZSC1_S
#define GTZC_TZSC1_BASE                 GTZC_TZSC1_BASE_S
#define GTZC_TZIC1                      GTZC_TZIC1_S
#define GTZC_TZIC1_BASE                 GTZC_TZIC1_BASE_S
#define HASH                            HASH_S
#define HASH_BASE                       HASH_BASE_S
#define HASH_DIGEST                     HASH_DIGEST_S
#define HASH_DIGEST_BASE                HASH_DIGEST_BASE_S
#define I2C1                            I2C1_S
#define I2C1_BASE                       I2C1_BASE_S
#define I2C2                            I2C2_S
#define I2C2_BASE                       I2C2_BASE_S
#define I2C3                            I2C3_S
#define I2C3_BASE                       I2C3_BASE_S
#define I3C1                            I3C1_S
#define I3C1_BASE                       I3C1_BASE_S
#define I3C2                            I3C2_S
#define I3C2_BASE                       I3C2_BASE_S
#define ICACHE                          ICACHE_S
#define ICACHE_BASE                     ICACHE_BASE_S
#define IWDG                            IWDG_S
#define IWDG_BASE                       IWDG_BASE_S
#define LPTIM1                          LPTIM1_S
#define LPTIM1_BASE                     LPTIM1_BASE_S
#define LPTIM2                          LPTIM2_S
#define LPTIM2_BASE                     LPTIM2_BASE_S
#define LPTIM3                          LPTIM3_S
#define LPTIM3_BASE                     LPTIM3_BASE_S
#define LPTIM4                          LPTIM4_S
#define LPTIM4_BASE                     LPTIM4_BASE_S
#define LPUART1                         LPUART1_S
#define LPUART1_BASE                    LPUART1_BASE_S
#define OCTOSPI1                        OCTOSPI1_S
#define OCTOSPI1_R_BASE                 OCTOSPI1_R_BASE_S
#define OPAMP1                          OPAMP1_S
#define OPAMP1_BASE                     OPAMP1_BASE_S
#define OPAMP2                          OPAMP2_S
#define OPAMP2_BASE                     OPAMP2_BASE_S
#define OPAMP12_COMMON                  OPAMP12_COMMON_S
#define OPAMP12_COMMON_BASE             OPAMP12_COMMON_BASE_S
#define PKA                             PKA_S
#define PKA_BASE                        PKA_BASE_S
#define PKA_RAM_BASE                    PKA_RAM_BASE_S
#define PWR                             PWR_S
#define PWR_BASE                        PWR_BASE_S
#define RAMCFG_SRAM1                    RAMCFG_SRAM1_S
#define RAMCFG_SRAM1_BASE               RAMCFG_SRAM1_BASE_S
#define RAMCFG_SRAM2                    RAMCFG_SRAM2_S
#define RAMCFG_SRAM2_BASE               RAMCFG_SRAM2_BASE_S
#define RCC                             RCC_S
#define RCC_BASE                        RCC_BASE_S
#define RNG                             RNG_S
#define RNG_BASE                        RNG_BASE_S
#define RTC                             RTC_S
#define RTC_BASE                        RTC_BASE_S
#define SAES                            SAES_S
#define SAES_BASE                       SAES_BASE_S
#define SAI1                            SAI1_S
#define SAI1_BASE                       SAI1_BASE_S
#define SAI1_Block_A                    SAI1_Block_A_S
#define SAI1_Block_A_BASE               SAI1_Block_A_BASE_S
#define SAI1_Block_B                    SAI1_Block_B_S
#define SAI1_Block_B_BASE               SAI1_Block_B_BASE_S
#define SDMMC1                          SDMMC1_S
#define SDMMC1_BASE                     SDMMC1_BASE_S
#define SPI1                            SPI1_S
#define SPI1_BASE                       SPI1_BASE_S
#define SPI2                            SPI2_S
#define SPI2_BASE                       SPI2_BASE_S
#define SPI3                            SPI3_S
#define SPI3_BASE                       SPI3_BASE_S
#define SRAMCAN_BASE                    SRAMCAN_BASE_S
#define SYSCFG                          SYSCFG_S
#define SYSCFG_BASE                     SYSCFG_BASE_S
#define TAMP                            TAMP_S
#define TAMP_BASE                       TAMP_BASE_S
#define TIM1                            TIM1_S
#define TIM1_BASE                       TIM1_BASE_S
#define TIM2                            TIM2_S
#define TIM2_BASE                       TIM2_BASE_S
#define TIM3                            TIM3_S
#define TIM3_BASE                       TIM3_BASE_S
#define TIM4                            TIM4_S
#define TIM4_BASE                       TIM4_BASE_S
#define TIM6                            TIM6_S
#define TIM6_BASE                       TIM6_BASE_S
#define TIM7                            TIM7_S
#define TIM7_BASE                       TIM7_BASE_S
#define TIM15                           TIM15_S
#define TIM15_BASE                      TIM15_BASE_S
#define TIM16                           TIM16_S
#define TIM16_BASE                      TIM16_BASE_S
#define TIM17                           TIM17_S
#define TIM17_BASE                      TIM17_BASE_S
#define TSC                             TSC_S
#define TSC_BASE                        TSC_BASE_S
#define UART4                           UART4_S
#define UART4_BASE                      UART4_BASE_S
#define UART5                           UART5_S
#define UART5_BASE                      UART5_BASE_S
#define USART1                          USART1_S
#define USART1_BASE                     USART1_BASE_S
#define USART3                          USART3_S
#define USART3_BASE                     USART3_BASE_S
#define USB_DRD_FS                      USB_DRD_FS_S
#define USB_DRD_BASE                    USB_DRD_BASE_S
#define USB_DRD_PMAADDR                 USB_DRD_PMAADDR_S
#define USB_DRD_PMA_BUFF                USB_DRD_PMA_BUFF_S
#define VREFBUF                         VREFBUF_S
#define VREFBUF_BASE                    VREFBUF_BASE_S
#define WWDG                            WWDG_S
#define WWDG_BASE                       WWDG_BASE_S

#else /* CPU_IN_SECURE_STATE */
/*!< Memory base addresses for Secure peripherals */
#define FLASH_BASE                      FLASH_BASE_NS
#define SRAM1_BASE                      SRAM1_BASE_NS
#define SRAM2_BASE                      SRAM2_BASE_NS

/*!< Instance aliases and base addresses for Secure peripherals */
#define ADC12_COMMON                    ADC12_COMMON_NS
#define ADC12_COMMON_BASE               ADC12_COMMON_BASE_NS
#define ADC1                            ADC1_NS
#define ADC1_BASE                       ADC1_BASE_NS
#define ADC2                            ADC2_NS
#define ADC2_BASE                       ADC2_BASE_NS
#define ADF1                            ADF1_NS
#define ADF1_BASE                       ADF1_BASE_NS
#define ADF1_Filter0                    ADF1_Filter0_NS
#define ADF1_Filter0_BASE               ADF1_Filter0_BASE_NS
#define AES                             AES_NS
#define AES_BASE                        AES_BASE_NS
#define CCB                             CCB_NS
#define CCB_BASE                        CCB_BASE_NS
#define COMP1                           COMP1_NS
#define COMP1_BASE                      COMP1_BASE_NS
#define COMP2                           COMP2_NS
#define COMP2_BASE                      COMP2_BASE_NS
#define COMP12_COMMON                   COMP12_COMMON_NS
#define COMP12_COMMON_BASE              COMP12_BASE_NS
#define CRC                             CRC_NS
#define CRC_BASE                        CRC_BASE_NS
#define CRS                             CRS_NS
#define CRS_BASE                        CRS_BASE_NS
#define DAC1                            DAC1_NS
#define DAC1_BASE                       DAC1_BASE_NS
#define DLYB_SDMMC1                     DLYB_SDMMC1_NS
#define DLYB_SDMMC1_BASE                DLYB_SDMMC1_BASE_NS
#define DLYB_OCTOSPI1                   DLYB_OCTOSPI1_NS
#define DLYB_OCTOSPI1_BASE              DLYB_OCTOSPI1_BASE_NS
#define EXTI                            EXTI_NS
#define EXTI_BASE                       EXTI_BASE_NS
#define FDCAN1                          FDCAN1_NS
#define FDCAN1_BASE                     FDCAN1_BASE_NS
#define FDCAN_CONFIG                    FDCAN_CONFIG_NS
#define FDCAN_CONFIG_BASE               FDCAN_CONFIG_BASE_NS
#define FLASH                           FLASH_NS
#define FLASH_R_BASE                    FLASH_R_BASE_NS
#define GPDMA1                          GPDMA1_NS
#define GPDMA1_BASE                     GPDMA1_BASE_NS
#define GPDMA1_Channel0                 GPDMA1_Channel0_NS
#define GPDMA1_Channel0_BASE            GPDMA1_Channel0_BASE_NS
#define GPDMA1_Channel1                 GPDMA1_Channel1_NS
#define GPDMA1_Channel1_BASE            GPDMA1_Channel1_BASE_NS
#define GPDMA1_Channel2                 GPDMA1_Channel2_NS
#define GPDMA1_Channel2_BASE            GPDMA1_Channel2_BASE_NS
#define GPDMA1_Channel3                 GPDMA1_Channel3_NS
#define GPDMA1_Channel3_BASE            GPDMA1_Channel3_BASE_NS
#define GPDMA1_Channel4                 GPDMA1_Channel4_NS
#define GPDMA1_Channel4_BASE            GPDMA1_Channel4_BASE_NS
#define GPDMA1_Channel5                 GPDMA1_Channel5_NS
#define GPDMA1_Channel5_BASE            GPDMA1_Channel5_BASE_NS
#define GPDMA1_Channel6                 GPDMA1_Channel6_NS
#define GPDMA1_Channel6_BASE            GPDMA1_Channel6_BASE_NS
#define GPDMA1_Channel7                 GPDMA1_Channel7_NS
#define GPDMA1_Channel7_BASE            GPDMA1_Channel7_BASE_NS
#define GPDMA1_Channel8                 GPDMA1_Channel8_NS
#define GPDMA1_Channel8_BASE            GPDMA1_Channel8_BASE_NS
#define GPDMA1_Channel9                 GPDMA1_Channel9_NS
#define GPDMA1_Channel9_BASE            GPDMA1_Channel9_BASE_NS
#define GPDMA1_Channel10                GPDMA1_Channel10_NS
#define GPDMA1_Channel10_BASE           GPDMA1_Channel10_BASE_NS
#define GPDMA1_Channel11                GPDMA1_Channel11_NS
#define GPDMA1_Channel11_BASE           GPDMA1_Channel11_BASE_NS
#define GPIOA                           GPIOA_NS
#define GPIOA_BASE                      GPIOA_BASE_NS
#define GPIOB                           GPIOB_NS
#define GPIOB_BASE                      GPIOB_BASE_NS
#define GPIOC                           GPIOC_NS
#define GPIOC_BASE                      GPIOC_BASE_NS
#define GPIOD                           GPIOD_NS
#define GPIOD_BASE                      GPIOD_BASE_NS
#define GPIOE                           GPIOE_NS
#define GPIOE_BASE                      GPIOE_BASE_NS
#define GPIOG                           GPIOG_NS
#define GPIOG_BASE                      GPIOG_BASE_NS
#define GPIOH                           GPIOH_NS
#define GPIOH_BASE                      GPIOH_BASE_NS
#define GTZC_MPCBB1                     GTZC_MPCBB1_NS
#define GTZC_MPCBB1_BASE                GTZC_MPCBB1_BASE_NS
#define GTZC_MPCBB2                     GTZC_MPCBB2_NS
#define GTZC_MPCBB2_BASE                GTZC_MPCBB2_BASE_NS
#define GTZC_TZSC1                      GTZC_TZSC1_NS
#define GTZC_TZSC1_BASE                 GTZC_TZSC1_BASE_NS
#define HASH                            HASH_NS
#define HASH_BASE                       HASH_BASE_NS
#define HASH_DIGEST                     HASH_DIGEST_NS
#define HASH_DIGEST_BASE                HASH_DIGEST_BASE_NS
#define I2C1                            I2C1_NS
#define I2C1_BASE                       I2C1_BASE_NS
#define I2C2                            I2C2_NS
#define I2C2_BASE                       I2C2_BASE_NS
#define I2C3                            I2C3_NS
#define I2C3_BASE                       I2C3_BASE_NS
#define I3C1                            I3C1_NS
#define I3C1_BASE                       I3C1_BASE_NS
#define I3C2                            I3C2_NS
#define I3C2_BASE                       I3C2_BASE_NS
#define ICACHE                          ICACHE_NS
#define ICACHE_BASE                     ICACHE_BASE_NS
#define IWDG                            IWDG_NS
#define IWDG_BASE                       IWDG_BASE_NS
#define LPTIM1                          LPTIM1_NS
#define LPTIM1_BASE                     LPTIM1_BASE_NS
#define LPTIM2                          LPTIM2_NS
#define LPTIM2_BASE                     LPTIM2_BASE_NS
#define LPTIM3                          LPTIM3_NS
#define LPTIM3_BASE                     LPTIM3_BASE_NS
#define LPTIM4                          LPTIM4_NS
#define LPTIM4_BASE                     LPTIM4_BASE_NS
#define LPUART1                         LPUART1_NS
#define LPUART1_BASE                    LPUART1_BASE_NS
#define OCTOSPI1                        OCTOSPI1_NS
#define OCTOSPI1_R_BASE                 OCTOSPI1_R_BASE_NS
#define OPAMP1                          OPAMP1_NS
#define OPAMP1_BASE                     OPAMP1_BASE_NS
#define OPAMP2                          OPAMP2_NS
#define OPAMP2_BASE                     OPAMP2_BASE_NS
#define OPAMP12_COMMON                  OPAMP12_COMMON_NS
#define OPAMP12_COMMON_BASE             OPAMP12_COMMON_BASE_NS
#define PKA                             PKA_NS
#define PKA_BASE                        PKA_BASE_NS
#define PKA_RAM_BASE                    PKA_RAM_BASE_NS
#define PWR                             PWR_NS
#define PWR_BASE                        PWR_BASE_NS
#define RAMCFG_SRAM1                    RAMCFG_SRAM1_NS
#define RAMCFG_SRAM1_BASE               RAMCFG_SRAM1_BASE_NS
#define RAMCFG_SRAM2                    RAMCFG_SRAM2_NS
#define RAMCFG_SRAM2_BASE               RAMCFG_SRAM2_BASE_NS
#define RCC                             RCC_NS
#define RCC_BASE                        RCC_BASE_NS
#define RNG                             RNG_NS
#define RNG_BASE                        RNG_BASE_NS
#define RTC                             RTC_NS
#define RTC_BASE                        RTC_BASE_NS
#define SAES                            SAES_NS
#define SAES_BASE                       SAES_BASE_NS
#define SAI1                            SAI1_NS
#define SAI1_BASE                       SAI1_BASE_NS
#define SAI1_Block_A                    SAI1_Block_A_NS
#define SAI1_Block_A_BASE               SAI1_Block_A_BASE_NS
#define SAI1_Block_B                    SAI1_Block_B_NS
#define SAI1_Block_B_BASE               SAI1_Block_B_BASE_NS
#define SDMMC1                          SDMMC1_NS
#define SDMMC1_BASE                     SDMMC1_BASE_NS
#define SPI1                            SPI1_NS
#define SPI1_BASE                       SPI1_BASE_NS
#define SPI2                            SPI2_NS
#define SPI2_BASE                       SPI2_BASE_NS
#define SPI3                            SPI3_NS
#define SPI3_BASE                       SPI3_BASE_NS
#define SRAMCAN_BASE                    SRAMCAN_BASE_NS
#define SYSCFG                          SYSCFG_NS
#define SYSCFG_BASE                     SYSCFG_BASE_NS
#define TAMP                            TAMP_NS
#define TAMP_BASE                       TAMP_BASE_NS
#define TIM1                            TIM1_NS
#define TIM1_BASE                       TIM1_BASE_NS
#define TIM2                            TIM2_NS
#define TIM2_BASE                       TIM2_BASE_NS
#define TIM3                            TIM3_NS
#define TIM3_BASE                       TIM3_BASE_NS
#define TIM4                            TIM4_NS
#define TIM4_BASE                       TIM4_BASE_NS
#define TIM6                            TIM6_NS
#define TIM6_BASE                       TIM6_BASE_NS
#define TIM7                            TIM7_NS
#define TIM7_BASE                       TIM7_BASE_NS
#define TIM15                           TIM15_NS
#define TIM15_BASE                      TIM15_BASE_NS
#define TIM16                           TIM16_NS
#define TIM16_BASE                      TIM16_BASE_NS
#define TIM17                           TIM17_NS
#define TIM17_BASE                      TIM17_BASE_NS
#define TSC                             TSC_NS
#define TSC_BASE                        TSC_BASE_NS
#define UART4                           UART4_NS
#define UART4_BASE                      UART4_BASE_NS
#define UART5                           UART5_NS
#define UART5_BASE                      UART5_BASE_NS
#define USART1                          USART1_NS
#define USART1_BASE                     USART1_BASE_NS
#define USART3                          USART3_NS
#define USART3_BASE                     USART3_BASE_NS
#define USB_DRD_FS                      USB_DRD_FS_NS
#define USB_DRD_BASE                    USB_DRD_BASE_NS
#define USB_DRD_PMAADDR                 USB_DRD_PMAADDR_NS
#define USB_DRD_PMA_BUFF                USB_DRD_PMA_BUFF_NS
#define VREFBUF                         VREFBUF_NS
#define VREFBUF_BASE                    VREFBUF_BASE_NS
#define WWDG                            WWDG_NS
#define WWDG_BASE                       WWDG_BASE_NS
#endif /* CPU_IN_SECURE_STATE */

/** @addtogroup Exported_constants
  * @{
  */

/** @addtogroup Hardware_Constant_Definition
  * @{
  */
#define LSI_STARTUP_TIME                16000U /*!< LSI Maximum startup time in us : 4 cycles @ 250 Hz = 16 ms */
/**
  * @}
  */

/** @addtogroup Peripheral_Registers_Bits_Definition
  * @{
  */

/******************************************************************************/
/*                                                                            */
/*                        Analog to Digital Converter (ADC)                   */
/*                                                                            */
/******************************************************************************/

/* Specific device feature definitions */
#define ADC_MULTIMODE_SUPPORT         /*!< ADC feature available only on specific devices: multimode available on devices with several ADC instances */

/********************  Bit definition for ADC_ISR register  *******************/
#define ADC_ISR_ADRDY_Pos                   (0UL)
#define ADC_ISR_ADRDY_Msk                   (0x1UL << ADC_ISR_ADRDY_Pos)            /*!< 0x00000001 */
#define ADC_ISR_ADRDY                       ADC_ISR_ADRDY_Msk                       /*!< ADC ready flag */
#define ADC_ISR_EOSMP_Pos                   (1UL)
#define ADC_ISR_EOSMP_Msk                   (0x1UL << ADC_ISR_EOSMP_Pos)            /*!< 0x00000002 */
#define ADC_ISR_EOSMP                       ADC_ISR_EOSMP_Msk                       /*!< ADC group regular end of sampling flag */
#define ADC_ISR_EOC_Pos                     (2UL)
#define ADC_ISR_EOC_Msk                     (0x1UL << ADC_ISR_EOC_Pos)              /*!< 0x00000004 */
#define ADC_ISR_EOC                         ADC_ISR_EOC_Msk                         /*!< ADC group regular end of unitary conversion flag */
#define ADC_ISR_EOS_Pos                     (3UL)
#define ADC_ISR_EOS_Msk                     (0x1UL << ADC_ISR_EOS_Pos)              /*!< 0x00000008 */
#define ADC_ISR_EOS                         ADC_ISR_EOS_Msk                         /*!< ADC group regular end of sequence conversions flag */
#define ADC_ISR_OVR_Pos                     (4UL)
#define ADC_ISR_OVR_Msk                     (0x1UL << ADC_ISR_OVR_Pos)              /*!< 0x00000010 */
#define ADC_ISR_OVR                         ADC_ISR_OVR_Msk                         /*!< ADC group regular overrun flag */
#define ADC_ISR_JEOC_Pos                    (5UL)
#define ADC_ISR_JEOC_Msk                    (0x1UL << ADC_ISR_JEOC_Pos)             /*!< 0x00000020 */
#define ADC_ISR_JEOC                        ADC_ISR_JEOC_Msk                        /*!< ADC group injected end of unitary conversion flag */
#define ADC_ISR_JEOS_Pos                    (6UL)
#define ADC_ISR_JEOS_Msk                    (0x1UL << ADC_ISR_JEOS_Pos)             /*!< 0x00000040 */
#define ADC_ISR_JEOS                        ADC_ISR_JEOS_Msk                        /*!< ADC group injected end of sequence conversions flag */
#define ADC_ISR_AWD1_Pos                    (7UL)
#define ADC_ISR_AWD1_Msk                    (0x1UL << ADC_ISR_AWD1_Pos)             /*!< 0x00000080 */
#define ADC_ISR_AWD1                        ADC_ISR_AWD1_Msk                        /*!< ADC analog watchdog 1 flag */
#define ADC_ISR_AWD2_Pos                    (8UL)
#define ADC_ISR_AWD2_Msk                    (0x1UL << ADC_ISR_AWD2_Pos)             /*!< 0x00000100 */
#define ADC_ISR_AWD2                        ADC_ISR_AWD2_Msk                        /*!< ADC analog watchdog 2 flag */
#define ADC_ISR_AWD3_Pos                    (9UL)
#define ADC_ISR_AWD3_Msk                    (0x1UL << ADC_ISR_AWD3_Pos)             /*!< 0x00000200 */
#define ADC_ISR_AWD3                        ADC_ISR_AWD3_Msk                        /*!< ADC analog watchdog 3 flag */
#define ADC_ISR_JQOVF_Pos                   (10UL)
#define ADC_ISR_JQOVF_Msk                   (0x1UL << ADC_ISR_JQOVF_Pos)            /*!< 0x00000400 */
#define ADC_ISR_JQOVF                       ADC_ISR_JQOVF_Msk                       /*!< ADC group injected contexts queue overflow flag */
#define ADC_ISR_LDORDY_Pos                  (12UL)
#define ADC_ISR_LDORDY_Msk                  (0x1UL << ADC_ISR_LDORDY_Pos)           /*!< 0x00001000 */
#define ADC_ISR_LDORDY                      ADC_ISR_LDORDY_Msk                      /*!< ADC internal voltage regulator output ready flag */

/********************  Bit definition for ADC_IER register  *******************/
#define ADC_IER_ADRDYIE_Pos                 (0UL)
#define ADC_IER_ADRDYIE_Msk                 (0x1UL << ADC_IER_ADRDYIE_Pos)          /*!< 0x00000001 */
#define ADC_IER_ADRDYIE                     ADC_IER_ADRDYIE_Msk                     /*!< ADC ready interrupt */
#define ADC_IER_EOSMPIE_Pos                 (1UL)
#define ADC_IER_EOSMPIE_Msk                 (0x1UL << ADC_IER_EOSMPIE_Pos)          /*!< 0x00000002 */
#define ADC_IER_EOSMPIE                     ADC_IER_EOSMPIE_Msk                     /*!< ADC group regular end of sampling interrupt */
#define ADC_IER_EOCIE_Pos                   (2UL)
#define ADC_IER_EOCIE_Msk                   (0x1UL << ADC_IER_EOCIE_Pos)            /*!< 0x00000004 */
#define ADC_IER_EOCIE                       ADC_IER_EOCIE_Msk                       /*!< ADC group regular end of unitary conversion interrupt */
#define ADC_IER_EOSIE_Pos                   (3UL)
#define ADC_IER_EOSIE_Msk                   (0x1UL << ADC_IER_EOSIE_Pos)            /*!< 0x00000008 */
#define ADC_IER_EOSIE                       ADC_IER_EOSIE_Msk                       /*!< ADC group regular end of sequence conversions interrupt */
#define ADC_IER_OVRIE_Pos                   (4UL)
#define ADC_IER_OVRIE_Msk                   (0x1UL << ADC_IER_OVRIE_Pos)            /*!< 0x00000010 */
#define ADC_IER_OVRIE                       ADC_IER_OVRIE_Msk                       /*!< ADC group regular overrun interrupt */
#define ADC_IER_JEOCIE_Pos                  (5UL)
#define ADC_IER_JEOCIE_Msk                  (0x1UL << ADC_IER_JEOCIE_Pos)           /*!< 0x00000020 */
#define ADC_IER_JEOCIE                      ADC_IER_JEOCIE_Msk                      /*!< ADC group injected end of unitary conversion interrupt */
#define ADC_IER_JEOSIE_Pos                  (6UL)
#define ADC_IER_JEOSIE_Msk                  (0x1UL << ADC_IER_JEOSIE_Pos)           /*!< 0x00000040 */
#define ADC_IER_JEOSIE                      ADC_IER_JEOSIE_Msk                      /*!< ADC group injected end of sequence conversions interrupt */
#define ADC_IER_AWD1IE_Pos                  (7UL)
#define ADC_IER_AWD1IE_Msk                  (0x1UL << ADC_IER_AWD1IE_Pos)           /*!< 0x00000080 */
#define ADC_IER_AWD1IE                      ADC_IER_AWD1IE_Msk                      /*!< ADC analog watchdog 1 interrupt */
#define ADC_IER_AWD2IE_Pos                  (8UL)
#define ADC_IER_AWD2IE_Msk                  (0x1UL << ADC_IER_AWD2IE_Pos)           /*!< 0x00000100 */
#define ADC_IER_AWD2IE                      ADC_IER_AWD2IE_Msk                      /*!< ADC analog watchdog 2 interrupt */
#define ADC_IER_AWD3IE_Pos                  (9UL)
#define ADC_IER_AWD3IE_Msk                  (0x1UL << ADC_IER_AWD3IE_Pos)           /*!< 0x00000200 */
#define ADC_IER_AWD3IE                      ADC_IER_AWD3IE_Msk                      /*!< ADC analog watchdog 3 interrupt */
#define ADC_IER_JQOVFIE_Pos                 (10UL)
#define ADC_IER_JQOVFIE_Msk                 (0x1UL << ADC_IER_JQOVFIE_Pos)          /*!< 0x00000400 */
#define ADC_IER_JQOVFIE                     ADC_IER_JQOVFIE_Msk                     /*!< ADC group injected contexts queue overflow interrupt */
#define ADC_IER_LDORDYIE_Pos                (12UL)
#define ADC_IER_LDORDYIE_Msk                (0x1UL << ADC_IER_LDORDYIE_Pos)         /*!< 0x00001000 */
#define ADC_IER_LDORDYIE                    ADC_IER_LDORDYIE_Msk                    /*!< ADC internal voltage regulator interrupt*/

/********************  Bit definition for ADC_CR register  ********************/
#define ADC_CR_ADEN_Pos                     (0UL)
#define ADC_CR_ADEN_Msk                     (0x1UL << ADC_CR_ADEN_Pos)              /*!< 0x00000001 */
#define ADC_CR_ADEN                         ADC_CR_ADEN_Msk                         /*!< ADC enable */
#define ADC_CR_ADDIS_Pos                    (1UL)
#define ADC_CR_ADDIS_Msk                    (0x1UL << ADC_CR_ADDIS_Pos)             /*!< 0x00000002 */
#define ADC_CR_ADDIS                        ADC_CR_ADDIS_Msk                        /*!< ADC disable */
#define ADC_CR_ADSTART_Pos                  (2UL)
#define ADC_CR_ADSTART_Msk                  (0x1UL << ADC_CR_ADSTART_Pos)           /*!< 0x00000004 */
#define ADC_CR_ADSTART                      ADC_CR_ADSTART_Msk                      /*!< ADC group regular conversion start */
#define ADC_CR_JADSTART_Pos                 (3UL)
#define ADC_CR_JADSTART_Msk                 (0x1UL << ADC_CR_JADSTART_Pos)          /*!< 0x00000008 */
#define ADC_CR_JADSTART                     ADC_CR_JADSTART_Msk                     /*!< ADC group injected conversion start */
#define ADC_CR_ADSTP_Pos                    (4UL)
#define ADC_CR_ADSTP_Msk                    (0x1UL << ADC_CR_ADSTP_Pos)             /*!< 0x00000010 */
#define ADC_CR_ADSTP                        ADC_CR_ADSTP_Msk                        /*!< ADC group regular conversion stop */
#define ADC_CR_JADSTP_Pos                   (5UL)
#define ADC_CR_JADSTP_Msk                   (0x1UL << ADC_CR_JADSTP_Pos)            /*!< 0x00000020 */
#define ADC_CR_JADSTP                       ADC_CR_JADSTP_Msk                       /*!< ADC group injected conversion stop */
#define ADC_CR_ADVREGEN_Pos                 (28UL)
#define ADC_CR_ADVREGEN_Msk                 (0x1UL << ADC_CR_ADVREGEN_Pos)          /*!< 0x10000000 */
#define ADC_CR_ADVREGEN                     ADC_CR_ADVREGEN_Msk                     /*!< ADC internal voltage regulator */
#define ADC_CR_DEEPPWD_Pos                  (29UL)
#define ADC_CR_DEEPPWD_Msk                  (0x1UL << ADC_CR_DEEPPWD_Pos)           /*!< 0x20000000 */
#define ADC_CR_DEEPPWD                      ADC_CR_DEEPPWD_Msk                      /*!< ADC deep power down enable */
#define ADC_CR_ADCAL_Pos                    (31UL)
#define ADC_CR_ADCAL_Msk                    (0x1UL << ADC_CR_ADCAL_Pos)             /*!< 0x80000000 */
#define ADC_CR_ADCAL                        ADC_CR_ADCAL_Msk                        /*!< ADC calibration */

/********************  Bit definition for ADC_CFGR1 register  ******************/
#define ADC_CFGR1_DMNGT_Pos                 (0UL)
#define ADC_CFGR1_DMNGT_Msk                 (0x3UL << ADC_CFGR1_DMNGT_Pos)          /*!< 0x00000003 */
#define ADC_CFGR1_DMNGT                     ADC_CFGR1_DMNGT_Msk                     /*!< ADC data management configuration */
#define ADC_CFGR1_DMNGT_0                   (0x1UL << ADC_CFGR1_DMNGT_Pos)          /*!< 0x00000001 */
#define ADC_CFGR1_DMNGT_1                   (0x2UL << ADC_CFGR1_DMNGT_Pos)          /*!< 0x00000002 */

#define ADC_CFGR1_RES_Pos                   (2UL)
#define ADC_CFGR1_RES_Msk                   (0x3UL << ADC_CFGR1_RES_Pos)            /*!< 0x0000000C */
#define ADC_CFGR1_RES                       ADC_CFGR1_RES_Msk                       /*!< ADC data resolution */
#define ADC_CFGR1_RES_0                     (0x1UL << ADC_CFGR1_RES_Pos)            /*!< 0x00000004 */
#define ADC_CFGR1_RES_1                     (0x2UL << ADC_CFGR1_RES_Pos)            /*!< 0x00000008 */

#define ADC_CFGR1_EXTSEL_Pos                (5UL)
#define ADC_CFGR1_EXTSEL_Msk                (0x1FUL << ADC_CFGR1_EXTSEL_Pos)        /*!< 0x000003E0 */
#define ADC_CFGR1_EXTSEL                    ADC_CFGR1_EXTSEL_Msk                    /*!< ADC group regular external trigger source */
#define ADC_CFGR1_EXTSEL_0                  (0x01UL << ADC_CFGR1_EXTSEL_Pos)        /*!< 0x00000020 */
#define ADC_CFGR1_EXTSEL_1                  (0x02UL << ADC_CFGR1_EXTSEL_Pos)        /*!< 0x00000040 */
#define ADC_CFGR1_EXTSEL_2                  (0x04UL << ADC_CFGR1_EXTSEL_Pos)        /*!< 0x00000080 */
#define ADC_CFGR1_EXTSEL_3                  (0x08UL << ADC_CFGR1_EXTSEL_Pos)        /*!< 0x00000100 */
#define ADC_CFGR1_EXTSEL_4                  (0x10UL << ADC_CFGR1_EXTSEL_Pos)        /*!< 0x00000200 */

#define ADC_CFGR1_EXTEN_Pos                 (10UL)
#define ADC_CFGR1_EXTEN_Msk                 (0x3UL << ADC_CFGR1_EXTEN_Pos)          /*!< 0x00000C00 */
#define ADC_CFGR1_EXTEN                     ADC_CFGR1_EXTEN_Msk                     /*!< ADC group regular external trigger polarity */
#define ADC_CFGR1_EXTEN_0                   (0x1UL << ADC_CFGR1_EXTEN_Pos)          /*!< 0x00000400 */
#define ADC_CFGR1_EXTEN_1                   (0x2UL << ADC_CFGR1_EXTEN_Pos)          /*!< 0x00000800 */

#define ADC_CFGR1_OVRMOD_Pos                (12UL)
#define ADC_CFGR1_OVRMOD_Msk                (0x1UL << ADC_CFGR1_OVRMOD_Pos)         /*!< 0x00001000 */
#define ADC_CFGR1_OVRMOD                    ADC_CFGR1_OVRMOD_Msk                    /*!< ADC group regular overrun configuration */
#define ADC_CFGR1_CONT_Pos                  (13UL)
#define ADC_CFGR1_CONT_Msk                  (0x1UL << ADC_CFGR1_CONT_Pos)           /*!< 0x00002000 */
#define ADC_CFGR1_CONT                      ADC_CFGR1_CONT_Msk                      /*!< ADC group regular continuous conversion mode */
#define ADC_CFGR1_AUTDLY_Pos                (14UL)
#define ADC_CFGR1_AUTDLY_Msk                (0x1UL << ADC_CFGR1_AUTDLY_Pos)         /*!< 0x00004000 */
#define ADC_CFGR1_AUTDLY                    ADC_CFGR1_AUTDLY_Msk                    /*!< ADC low power auto wait */

#define ADC_CFGR1_DISCEN_Pos                (16UL)
#define ADC_CFGR1_DISCEN_Msk                (0x1UL << ADC_CFGR1_DISCEN_Pos)         /*!< 0x00010000 */
#define ADC_CFGR1_DISCEN                    ADC_CFGR1_DISCEN_Msk                    /*!< ADC group regular sequencer discontinuous mode */

#define ADC_CFGR1_DISCNUM_Pos               (17UL)
#define ADC_CFGR1_DISCNUM_Msk               (0x7UL << ADC_CFGR1_DISCNUM_Pos)        /*!< 0x000E0000 */
#define ADC_CFGR1_DISCNUM                   ADC_CFGR1_DISCNUM_Msk                   /*!< ADC group regular sequencer discontinuous number of ranks */
#define ADC_CFGR1_DISCNUM_0                 (0x1UL << ADC_CFGR1_DISCNUM_Pos)        /*!< 0x00020000 */
#define ADC_CFGR1_DISCNUM_1                 (0x2UL << ADC_CFGR1_DISCNUM_Pos)        /*!< 0x00040000 */
#define ADC_CFGR1_DISCNUM_2                 (0x4UL << ADC_CFGR1_DISCNUM_Pos)        /*!< 0x00080000 */

#define ADC_CFGR1_JDISCEN_Pos               (20UL)
#define ADC_CFGR1_JDISCEN_Msk               (0x1UL << ADC_CFGR1_JDISCEN_Pos)        /*!< 0x00100000 */
#define ADC_CFGR1_JDISCEN                   ADC_CFGR1_JDISCEN_Msk                   /*!< ADC group injected sequencer discontinuous mode */

#define ADC_CFGR1_JQM_Pos                   (21UL)
#define ADC_CFGR1_JQM_Msk                   (0x1UL << ADC_CFGR1_JQM_Pos)            /*!< 0x00200000 */
#define ADC_CFGR1_JQM                       ADC_CFGR1_JQM_Msk                       /*!< ADC group injected contexts queue mode */

#define ADC_CFGR1_AWD1SGL_Pos               (22UL)
#define ADC_CFGR1_AWD1SGL_Msk               (0x1UL << ADC_CFGR1_AWD1SGL_Pos)        /*!< 0x00400000 */
#define ADC_CFGR1_AWD1SGL                   ADC_CFGR1_AWD1SGL_Msk                   /*!< ADC analog watchdog 1 monitoring a single channel or all channels */
#define ADC_CFGR1_AWD1EN_Pos                (23UL)
#define ADC_CFGR1_AWD1EN_Msk                (0x1UL << ADC_CFGR1_AWD1EN_Pos)         /*!< 0x00800000 */
#define ADC_CFGR1_AWD1EN                    ADC_CFGR1_AWD1EN_Msk                    /*!< ADC analog watchdog 1 enable on scope ADC group regular */
#define ADC_CFGR1_JAWD1EN_Pos               (24UL)
#define ADC_CFGR1_JAWD1EN_Msk               (0x1UL << ADC_CFGR1_JAWD1EN_Pos)        /*!< 0x01000000 */
#define ADC_CFGR1_JAWD1EN                   ADC_CFGR1_JAWD1EN_Msk                   /*!< ADC analog watchdog 1 enable on scope ADC group injected */
#define ADC_CFGR1_JAUTO_Pos                 (25UL)
#define ADC_CFGR1_JAUTO_Msk                 (0x1UL << ADC_CFGR1_JAUTO_Pos)          /*!< 0x02000000 */
#define ADC_CFGR1_JAUTO                     ADC_CFGR1_JAUTO_Msk                     /*!< ADC group injected automatic trigger mode */

#define ADC_CFGR1_AWD1CH_Pos                (26UL)
#define ADC_CFGR1_AWD1CH_Msk                (0x1FUL << ADC_CFGR1_AWD1CH_Pos)        /*!< 0x7C000000 */
#define ADC_CFGR1_AWD1CH                    ADC_CFGR1_AWD1CH_Msk                    /*!< ADC analog watchdog 1 monitored channel selection */
#define ADC_CFGR1_AWD1CH_0                  (0x01UL << ADC_CFGR1_AWD1CH_Pos)        /*!< 0x04000000 */
#define ADC_CFGR1_AWD1CH_1                  (0x02UL << ADC_CFGR1_AWD1CH_Pos)        /*!< 0x08000000 */
#define ADC_CFGR1_AWD1CH_2                  (0x04UL << ADC_CFGR1_AWD1CH_Pos)        /*!< 0x10000000 */
#define ADC_CFGR1_AWD1CH_3                  (0x08UL << ADC_CFGR1_AWD1CH_Pos)        /*!< 0x20000000 */
#define ADC_CFGR1_AWD1CH_4                  (0x10UL << ADC_CFGR1_AWD1CH_Pos)        /*!< 0x40000000 */

#define ADC_CFGR1_JQDIS_Pos                 (31UL)
#define ADC_CFGR1_JQDIS_Msk                 (0x1UL << ADC_CFGR1_JQDIS_Pos)          /*!< 0x80000000 */
#define ADC_CFGR1_JQDIS                     ADC_CFGR1_JQDIS_Msk                     /*!< ADC group injected contexts queue disable */

/********************  Bit definition for ADC_CFGR2 register  *****************/
#define ADC_CFGR2_ROVSE_Pos                 (0UL)
#define ADC_CFGR2_ROVSE_Msk                 (0x1UL << ADC_CFGR2_ROVSE_Pos)          /*!< 0x00000001 */
#define ADC_CFGR2_ROVSE                     ADC_CFGR2_ROVSE_Msk                     /*!< ADC oversampler enable on scope ADC group regular */
#define ADC_CFGR2_JOVSE_Pos                 (1UL)
#define ADC_CFGR2_JOVSE_Msk                 (0x1UL << ADC_CFGR2_JOVSE_Pos)          /*!< 0x00000002 */
#define ADC_CFGR2_JOVSE                     ADC_CFGR2_JOVSE_Msk                     /*!< ADC oversampler enable on scope ADC group injected */

#define ADC_CFGR2_OVSS_Pos                  (5UL)
#define ADC_CFGR2_OVSS_Msk                  (0xFUL << ADC_CFGR2_OVSS_Pos)           /*!< 0x000001E0 */
#define ADC_CFGR2_OVSS                      ADC_CFGR2_OVSS_Msk                      /*!< ADC oversampling shift */
#define ADC_CFGR2_OVSS_0                    (0x1UL << ADC_CFGR2_OVSS_Pos)           /*!< 0x00000020 */
#define ADC_CFGR2_OVSS_1                    (0x2UL << ADC_CFGR2_OVSS_Pos)           /*!< 0x00000040 */
#define ADC_CFGR2_OVSS_2                    (0x4UL << ADC_CFGR2_OVSS_Pos)           /*!< 0x00000080 */
#define ADC_CFGR2_OVSS_3                    (0x8UL << ADC_CFGR2_OVSS_Pos)           /*!< 0x00000100 */

#define ADC_CFGR2_TROVS_Pos                 (9UL)
#define ADC_CFGR2_TROVS_Msk                 (0x1UL << ADC_CFGR2_TROVS_Pos)          /*!< 0x00000200 */
#define ADC_CFGR2_TROVS                     ADC_CFGR2_TROVS_Msk                     /*!< ADC oversampling discontinuous mode (triggered mode) for ADC group regular */
#define ADC_CFGR2_ROVSM_Pos                 (10UL)
#define ADC_CFGR2_ROVSM_Msk                 (0x1UL << ADC_CFGR2_ROVSM_Pos)          /*!< 0x00000400 */
#define ADC_CFGR2_ROVSM                     ADC_CFGR2_ROVSM_Msk                     /*!< ADC oversampling mode managing interlaced conversions of ADC group regular and group injected */

#define ADC_CFGR2_BULB_Pos                  (13UL)
#define ADC_CFGR2_BULB_Msk                  (0x1UL << ADC_CFGR2_BULB_Pos)            /*!< 0x00002000 */
#define ADC_CFGR2_BULB                      ADC_CFGR2_BULB_Msk                       /*!< ADC bulb sampling mode */

#define ADC_CFGR2_SWTRIG_Pos                (14UL)
#define ADC_CFGR2_SWTRIG_Msk                (0x1UL << ADC_CFGR2_SWTRIG_Pos)          /*!< 0x00004000 */
#define ADC_CFGR2_SWTRIG                    ADC_CFGR2_SWTRIG_Msk                     /*!< ADC software trigger bit for sampling time control trigger mode */

#define ADC_CFGR2_SMPTRIG_Pos               (15UL)
#define ADC_CFGR2_SMPTRIG_Msk               (0x1UL << ADC_CFGR2_SMPTRIG_Pos)         /*!< 0x00008000 */
#define ADC_CFGR2_SMPTRIG                   ADC_CFGR2_SMPTRIG_Msk                    /*!< ADC sampling time control trigger mode */

#define ADC_CFGR2_OVSR_Pos                  (16UL)
#define ADC_CFGR2_OVSR_Msk                  (0x3FFUL << ADC_CFGR2_OVSR_Pos)          /*!< 0x03FF0000 */
#define ADC_CFGR2_OVSR                      ADC_CFGR2_OVSR_Msk                       /*!< ADC oversampling ratio */
#define ADC_CFGR2_OVSR_0                    (0x001UL << ADC_CFGR2_OVSR_Pos)          /*!< 0x00010000 */
#define ADC_CFGR2_OVSR_1                    (0x002UL << ADC_CFGR2_OVSR_Pos)          /*!< 0x00020000 */
#define ADC_CFGR2_OVSR_2                    (0x004UL << ADC_CFGR2_OVSR_Pos)          /*!< 0x00040000 */
#define ADC_CFGR2_OVSR_3                    (0x008UL << ADC_CFGR2_OVSR_Pos)          /*!< 0x00080000 */
#define ADC_CFGR2_OVSR_4                    (0x010UL << ADC_CFGR2_OVSR_Pos)          /*!< 0x00100000 */
#define ADC_CFGR2_OVSR_5                    (0x020UL << ADC_CFGR2_OVSR_Pos)          /*!< 0x00200000 */
#define ADC_CFGR2_OVSR_6                    (0x040UL << ADC_CFGR2_OVSR_Pos)          /*!< 0x00400000 */
#define ADC_CFGR2_OVSR_7                    (0x080UL << ADC_CFGR2_OVSR_Pos)          /*!< 0x00800000 */
#define ADC_CFGR2_OVSR_8                    (0x100UL << ADC_CFGR2_OVSR_Pos)          /*!< 0x01000000 */
#define ADC_CFGR2_OVSR_9                    (0x200UL << ADC_CFGR2_OVSR_Pos)          /*!< 0x02000000 */

#define ADC_CFGR2_LFTRIG_Pos                (27UL)
#define ADC_CFGR2_LFTRIG_Msk                (0x1UL << ADC_CFGR2_LFTRIG_Pos)          /*!< 0x08000000 */
#define ADC_CFGR2_LFTRIG                    ADC_CFGR2_LFTRIG_Msk                     /*!< ADC Low-frequency trigge */

#define ADC_CFGR2_LSHIFT_Pos                (28UL)
#define ADC_CFGR2_LSHIFT_Msk                (0xFUL << ADC_CFGR2_LSHIFT_Pos)          /*!< 0xF0000000 */
#define ADC_CFGR2_LSHIFT                    ADC_CFGR2_LSHIFT_Msk                     /*!< ADC left shift factor */
#define ADC_CFGR2_LSHIFT_0                  (0x1UL << ADC_CFGR2_LSHIFT_Pos)          /*!< 0x10000000 */
#define ADC_CFGR2_LSHIFT_1                  (0x2UL << ADC_CFGR2_LSHIFT_Pos)          /*!< 0x20000000 */
#define ADC_CFGR2_LSHIFT_2                  (0x4UL << ADC_CFGR2_LSHIFT_Pos)          /*!< 0x40000000 */
#define ADC_CFGR2_LSHIFT_3                  (0x8UL << ADC_CFGR2_LSHIFT_Pos)          /*!< 0x80000000 */

/********************  Bit definition for ADC_SMPR1 register  *****************/
#define ADC_SMPR1_SMP0_Pos                  (0UL)
#define ADC_SMPR1_SMP0_Msk                  (0x7UL << ADC_SMPR1_SMP0_Pos)           /*!< 0x00000007 */
#define ADC_SMPR1_SMP0                      ADC_SMPR1_SMP0_Msk                      /*!< ADC channel 0 sampling time selection  */
#define ADC_SMPR1_SMP0_0                    (0x1UL << ADC_SMPR1_SMP0_Pos)           /*!< 0x00000001 */
#define ADC_SMPR1_SMP0_1                    (0x2UL << ADC_SMPR1_SMP0_Pos)           /*!< 0x00000002 */
#define ADC_SMPR1_SMP0_2                    (0x4UL << ADC_SMPR1_SMP0_Pos)           /*!< 0x00000004 */

#define ADC_SMPR1_SMP1_Pos                  (3UL)
#define ADC_SMPR1_SMP1_Msk                  (0x7UL << ADC_SMPR1_SMP1_Pos)           /*!< 0x00000038 */
#define ADC_SMPR1_SMP1                      ADC_SMPR1_SMP1_Msk                      /*!< ADC channel 1 sampling time selection  */
#define ADC_SMPR1_SMP1_0                    (0x1UL << ADC_SMPR1_SMP1_Pos)           /*!< 0x00000008 */
#define ADC_SMPR1_SMP1_1                    (0x2UL << ADC_SMPR1_SMP1_Pos)           /*!< 0x00000010 */
#define ADC_SMPR1_SMP1_2                    (0x4UL << ADC_SMPR1_SMP1_Pos)           /*!< 0x00000020 */

#define ADC_SMPR1_SMP2_Pos                  (6UL)
#define ADC_SMPR1_SMP2_Msk                  (0x7UL << ADC_SMPR1_SMP2_Pos)           /*!< 0x000001C0 */
#define ADC_SMPR1_SMP2                      ADC_SMPR1_SMP2_Msk                      /*!< ADC channel 2 sampling time selection  */
#define ADC_SMPR1_SMP2_0                    (0x1UL << ADC_SMPR1_SMP2_Pos)           /*!< 0x00000040 */
#define ADC_SMPR1_SMP2_1                    (0x2UL << ADC_SMPR1_SMP2_Pos)           /*!< 0x00000080 */
#define ADC_SMPR1_SMP2_2                    (0x4UL << ADC_SMPR1_SMP2_Pos)           /*!< 0x00000100 */

#define ADC_SMPR1_SMP3_Pos                  (9UL)
#define ADC_SMPR1_SMP3_Msk                  (0x7UL << ADC_SMPR1_SMP3_Pos)           /*!< 0x00000E00 */
#define ADC_SMPR1_SMP3                      ADC_SMPR1_SMP3_Msk                      /*!< ADC channel 3 sampling time selection  */
#define ADC_SMPR1_SMP3_0                    (0x1UL << ADC_SMPR1_SMP3_Pos)           /*!< 0x00000200 */
#define ADC_SMPR1_SMP3_1                    (0x2UL << ADC_SMPR1_SMP3_Pos)           /*!< 0x00000400 */
#define ADC_SMPR1_SMP3_2                    (0x4UL << ADC_SMPR1_SMP3_Pos)           /*!< 0x00000800 */

#define ADC_SMPR1_SMP4_Pos                  (12UL)
#define ADC_SMPR1_SMP4_Msk                  (0x7UL << ADC_SMPR1_SMP4_Pos)           /*!< 0x00007000 */
#define ADC_SMPR1_SMP4                      ADC_SMPR1_SMP4_Msk                      /*!< ADC channel 4 sampling time selection  */
#define ADC_SMPR1_SMP4_0                    (0x1UL << ADC_SMPR1_SMP4_Pos)           /*!< 0x00001000 */
#define ADC_SMPR1_SMP4_1                    (0x2UL << ADC_SMPR1_SMP4_Pos)           /*!< 0x00002000 */
#define ADC_SMPR1_SMP4_2                    (0x4UL << ADC_SMPR1_SMP4_Pos)           /*!< 0x00004000 */

#define ADC_SMPR1_SMP5_Pos                  (15UL)
#define ADC_SMPR1_SMP5_Msk                  (0x7UL << ADC_SMPR1_SMP5_Pos)           /*!< 0x00038000 */
#define ADC_SMPR1_SMP5                      ADC_SMPR1_SMP5_Msk                      /*!< ADC channel 5 sampling time selection  */
#define ADC_SMPR1_SMP5_0                    (0x1UL << ADC_SMPR1_SMP5_Pos)           /*!< 0x00008000 */
#define ADC_SMPR1_SMP5_1                    (0x2UL << ADC_SMPR1_SMP5_Pos)           /*!< 0x00010000 */
#define ADC_SMPR1_SMP5_2                    (0x4UL << ADC_SMPR1_SMP5_Pos)           /*!< 0x00020000 */

#define ADC_SMPR1_SMP6_Pos                  (18UL)
#define ADC_SMPR1_SMP6_Msk                  (0x7UL << ADC_SMPR1_SMP6_Pos)           /*!< 0x001C0000 */
#define ADC_SMPR1_SMP6                      ADC_SMPR1_SMP6_Msk                      /*!< ADC channel 6 sampling time selection  */
#define ADC_SMPR1_SMP6_0                    (0x1UL << ADC_SMPR1_SMP6_Pos)           /*!< 0x00040000 */
#define ADC_SMPR1_SMP6_1                    (0x2UL << ADC_SMPR1_SMP6_Pos)           /*!< 0x00080000 */
#define ADC_SMPR1_SMP6_2                    (0x4UL << ADC_SMPR1_SMP6_Pos)           /*!< 0x00100000 */

#define ADC_SMPR1_SMP7_Pos                  (21UL)
#define ADC_SMPR1_SMP7_Msk                  (0x7UL << ADC_SMPR1_SMP7_Pos)           /*!< 0x00E00000 */
#define ADC_SMPR1_SMP7                      ADC_SMPR1_SMP7_Msk                      /*!< ADC channel 7 sampling time selection  */
#define ADC_SMPR1_SMP7_0                    (0x1UL << ADC_SMPR1_SMP7_Pos)           /*!< 0x00200000 */
#define ADC_SMPR1_SMP7_1                    (0x2UL << ADC_SMPR1_SMP7_Pos)           /*!< 0x00400000 */
#define ADC_SMPR1_SMP7_2                    (0x4UL << ADC_SMPR1_SMP7_Pos)           /*!< 0x00800000 */

#define ADC_SMPR1_SMP8_Pos                  (24UL)
#define ADC_SMPR1_SMP8_Msk                  (0x7UL << ADC_SMPR1_SMP8_Pos)           /*!< 0x07000000 */
#define ADC_SMPR1_SMP8                      ADC_SMPR1_SMP8_Msk                      /*!< ADC channel 8 sampling time selection  */
#define ADC_SMPR1_SMP8_0                    (0x1UL << ADC_SMPR1_SMP8_Pos)           /*!< 0x01000000 */
#define ADC_SMPR1_SMP8_1                    (0x2UL << ADC_SMPR1_SMP8_Pos)           /*!< 0x02000000 */
#define ADC_SMPR1_SMP8_2                    (0x4UL << ADC_SMPR1_SMP8_Pos)           /*!< 0x04000000 */

#define ADC_SMPR1_SMP9_Pos                  (27UL)
#define ADC_SMPR1_SMP9_Msk                  (0x7UL << ADC_SMPR1_SMP9_Pos)           /*!< 0x38000000 */
#define ADC_SMPR1_SMP9                      ADC_SMPR1_SMP9_Msk                      /*!< ADC channel 9 sampling time selection  */
#define ADC_SMPR1_SMP9_0                    (0x1UL << ADC_SMPR1_SMP9_Pos)           /*!< 0x08000000 */
#define ADC_SMPR1_SMP9_1                    (0x2UL << ADC_SMPR1_SMP9_Pos)           /*!< 0x10000000 */
#define ADC_SMPR1_SMP9_2                    (0x4UL << ADC_SMPR1_SMP9_Pos)           /*!< 0x20000000 */

/********************  Bit definition for ADC_SMPR2 register  *****************/
#define ADC_SMPR2_SMP10_Pos                 (0UL)
#define ADC_SMPR2_SMP10_Msk                 (0x7UL << ADC_SMPR2_SMP10_Pos)          /*!< 0x00000007 */
#define ADC_SMPR2_SMP10                     ADC_SMPR2_SMP10_Msk                     /*!< ADC channel 10 sampling time selection  */
#define ADC_SMPR2_SMP10_0                   (0x1UL << ADC_SMPR2_SMP10_Pos)          /*!< 0x00000001 */
#define ADC_SMPR2_SMP10_1                   (0x2UL << ADC_SMPR2_SMP10_Pos)          /*!< 0x00000002 */
#define ADC_SMPR2_SMP10_2                   (0x4UL << ADC_SMPR2_SMP10_Pos)          /*!< 0x00000004 */

#define ADC_SMPR2_SMP11_Pos                 (3UL)
#define ADC_SMPR2_SMP11_Msk                 (0x7UL << ADC_SMPR2_SMP11_Pos)          /*!< 0x00000038 */
#define ADC_SMPR2_SMP11                     ADC_SMPR2_SMP11_Msk                     /*!< ADC channel 11 sampling time selection  */
#define ADC_SMPR2_SMP11_0                   (0x1UL << ADC_SMPR2_SMP11_Pos)          /*!< 0x00000008 */
#define ADC_SMPR2_SMP11_1                   (0x2UL << ADC_SMPR2_SMP11_Pos)          /*!< 0x00000010 */
#define ADC_SMPR2_SMP11_2                   (0x4UL << ADC_SMPR2_SMP11_Pos)          /*!< 0x00000020 */

#define ADC_SMPR2_SMP12_Pos                 (6UL)
#define ADC_SMPR2_SMP12_Msk                 (0x7UL << ADC_SMPR2_SMP12_Pos)          /*!< 0x000001C0 */
#define ADC_SMPR2_SMP12                     ADC_SMPR2_SMP12_Msk                     /*!< ADC channel 12 sampling time selection  */
#define ADC_SMPR2_SMP12_0                   (0x1UL << ADC_SMPR2_SMP12_Pos)          /*!< 0x00000040 */
#define ADC_SMPR2_SMP12_1                   (0x2UL << ADC_SMPR2_SMP12_Pos)          /*!< 0x00000080 */
#define ADC_SMPR2_SMP12_2                   (0x4UL << ADC_SMPR2_SMP12_Pos)          /*!< 0x00000100 */

#define ADC_SMPR2_SMP13_Pos                 (9UL)
#define ADC_SMPR2_SMP13_Msk                 (0x7UL << ADC_SMPR2_SMP13_Pos)          /*!< 0x00000E00 */
#define ADC_SMPR2_SMP13                     ADC_SMPR2_SMP13_Msk                     /*!< ADC channel 13 sampling time selection  */
#define ADC_SMPR2_SMP13_0                   (0x1UL << ADC_SMPR2_SMP13_Pos)          /*!< 0x00000200 */
#define ADC_SMPR2_SMP13_1                   (0x2UL << ADC_SMPR2_SMP13_Pos)          /*!< 0x00000400 */
#define ADC_SMPR2_SMP13_2                   (0x4UL << ADC_SMPR2_SMP13_Pos)          /*!< 0x00000800 */

#define ADC_SMPR2_SMP14_Pos                 (12UL)
#define ADC_SMPR2_SMP14_Msk                 (0x7UL << ADC_SMPR2_SMP14_Pos)          /*!< 0x00007000 */
#define ADC_SMPR2_SMP14                     ADC_SMPR2_SMP14_Msk                     /*!< ADC channel 14 sampling time selection  */
#define ADC_SMPR2_SMP14_0                   (0x1UL << ADC_SMPR2_SMP14_Pos)          /*!< 0x00001000 */
#define ADC_SMPR2_SMP14_1                   (0x2UL << ADC_SMPR2_SMP14_Pos)          /*!< 0x00002000 */
#define ADC_SMPR2_SMP14_2                   (0x4UL << ADC_SMPR2_SMP14_Pos)          /*!< 0x00004000 */

#define ADC_SMPR2_SMP15_Pos                 (15UL)
#define ADC_SMPR2_SMP15_Msk                 (0x7UL << ADC_SMPR2_SMP15_Pos)          /*!< 0x00038000 */
#define ADC_SMPR2_SMP15                     ADC_SMPR2_SMP15_Msk                     /*!< ADC channel 15 sampling time selection  */
#define ADC_SMPR2_SMP15_0                   (0x1UL << ADC_SMPR2_SMP15_Pos)          /*!< 0x00008000 */
#define ADC_SMPR2_SMP15_1                   (0x2UL << ADC_SMPR2_SMP15_Pos)          /*!< 0x00010000 */
#define ADC_SMPR2_SMP15_2                   (0x4UL << ADC_SMPR2_SMP15_Pos)          /*!< 0x00020000 */

#define ADC_SMPR2_SMP16_Pos                 (18UL)
#define ADC_SMPR2_SMP16_Msk                 (0x7UL << ADC_SMPR2_SMP16_Pos)          /*!< 0x001C0000 */
#define ADC_SMPR2_SMP16                     ADC_SMPR2_SMP16_Msk                     /*!< ADC channel 16 sampling time selection  */
#define ADC_SMPR2_SMP16_0                   (0x1UL << ADC_SMPR2_SMP16_Pos)          /*!< 0x00040000 */
#define ADC_SMPR2_SMP16_1                   (0x2UL << ADC_SMPR2_SMP16_Pos)          /*!< 0x00080000 */
#define ADC_SMPR2_SMP16_2                   (0x4UL << ADC_SMPR2_SMP16_Pos)          /*!< 0x00100000 */

#define ADC_SMPR2_SMP17_Pos                 (21UL)
#define ADC_SMPR2_SMP17_Msk                 (0x7UL << ADC_SMPR2_SMP17_Pos)          /*!< 0x00E00000 */
#define ADC_SMPR2_SMP17                     ADC_SMPR2_SMP17_Msk                     /*!< ADC channel 17 sampling time selection  */
#define ADC_SMPR2_SMP17_0                   (0x1UL << ADC_SMPR2_SMP17_Pos)          /*!< 0x00200000 */
#define ADC_SMPR2_SMP17_1                   (0x2UL << ADC_SMPR2_SMP17_Pos)          /*!< 0x00400000 */
#define ADC_SMPR2_SMP17_2                   (0x4UL << ADC_SMPR2_SMP17_Pos)          /*!< 0x00800000 */

#define ADC_SMPR2_SMP18_Pos                 (24UL)
#define ADC_SMPR2_SMP18_Msk                 (0x7UL << ADC_SMPR2_SMP18_Pos)          /*!< 0x07000000 */
#define ADC_SMPR2_SMP18                     ADC_SMPR2_SMP18_Msk                     /*!< ADC channel 18 sampling time selection  */
#define ADC_SMPR2_SMP18_0                   (0x1UL << ADC_SMPR2_SMP18_Pos)          /*!< 0x01000000 */
#define ADC_SMPR2_SMP18_1                   (0x2UL << ADC_SMPR2_SMP18_Pos)          /*!< 0x02000000 */
#define ADC_SMPR2_SMP18_2                   (0x4UL << ADC_SMPR2_SMP18_Pos)          /*!< 0x04000000 */

#define ADC_SMPR2_SMP19_Pos                 (27UL)
#define ADC_SMPR2_SMP19_Msk                 (0x7UL << ADC_SMPR2_SMP19_Pos)          /*!< 0x38000000 */
#define ADC_SMPR2_SMP19                     ADC_SMPR2_SMP19_Msk                     /*!< ADC Channel 19 Sampling time selection  */
#define ADC_SMPR2_SMP19_0                   (0x1UL << ADC_SMPR2_SMP19_Pos)          /*!< 0x08000000 */
#define ADC_SMPR2_SMP19_1                   (0x2UL << ADC_SMPR2_SMP19_Pos)          /*!< 0x10000000 */
#define ADC_SMPR2_SMP19_2                   (0x4UL << ADC_SMPR2_SMP19_Pos)          /*!< 0x20000000 */

/********************  Bit definition for ADC_PCSEL register  *****************/
#define ADC_PCSEL_PCSEL_Pos                 (0UL)
#define ADC_PCSEL_PCSEL_Msk                 (0xFFFFFUL << ADC_PCSEL_PCSEL_Pos)    /*!< 0x000FFFFF */
#define ADC_PCSEL_PCSEL                     ADC_PCSEL_PCSEL_Msk                   /*!< ADC channel preselection */
#define ADC_PCSEL_PCSEL_0                   (0x00001UL << ADC_PCSEL_PCSEL_Pos)    /*!< 0x00000001 */
#define ADC_PCSEL_PCSEL_1                   (0x00002UL << ADC_PCSEL_PCSEL_Pos)    /*!< 0x00000002 */
#define ADC_PCSEL_PCSEL_2                   (0x00004UL << ADC_PCSEL_PCSEL_Pos)    /*!< 0x00000004 */
#define ADC_PCSEL_PCSEL_3                   (0x00008UL << ADC_PCSEL_PCSEL_Pos)    /*!< 0x00000008 */
#define ADC_PCSEL_PCSEL_4                   (0x00010UL << ADC_PCSEL_PCSEL_Pos)    /*!< 0x00000010 */
#define ADC_PCSEL_PCSEL_5                   (0x00020UL << ADC_PCSEL_PCSEL_Pos)    /*!< 0x00000020 */
#define ADC_PCSEL_PCSEL_6                   (0x00040UL << ADC_PCSEL_PCSEL_Pos)    /*!< 0x00000040 */
#define ADC_PCSEL_PCSEL_7                   (0x00080UL << ADC_PCSEL_PCSEL_Pos)    /*!< 0x00000080 */
#define ADC_PCSEL_PCSEL_8                   (0x00100UL << ADC_PCSEL_PCSEL_Pos)    /*!< 0x00000100 */
#define ADC_PCSEL_PCSEL_9                   (0x00200UL << ADC_PCSEL_PCSEL_Pos)    /*!< 0x00000200 */
#define ADC_PCSEL_PCSEL_10                  (0x00400UL << ADC_PCSEL_PCSEL_Pos)    /*!< 0x00000400 */
#define ADC_PCSEL_PCSEL_11                  (0x00800UL << ADC_PCSEL_PCSEL_Pos)    /*!< 0x00000800 */
#define ADC_PCSEL_PCSEL_12                  (0x01000UL << ADC_PCSEL_PCSEL_Pos)    /*!< 0x00001000 */
#define ADC_PCSEL_PCSEL_13                  (0x02000UL << ADC_PCSEL_PCSEL_Pos)    /*!< 0x00002000 */
#define ADC_PCSEL_PCSEL_14                  (0x04000UL << ADC_PCSEL_PCSEL_Pos)    /*!< 0x00004000 */
#define ADC_PCSEL_PCSEL_15                  (0x08000UL << ADC_PCSEL_PCSEL_Pos)    /*!< 0x00008000 */
#define ADC_PCSEL_PCSEL_16                  (0x10000UL << ADC_PCSEL_PCSEL_Pos)    /*!< 0x00010000 */
#define ADC_PCSEL_PCSEL_17                  (0x20000UL << ADC_PCSEL_PCSEL_Pos)    /*!< 0x00020000 */
#define ADC_PCSEL_PCSEL_18                  (0x40000UL << ADC_PCSEL_PCSEL_Pos)    /*!< 0x00040000 */

/********************  Bit definition for ADC_SQR1 register  ******************/
#define ADC_SQR1_L_Pos                      (0UL)
#define ADC_SQR1_L_Msk                      (0xFUL << ADC_SQR1_L_Pos)               /*!< 0x0000000F */
#define ADC_SQR1_L                          ADC_SQR1_L_Msk                          /*!< ADC group regular sequencer scan length */
#define ADC_SQR1_L_0                        (0x1UL << ADC_SQR1_L_Pos)               /*!< 0x00000001 */
#define ADC_SQR1_L_1                        (0x2UL << ADC_SQR1_L_Pos)               /*!< 0x00000002 */
#define ADC_SQR1_L_2                        (0x4UL << ADC_SQR1_L_Pos)               /*!< 0x00000004 */
#define ADC_SQR1_L_3                        (0x8UL << ADC_SQR1_L_Pos)               /*!< 0x00000008 */

#define ADC_SQR1_SQ1_Pos                    (6UL)
#define ADC_SQR1_SQ1_Msk                    (0x1FUL << ADC_SQR1_SQ1_Pos)            /*!< 0x000007C0 */
#define ADC_SQR1_SQ1                        ADC_SQR1_SQ1_Msk                        /*!< ADC group regular sequencer rank 1 */
#define ADC_SQR1_SQ1_0                      (0x01UL << ADC_SQR1_SQ1_Pos)            /*!< 0x00000040 */
#define ADC_SQR1_SQ1_1                      (0x02UL << ADC_SQR1_SQ1_Pos)            /*!< 0x00000080 */
#define ADC_SQR1_SQ1_2                      (0x04UL << ADC_SQR1_SQ1_Pos)            /*!< 0x00000100 */
#define ADC_SQR1_SQ1_3                      (0x08UL << ADC_SQR1_SQ1_Pos)            /*!< 0x00000200 */
#define ADC_SQR1_SQ1_4                      (0x10UL << ADC_SQR1_SQ1_Pos)            /*!< 0x00000400 */

#define ADC_SQR1_SQ2_Pos                    (12UL)
#define ADC_SQR1_SQ2_Msk                    (0x1FUL << ADC_SQR1_SQ2_Pos)            /*!< 0x0001F000 */
#define ADC_SQR1_SQ2                        ADC_SQR1_SQ2_Msk                        /*!< ADC group regular sequencer rank 2 */
#define ADC_SQR1_SQ2_0                      (0x01UL << ADC_SQR1_SQ2_Pos)            /*!< 0x00001000 */
#define ADC_SQR1_SQ2_1                      (0x02UL << ADC_SQR1_SQ2_Pos)            /*!< 0x00002000 */
#define ADC_SQR1_SQ2_2                      (0x04UL << ADC_SQR1_SQ2_Pos)            /*!< 0x00004000 */
#define ADC_SQR1_SQ2_3                      (0x08UL << ADC_SQR1_SQ2_Pos)            /*!< 0x00008000 */
#define ADC_SQR1_SQ2_4                      (0x10UL << ADC_SQR1_SQ2_Pos)            /*!< 0x00010000 */

#define ADC_SQR1_SQ3_Pos                    (18UL)
#define ADC_SQR1_SQ3_Msk                    (0x1FUL << ADC_SQR1_SQ3_Pos)            /*!< 0x007C0000 */
#define ADC_SQR1_SQ3                        ADC_SQR1_SQ3_Msk                        /*!< ADC group regular sequencer rank 3 */
#define ADC_SQR1_SQ3_0                      (0x01UL << ADC_SQR1_SQ3_Pos)            /*!< 0x00040000 */
#define ADC_SQR1_SQ3_1                      (0x02UL << ADC_SQR1_SQ3_Pos)            /*!< 0x00080000 */
#define ADC_SQR1_SQ3_2                      (0x04UL << ADC_SQR1_SQ3_Pos)            /*!< 0x00100000 */
#define ADC_SQR1_SQ3_3                      (0x08UL << ADC_SQR1_SQ3_Pos)            /*!< 0x00200000 */
#define ADC_SQR1_SQ3_4                      (0x10UL << ADC_SQR1_SQ3_Pos)            /*!< 0x00400000 */

#define ADC_SQR1_SQ4_Pos                    (24UL)
#define ADC_SQR1_SQ4_Msk                    (0x1FUL << ADC_SQR1_SQ4_Pos)            /*!< 0x1F000000 */
#define ADC_SQR1_SQ4                        ADC_SQR1_SQ4_Msk                        /*!< ADC group regular sequencer rank 4 */
#define ADC_SQR1_SQ4_0                      (0x01UL << ADC_SQR1_SQ4_Pos)            /*!< 0x01000000 */
#define ADC_SQR1_SQ4_1                      (0x02UL << ADC_SQR1_SQ4_Pos)            /*!< 0x02000000 */
#define ADC_SQR1_SQ4_2                      (0x04UL << ADC_SQR1_SQ4_Pos)            /*!< 0x04000000 */
#define ADC_SQR1_SQ4_3                      (0x08UL << ADC_SQR1_SQ4_Pos)            /*!< 0x08000000 */
#define ADC_SQR1_SQ4_4                      (0x10UL << ADC_SQR1_SQ4_Pos)            /*!< 0x10000000 */

/********************  Bit definition for ADC_SQR2 register  ******************/
#define ADC_SQR2_SQ5_Pos                    (0UL)
#define ADC_SQR2_SQ5_Msk                    (0x1FUL << ADC_SQR2_SQ5_Pos)            /*!< 0x0000001F */
#define ADC_SQR2_SQ5                        ADC_SQR2_SQ5_Msk                        /*!< ADC group regular sequencer rank 5 */
#define ADC_SQR2_SQ5_0                      (0x01UL << ADC_SQR2_SQ5_Pos)            /*!< 0x00000001 */
#define ADC_SQR2_SQ5_1                      (0x02UL << ADC_SQR2_SQ5_Pos)            /*!< 0x00000002 */
#define ADC_SQR2_SQ5_2                      (0x04UL << ADC_SQR2_SQ5_Pos)            /*!< 0x00000004 */
#define ADC_SQR2_SQ5_3                      (0x08UL << ADC_SQR2_SQ5_Pos)            /*!< 0x00000008 */
#define ADC_SQR2_SQ5_4                      (0x10UL << ADC_SQR2_SQ5_Pos)            /*!< 0x00000010 */

#define ADC_SQR2_SQ6_Pos                    (6UL)
#define ADC_SQR2_SQ6_Msk                    (0x1FUL << ADC_SQR2_SQ6_Pos)            /*!< 0x000007C0 */
#define ADC_SQR2_SQ6                        ADC_SQR2_SQ6_Msk                        /*!< ADC group regular sequencer rank 6 */
#define ADC_SQR2_SQ6_0                      (0x01UL << ADC_SQR2_SQ6_Pos)            /*!< 0x00000040 */
#define ADC_SQR2_SQ6_1                      (0x02UL << ADC_SQR2_SQ6_Pos)            /*!< 0x00000080 */
#define ADC_SQR2_SQ6_2                      (0x04UL << ADC_SQR2_SQ6_Pos)            /*!< 0x00000100 */
#define ADC_SQR2_SQ6_3                      (0x08UL << ADC_SQR2_SQ6_Pos)            /*!< 0x00000200 */
#define ADC_SQR2_SQ6_4                      (0x10UL << ADC_SQR2_SQ6_Pos)            /*!< 0x00000400 */

#define ADC_SQR2_SQ7_Pos                    (12UL)
#define ADC_SQR2_SQ7_Msk                    (0x1FUL << ADC_SQR2_SQ7_Pos)            /*!< 0x0001F000 */
#define ADC_SQR2_SQ7                        ADC_SQR2_SQ7_Msk                        /*!< ADC group regular sequencer rank 7 */
#define ADC_SQR2_SQ7_0                      (0x01UL << ADC_SQR2_SQ7_Pos)            /*!< 0x00001000 */
#define ADC_SQR2_SQ7_1                      (0x02UL << ADC_SQR2_SQ7_Pos)            /*!< 0x00002000 */
#define ADC_SQR2_SQ7_2                      (0x04UL << ADC_SQR2_SQ7_Pos)            /*!< 0x00004000 */
#define ADC_SQR2_SQ7_3                      (0x08UL << ADC_SQR2_SQ7_Pos)            /*!< 0x00008000 */
#define ADC_SQR2_SQ7_4                      (0x10UL << ADC_SQR2_SQ7_Pos)            /*!< 0x00010000 */

#define ADC_SQR2_SQ8_Pos                    (18UL)
#define ADC_SQR2_SQ8_Msk                    (0x1FUL << ADC_SQR2_SQ8_Pos)            /*!< 0x007C0000 */
#define ADC_SQR2_SQ8                        ADC_SQR2_SQ8_Msk                        /*!< ADC group regular sequencer rank 8 */
#define ADC_SQR2_SQ8_0                      (0x01UL << ADC_SQR2_SQ8_Pos)            /*!< 0x00040000 */
#define ADC_SQR2_SQ8_1                      (0x02UL << ADC_SQR2_SQ8_Pos)            /*!< 0x00080000 */
#define ADC_SQR2_SQ8_2                      (0x04UL << ADC_SQR2_SQ8_Pos)            /*!< 0x00100000 */
#define ADC_SQR2_SQ8_3                      (0x08UL << ADC_SQR2_SQ8_Pos)            /*!< 0x00200000 */
#define ADC_SQR2_SQ8_4                      (0x10UL << ADC_SQR2_SQ8_Pos)            /*!< 0x00400000 */

#define ADC_SQR2_SQ9_Pos                    (24UL)
#define ADC_SQR2_SQ9_Msk                    (0x1FUL << ADC_SQR2_SQ9_Pos)            /*!< 0x1F000000 */
#define ADC_SQR2_SQ9                        ADC_SQR2_SQ9_Msk                        /*!< ADC group regular sequencer rank 9 */
#define ADC_SQR2_SQ9_0                      (0x01UL << ADC_SQR2_SQ9_Pos)            /*!< 0x01000000 */
#define ADC_SQR2_SQ9_1                      (0x02UL << ADC_SQR2_SQ9_Pos)            /*!< 0x02000000 */
#define ADC_SQR2_SQ9_2                      (0x04UL << ADC_SQR2_SQ9_Pos)            /*!< 0x04000000 */
#define ADC_SQR2_SQ9_3                      (0x08UL << ADC_SQR2_SQ9_Pos)            /*!< 0x08000000 */
#define ADC_SQR2_SQ9_4                      (0x10UL << ADC_SQR2_SQ9_Pos)            /*!< 0x10000000 */

/********************  Bit definition for ADC_SQR3 register  ******************/
#define ADC_SQR3_SQ10_Pos                   (0UL)
#define ADC_SQR3_SQ10_Msk                   (0x1FUL << ADC_SQR3_SQ10_Pos)           /*!< 0x0000001F */
#define ADC_SQR3_SQ10                       ADC_SQR3_SQ10_Msk                       /*!< ADC group regular sequencer rank 10 */
#define ADC_SQR3_SQ10_0                     (0x01UL << ADC_SQR3_SQ10_Pos)           /*!< 0x00000001 */
#define ADC_SQR3_SQ10_1                     (0x02UL << ADC_SQR3_SQ10_Pos)           /*!< 0x00000002 */
#define ADC_SQR3_SQ10_2                     (0x04UL << ADC_SQR3_SQ10_Pos)           /*!< 0x00000004 */
#define ADC_SQR3_SQ10_3                     (0x08UL << ADC_SQR3_SQ10_Pos)           /*!< 0x00000008 */
#define ADC_SQR3_SQ10_4                     (0x10UL << ADC_SQR3_SQ10_Pos)           /*!< 0x00000010 */

#define ADC_SQR3_SQ11_Pos                   (6UL)
#define ADC_SQR3_SQ11_Msk                   (0x1FUL << ADC_SQR3_SQ11_Pos)           /*!< 0x000007C0 */
#define ADC_SQR3_SQ11                       ADC_SQR3_SQ11_Msk                       /*!< ADC group regular sequencer rank 11 */
#define ADC_SQR3_SQ11_0                     (0x01UL << ADC_SQR3_SQ11_Pos)           /*!< 0x00000040 */
#define ADC_SQR3_SQ11_1                     (0x02UL << ADC_SQR3_SQ11_Pos)           /*!< 0x00000080 */
#define ADC_SQR3_SQ11_2                     (0x04UL << ADC_SQR3_SQ11_Pos)           /*!< 0x00000100 */
#define ADC_SQR3_SQ11_3                     (0x08UL << ADC_SQR3_SQ11_Pos)           /*!< 0x00000200 */
#define ADC_SQR3_SQ11_4                     (0x10UL << ADC_SQR3_SQ11_Pos)           /*!< 0x00000400 */

#define ADC_SQR3_SQ12_Pos                   (12UL)
#define ADC_SQR3_SQ12_Msk                   (0x1FUL << ADC_SQR3_SQ12_Pos)           /*!< 0x0001F000 */
#define ADC_SQR3_SQ12                       ADC_SQR3_SQ12_Msk                       /*!< ADC group regular sequencer rank 12 */
#define ADC_SQR3_SQ12_0                     (0x01UL << ADC_SQR3_SQ12_Pos)           /*!< 0x00001000 */
#define ADC_SQR3_SQ12_1                     (0x02UL << ADC_SQR3_SQ12_Pos)           /*!< 0x00002000 */
#define ADC_SQR3_SQ12_2                     (0x04UL << ADC_SQR3_SQ12_Pos)           /*!< 0x00004000 */
#define ADC_SQR3_SQ12_3                     (0x08UL << ADC_SQR3_SQ12_Pos)           /*!< 0x00008000 */
#define ADC_SQR3_SQ12_4                     (0x10UL << ADC_SQR3_SQ12_Pos)           /*!< 0x00010000 */

#define ADC_SQR3_SQ13_Pos                   (18UL)
#define ADC_SQR3_SQ13_Msk                   (0x1FUL << ADC_SQR3_SQ13_Pos)           /*!< 0x007C0000 */
#define ADC_SQR3_SQ13                       ADC_SQR3_SQ13_Msk                       /*!< ADC group regular sequencer rank 13 */
#define ADC_SQR3_SQ13_0                     (0x01UL << ADC_SQR3_SQ13_Pos)           /*!< 0x00040000 */
#define ADC_SQR3_SQ13_1                     (0x02UL << ADC_SQR3_SQ13_Pos)           /*!< 0x00080000 */
#define ADC_SQR3_SQ13_2                     (0x04UL << ADC_SQR3_SQ13_Pos)           /*!< 0x00100000 */
#define ADC_SQR3_SQ13_3                     (0x08UL << ADC_SQR3_SQ13_Pos)           /*!< 0x00200000 */
#define ADC_SQR3_SQ13_4                     (0x10UL << ADC_SQR3_SQ13_Pos)           /*!< 0x00400000 */

#define ADC_SQR3_SQ14_Pos                   (24UL)
#define ADC_SQR3_SQ14_Msk                   (0x1FUL << ADC_SQR3_SQ14_Pos)           /*!< 0x1F000000 */
#define ADC_SQR3_SQ14                       ADC_SQR3_SQ14_Msk                       /*!< ADC group regular sequencer rank 14 */
#define ADC_SQR3_SQ14_0                     (0x01UL << ADC_SQR3_SQ14_Pos)           /*!< 0x01000000 */
#define ADC_SQR3_SQ14_1                     (0x02UL << ADC_SQR3_SQ14_Pos)           /*!< 0x02000000 */
#define ADC_SQR3_SQ14_2                     (0x04UL << ADC_SQR3_SQ14_Pos)           /*!< 0x04000000 */
#define ADC_SQR3_SQ14_3                     (0x08UL << ADC_SQR3_SQ14_Pos)           /*!< 0x08000000 */
#define ADC_SQR3_SQ14_4                     (0x10UL << ADC_SQR3_SQ14_Pos)           /*!< 0x10000000 */

/********************  Bit definition for ADC_SQR4 register  ******************/
#define ADC_SQR4_SQ15_Pos                   (0UL)
#define ADC_SQR4_SQ15_Msk                   (0x1FUL << ADC_SQR4_SQ15_Pos)           /*!< 0x0000001F */
#define ADC_SQR4_SQ15                       ADC_SQR4_SQ15_Msk                       /*!< ADC group regular sequencer rank 15 */
#define ADC_SQR4_SQ15_0                     (0x01UL << ADC_SQR4_SQ15_Pos)           /*!< 0x00000001 */
#define ADC_SQR4_SQ15_1                     (0x02UL << ADC_SQR4_SQ15_Pos)           /*!< 0x00000002 */
#define ADC_SQR4_SQ15_2                     (0x04UL << ADC_SQR4_SQ15_Pos)           /*!< 0x00000004 */
#define ADC_SQR4_SQ15_3                     (0x08UL << ADC_SQR4_SQ15_Pos)           /*!< 0x00000008 */
#define ADC_SQR4_SQ15_4                     (0x10UL << ADC_SQR4_SQ15_Pos)           /*!< 0x00000010 */

#define ADC_SQR4_SQ16_Pos                   (6UL)
#define ADC_SQR4_SQ16_Msk                   (0x1FUL << ADC_SQR4_SQ16_Pos)           /*!< 0x000007C0 */
#define ADC_SQR4_SQ16                       ADC_SQR4_SQ16_Msk                       /*!< ADC group regular sequencer rank 16 */
#define ADC_SQR4_SQ16_0                     (0x01UL << ADC_SQR4_SQ16_Pos)           /*!< 0x00000040 */
#define ADC_SQR4_SQ16_1                     (0x02UL << ADC_SQR4_SQ16_Pos)           /*!< 0x00000080 */
#define ADC_SQR4_SQ16_2                     (0x04UL << ADC_SQR4_SQ16_Pos)           /*!< 0x00000100 */
#define ADC_SQR4_SQ16_3                     (0x08UL << ADC_SQR4_SQ16_Pos)           /*!< 0x00000200 */
#define ADC_SQR4_SQ16_4                     (0x10UL << ADC_SQR4_SQ16_Pos)           /*!< 0x00000400 */

/********************  Bit definition for ADC_DR register  ********************/
#define ADC_DR_RDATA_Pos                    (0UL)
#define ADC_DR_RDATA_Msk                    (0xFFFFFFFFUL << ADC_DR_RDATA_Pos)      /*!< 0xFFFFFFFF */
#define ADC_DR_RDATA                        ADC_DR_RDATA_Msk                        /*!< ADC group regular conversion data */
#define ADC_DR_RDATA_0                      (0x00000001UL << ADC_DR_RDATA_Pos)      /*!< 0x00000001 */
#define ADC_DR_RDATA_1                      (0x00000002UL << ADC_DR_RDATA_Pos)      /*!< 0x00000002 */
#define ADC_DR_RDATA_2                      (0x00000004UL << ADC_DR_RDATA_Pos)      /*!< 0x00000004 */
#define ADC_DR_RDATA_3                      (0x00000008UL << ADC_DR_RDATA_Pos)      /*!< 0x00000008 */
#define ADC_DR_RDATA_4                      (0x00000010UL << ADC_DR_RDATA_Pos)      /*!< 0x00000010 */
#define ADC_DR_RDATA_5                      (0x00000020UL << ADC_DR_RDATA_Pos)      /*!< 0x00000020 */
#define ADC_DR_RDATA_6                      (0x00000040UL << ADC_DR_RDATA_Pos)      /*!< 0x00000040 */
#define ADC_DR_RDATA_7                      (0x00000080UL << ADC_DR_RDATA_Pos)      /*!< 0x00000080 */
#define ADC_DR_RDATA_8                      (0x00000100UL << ADC_DR_RDATA_Pos)      /*!< 0x00000100 */
#define ADC_DR_RDATA_9                      (0x00000200UL << ADC_DR_RDATA_Pos)      /*!< 0x00000200 */
#define ADC_DR_RDATA_10                     (0x00000400UL << ADC_DR_RDATA_Pos)      /*!< 0x00000400 */
#define ADC_DR_RDATA_11                     (0x00000800UL << ADC_DR_RDATA_Pos)      /*!< 0x00000800 */
#define ADC_DR_RDATA_12                     (0x00001000UL << ADC_DR_RDATA_Pos)      /*!< 0x00001000 */
#define ADC_DR_RDATA_13                     (0x00002000UL << ADC_DR_RDATA_Pos)      /*!< 0x00002000 */
#define ADC_DR_RDATA_14                     (0x00004000UL << ADC_DR_RDATA_Pos)      /*!< 0x00004000 */
#define ADC_DR_RDATA_15                     (0x00008000UL << ADC_DR_RDATA_Pos)      /*!< 0x00008000 */
#define ADC_DR_RDATA_16                     (0x00010000UL << ADC_DR_RDATA_Pos)      /*!< 0x00010000 */
#define ADC_DR_RDATA_17                     (0x00020000UL << ADC_DR_RDATA_Pos)      /*!< 0x00020000 */
#define ADC_DR_RDATA_18                     (0x00040000UL << ADC_DR_RDATA_Pos)      /*!< 0x00040000 */
#define ADC_DR_RDATA_19                     (0x00080000UL << ADC_DR_RDATA_Pos)      /*!< 0x00080000 */
#define ADC_DR_RDATA_20                     (0x00100000UL << ADC_DR_RDATA_Pos)      /*!< 0x00100000 */
#define ADC_DR_RDATA_21                     (0x00200000UL << ADC_DR_RDATA_Pos)      /*!< 0x00200000 */
#define ADC_DR_RDATA_22                     (0x00400000UL << ADC_DR_RDATA_Pos)      /*!< 0x00400000 */
#define ADC_DR_RDATA_23                     (0x00800000UL << ADC_DR_RDATA_Pos)      /*!< 0x00800000 */
#define ADC_DR_RDATA_24                     (0x01000000UL << ADC_DR_RDATA_Pos)      /*!< 0x01000000 */
#define ADC_DR_RDATA_25                     (0x02000000UL << ADC_DR_RDATA_Pos)      /*!< 0x02000000 */
#define ADC_DR_RDATA_26                     (0x04000000UL << ADC_DR_RDATA_Pos)      /*!< 0x04000000 */
#define ADC_DR_RDATA_27                     (0x08000000UL << ADC_DR_RDATA_Pos)      /*!< 0x08000000 */
#define ADC_DR_RDATA_28                     (0x10000000UL << ADC_DR_RDATA_Pos)      /*!< 0x10000000 */
#define ADC_DR_RDATA_29                     (0x20000000UL << ADC_DR_RDATA_Pos)      /*!< 0x20000000 */
#define ADC_DR_RDATA_30                     (0x40000000UL << ADC_DR_RDATA_Pos)      /*!< 0x40000000 */
#define ADC_DR_RDATA_31                     (0x80000000UL << ADC_DR_RDATA_Pos)      /*!< 0x80000000 */

/********************  Bit definition for ADC_JSQR register  ******************/
#define ADC_JSQR_JL_Pos                     (0UL)
#define ADC_JSQR_JL_Msk                     (0x3UL << ADC_JSQR_JL_Pos)              /*!< 0x00000003 */
#define ADC_JSQR_JL                         ADC_JSQR_JL_Msk                         /*!< ADC group injected sequencer scan length */
#define ADC_JSQR_JL_0                       (0x1UL << ADC_JSQR_JL_Pos)              /*!< 0x00000001 */
#define ADC_JSQR_JL_1                       (0x2UL << ADC_JSQR_JL_Pos)              /*!< 0x00000002 */

#define ADC_JSQR_JEXTSEL_Pos                (2UL)
#define ADC_JSQR_JEXTSEL_Msk                (0x1FUL << ADC_JSQR_JEXTSEL_Pos)        /*!< 0x0000007C */
#define ADC_JSQR_JEXTSEL                    ADC_JSQR_JEXTSEL_Msk                    /*!< ADC group injected external trigger source */
#define ADC_JSQR_JEXTSEL_0                  (0x01UL << ADC_JSQR_JEXTSEL_Pos)        /*!< 0x00000004 */
#define ADC_JSQR_JEXTSEL_1                  (0x02UL << ADC_JSQR_JEXTSEL_Pos)        /*!< 0x00000008 */
#define ADC_JSQR_JEXTSEL_2                  (0x04UL << ADC_JSQR_JEXTSEL_Pos)        /*!< 0x00000010 */
#define ADC_JSQR_JEXTSEL_3                  (0x08UL << ADC_JSQR_JEXTSEL_Pos)        /*!< 0x00000020 */
#define ADC_JSQR_JEXTSEL_4                  (0x10UL << ADC_JSQR_JEXTSEL_Pos)        /*!< 0x00000040 */

#define ADC_JSQR_JEXTEN_Pos                 (7UL)
#define ADC_JSQR_JEXTEN_Msk                 (0x3UL << ADC_JSQR_JEXTEN_Pos)          /*!< 0x00000180 */
#define ADC_JSQR_JEXTEN                     ADC_JSQR_JEXTEN_Msk                     /*!< ADC group injected external trigger polarity */
#define ADC_JSQR_JEXTEN_0                   (0x1UL << ADC_JSQR_JEXTEN_Pos)          /*!< 0x00000080 */
#define ADC_JSQR_JEXTEN_1                   (0x2UL << ADC_JSQR_JEXTEN_Pos)          /*!< 0x00000100 */

#define ADC_JSQR_JSQ1_Pos                   (9UL)
#define ADC_JSQR_JSQ1_Msk                   (0x1FUL << ADC_JSQR_JSQ1_Pos)           /*!< 0x00003E00 */
#define ADC_JSQR_JSQ1                       ADC_JSQR_JSQ1_Msk                       /*!< ADC group injected sequencer rank 1 */
#define ADC_JSQR_JSQ1_0                     (0x01UL << ADC_JSQR_JSQ1_Pos)           /*!< 0x00000200 */
#define ADC_JSQR_JSQ1_1                     (0x02UL << ADC_JSQR_JSQ1_Pos)           /*!< 0x00000400 */
#define ADC_JSQR_JSQ1_2                     (0x04UL << ADC_JSQR_JSQ1_Pos)           /*!< 0x00000800 */
#define ADC_JSQR_JSQ1_3                     (0x08UL << ADC_JSQR_JSQ1_Pos)           /*!< 0x00001000 */
#define ADC_JSQR_JSQ1_4                     (0x10UL << ADC_JSQR_JSQ1_Pos)           /*!< 0x00002000 */

#define ADC_JSQR_JSQ2_Pos                   (15UL)
#define ADC_JSQR_JSQ2_Msk                   (0x1FUL << ADC_JSQR_JSQ2_Pos)           /*!< 0x000F8000 */
#define ADC_JSQR_JSQ2                       ADC_JSQR_JSQ2_Msk                       /*!< ADC group injected sequencer rank 2 */
#define ADC_JSQR_JSQ2_0                     (0x01UL << ADC_JSQR_JSQ2_Pos)           /*!< 0x00008000 */
#define ADC_JSQR_JSQ2_1                     (0x02UL << ADC_JSQR_JSQ2_Pos)           /*!< 0x00010000 */
#define ADC_JSQR_JSQ2_2                     (0x04UL << ADC_JSQR_JSQ2_Pos)           /*!< 0x00020000 */
#define ADC_JSQR_JSQ2_3                     (0x08UL << ADC_JSQR_JSQ2_Pos)           /*!< 0x00040000 */
#define ADC_JSQR_JSQ2_4                     (0x10UL << ADC_JSQR_JSQ2_Pos)           /*!< 0x00080000 */

#define ADC_JSQR_JSQ3_Pos                   (21UL)
#define ADC_JSQR_JSQ3_Msk                   (0x1FUL << ADC_JSQR_JSQ3_Pos)           /*!< 0x03E00000 */
#define ADC_JSQR_JSQ3                       ADC_JSQR_JSQ3_Msk                       /*!< ADC group injected sequencer rank 3 */
#define ADC_JSQR_JSQ3_0                     (0x01UL << ADC_JSQR_JSQ3_Pos)           /*!< 0x00200000 */
#define ADC_JSQR_JSQ3_1                     (0x02UL << ADC_JSQR_JSQ3_Pos)           /*!< 0x00400000 */
#define ADC_JSQR_JSQ3_2                     (0x04UL << ADC_JSQR_JSQ3_Pos)           /*!< 0x00800000 */
#define ADC_JSQR_JSQ3_3                     (0x08UL << ADC_JSQR_JSQ3_Pos)           /*!< 0x01000000 */
#define ADC_JSQR_JSQ3_4                     (0x10UL << ADC_JSQR_JSQ3_Pos)           /*!< 0x02000000 */

#define ADC_JSQR_JSQ4_Pos                   (27UL)
#define ADC_JSQR_JSQ4_Msk                   (0x1FUL << ADC_JSQR_JSQ4_Pos)           /*!< 0xF8000000 */
#define ADC_JSQR_JSQ4                       ADC_JSQR_JSQ4_Msk                       /*!< ADC group injected sequencer rank 4 */
#define ADC_JSQR_JSQ4_0                     (0x01UL << ADC_JSQR_JSQ4_Pos)           /*!< 0x08000000 */
#define ADC_JSQR_JSQ4_1                     (0x02UL << ADC_JSQR_JSQ4_Pos)           /*!< 0x10000000 */
#define ADC_JSQR_JSQ4_2                     (0x04UL << ADC_JSQR_JSQ4_Pos)           /*!< 0x20000000 */
#define ADC_JSQR_JSQ4_3                     (0x08UL << ADC_JSQR_JSQ4_Pos)           /*!< 0x40000000 */
#define ADC_JSQR_JSQ4_4                     (0x10UL << ADC_JSQR_JSQ4_Pos)           /*!< 0x80000000 */

/********************  Bit definition for ADC_OFCFGR1 register  ***************/
#define ADC_OFCFGR1_POSOFF_Pos              (24UL)
#define ADC_OFCFGR1_POSOFF_Msk              (0x01UL << ADC_OFCFGR1_POSOFF_Pos)      /*!< 0x01000000 */
#define ADC_OFCFGR1_POSOFF                  ADC_OFCFGR1_POSOFF_Msk                  /*!< ADC offset instance 1 positive offset enable */

#define ADC_OFCFGR1_USAT_Pos                (25UL)
#define ADC_OFCFGR1_USAT_Msk                (0x01UL << ADC_OFCFGR1_USAT_Pos)        /*!< 0x02000000 */
#define ADC_OFCFGR1_USAT                    ADC_OFCFGR1_USAT_Msk                    /*!< ADC offset instance 1  unsigned saturation value */

#define ADC_OFCFGR1_SSAT_Pos                (26UL)
#define ADC_OFCFGR1_SSAT_Msk                (0x01UL << ADC_OFCFGR1_SSAT_Pos)        /*!< 0x04000000 */
#define ADC_OFCFGR1_SSAT                    ADC_OFCFGR1_SSAT_Msk                    /*!< ADC offset instance 1 signed satuaration enable */

#define ADC_OFCFGR1_OFFSET_CH_Pos           (27UL)
#define ADC_OFCFGR1_OFFSET_CH_Msk           (0x1FUL << ADC_OFCFGR1_OFFSET_CH_Pos)   /*!< 0xF8000000 */
#define ADC_OFCFGR1_OFFSET_CH               ADC_OFCFGR1_OFFSET_CH_Msk               /*!< ADC offset instance 1 channel selection */
#define ADC_OFCFGR1_OFFSET_CH_0             (0x01UL << ADC_OFCFGR1_OFFSET_CH_Pos)   /*!< 0x08000000 */
#define ADC_OFCFGR1_OFFSET_CH_1             (0x02UL << ADC_OFCFGR1_OFFSET_CH_Pos)   /*!< 0x10000000 */
#define ADC_OFCFGR1_OFFSET_CH_2             (0x03UL << ADC_OFCFGR1_OFFSET_CH_Pos)   /*!< 0x20000000 */
#define ADC_OFCFGR1_OFFSET_CH_3             (0x04UL << ADC_OFCFGR1_OFFSET_CH_Pos)   /*!< 0x40000000 */
#define ADC_OFCFGR1_OFFSET_CH_4             (0x05UL << ADC_OFCFGR1_OFFSET_CH_Pos)   /*!< 0x80000000 */

/********************  Bit definition for ADC_OFCFGR2 register  ***************/
#define ADC_OFCFGR2_POSOFF_Pos              (24UL)
#define ADC_OFCFGR2_POSOFF_Msk              (0x01UL << ADC_OFCFGR2_POSOFF_Pos)      /*!< 0x01000000 */
#define ADC_OFCFGR2_POSOFF                  ADC_OFCFGR2_POSOFF_Msk                  /*!< ADC offset instance 2 positive offset enable */

#define ADC_OFCFGR2_USAT_Pos                (25UL)
#define ADC_OFCFGR2_USAT_Msk                (0x01UL << ADC_OFCFGR2_USAT_Pos)        /*!< 0x02000000 */
#define ADC_OFCFGR2_USAT                    ADC_OFCFGR2_USAT_Msk                    /*!< ADC offset instance 2 unsigned saturation value */

#define ADC_OFCFGR2_SSAT_Pos                (26UL)
#define ADC_OFCFGR2_SSAT_Msk                (0x01UL << ADC_OFCFGR2_SSAT_Pos)        /*!< 0x04000000 */
#define ADC_OFCFGR2_SSAT                    ADC_OFCFGR2_SSAT_Msk                    /*!< ADC offset instance 2 signed satuaration enable */

#define ADC_OFCFGR2_OFFSET_CH_Pos           (27UL)
#define ADC_OFCFGR2_OFFSET_CH_Msk           (0x1FUL << ADC_OFCFGR2_OFFSET_CH_Pos)   /*!< 0xF8000000 */
#define ADC_OFCFGR2_OFFSET_CH               ADC_OFCFGR2_OFFSET_CH_Msk               /*!< ADC offset instance 2 channel selection */
#define ADC_OFCFGR2_OFFSET_CH_0             (0x01UL << ADC_OFCFGR2_OFFSET_CH_Pos)   /*!< 0x08000000 */
#define ADC_OFCFGR2_OFFSET_CH_1             (0x02UL << ADC_OFCFGR2_OFFSET_CH_Pos)   /*!< 0x10000000 */
#define ADC_OFCFGR2_OFFSET_CH_2             (0x03UL << ADC_OFCFGR2_OFFSET_CH_Pos)   /*!< 0x20000000 */
#define ADC_OFCFGR2_OFFSET_CH_3             (0x04UL << ADC_OFCFGR2_OFFSET_CH_Pos)   /*!< 0x40000000 */
#define ADC_OFCFGR2_OFFSET_CH_4             (0x05UL << ADC_OFCFGR2_OFFSET_CH_Pos)   /*!< 0x80000000 */

/********************  Bit definition for ADC_OFCFGR3 register  ***************/
#define ADC_OFCFGR3_POSOFF_Pos              (24UL)
#define ADC_OFCFGR3_POSOFF_Msk              (0x01UL << ADC_OFCFGR3_POSOFF_Pos)      /*!< 0x01000000 */
#define ADC_OFCFGR3_POSOFF                  ADC_OFCFGR3_POSOFF_Msk                  /*!< ADC offset instance 3 positive offset enable */

#define ADC_OFCFGR3_USAT_Pos                (25UL)
#define ADC_OFCFGR3_USAT_Msk                (0x01UL << ADC_OFCFGR3_USAT_Pos)        /*!< 0x02000000 */
#define ADC_OFCFGR3_USAT                    ADC_OFCFGR3_USAT_Msk                    /*!< ADC offset instance 3 unsigned saturation value */

#define ADC_OFCFGR3_SSAT_Pos                (26UL)
#define ADC_OFCFGR3_SSAT_Msk                (0x01UL << ADC_OFCFGR3_SSAT_Pos)        /*!< 0x04000000 */
#define ADC_OFCFGR3_SSAT                    ADC_OFCFGR3_SSAT_Msk                    /*!< ADC offset instance 3 signed satuaration enable */

#define ADC_OFCFGR3_OFFSET_CH_Pos           (27UL)
#define ADC_OFCFGR3_OFFSET_CH_Msk           (0x1FUL << ADC_OFCFGR3_OFFSET_CH_Pos)   /*!< 0xF8000000 */
#define ADC_OFCFGR3_OFFSET_CH               ADC_OFCFGR3_OFFSET_CH_Msk               /*!< ADC offset instance 3 channel selection for the data offset */
#define ADC_OFCFGR3_OFFSET_CH_0             (0x01UL << ADC_OFCFGR3_OFFSET_CH_Pos)   /*!< 0x08000000 */
#define ADC_OFCFGR3_OFFSET_CH_1             (0x02UL << ADC_OFCFGR3_OFFSET_CH_Pos)   /*!< 0x10000000 */
#define ADC_OFCFGR3_OFFSET_CH_2             (0x03UL << ADC_OFCFGR3_OFFSET_CH_Pos)   /*!< 0x20000000 */
#define ADC_OFCFGR3_OFFSET_CH_3             (0x04UL << ADC_OFCFGR3_OFFSET_CH_Pos)   /*!< 0x40000000 */
#define ADC_OFCFGR3_OFFSET_CH_4             (0x05UL << ADC_OFCFGR3_OFFSET_CH_Pos)   /*!< 0x80000000 */

/********************  Bit definition for ADC_OFCFGR4 register  ***************/
#define ADC_OFCFGR4_POSOFF_Pos              (24UL)
#define ADC_OFCFGR4_POSOFF_Msk              (0x01UL << ADC_OFCFGR4_POSOFF_Pos)      /*!< 0x01000000 */
#define ADC_OFCFGR4_POSOFF                  ADC_OFCFGR4_POSOFF_Msk                  /*!< ADC offset instance 4 positive offset enable */

#define ADC_OFCFGR4_USAT_Pos                (25UL)
#define ADC_OFCFGR4_USAT_Msk                (0x01UL << ADC_OFCFGR4_USAT_Pos)        /*!< 0x02000000 */
#define ADC_OFCFGR4_USAT                    ADC_OFCFGR4_USAT_Msk                    /*!< ADC offset instance 4 unsigned saturation value */

#define ADC_OFCFGR4_SSAT_Pos                (26UL)
#define ADC_OFCFGR4_SSAT_Msk                (0x01UL << ADC_OFCFGR4_SSAT_Pos)        /*!< 0x04000000 */
#define ADC_OFCFGR4_SSAT                    ADC_OFCFGR4_SSAT_Msk                    /*!< ADC offset instance 4 signed satuaration enable */

#define ADC_OFCFGR4_OFFSET_CH_Pos           (27UL)
#define ADC_OFCFGR4_OFFSET_CH_Msk           (0x1FUL << ADC_OFCFGR4_OFFSET_CH_Pos)   /*!< 0xF8000000 */
#define ADC_OFCFGR4_OFFSET_CH               ADC_OFCFGR4_OFFSET_CH_Msk               /*!< ADC offset instance 4 channel selection for the data offset */
#define ADC_OFCFGR4_OFFSET_CH_0             (0x01UL << ADC_OFCFGR4_OFFSET_CH_Pos)   /*!< 0x08000000 */
#define ADC_OFCFGR4_OFFSET_CH_1             (0x02UL << ADC_OFCFGR4_OFFSET_CH_Pos)   /*!< 0x10000000 */
#define ADC_OFCFGR4_OFFSET_CH_2             (0x03UL << ADC_OFCFGR4_OFFSET_CH_Pos)   /*!< 0x20000000 */
#define ADC_OFCFGR4_OFFSET_CH_3             (0x04UL << ADC_OFCFGR4_OFFSET_CH_Pos)   /*!< 0x40000000 */
#define ADC_OFCFGR4_OFFSET_CH_4             (0x05UL << ADC_OFCFGR4_OFFSET_CH_Pos)   /*!< 0x80000000 */

/********************  Bit definition for ADC_OFR1 register  ******************/
#define ADC_OFR1_OFFSET_Pos                 (0UL)
#define ADC_OFR1_OFFSET_Msk                 (0x03FFFFFUL << ADC_OFR1_OFFSET_Pos)    /*!< 0x003FFFFF */
#define ADC_OFR1_OFFSET                     ADC_OFR1_OFFSET_Msk                     /*!< ADC offset instance 1 offset level */
#define ADC_OFR1_OFFSET_0                   (0x0000001UL << ADC_OFR1_OFFSET_Pos)    /*!< 0x00000001 */
#define ADC_OFR1_OFFSET_1                   (0x0000002UL << ADC_OFR1_OFFSET_Pos)    /*!< 0x00000002 */
#define ADC_OFR1_OFFSET_2                   (0x0000004UL << ADC_OFR1_OFFSET_Pos)    /*!< 0x00000004 */
#define ADC_OFR1_OFFSET_3                   (0x0000008UL << ADC_OFR1_OFFSET_Pos)    /*!< 0x00000008 */
#define ADC_OFR1_OFFSET_4                   (0x0000010UL << ADC_OFR1_OFFSET_Pos)    /*!< 0x00000010 */
#define ADC_OFR1_OFFSET_5                   (0x0000020UL << ADC_OFR1_OFFSET_Pos)    /*!< 0x00000020 */
#define ADC_OFR1_OFFSET_6                   (0x0000040UL << ADC_OFR1_OFFSET_Pos)    /*!< 0x00000040 */
#define ADC_OFR1_OFFSET_7                   (0x0000080UL << ADC_OFR1_OFFSET_Pos)    /*!< 0x00000080 */
#define ADC_OFR1_OFFSET_8                   (0x0000100UL << ADC_OFR1_OFFSET_Pos)    /*!< 0x00000100 */
#define ADC_OFR1_OFFSET_9                   (0x0000200UL << ADC_OFR1_OFFSET_Pos)    /*!< 0x00000200 */
#define ADC_OFR1_OFFSET_10                  (0x0000400UL << ADC_OFR1_OFFSET_Pos)    /*!< 0x00000400 */
#define ADC_OFR1_OFFSET_11                  (0x0000800UL << ADC_OFR1_OFFSET_Pos)    /*!< 0x00000800 */
#define ADC_OFR1_OFFSET_12                  (0x0001000UL << ADC_OFR1_OFFSET_Pos)    /*!< 0x00001000 */
#define ADC_OFR1_OFFSET_13                  (0x0002000UL << ADC_OFR1_OFFSET_Pos)    /*!< 0x00002000 */
#define ADC_OFR1_OFFSET_14                  (0x0004000UL << ADC_OFR1_OFFSET_Pos)    /*!< 0x00004000 */
#define ADC_OFR1_OFFSET_15                  (0x0008000UL << ADC_OFR1_OFFSET_Pos)    /*!< 0x00008000 */
#define ADC_OFR1_OFFSET_16                  (0x0010000UL << ADC_OFR1_OFFSET_Pos)    /*!< 0x00010000 */
#define ADC_OFR1_OFFSET_17                  (0x0020000UL << ADC_OFR1_OFFSET_Pos)    /*!< 0x00020000 */
#define ADC_OFR1_OFFSET_18                  (0x0040000UL << ADC_OFR1_OFFSET_Pos)    /*!< 0x00040000 */
#define ADC_OFR1_OFFSET_19                  (0x0080000UL << ADC_OFR1_OFFSET_Pos)    /*!< 0x00080000 */
#define ADC_OFR1_OFFSET_20                  (0x0100000UL << ADC_OFR1_OFFSET_Pos)    /*!< 0x00100000 */
#define ADC_OFR1_OFFSET_21                  (0x0200000UL << ADC_OFR1_OFFSET_Pos)    /*!< 0x00200000 */

/********************  Bit definition for ADC_OFR2 register  ******************/
#define ADC_OFR2_OFFSET_Pos                 (0UL)
#define ADC_OFR2_OFFSET_Msk                 (0x03FFFFFUL << ADC_OFR2_OFFSET_Pos)    /*!< 0x003FFFFF */
#define ADC_OFR2_OFFSET                     ADC_OFR2_OFFSET_Msk                     /*!< ADC offset instance 2 offset level */
#define ADC_OFR2_OFFSET_0                   (0x0000001UL << ADC_OFR2_OFFSET_Pos)    /*!< 0x00000001 */
#define ADC_OFR2_OFFSET_1                   (0x0000002UL << ADC_OFR2_OFFSET_Pos)    /*!< 0x00000002 */
#define ADC_OFR2_OFFSET_2                   (0x0000004UL << ADC_OFR2_OFFSET_Pos)    /*!< 0x00000004 */
#define ADC_OFR2_OFFSET_3                   (0x0000008UL << ADC_OFR2_OFFSET_Pos)    /*!< 0x00000008 */
#define ADC_OFR2_OFFSET_4                   (0x0000010UL << ADC_OFR2_OFFSET_Pos)    /*!< 0x00000010 */
#define ADC_OFR2_OFFSET_5                   (0x0000020UL << ADC_OFR2_OFFSET_Pos)    /*!< 0x00000020 */
#define ADC_OFR2_OFFSET_6                   (0x0000040UL << ADC_OFR2_OFFSET_Pos)    /*!< 0x00000040 */
#define ADC_OFR2_OFFSET_7                   (0x0000080UL << ADC_OFR2_OFFSET_Pos)    /*!< 0x00000080 */
#define ADC_OFR2_OFFSET_8                   (0x0000100UL << ADC_OFR2_OFFSET_Pos)    /*!< 0x00000100 */
#define ADC_OFR2_OFFSET_9                   (0x0000200UL << ADC_OFR2_OFFSET_Pos)    /*!< 0x00000200 */
#define ADC_OFR2_OFFSET_10                  (0x0000400UL << ADC_OFR2_OFFSET_Pos)    /*!< 0x00000400 */
#define ADC_OFR2_OFFSET_11                  (0x0000800UL << ADC_OFR2_OFFSET_Pos)    /*!< 0x00000800 */
#define ADC_OFR2_OFFSET_12                  (0x0001000UL << ADC_OFR2_OFFSET_Pos)    /*!< 0x00001000 */
#define ADC_OFR2_OFFSET_13                  (0x0002000UL << ADC_OFR2_OFFSET_Pos)    /*!< 0x00002000 */
#define ADC_OFR2_OFFSET_14                  (0x0004000UL << ADC_OFR2_OFFSET_Pos)    /*!< 0x00004000 */
#define ADC_OFR2_OFFSET_15                  (0x0008000UL << ADC_OFR2_OFFSET_Pos)    /*!< 0x00008000 */
#define ADC_OFR2_OFFSET_16                  (0x0010000UL << ADC_OFR2_OFFSET_Pos)    /*!< 0x00010000 */
#define ADC_OFR2_OFFSET_17                  (0x0020000UL << ADC_OFR2_OFFSET_Pos)    /*!< 0x00020000 */
#define ADC_OFR2_OFFSET_18                  (0x0040000UL << ADC_OFR2_OFFSET_Pos)    /*!< 0x00040000 */
#define ADC_OFR2_OFFSET_19                  (0x0080000UL << ADC_OFR2_OFFSET_Pos)    /*!< 0x00080000 */
#define ADC_OFR2_OFFSET_20                  (0x0100000UL << ADC_OFR2_OFFSET_Pos)    /*!< 0x00100000 */
#define ADC_OFR2_OFFSET_21                  (0x0200000UL << ADC_OFR2_OFFSET_Pos)    /*!< 0x00200000 */

/********************  Bit definition for ADC_OFR3 register  ******************/
#define ADC_OFR3_OFFSET_Pos                 (0UL)
#define ADC_OFR3_OFFSET_Msk                 (0x03FFFFFUL << ADC_OFR3_OFFSET_Pos)    /*!< 0x003FFFFF */
#define ADC_OFR3_OFFSET                     ADC_OFR3_OFFSET_Msk                     /*!< ADC offset instance 3 offset level */
#define ADC_OFR3_OFFSET_0                   (0x0000001UL << ADC_OFR3_OFFSET_Pos)    /*!< 0x00000001 */
#define ADC_OFR3_OFFSET_1                   (0x0000002UL << ADC_OFR3_OFFSET_Pos)    /*!< 0x00000002 */
#define ADC_OFR3_OFFSET_2                   (0x0000004UL << ADC_OFR3_OFFSET_Pos)    /*!< 0x00000004 */
#define ADC_OFR3_OFFSET_3                   (0x0000008UL << ADC_OFR3_OFFSET_Pos)    /*!< 0x00000008 */
#define ADC_OFR3_OFFSET_4                   (0x0000010UL << ADC_OFR3_OFFSET_Pos)    /*!< 0x00000010 */
#define ADC_OFR3_OFFSET_5                   (0x0000020UL << ADC_OFR3_OFFSET_Pos)    /*!< 0x00000020 */
#define ADC_OFR3_OFFSET_6                   (0x0000040UL << ADC_OFR3_OFFSET_Pos)    /*!< 0x00000040 */
#define ADC_OFR3_OFFSET_7                   (0x0000080UL << ADC_OFR3_OFFSET_Pos)    /*!< 0x00000080 */
#define ADC_OFR3_OFFSET_8                   (0x0000100UL << ADC_OFR3_OFFSET_Pos)    /*!< 0x00000100 */
#define ADC_OFR3_OFFSET_9                   (0x0000200UL << ADC_OFR3_OFFSET_Pos)    /*!< 0x00000200 */
#define ADC_OFR3_OFFSET_10                  (0x0000400UL << ADC_OFR3_OFFSET_Pos)    /*!< 0x00000400 */
#define ADC_OFR3_OFFSET_11                  (0x0000800UL << ADC_OFR3_OFFSET_Pos)    /*!< 0x00000800 */
#define ADC_OFR3_OFFSET_12                  (0x0001000UL << ADC_OFR3_OFFSET_Pos)    /*!< 0x00001000 */
#define ADC_OFR3_OFFSET_13                  (0x0002000UL << ADC_OFR3_OFFSET_Pos)    /*!< 0x00002000 */
#define ADC_OFR3_OFFSET_14                  (0x0004000UL << ADC_OFR3_OFFSET_Pos)    /*!< 0x00004000 */
#define ADC_OFR3_OFFSET_15                  (0x0008000UL << ADC_OFR3_OFFSET_Pos)    /*!< 0x00008000 */
#define ADC_OFR3_OFFSET_16                  (0x0010000UL << ADC_OFR3_OFFSET_Pos)    /*!< 0x00010000 */
#define ADC_OFR3_OFFSET_17                  (0x0020000UL << ADC_OFR3_OFFSET_Pos)    /*!< 0x00020000 */
#define ADC_OFR3_OFFSET_18                  (0x0040000UL << ADC_OFR3_OFFSET_Pos)    /*!< 0x00040000 */
#define ADC_OFR3_OFFSET_19                  (0x0080000UL << ADC_OFR3_OFFSET_Pos)    /*!< 0x00080000 */
#define ADC_OFR3_OFFSET_20                  (0x0100000UL << ADC_OFR3_OFFSET_Pos)    /*!< 0x00100000 */
#define ADC_OFR3_OFFSET_21                  (0x0200000UL << ADC_OFR3_OFFSET_Pos)    /*!< 0x00200000 */

/********************  Bit definition for ADC_OFR4 register  ******************/
#define ADC_OFR4_OFFSET_Pos                 (0UL)
#define ADC_OFR4_OFFSET_Msk                 (0x03FFFFFUL << ADC_OFR4_OFFSET_Pos)    /*!< 0x003FFFFF */
#define ADC_OFR4_OFFSET                     ADC_OFR4_OFFSET_Msk                     /*!< ADC offset instance 4 offset level */
#define ADC_OFR4_OFFSET_0                   (0x0000001UL << ADC_OFR4_OFFSET_Pos)    /*!< 0x00000001 */
#define ADC_OFR4_OFFSET_1                   (0x0000002UL << ADC_OFR4_OFFSET_Pos)    /*!< 0x00000002 */
#define ADC_OFR4_OFFSET_2                   (0x0000004UL << ADC_OFR4_OFFSET_Pos)    /*!< 0x00000004 */
#define ADC_OFR4_OFFSET_3                   (0x0000008UL << ADC_OFR4_OFFSET_Pos)    /*!< 0x00000008 */
#define ADC_OFR4_OFFSET_4                   (0x0000010UL << ADC_OFR4_OFFSET_Pos)    /*!< 0x00000010 */
#define ADC_OFR4_OFFSET_5                   (0x0000020UL << ADC_OFR4_OFFSET_Pos)    /*!< 0x00000020 */
#define ADC_OFR4_OFFSET_6                   (0x0000040UL << ADC_OFR4_OFFSET_Pos)    /*!< 0x00000040 */
#define ADC_OFR4_OFFSET_7                   (0x0000080UL << ADC_OFR4_OFFSET_Pos)    /*!< 0x00000080 */
#define ADC_OFR4_OFFSET_8                   (0x0000100UL << ADC_OFR4_OFFSET_Pos)    /*!< 0x00000100 */
#define ADC_OFR4_OFFSET_9                   (0x0000200UL << ADC_OFR4_OFFSET_Pos)    /*!< 0x00000200 */
#define ADC_OFR4_OFFSET_10                  (0x0000400UL << ADC_OFR4_OFFSET_Pos)    /*!< 0x00000400 */
#define ADC_OFR4_OFFSET_11                  (0x0000800UL << ADC_OFR4_OFFSET_Pos)    /*!< 0x00000800 */
#define ADC_OFR4_OFFSET_12                  (0x0001000UL << ADC_OFR4_OFFSET_Pos)    /*!< 0x00001000 */
#define ADC_OFR4_OFFSET_13                  (0x0002000UL << ADC_OFR4_OFFSET_Pos)    /*!< 0x00002000 */
#define ADC_OFR4_OFFSET_14                  (0x0004000UL << ADC_OFR4_OFFSET_Pos)    /*!< 0x00004000 */
#define ADC_OFR4_OFFSET_15                  (0x0008000UL << ADC_OFR4_OFFSET_Pos)    /*!< 0x00008000 */
#define ADC_OFR4_OFFSET_16                  (0x0010000UL << ADC_OFR4_OFFSET_Pos)    /*!< 0x00010000 */
#define ADC_OFR4_OFFSET_17                  (0x0020000UL << ADC_OFR4_OFFSET_Pos)    /*!< 0x00020000 */
#define ADC_OFR4_OFFSET_18                  (0x0040000UL << ADC_OFR4_OFFSET_Pos)    /*!< 0x00040000 */
#define ADC_OFR4_OFFSET_19                  (0x0080000UL << ADC_OFR4_OFFSET_Pos)    /*!< 0x00080000 */
#define ADC_OFR4_OFFSET_20                  (0x0100000UL << ADC_OFR4_OFFSET_Pos)    /*!< 0x00100000 */
#define ADC_OFR4_OFFSET_21                  (0x0200000UL << ADC_OFR4_OFFSET_Pos)    /*!< 0x00200000 */

/********************  Bit definition for ADC_GCOMP register  *****************/
#define ADC_GCOMP_GCOMPCOEFF_Pos            (0UL)
#define ADC_GCOMP_GCOMPCOEFF_Msk            (0x3FFFUL << ADC_GCOMP_GCOMPCOEFF_Pos)  /*!< 0x00003FFF */
#define ADC_GCOMP_GCOMPCOEFF                ADC_GCOMP_GCOMPCOEFF_Msk                /*!< Gain compensation coefficient */
#define ADC_GCOMP_GCOMPCOEFF_0              (0x0001UL << ADC_GCOMP_GCOMPCOEFF_Pos)  /*!< 0x00000001 */
#define ADC_GCOMP_GCOMPCOEFF_1              (0x0002UL << ADC_GCOMP_GCOMPCOEFF_Pos)  /*!< 0x00000002 */
#define ADC_GCOMP_GCOMPCOEFF_2              (0x0004UL << ADC_GCOMP_GCOMPCOEFF_Pos)  /*!< 0x00000004 */
#define ADC_GCOMP_GCOMPCOEFF_3              (0x0008UL << ADC_GCOMP_GCOMPCOEFF_Pos)  /*!< 0x00000008 */
#define ADC_GCOMP_GCOMPCOEFF_4              (0x0010UL << ADC_GCOMP_GCOMPCOEFF_Pos)  /*!< 0x00000010 */
#define ADC_GCOMP_GCOMPCOEFF_5              (0x0020UL << ADC_GCOMP_GCOMPCOEFF_Pos)  /*!< 0x00000020 */
#define ADC_GCOMP_GCOMPCOEFF_6              (0x0040UL << ADC_GCOMP_GCOMPCOEFF_Pos)  /*!< 0x00000040 */
#define ADC_GCOMP_GCOMPCOEFF_7              (0x0080UL << ADC_GCOMP_GCOMPCOEFF_Pos)  /*!< 0x00000080 */
#define ADC_GCOMP_GCOMPCOEFF_8              (0x0100UL << ADC_GCOMP_GCOMPCOEFF_Pos)  /*!< 0x00000100 */
#define ADC_GCOMP_GCOMPCOEFF_9              (0x0200UL << ADC_GCOMP_GCOMPCOEFF_Pos)  /*!< 0x00000200 */
#define ADC_GCOMP_GCOMPCOEFF_10             (0x0400UL << ADC_GCOMP_GCOMPCOEFF_Pos)  /*!< 0x00000400 */
#define ADC_GCOMP_GCOMPCOEFF_11             (0x0800UL << ADC_GCOMP_GCOMPCOEFF_Pos)  /*!< 0x00000800 */
#define ADC_GCOMP_GCOMPCOEFF_12             (0x1000UL << ADC_GCOMP_GCOMPCOEFF_Pos)  /*!< 0x00001000 */
#define ADC_GCOMP_GCOMPCOEFF_13             (0x2000UL << ADC_GCOMP_GCOMPCOEFF_Pos)   /*!< 0x00002000 */

#define ADC_GCOMP_GCOMP_Pos                 (31UL)
#define ADC_GCOMP_GCOMP_Msk                 (0x1UL << ADC_GCOMP_GCOMP_Pos)          /*!< 0x80000000 */
#define ADC_GCOMP_GCOMP                     ADC_GCOMP_GCOMP_Msk                     /*!< Gain compensation mode */

/********************  Bit definition for ADC_JDR1 register  ******************/
#define ADC_JDR1_JDATA_Pos                  (0UL)
#define ADC_JDR1_JDATA_Msk                  (0xFFFFFFFFUL << ADC_JDR1_JDATA_Pos)    /*!< 0xFFFFFFFF */
#define ADC_JDR1_JDATA                      ADC_JDR1_JDATA_Msk                      /*!< ADC group injected sequencer rank 1 conversion data */
#define ADC_JDR1_JDATA_0                    (0x00000001UL << ADC_JDR1_JDATA_Pos)    /*!< 0x00000001 */
#define ADC_JDR1_JDATA_1                    (0x00000002UL << ADC_JDR1_JDATA_Pos)    /*!< 0x00000002 */
#define ADC_JDR1_JDATA_2                    (0x00000004UL << ADC_JDR1_JDATA_Pos)    /*!< 0x00000004 */
#define ADC_JDR1_JDATA_3                    (0x00000008UL << ADC_JDR1_JDATA_Pos)    /*!< 0x00000008 */
#define ADC_JDR1_JDATA_4                    (0x00000010UL << ADC_JDR1_JDATA_Pos)    /*!< 0x00000010 */
#define ADC_JDR1_JDATA_5                    (0x00000020UL << ADC_JDR1_JDATA_Pos)    /*!< 0x00000020 */
#define ADC_JDR1_JDATA_6                    (0x00000040UL << ADC_JDR1_JDATA_Pos)    /*!< 0x00000040 */
#define ADC_JDR1_JDATA_7                    (0x00000080UL << ADC_JDR1_JDATA_Pos)    /*!< 0x00000080 */
#define ADC_JDR1_JDATA_8                    (0x00000100UL << ADC_JDR1_JDATA_Pos)    /*!< 0x00000100 */
#define ADC_JDR1_JDATA_9                    (0x00000200UL << ADC_JDR1_JDATA_Pos)    /*!< 0x00000200 */
#define ADC_JDR1_JDATA_10                   (0x00000400UL << ADC_JDR1_JDATA_Pos)    /*!< 0x00000400 */
#define ADC_JDR1_JDATA_11                   (0x00000800UL << ADC_JDR1_JDATA_Pos)    /*!< 0x00000800 */
#define ADC_JDR1_JDATA_12                   (0x00001000UL << ADC_JDR1_JDATA_Pos)    /*!< 0x00001000 */
#define ADC_JDR1_JDATA_13                   (0x00002000UL << ADC_JDR1_JDATA_Pos)    /*!< 0x00002000 */
#define ADC_JDR1_JDATA_14                   (0x00004000UL << ADC_JDR1_JDATA_Pos)    /*!< 0x00004000 */
#define ADC_JDR1_JDATA_15                   (0x00008000UL << ADC_JDR1_JDATA_Pos)    /*!< 0x00008000 */
#define ADC_JDR1_JDATA_16                   (0x00010000UL << ADC_JDR1_JDATA_Pos)    /*!< 0x00010000 */
#define ADC_JDR1_JDATA_17                   (0x00020000UL << ADC_JDR1_JDATA_Pos)    /*!< 0x00020000 */
#define ADC_JDR1_JDATA_18                   (0x00040000UL << ADC_JDR1_JDATA_Pos)    /*!< 0x00040000 */
#define ADC_JDR1_JDATA_19                   (0x00080000UL << ADC_JDR1_JDATA_Pos)    /*!< 0x00080000 */
#define ADC_JDR1_JDATA_20                   (0x00100000UL << ADC_JDR1_JDATA_Pos)    /*!< 0x00100000 */
#define ADC_JDR1_JDATA_21                   (0x00200000UL << ADC_JDR1_JDATA_Pos)    /*!< 0x00200000 */
#define ADC_JDR1_JDATA_22                   (0x00400000UL << ADC_JDR1_JDATA_Pos)    /*!< 0x00400000 */
#define ADC_JDR1_JDATA_23                   (0x00800000UL << ADC_JDR1_JDATA_Pos)    /*!< 0x00800000 */
#define ADC_JDR1_JDATA_24                   (0x01000000UL << ADC_JDR1_JDATA_Pos)    /*!< 0x01000000 */
#define ADC_JDR1_JDATA_25                   (0x02000000UL << ADC_JDR1_JDATA_Pos)    /*!< 0x02000000 */
#define ADC_JDR1_JDATA_26                   (0x04000000UL << ADC_JDR1_JDATA_Pos)    /*!< 0x04000000 */
#define ADC_JDR1_JDATA_27                   (0x08000000UL << ADC_JDR1_JDATA_Pos)    /*!< 0x08000000 */
#define ADC_JDR1_JDATA_28                   (0x10000000UL << ADC_JDR1_JDATA_Pos)    /*!< 0x10000000 */
#define ADC_JDR1_JDATA_29                   (0x20000000UL << ADC_JDR1_JDATA_Pos)    /*!< 0x20000000 */
#define ADC_JDR1_JDATA_30                   (0x40000000UL << ADC_JDR1_JDATA_Pos)    /*!< 0x40000000 */
#define ADC_JDR1_JDATA_31                   (0x80000000UL << ADC_JDR1_JDATA_Pos)    /*!< 0x80000000 */

/********************  Bit definition for ADC_JDR2 register  ********************/
#define ADC_JDR2_JDATA_Pos                  (0UL)
#define ADC_JDR2_JDATA_Msk                  (0xFFFFFFFFUL << ADC_JDR2_JDATA_Pos)    /*!< 0xFFFFFFFF */
#define ADC_JDR2_JDATA                      ADC_JDR2_JDATA_Msk                      /*!< ADC group injected sequencer rank 2 conversion data */
#define ADC_JDR2_JDATA_0                    (0x00000001UL << ADC_JDR2_JDATA_Pos)    /*!< 0x00000001 */
#define ADC_JDR2_JDATA_1                    (0x00000002UL << ADC_JDR2_JDATA_Pos)    /*!< 0x00000002 */
#define ADC_JDR2_JDATA_2                    (0x00000004UL << ADC_JDR2_JDATA_Pos)    /*!< 0x00000004 */
#define ADC_JDR2_JDATA_3                    (0x00000008UL << ADC_JDR2_JDATA_Pos)    /*!< 0x00000008 */
#define ADC_JDR2_JDATA_4                    (0x00000010UL << ADC_JDR2_JDATA_Pos)    /*!< 0x00000010 */
#define ADC_JDR2_JDATA_5                    (0x00000020UL << ADC_JDR2_JDATA_Pos)    /*!< 0x00000020 */
#define ADC_JDR2_JDATA_6                    (0x00000040UL << ADC_JDR2_JDATA_Pos)    /*!< 0x00000040 */
#define ADC_JDR2_JDATA_7                    (0x00000080UL << ADC_JDR2_JDATA_Pos)    /*!< 0x00000080 */
#define ADC_JDR2_JDATA_8                    (0x00000100UL << ADC_JDR2_JDATA_Pos)    /*!< 0x00000100 */
#define ADC_JDR2_JDATA_9                    (0x00000200UL << ADC_JDR2_JDATA_Pos)    /*!< 0x00000200 */
#define ADC_JDR2_JDATA_10                   (0x00000400UL << ADC_JDR2_JDATA_Pos)    /*!< 0x00000400 */
#define ADC_JDR2_JDATA_11                   (0x00000800UL << ADC_JDR2_JDATA_Pos)    /*!< 0x00000800 */
#define ADC_JDR2_JDATA_12                   (0x00001000UL << ADC_JDR2_JDATA_Pos)    /*!< 0x00001000 */
#define ADC_JDR2_JDATA_13                   (0x00002000UL << ADC_JDR2_JDATA_Pos)    /*!< 0x00002000 */
#define ADC_JDR2_JDATA_14                   (0x00004000UL << ADC_JDR2_JDATA_Pos)    /*!< 0x00004000 */
#define ADC_JDR2_JDATA_15                   (0x00008000UL << ADC_JDR2_JDATA_Pos)    /*!< 0x00008000 */
#define ADC_JDR2_JDATA_16                   (0x00010000UL << ADC_JDR2_JDATA_Pos)    /*!< 0x00010000 */
#define ADC_JDR2_JDATA_17                   (0x00020000UL << ADC_JDR2_JDATA_Pos)    /*!< 0x00020000 */
#define ADC_JDR2_JDATA_18                   (0x00040000UL << ADC_JDR2_JDATA_Pos)    /*!< 0x00040000 */
#define ADC_JDR2_JDATA_19                   (0x00080000UL << ADC_JDR2_JDATA_Pos)    /*!< 0x00080000 */
#define ADC_JDR2_JDATA_20                   (0x00100000UL << ADC_JDR2_JDATA_Pos)    /*!< 0x00100000 */
#define ADC_JDR2_JDATA_21                   (0x00200000UL << ADC_JDR2_JDATA_Pos)    /*!< 0x00200000 */
#define ADC_JDR2_JDATA_22                   (0x00400000UL << ADC_JDR2_JDATA_Pos)    /*!< 0x00400000 */
#define ADC_JDR2_JDATA_23                   (0x00800000UL << ADC_JDR2_JDATA_Pos)    /*!< 0x00800000 */
#define ADC_JDR2_JDATA_24                   (0x01000000UL << ADC_JDR2_JDATA_Pos)    /*!< 0x01000000 */
#define ADC_JDR2_JDATA_25                   (0x02000000UL << ADC_JDR2_JDATA_Pos)    /*!< 0x02000000 */
#define ADC_JDR2_JDATA_26                   (0x04000000UL << ADC_JDR2_JDATA_Pos)    /*!< 0x04000000 */
#define ADC_JDR2_JDATA_27                   (0x08000000UL << ADC_JDR2_JDATA_Pos)    /*!< 0x08000000 */
#define ADC_JDR2_JDATA_28                   (0x10000000UL << ADC_JDR2_JDATA_Pos)    /*!< 0x10000000 */
#define ADC_JDR2_JDATA_29                   (0x20000000UL << ADC_JDR2_JDATA_Pos)    /*!< 0x20000000 */
#define ADC_JDR2_JDATA_30                   (0x40000000UL << ADC_JDR2_JDATA_Pos)    /*!< 0x40000000 */
#define ADC_JDR2_JDATA_31                   (0x80000000UL << ADC_JDR2_JDATA_Pos)    /*!< 0x80000000 */

/********************  Bit definition for ADC_JDR3 register  ********************/
#define ADC_JDR3_JDATA_Pos                  (0UL)
#define ADC_JDR3_JDATA_Msk                  (0xFFFFFFFFUL << ADC_JDR3_JDATA_Pos)    /*!< 0xFFFFFFFF */
#define ADC_JDR3_JDATA                      ADC_JDR3_JDATA_Msk                      /*!< ADC group injected sequencer rank 3 conversion data */
#define ADC_JDR3_JDATA_0                    (0x00000001UL << ADC_JDR3_JDATA_Pos)    /*!< 0x00000001 */
#define ADC_JDR3_JDATA_1                    (0x00000002UL << ADC_JDR3_JDATA_Pos)    /*!< 0x00000002 */
#define ADC_JDR3_JDATA_2                    (0x00000004UL << ADC_JDR3_JDATA_Pos)    /*!< 0x00000004 */
#define ADC_JDR3_JDATA_3                    (0x00000008UL << ADC_JDR3_JDATA_Pos)    /*!< 0x00000008 */
#define ADC_JDR3_JDATA_4                    (0x00000010UL << ADC_JDR3_JDATA_Pos)    /*!< 0x00000010 */
#define ADC_JDR3_JDATA_5                    (0x00000020UL << ADC_JDR3_JDATA_Pos)    /*!< 0x00000020 */
#define ADC_JDR3_JDATA_6                    (0x00000040UL << ADC_JDR3_JDATA_Pos)    /*!< 0x00000040 */
#define ADC_JDR3_JDATA_7                    (0x00000080UL << ADC_JDR3_JDATA_Pos)    /*!< 0x00000080 */
#define ADC_JDR3_JDATA_8                    (0x00000100UL << ADC_JDR3_JDATA_Pos)    /*!< 0x00000100 */
#define ADC_JDR3_JDATA_9                    (0x00000200UL << ADC_JDR3_JDATA_Pos)    /*!< 0x00000200 */
#define ADC_JDR3_JDATA_10                   (0x00000400UL << ADC_JDR3_JDATA_Pos)    /*!< 0x00000400 */
#define ADC_JDR3_JDATA_11                   (0x00000800UL << ADC_JDR3_JDATA_Pos)    /*!< 0x00000800 */
#define ADC_JDR3_JDATA_12                   (0x00001000UL << ADC_JDR3_JDATA_Pos)    /*!< 0x00001000 */
#define ADC_JDR3_JDATA_13                   (0x00002000UL << ADC_JDR3_JDATA_Pos)    /*!< 0x00002000 */
#define ADC_JDR3_JDATA_14                   (0x00004000UL << ADC_JDR3_JDATA_Pos)    /*!< 0x00004000 */
#define ADC_JDR3_JDATA_15                   (0x00008000UL << ADC_JDR3_JDATA_Pos)    /*!< 0x00008000 */
#define ADC_JDR3_JDATA_16                   (0x00010000UL << ADC_JDR3_JDATA_Pos)    /*!< 0x00010000 */
#define ADC_JDR3_JDATA_17                   (0x00020000UL << ADC_JDR3_JDATA_Pos)    /*!< 0x00020000 */
#define ADC_JDR3_JDATA_18                   (0x00040000UL << ADC_JDR3_JDATA_Pos)    /*!< 0x00040000 */
#define ADC_JDR3_JDATA_19                   (0x00080000UL << ADC_JDR3_JDATA_Pos)    /*!< 0x00080000 */
#define ADC_JDR3_JDATA_20                   (0x00100000UL << ADC_JDR3_JDATA_Pos)    /*!< 0x00100000 */
#define ADC_JDR3_JDATA_21                   (0x00200000UL << ADC_JDR3_JDATA_Pos)    /*!< 0x00200000 */
#define ADC_JDR3_JDATA_22                   (0x00400000UL << ADC_JDR3_JDATA_Pos)    /*!< 0x00400000 */
#define ADC_JDR3_JDATA_23                   (0x00800000UL << ADC_JDR3_JDATA_Pos)    /*!< 0x00800000 */
#define ADC_JDR3_JDATA_24                   (0x01000000UL << ADC_JDR3_JDATA_Pos)    /*!< 0x01000000 */
#define ADC_JDR3_JDATA_25                   (0x02000000UL << ADC_JDR3_JDATA_Pos)    /*!< 0x02000000 */
#define ADC_JDR3_JDATA_26                   (0x04000000UL << ADC_JDR3_JDATA_Pos)    /*!< 0x04000000 */
#define ADC_JDR3_JDATA_27                   (0x08000000UL << ADC_JDR3_JDATA_Pos)    /*!< 0x08000000 */
#define ADC_JDR3_JDATA_28                   (0x10000000UL << ADC_JDR3_JDATA_Pos)    /*!< 0x10000000 */
#define ADC_JDR3_JDATA_29                   (0x20000000UL << ADC_JDR3_JDATA_Pos)    /*!< 0x20000000 */
#define ADC_JDR3_JDATA_30                   (0x40000000UL << ADC_JDR3_JDATA_Pos)    /*!< 0x40000000 */
#define ADC_JDR3_JDATA_31                   (0x80000000UL << ADC_JDR3_JDATA_Pos)    /*!< 0x80000000 */

/********************  Bit definition for ADC_JDR4 register  ********************/
#define ADC_JDR4_JDATA_Pos                  (0UL)
#define ADC_JDR4_JDATA_Msk                  (0xFFFFFFFFUL << ADC_JDR4_JDATA_Pos)    /*!< 0xFFFFFFFF */
#define ADC_JDR4_JDATA                      ADC_JDR4_JDATA_Msk                      /*!< ADC group injected sequencer rank 4 conversion data */
#define ADC_JDR4_JDATA_0                    (0x00000001UL << ADC_JDR4_JDATA_Pos)    /*!< 0x00000001 */
#define ADC_JDR4_JDATA_1                    (0x00000002UL << ADC_JDR4_JDATA_Pos)    /*!< 0x00000002 */
#define ADC_JDR4_JDATA_2                    (0x00000004UL << ADC_JDR4_JDATA_Pos)    /*!< 0x00000004 */
#define ADC_JDR4_JDATA_3                    (0x00000008UL << ADC_JDR4_JDATA_Pos)    /*!< 0x00000008 */
#define ADC_JDR4_JDATA_4                    (0x00000010UL << ADC_JDR4_JDATA_Pos)    /*!< 0x00000010 */
#define ADC_JDR4_JDATA_5                    (0x00000020UL << ADC_JDR4_JDATA_Pos)    /*!< 0x00000020 */
#define ADC_JDR4_JDATA_6                    (0x00000040UL << ADC_JDR4_JDATA_Pos)    /*!< 0x00000040 */
#define ADC_JDR4_JDATA_7                    (0x00000080UL << ADC_JDR4_JDATA_Pos)    /*!< 0x00000080 */
#define ADC_JDR4_JDATA_8                    (0x00000100UL << ADC_JDR4_JDATA_Pos)    /*!< 0x00000100 */
#define ADC_JDR4_JDATA_9                    (0x00000200UL << ADC_JDR4_JDATA_Pos)    /*!< 0x00000200 */
#define ADC_JDR4_JDATA_10                   (0x00000400UL << ADC_JDR4_JDATA_Pos)    /*!< 0x00000400 */
#define ADC_JDR4_JDATA_11                   (0x00000800UL << ADC_JDR4_JDATA_Pos)    /*!< 0x00000800 */
#define ADC_JDR4_JDATA_12                   (0x00001000UL << ADC_JDR4_JDATA_Pos)    /*!< 0x00001000 */
#define ADC_JDR4_JDATA_13                   (0x00002000UL << ADC_JDR4_JDATA_Pos)    /*!< 0x00002000 */
#define ADC_JDR4_JDATA_14                   (0x00004000UL << ADC_JDR4_JDATA_Pos)    /*!< 0x00004000 */
#define ADC_JDR4_JDATA_15                   (0x00008000UL << ADC_JDR4_JDATA_Pos)    /*!< 0x00008000 */
#define ADC_JDR4_JDATA_16                   (0x00010000UL << ADC_JDR4_JDATA_Pos)    /*!< 0x00010000 */
#define ADC_JDR4_JDATA_17                   (0x00020000UL << ADC_JDR4_JDATA_Pos)    /*!< 0x00020000 */
#define ADC_JDR4_JDATA_18                   (0x00040000UL << ADC_JDR4_JDATA_Pos)    /*!< 0x00040000 */
#define ADC_JDR4_JDATA_19                   (0x00080000UL << ADC_JDR4_JDATA_Pos)    /*!< 0x00080000 */
#define ADC_JDR4_JDATA_20                   (0x00100000UL << ADC_JDR4_JDATA_Pos)    /*!< 0x00100000 */
#define ADC_JDR4_JDATA_21                   (0x00200000UL << ADC_JDR4_JDATA_Pos)    /*!< 0x00200000 */
#define ADC_JDR4_JDATA_22                   (0x00400000UL << ADC_JDR4_JDATA_Pos)    /*!< 0x00400000 */
#define ADC_JDR4_JDATA_23                   (0x00800000UL << ADC_JDR4_JDATA_Pos)    /*!< 0x00800000 */
#define ADC_JDR4_JDATA_24                   (0x01000000UL << ADC_JDR4_JDATA_Pos)    /*!< 0x01000000 */
#define ADC_JDR4_JDATA_25                   (0x02000000UL << ADC_JDR4_JDATA_Pos)    /*!< 0x02000000 */
#define ADC_JDR4_JDATA_26                   (0x04000000UL << ADC_JDR4_JDATA_Pos)    /*!< 0x04000000 */
#define ADC_JDR4_JDATA_27                   (0x08000000UL << ADC_JDR4_JDATA_Pos)    /*!< 0x08000000 */
#define ADC_JDR4_JDATA_28                   (0x10000000UL << ADC_JDR4_JDATA_Pos)    /*!< 0x10000000 */
#define ADC_JDR4_JDATA_29                   (0x20000000UL << ADC_JDR4_JDATA_Pos)    /*!< 0x20000000 */
#define ADC_JDR4_JDATA_30                   (0x40000000UL << ADC_JDR4_JDATA_Pos)    /*!< 0x40000000 */
#define ADC_JDR4_JDATA_31                   (0x80000000UL << ADC_JDR4_JDATA_Pos)    /*!< 0x80000000 */

/********************  Bit definition for ADC_AWD2CR register  ****************/
#define ADC_AWD2CR_AWD2CH_Pos               (0UL)
#define ADC_AWD2CR_AWD2CH_Msk               (0x7FFFFUL << ADC_AWD2CR_AWD2CH_Pos)    /*!< 0x000FFFFF */
#define ADC_AWD2CR_AWD2CH                   ADC_AWD2CR_AWD2CH_Msk                   /*!< ADC analog watchdog 2 monitored channel selection */
#define ADC_AWD2CR_AWD2CH_0                 (0x00001UL << ADC_AWD2CR_AWD2CH_Pos)    /*!< 0x00000001 */
#define ADC_AWD2CR_AWD2CH_1                 (0x00002UL << ADC_AWD2CR_AWD2CH_Pos)    /*!< 0x00000002 */
#define ADC_AWD2CR_AWD2CH_2                 (0x00004UL << ADC_AWD2CR_AWD2CH_Pos)    /*!< 0x00000004 */
#define ADC_AWD2CR_AWD2CH_3                 (0x00008UL << ADC_AWD2CR_AWD2CH_Pos)    /*!< 0x00000008 */
#define ADC_AWD2CR_AWD2CH_4                 (0x00010UL << ADC_AWD2CR_AWD2CH_Pos)    /*!< 0x00000010 */
#define ADC_AWD2CR_AWD2CH_5                 (0x00020UL << ADC_AWD2CR_AWD2CH_Pos)    /*!< 0x00000020 */
#define ADC_AWD2CR_AWD2CH_6                 (0x00040UL << ADC_AWD2CR_AWD2CH_Pos)    /*!< 0x00000040 */
#define ADC_AWD2CR_AWD2CH_7                 (0x00080UL << ADC_AWD2CR_AWD2CH_Pos)    /*!< 0x00000080 */
#define ADC_AWD2CR_AWD2CH_8                 (0x00100UL << ADC_AWD2CR_AWD2CH_Pos)    /*!< 0x00000100 */
#define ADC_AWD2CR_AWD2CH_9                 (0x00200UL << ADC_AWD2CR_AWD2CH_Pos)    /*!< 0x00000200 */
#define ADC_AWD2CR_AWD2CH_10                (0x00400UL << ADC_AWD2CR_AWD2CH_Pos)    /*!< 0x00000400 */
#define ADC_AWD2CR_AWD2CH_11                (0x00800UL << ADC_AWD2CR_AWD2CH_Pos)    /*!< 0x00000800 */
#define ADC_AWD2CR_AWD2CH_12                (0x01000UL << ADC_AWD2CR_AWD2CH_Pos)    /*!< 0x00001000 */
#define ADC_AWD2CR_AWD2CH_13                (0x02000UL << ADC_AWD2CR_AWD2CH_Pos)    /*!< 0x00002000 */
#define ADC_AWD2CR_AWD2CH_14                (0x04000UL << ADC_AWD2CR_AWD2CH_Pos)    /*!< 0x00004000 */
#define ADC_AWD2CR_AWD2CH_15                (0x08000UL << ADC_AWD2CR_AWD2CH_Pos)    /*!< 0x00008000 */
#define ADC_AWD2CR_AWD2CH_16                (0x10000UL << ADC_AWD2CR_AWD2CH_Pos)    /*!< 0x00010000 */
#define ADC_AWD2CR_AWD2CH_17                (0x20000UL << ADC_AWD2CR_AWD2CH_Pos)    /*!< 0x00020000 */
#define ADC_AWD2CR_AWD2CH_18                (0x40000UL << ADC_AWD2CR_AWD2CH_Pos)    /*!< 0x00040000 */

/********************  Bit definition for ADC_AWD3CR register  ****************/
#define ADC_AWD3CR_AWD3CH_Pos               (0UL)
#define ADC_AWD3CR_AWD3CH_Msk               (0x7FFFFUL << ADC_AWD3CR_AWD3CH_Pos)    /*!< 0x000FFFFF */
#define ADC_AWD3CR_AWD3CH                   ADC_AWD3CR_AWD3CH_Msk                   /*!< ADC analog watchdog 3 monitored channel selection */
#define ADC_AWD3CR_AWD3CH_0                 (0x00001UL << ADC_AWD3CR_AWD3CH_Pos)    /*!< 0x00000001 */
#define ADC_AWD3CR_AWD3CH_1                 (0x00002UL << ADC_AWD3CR_AWD3CH_Pos)    /*!< 0x00000002 */
#define ADC_AWD3CR_AWD3CH_2                 (0x00004UL << ADC_AWD3CR_AWD3CH_Pos)    /*!< 0x00000004 */
#define ADC_AWD3CR_AWD3CH_3                 (0x00008UL << ADC_AWD3CR_AWD3CH_Pos)    /*!< 0x00000008 */
#define ADC_AWD3CR_AWD3CH_4                 (0x00010UL << ADC_AWD3CR_AWD3CH_Pos)    /*!< 0x00000010 */
#define ADC_AWD3CR_AWD3CH_5                 (0x00020UL << ADC_AWD3CR_AWD3CH_Pos)    /*!< 0x00000020 */
#define ADC_AWD3CR_AWD3CH_6                 (0x00040UL << ADC_AWD3CR_AWD3CH_Pos)    /*!< 0x00000040 */
#define ADC_AWD3CR_AWD3CH_7                 (0x00080UL << ADC_AWD3CR_AWD3CH_Pos)    /*!< 0x00000080 */
#define ADC_AWD3CR_AWD3CH_8                 (0x00100UL << ADC_AWD3CR_AWD3CH_Pos)    /*!< 0x00000100 */
#define ADC_AWD3CR_AWD3CH_9                 (0x00200UL << ADC_AWD3CR_AWD3CH_Pos)    /*!< 0x00000200 */
#define ADC_AWD3CR_AWD3CH_10                (0x00400UL << ADC_AWD3CR_AWD3CH_Pos)    /*!< 0x00000400 */
#define ADC_AWD3CR_AWD3CH_11                (0x00800UL << ADC_AWD3CR_AWD3CH_Pos)    /*!< 0x00000800 */
#define ADC_AWD3CR_AWD3CH_12                (0x01000UL << ADC_AWD3CR_AWD3CH_Pos)    /*!< 0x00001000 */
#define ADC_AWD3CR_AWD3CH_13                (0x02000UL << ADC_AWD3CR_AWD3CH_Pos)    /*!< 0x00002000 */
#define ADC_AWD3CR_AWD3CH_14                (0x04000UL << ADC_AWD3CR_AWD3CH_Pos)    /*!< 0x00004000 */
#define ADC_AWD3CR_AWD3CH_15                (0x08000UL << ADC_AWD3CR_AWD3CH_Pos)    /*!< 0x00008000 */
#define ADC_AWD3CR_AWD3CH_16                (0x10000UL << ADC_AWD3CR_AWD3CH_Pos)    /*!< 0x00010000 */
#define ADC_AWD3CR_AWD3CH_17                (0x20000UL << ADC_AWD3CR_AWD3CH_Pos)    /*!< 0x00020000 */
#define ADC_AWD3CR_AWD3CH_18                (0x40000UL << ADC_AWD3CR_AWD3CH_Pos)    /*!< 0x00040000 */

/********************  Bit definition for ADC_AWD1TR_LT register  *************/
#define ADC_AWD1LTR_LTR_Pos                 (0UL)
#define ADC_AWD1LTR_LTR_Msk                 (0x007FFFFFUL << ADC_AWD1LTR_LTR_Pos)   /*!< 0x007FFFFF */
#define ADC_AWD1LTR_LTR                     ADC_AWD1LTR_LTR_Msk                     /*!< ADC analog watchdog 1 threshold low */
#define ADC_AWD1LTR_LTR_0                   (0x000001UL << ADC_AWD1LTR_LTR_Pos)     /*!< 0x00000001 */
#define ADC_AWD1LTR_LTR_1                   (0x000002UL << ADC_AWD1LTR_LTR_Pos)     /*!< 0x00000002 */
#define ADC_AWD1LTR_LTR_2                   (0x000004UL << ADC_AWD1LTR_LTR_Pos)     /*!< 0x00000004 */
#define ADC_AWD1LTR_LTR_3                   (0x000008UL << ADC_AWD1LTR_LTR_Pos)     /*!< 0x00000008 */
#define ADC_AWD1LTR_LTR_4                   (0x000010UL << ADC_AWD1LTR_LTR_Pos)     /*!< 0x00000010 */
#define ADC_AWD1LTR_LTR_5                   (0x000020UL << ADC_AWD1LTR_LTR_Pos)     /*!< 0x00000020 */
#define ADC_AWD1LTR_LTR_6                   (0x000040UL << ADC_AWD1LTR_LTR_Pos)     /*!< 0x00000040 */
#define ADC_AWD1LTR_LTR_7                   (0x000080UL << ADC_AWD1LTR_LTR_Pos)     /*!< 0x00000080 */
#define ADC_AWD1LTR_LTR_8                   (0x000100UL << ADC_AWD1LTR_LTR_Pos)     /*!< 0x00000100 */
#define ADC_AWD1LTR_LTR_9                   (0x000200UL << ADC_AWD1LTR_LTR_Pos)     /*!< 0x00000200 */
#define ADC_AWD1LTR_LTR_10                  (0x000400UL << ADC_AWD1LTR_LTR_Pos)     /*!< 0x00000400 */
#define ADC_AWD1LTR_LTR_11                  (0x000800UL << ADC_AWD1LTR_LTR_Pos)     /*!< 0x00000800 */
#define ADC_AWD1LTR_LTR_12                  (0x001000UL << ADC_AWD1LTR_LTR_Pos)     /*!< 0x00001000 */
#define ADC_AWD1LTR_LTR_13                  (0x002000UL << ADC_AWD1LTR_LTR_Pos)     /*!< 0x00002000 */
#define ADC_AWD1LTR_LTR_14                  (0x004000UL << ADC_AWD1LTR_LTR_Pos)     /*!< 0x00004000 */
#define ADC_AWD1LTR_LTR_15                  (0x008000UL << ADC_AWD1LTR_LTR_Pos)     /*!< 0x00008000 */
#define ADC_AWD1LTR_LTR_16                  (0x010000UL << ADC_AWD1LTR_LTR_Pos)     /*!< 0x00010000 */
#define ADC_AWD1LTR_LTR_17                  (0x020000UL << ADC_AWD1LTR_LTR_Pos)     /*!< 0x00020000 */
#define ADC_AWD1LTR_LTR_18                  (0x040000UL << ADC_AWD1LTR_LTR_Pos)     /*!< 0x00040000 */
#define ADC_AWD1LTR_LTR_19                  (0x080000UL << ADC_AWD1LTR_LTR_Pos)     /*!< 0x00080000 */
#define ADC_AWD1LTR_LTR_20                  (0x100000UL << ADC_AWD1LTR_LTR_Pos)     /*!< 0x00100000 */
#define ADC_AWD1LTR_LTR_21                  (0x200000UL << ADC_AWD1LTR_LTR_Pos)     /*!< 0x00200000 */
#define ADC_AWD1LTR_LTR_22                  (0x400000UL << ADC_AWD1LTR_LTR_Pos)     /*!< 0x00400000 */

/********************  Bit definition for ADC_AWD1TR_HT register  *******************/
#define ADC_AWD1HTR_HTR_Pos                 (0UL)
#define ADC_AWD1HTR_HTR_Msk                 (0x007FFFFFUL << ADC_AWD1HTR_HTR_Pos)   /*!< 0x007FFFFF */
#define ADC_AWD1HTR_HTR                     ADC_AWD1HTR_HTR_Msk                     /*!< ADC analog watchdog 1 threshold high */
#define ADC_AWD1HTR_HTR_0                   (0x000001UL << ADC_AWD1HTR_HTR_Pos)     /*!< 0x00000001 */
#define ADC_AWD1HTR_HTR_1                   (0x000002UL << ADC_AWD1HTR_HTR_Pos)     /*!< 0x00000002 */
#define ADC_AWD1HTR_HTR_2                   (0x000004UL << ADC_AWD1HTR_HTR_Pos)     /*!< 0x00000004 */
#define ADC_AWD1HTR_HTR_3                   (0x000008UL << ADC_AWD1HTR_HTR_Pos)     /*!< 0x00000008 */
#define ADC_AWD1HTR_HTR_4                   (0x000010UL << ADC_AWD1HTR_HTR_Pos)     /*!< 0x00000010 */
#define ADC_AWD1HTR_HTR_5                   (0x000020UL << ADC_AWD1HTR_HTR_Pos)     /*!< 0x00000020 */
#define ADC_AWD1HTR_HTR_6                   (0x000040UL << ADC_AWD1HTR_HTR_Pos)     /*!< 0x00000040 */
#define ADC_AWD1HTR_HTR_7                   (0x000080UL << ADC_AWD1HTR_HTR_Pos)     /*!< 0x00000080 */
#define ADC_AWD1HTR_HTR_8                   (0x000100UL << ADC_AWD1HTR_HTR_Pos)     /*!< 0x00000100 */
#define ADC_AWD1HTR_HTR_9                   (0x000200UL << ADC_AWD1HTR_HTR_Pos)     /*!< 0x00000200 */
#define ADC_AWD1HTR_HTR_10                  (0x000400UL << ADC_AWD1HTR_HTR_Pos)     /*!< 0x00000400 */
#define ADC_AWD1HTR_HTR_11                  (0x000800UL << ADC_AWD1HTR_HTR_Pos)     /*!< 0x00000800 */
#define ADC_AWD1HTR_HTR_12                  (0x001000UL << ADC_AWD1HTR_HTR_Pos)     /*!< 0x00001000 */
#define ADC_AWD1HTR_HTR_13                  (0x002000UL << ADC_AWD1HTR_HTR_Pos)     /*!< 0x00002000 */
#define ADC_AWD1HTR_HTR_14                  (0x004000UL << ADC_AWD1HTR_HTR_Pos)     /*!< 0x00004000 */
#define ADC_AWD1HTR_HTR_15                  (0x008000UL << ADC_AWD1HTR_HTR_Pos)     /*!< 0x00008000 */
#define ADC_AWD1HTR_HTR_16                  (0x010000UL << ADC_AWD1HTR_HTR_Pos)     /*!< 0x00010000 */
#define ADC_AWD1HTR_HTR_17                  (0x020000UL << ADC_AWD1HTR_HTR_Pos)     /*!< 0x00020000 */
#define ADC_AWD1HTR_HTR_18                  (0x040000UL << ADC_AWD1HTR_HTR_Pos)     /*!< 0x00040000 */
#define ADC_AWD1HTR_HTR_19                  (0x080000UL << ADC_AWD1HTR_HTR_Pos)     /*!< 0x00080000 */
#define ADC_AWD1HTR_HTR_20                  (0x100000UL << ADC_AWD1HTR_HTR_Pos)     /*!< 0x00100000 */
#define ADC_AWD1HTR_HTR_21                  (0x200000UL << ADC_AWD1HTR_HTR_Pos)     /*!< 0x00200000 */
#define ADC_AWD1HTR_HTR_22                  (0x400000UL << ADC_AWD1HTR_HTR_Pos)     /*!< 0x00400000 */

#define ADC_AWD1HTR_AWDFILT_Pos             (29UL)
#define ADC_AWD1HTR_AWDFILT_Msk             (0x7UL << ADC_AWD1HTR_AWDFILT_Pos)      /*!< 0x00000007 */
#define ADC_AWD1HTR_AWDFILT                 ADC_AWD1HTR_AWDFILT_Msk                 /*!< ADC analog watchdog 1 filtering */
#define ADC_AWD1HTR_AWDFILT_0               (0x000001UL << ADC_AWD1HTR_AWDFILT_Pos) /*!< 0x00000001 */
#define ADC_AWD1HTR_AWDFILT_1               (0x000002UL << ADC_AWD1HTR_AWDFILT_Pos) /*!< 0x00000002 */
#define ADC_AWD1HTR_AWDFILT_2               (0x000004UL << ADC_AWD1HTR_AWDFILT_Pos) /*!< 0x00000004 */

/********************  Bit definition for ADC_AWD2TR_LT register  *******************/
#define ADC_AWD2LTR_LTR_Pos                 (0UL)
#define ADC_AWD2LTR_LTR_Msk                 (0x007FFFFFUL << ADC_AWD2LTR_LTR_Pos)   /*!< 0x007FFFFF */
#define ADC_AWD2LTR_LTR                     ADC_AWD2LTR_LTR_Msk                     /*!< ADC analog watchdog 2 threshold low */
#define ADC_AWD2LTR_LTR_0                   (0x000001UL << ADC_AWD2LTR_LTR_Pos)     /*!< 0x00000001 */
#define ADC_AWD2LTR_LTR_1                   (0x000002UL << ADC_AWD2LTR_LTR_Pos)     /*!< 0x00000002 */
#define ADC_AWD2LTR_LTR_2                   (0x000004UL << ADC_AWD2LTR_LTR_Pos)     /*!< 0x00000004 */
#define ADC_AWD2LTR_LTR_3                   (0x000008UL << ADC_AWD2LTR_LTR_Pos)     /*!< 0x00000008 */
#define ADC_AWD2LTR_LTR_4                   (0x000010UL << ADC_AWD2LTR_LTR_Pos)     /*!< 0x00000010 */
#define ADC_AWD2LTR_LTR_5                   (0x000020UL << ADC_AWD2LTR_LTR_Pos)     /*!< 0x00000020 */
#define ADC_AWD2LTR_LTR_6                   (0x000040UL << ADC_AWD2LTR_LTR_Pos)     /*!< 0x00000040 */
#define ADC_AWD2LTR_LTR_7                   (0x000080UL << ADC_AWD2LTR_LTR_Pos)     /*!< 0x00000080 */
#define ADC_AWD2LTR_LTR_8                   (0x000100UL << ADC_AWD2LTR_LTR_Pos)     /*!< 0x00000100 */
#define ADC_AWD2LTR_LTR_9                   (0x000200UL << ADC_AWD2LTR_LTR_Pos)     /*!< 0x00000200 */
#define ADC_AWD2LTR_LTR_10                  (0x000400UL << ADC_AWD2LTR_LTR_Pos)     /*!< 0x00000400 */
#define ADC_AWD2LTR_LTR_11                  (0x000800UL << ADC_AWD2LTR_LTR_Pos)     /*!< 0x00000800 */
#define ADC_AWD2LTR_LTR_12                  (0x001000UL << ADC_AWD2LTR_LTR_Pos)     /*!< 0x00001000 */
#define ADC_AWD2LTR_LTR_13                  (0x002000UL << ADC_AWD2LTR_LTR_Pos)     /*!< 0x00002000 */
#define ADC_AWD2LTR_LTR_14                  (0x004000UL << ADC_AWD2LTR_LTR_Pos)     /*!< 0x00004000 */
#define ADC_AWD2LTR_LTR_15                  (0x008000UL << ADC_AWD2LTR_LTR_Pos)     /*!< 0x00008000 */
#define ADC_AWD2LTR_LTR_16                  (0x010000UL << ADC_AWD2LTR_LTR_Pos)     /*!< 0x00010000 */
#define ADC_AWD2LTR_LTR_17                  (0x020000UL << ADC_AWD2LTR_LTR_Pos)     /*!< 0x00020000 */
#define ADC_AWD2LTR_LTR_18                  (0x040000UL << ADC_AWD2LTR_LTR_Pos)     /*!< 0x00040000 */
#define ADC_AWD2LTR_LTR_19                  (0x080000UL << ADC_AWD2LTR_LTR_Pos)     /*!< 0x00080000 */
#define ADC_AWD2LTR_LTR_20                  (0x100000UL << ADC_AWD2LTR_LTR_Pos)     /*!< 0x00100000 */
#define ADC_AWD2LTR_LTR_21                  (0x200000UL << ADC_AWD2LTR_LTR_Pos)     /*!< 0x00200000 */
#define ADC_AWD2LTR_LTR_22                  (0x400000UL << ADC_AWD2LTR_LTR_Pos)     /*!< 0x00400000 */

/********************  Bit definition for ADC_AWD2TR_HT register  *******************/
#define ADC_AWD2HTR_HTR_Pos                 (0UL)
#define ADC_AWD2HTR_HTR_Msk                 (0x007FFFFFUL << ADC_AWD2HTR_HTR_Pos)   /*!< 0x007FFFFF */
#define ADC_AWD2HTR_HTR                     ADC_AWD2HTR_HTR_Msk                     /*!< ADC analog watchdog 2 threshold high */
#define ADC_AWD2HTR_HTR_0                   (0x000001UL << ADC_AWD2HTR_HTR_Pos)     /*!< 0x00000001 */
#define ADC_AWD2HTR_HTR_1                   (0x000002UL << ADC_AWD2HTR_HTR_Pos)     /*!< 0x00000002 */
#define ADC_AWD2HTR_HTR_2                   (0x000004UL << ADC_AWD2HTR_HTR_Pos)     /*!< 0x00000004 */
#define ADC_AWD2HTR_HTR_3                   (0x000008UL << ADC_AWD2HTR_HTR_Pos)     /*!< 0x00000008 */
#define ADC_AWD2HTR_HTR_4                   (0x000010UL << ADC_AWD2HTR_HTR_Pos)     /*!< 0x00000010 */
#define ADC_AWD2HTR_HTR_5                   (0x000020UL << ADC_AWD2HTR_HTR_Pos)     /*!< 0x00000020 */
#define ADC_AWD2HTR_HTR_6                   (0x000040UL << ADC_AWD2HTR_HTR_Pos)     /*!< 0x00000040 */
#define ADC_AWD2HTR_HTR_7                   (0x000080UL << ADC_AWD2HTR_HTR_Pos)     /*!< 0x00000080 */
#define ADC_AWD2HTR_HTR_8                   (0x000100UL << ADC_AWD2HTR_HTR_Pos)     /*!< 0x00000100 */
#define ADC_AWD2HTR_HTR_9                   (0x000200UL << ADC_AWD2HTR_HTR_Pos)     /*!< 0x00000200 */
#define ADC_AWD2HTR_HTR_10                  (0x000400UL << ADC_AWD2HTR_HTR_Pos)     /*!< 0x00000400 */
#define ADC_AWD2HTR_HTR_11                  (0x000800UL << ADC_AWD2HTR_HTR_Pos)     /*!< 0x00000800 */
#define ADC_AWD2HTR_HTR_12                  (0x001000UL << ADC_AWD2HTR_HTR_Pos)     /*!< 0x00001000 */
#define ADC_AWD2HTR_HTR_13                  (0x002000UL << ADC_AWD2HTR_HTR_Pos)     /*!< 0x00002000 */
#define ADC_AWD2HTR_HTR_14                  (0x004000UL << ADC_AWD2HTR_HTR_Pos)     /*!< 0x00004000 */
#define ADC_AWD2HTR_HTR_15                  (0x008000UL << ADC_AWD2HTR_HTR_Pos)     /*!< 0x00008000 */
#define ADC_AWD2HTR_HTR_16                  (0x010000UL << ADC_AWD2HTR_HTR_Pos)     /*!< 0x00010000 */
#define ADC_AWD2HTR_HTR_17                  (0x020000UL << ADC_AWD2HTR_HTR_Pos)     /*!< 0x00020000 */
#define ADC_AWD2HTR_HTR_18                  (0x040000UL << ADC_AWD2HTR_HTR_Pos)     /*!< 0x00040000 */
#define ADC_AWD2HTR_HTR_19                  (0x080000UL << ADC_AWD2HTR_HTR_Pos)     /*!< 0x00080000 */
#define ADC_AWD2HTR_HTR_20                  (0x100000UL << ADC_AWD2HTR_HTR_Pos)     /*!< 0x00100000 */
#define ADC_AWD2HTR_HTR_21                  (0x200000UL << ADC_AWD2HTR_HTR_Pos)     /*!< 0x00200000 */
#define ADC_AWD2HTR_HTR_22                  (0x400000UL << ADC_AWD2HTR_HTR_Pos)     /*!< 0x00400000 */

/********************  Bit definition for ADC_AWD3TR_LT register  *******************/
#define ADC_AWD3LTR_LTR_Pos                 (0UL)
#define ADC_AWD3LTR_LTR_Msk                 (0x007FFFFFUL << ADC_AWD3LTR_LTR_Pos)   /*!< 0x007FFFFF */
#define ADC_AWD3LTR_LTR                     ADC_AWD3LTR_LTR_Msk                     /*!< ADC analog watchdog 3 threshold low */
#define ADC_AWD3LTR_LTR_0                   (0x000001UL << ADC_AWD3LTR_LTR_Pos)     /*!< 0x00000001 */
#define ADC_AWD3LTR_LTR_1                   (0x000002UL << ADC_AWD3LTR_LTR_Pos)     /*!< 0x00000002 */
#define ADC_AWD3LTR_LTR_2                   (0x000004UL << ADC_AWD3LTR_LTR_Pos)     /*!< 0x00000004 */
#define ADC_AWD3LTR_LTR_3                   (0x000008UL << ADC_AWD3LTR_LTR_Pos)     /*!< 0x00000008 */
#define ADC_AWD3LTR_LTR_4                   (0x000010UL << ADC_AWD3LTR_LTR_Pos)     /*!< 0x00000010 */
#define ADC_AWD3LTR_LTR_5                   (0x000020UL << ADC_AWD3LTR_LTR_Pos)     /*!< 0x00000020 */
#define ADC_AWD3LTR_LTR_6                   (0x000040UL << ADC_AWD3LTR_LTR_Pos)     /*!< 0x00000040 */
#define ADC_AWD3LTR_LTR_7                   (0x000080UL << ADC_AWD3LTR_LTR_Pos)     /*!< 0x00000080 */
#define ADC_AWD3LTR_LTR_8                   (0x000100UL << ADC_AWD3LTR_LTR_Pos)     /*!< 0x00000100 */
#define ADC_AWD3LTR_LTR_9                   (0x000200UL << ADC_AWD3LTR_LTR_Pos)     /*!< 0x00000200 */
#define ADC_AWD3LTR_LTR_10                  (0x000400UL << ADC_AWD3LTR_LTR_Pos)     /*!< 0x00000400 */
#define ADC_AWD3LTR_LTR_11                  (0x000800UL << ADC_AWD3LTR_LTR_Pos)     /*!< 0x00000800 */
#define ADC_AWD3LTR_LTR_12                  (0x001000UL << ADC_AWD3LTR_LTR_Pos)     /*!< 0x00001000 */
#define ADC_AWD3LTR_LTR_13                  (0x002000UL << ADC_AWD3LTR_LTR_Pos)     /*!< 0x00002000 */
#define ADC_AWD3LTR_LTR_14                  (0x004000UL << ADC_AWD3LTR_LTR_Pos)     /*!< 0x00004000 */
#define ADC_AWD3LTR_LTR_15                  (0x008000UL << ADC_AWD3LTR_LTR_Pos)     /*!< 0x00008000 */
#define ADC_AWD3LTR_LTR_16                  (0x010000UL << ADC_AWD3LTR_LTR_Pos)     /*!< 0x00010000 */
#define ADC_AWD3LTR_LTR_17                  (0x020000UL << ADC_AWD3LTR_LTR_Pos)     /*!< 0x00020000 */
#define ADC_AWD3LTR_LTR_18                  (0x040000UL << ADC_AWD3LTR_LTR_Pos)     /*!< 0x00040000 */
#define ADC_AWD3LTR_LTR_19                  (0x080000UL << ADC_AWD3LTR_LTR_Pos)     /*!< 0x00080000 */
#define ADC_AWD3LTR_LTR_20                  (0x100000UL << ADC_AWD3LTR_LTR_Pos)     /*!< 0x00100000 */
#define ADC_AWD3LTR_LTR_21                  (0x200000UL << ADC_AWD3LTR_LTR_Pos)     /*!< 0x00200000 */
#define ADC_AWD3LTR_LTR_22                  (0x400000UL << ADC_AWD3LTR_LTR_Pos)     /*!< 0x00400000 */

/********************  Bit definition for ADC_AWD3TR_HT register  *******************/
#define ADC_AWD3HTR_HTR_Pos                 (0UL)
#define ADC_AWD3HTR_HTR_Msk                 (0x007FFFFFUL << ADC_AWD3HTR_HTR_Pos)   /*!< 0x007FFFFF */
#define ADC_AWD3HTR_HTR                     ADC_AWD3HTR_HTR_Msk                     /*!< ADC analog watchdog 3 threshold high */
#define ADC_AWD3HTR_HTR_0                   (0x000001UL << ADC_AWD3HTR_HTR_Pos)     /*!< 0x00000001 */
#define ADC_AWD3HTR_HTR_1                   (0x000002UL << ADC_AWD3HTR_HTR_Pos)     /*!< 0x00000002 */
#define ADC_AWD3HTR_HTR_2                   (0x000004UL << ADC_AWD3HTR_HTR_Pos)     /*!< 0x00000004 */
#define ADC_AWD3HTR_HTR_3                   (0x000008UL << ADC_AWD3HTR_HTR_Pos)     /*!< 0x00000008 */
#define ADC_AWD3HTR_HTR_4                   (0x000010UL << ADC_AWD3HTR_HTR_Pos)     /*!< 0x00000010 */
#define ADC_AWD3HTR_HTR_5                   (0x000020UL << ADC_AWD3HTR_HTR_Pos)     /*!< 0x00000020 */
#define ADC_AWD3HTR_HTR_6                   (0x000040UL << ADC_AWD3HTR_HTR_Pos)     /*!< 0x00000040 */
#define ADC_AWD3HTR_HTR_7                   (0x000080UL << ADC_AWD3HTR_HTR_Pos)     /*!< 0x00000080 */
#define ADC_AWD3HTR_HTR_8                   (0x000100UL << ADC_AWD3HTR_HTR_Pos)     /*!< 0x00000100 */
#define ADC_AWD3HTR_HTR_9                   (0x000200UL << ADC_AWD3HTR_HTR_Pos)     /*!< 0x00000200 */
#define ADC_AWD3HTR_HTR_10                  (0x000400UL << ADC_AWD3HTR_HTR_Pos)     /*!< 0x00000400 */
#define ADC_AWD3HTR_HTR_11                  (0x000800UL << ADC_AWD3HTR_HTR_Pos)     /*!< 0x00000800 */
#define ADC_AWD3HTR_HTR_12                  (0x001000UL << ADC_AWD3HTR_HTR_Pos)     /*!< 0x00001000 */
#define ADC_AWD3HTR_HTR_13                  (0x002000UL << ADC_AWD3HTR_HTR_Pos)     /*!< 0x00002000 */
#define ADC_AWD3HTR_HTR_14                  (0x004000UL << ADC_AWD3HTR_HTR_Pos)     /*!< 0x00004000 */
#define ADC_AWD3HTR_HTR_15                  (0x008000UL << ADC_AWD3HTR_HTR_Pos)     /*!< 0x00008000 */
#define ADC_AWD3HTR_HTR_16                  (0x010000UL << ADC_AWD3HTR_HTR_Pos)     /*!< 0x00010000 */
#define ADC_AWD3HTR_HTR_17                  (0x020000UL << ADC_AWD3HTR_HTR_Pos)     /*!< 0x00020000 */
#define ADC_AWD3HTR_HTR_18                  (0x040000UL << ADC_AWD3HTR_HTR_Pos)     /*!< 0x00040000 */
#define ADC_AWD3HTR_HTR_19                  (0x080000UL << ADC_AWD3HTR_HTR_Pos)     /*!< 0x00080000 */
#define ADC_AWD3HTR_HTR_20                  (0x100000UL << ADC_AWD3HTR_HTR_Pos)     /*!< 0x00100000 */
#define ADC_AWD3HTR_HTR_21                  (0x200000UL << ADC_AWD3HTR_HTR_Pos)     /*!< 0x00200000 */
#define ADC_AWD3HTR_HTR_22                  (0x400000UL << ADC_AWD3HTR_HTR_Pos)     /*!< 0x00400000 */

/********************  Bit definition for ADC_DIFSEL register  ****************/
#define ADC_DIFSEL_DIFSEL_Pos               (0UL)
#define ADC_DIFSEL_DIFSEL_Msk               (0xFFFFFUL << ADC_DIFSEL_DIFSEL_Pos)    /*!< 0x000FFFFF */
#define ADC_DIFSEL_DIFSEL                   ADC_DIFSEL_DIFSEL_Msk                   /*!< ADC channel differential or single-ended mode selection */
#define ADC_DIFSEL_DIFSEL_0                 (0x00001UL << ADC_DIFSEL_DIFSEL_Pos)    /*!< 0x00000001 */
#define ADC_DIFSEL_DIFSEL_1                 (0x00002UL << ADC_DIFSEL_DIFSEL_Pos)    /*!< 0x00000002 */
#define ADC_DIFSEL_DIFSEL_2                 (0x00004UL << ADC_DIFSEL_DIFSEL_Pos)    /*!< 0x00000004 */
#define ADC_DIFSEL_DIFSEL_3                 (0x00008UL << ADC_DIFSEL_DIFSEL_Pos)    /*!< 0x00000008 */
#define ADC_DIFSEL_DIFSEL_4                 (0x00010UL << ADC_DIFSEL_DIFSEL_Pos)    /*!< 0x00000010 */
#define ADC_DIFSEL_DIFSEL_5                 (0x00020UL << ADC_DIFSEL_DIFSEL_Pos)    /*!< 0x00000020 */
#define ADC_DIFSEL_DIFSEL_6                 (0x00040UL << ADC_DIFSEL_DIFSEL_Pos)    /*!< 0x00000040 */
#define ADC_DIFSEL_DIFSEL_7                 (0x00080UL << ADC_DIFSEL_DIFSEL_Pos)    /*!< 0x00000080 */
#define ADC_DIFSEL_DIFSEL_8                 (0x00100UL << ADC_DIFSEL_DIFSEL_Pos)    /*!< 0x00000100 */
#define ADC_DIFSEL_DIFSEL_9                 (0x00200UL << ADC_DIFSEL_DIFSEL_Pos)    /*!< 0x00000200 */
#define ADC_DIFSEL_DIFSEL_10                (0x00400UL << ADC_DIFSEL_DIFSEL_Pos)    /*!< 0x00000400 */
#define ADC_DIFSEL_DIFSEL_11                (0x00800UL << ADC_DIFSEL_DIFSEL_Pos)    /*!< 0x00000800 */
#define ADC_DIFSEL_DIFSEL_12                (0x01000UL << ADC_DIFSEL_DIFSEL_Pos)    /*!< 0x00001000 */
#define ADC_DIFSEL_DIFSEL_13                (0x02000UL << ADC_DIFSEL_DIFSEL_Pos)    /*!< 0x00002000 */
#define ADC_DIFSEL_DIFSEL_14                (0x04000UL << ADC_DIFSEL_DIFSEL_Pos)    /*!< 0x00004000 */
#define ADC_DIFSEL_DIFSEL_15                (0x08000UL << ADC_DIFSEL_DIFSEL_Pos)    /*!< 0x00008000 */
#define ADC_DIFSEL_DIFSEL_16                (0x10000UL << ADC_DIFSEL_DIFSEL_Pos)    /*!< 0x00010000 */
#define ADC_DIFSEL_DIFSEL_17                (0x20000UL << ADC_DIFSEL_DIFSEL_Pos)    /*!< 0x00020000 */
#define ADC_DIFSEL_DIFSEL_18                (0x40000UL << ADC_DIFSEL_DIFSEL_Pos)    /*!< 0x00040000 */
#define ADC_DIFSEL_DIFSEL_19                (0x80000UL << ADC_DIFSEL_DIFSEL_Pos)    /*!< 0x00080000 */

/********************  Bit definition for ADC_CALFACT register  ***************/

#define ADC_CALFACT_CALFACT_Pos             (0UL)
#define ADC_CALFACT_CALFACT_Msk             (0x7FUL << ADC_CALFACT_CALFACT_Pos)     /*!< 0x0000007F */
#define ADC_CALFACT_CALFACT                 ADC_CALFACT_CALFACT_Msk                 /*!< ADC calibration factor in single-ended mode */
#define ADC_CALFACT_CALFACT_0               (0x01UL << ADC_CALFACT_CALFACT_Pos)     /*!< 0x00000001 */
#define ADC_CALFACT_CALFACT_1               (0x02UL << ADC_CALFACT_CALFACT_Pos)     /*!< 0x00000002 */
#define ADC_CALFACT_CALFACT_2               (0x04UL << ADC_CALFACT_CALFACT_Pos)     /*!< 0x00000004 */
#define ADC_CALFACT_CALFACT_3               (0x08UL << ADC_CALFACT_CALFACT_Pos)     /*!< 0x00000008 */
#define ADC_CALFACT_CALFACT_4               (0x10UL << ADC_CALFACT_CALFACT_Pos)     /*!< 0x00000010 */
#define ADC_CALFACT_CALFACT_5               (0x20UL << ADC_CALFACT_CALFACT_Pos)     /*!< 0x00000020 */
#define ADC_CALFACT_CALFACT_6               (0x40UL << ADC_CALFACT_CALFACT_Pos)     /*!< 0x00000040 */
#define ADC_CALFACT_CALFACT_7               (0x80UL << ADC_CALFACT_CALFACT_Pos)     /*!< 0x00000080 */
#define ADC_CALFACT_CALFACT_8               (0x100UL<< ADC_CALFACT_CALFACT_Pos)     /*!< 0x00000100 */
#define ADC_CALFACT_CALFACT_9               (0x200UL<< ADC_CALFACT_CALFACT_Pos)     /*!< 0x00000200 */


/********************  Bit definition for ADC_OR option register  ***************/
#define ADC_OR_VDDCOREEN_Pos                (0UL)
#define ADC_OR_VDDCOREEN_Msk                (0x1UL << ADC_OR_VDDCOREEN_Pos)         /*!< 0x00000004 */
#define ADC_OR_VDDCOREEN                    ADC_OR_VDDCOREEN_Msk                    /*!< ADC internal path to VDDCORE */

/*************************  ADC Common registers  *****************************/
/********************  Bit definition for ADC_CSR register  *******************/
#define ADC_CSR_ADRDY_MST_Pos               (0UL)
#define ADC_CSR_ADRDY_MST_Msk               (0x1UL << ADC_CSR_ADRDY_MST_Pos)        /*!< 0x00000001 */
#define ADC_CSR_ADRDY_MST                   ADC_CSR_ADRDY_MST_Msk                   /*!< ADC multimode master ready flag */
#define ADC_CSR_EOSMP_MST_Pos               (1UL)
#define ADC_CSR_EOSMP_MST_Msk               (0x1UL << ADC_CSR_EOSMP_MST_Pos)        /*!< 0x00000002 */
#define ADC_CSR_EOSMP_MST                   ADC_CSR_EOSMP_MST_Msk                   /*!< ADC multimode master group regular end of sampling flag */
#define ADC_CSR_EOC_MST_Pos                 (2UL)
#define ADC_CSR_EOC_MST_Msk                 (0x1UL << ADC_CSR_EOC_MST_Pos)          /*!< 0x00000004 */
#define ADC_CSR_EOC_MST                     ADC_CSR_EOC_MST_Msk                     /*!< ADC multimode master group regular end of unitary conversion flag */
#define ADC_CSR_EOS_MST_Pos                 (3UL)
#define ADC_CSR_EOS_MST_Msk                 (0x1UL << ADC_CSR_EOS_MST_Pos)          /*!< 0x00000008 */
#define ADC_CSR_EOS_MST                     ADC_CSR_EOS_MST_Msk                     /*!< ADC multimode master group regular end of sequence conversions flag */
#define ADC_CSR_OVR_MST_Pos                 (4UL)
#define ADC_CSR_OVR_MST_Msk                 (0x1UL << ADC_CSR_OVR_MST_Pos)          /*!< 0x00000010 */
#define ADC_CSR_OVR_MST                     ADC_CSR_OVR_MST_Msk                     /*!< ADC multimode master group regular overrun flag */
#define ADC_CSR_JEOC_MST_Pos                (5UL)
#define ADC_CSR_JEOC_MST_Msk                (0x1UL << ADC_CSR_JEOC_MST_Pos)         /*!< 0x00000020 */
#define ADC_CSR_JEOC_MST                    ADC_CSR_JEOC_MST_Msk                    /*!< ADC multimode master group injected end of unitary conversion flag */
#define ADC_CSR_JEOS_MST_Pos                (6UL)
#define ADC_CSR_JEOS_MST_Msk                (0x1UL << ADC_CSR_JEOS_MST_Pos)         /*!< 0x00000040 */
#define ADC_CSR_JEOS_MST                    ADC_CSR_JEOS_MST_Msk                    /*!< ADC multimode master group injected end of sequence conversions flag */
#define ADC_CSR_AWD1_MST_Pos                (7UL)
#define ADC_CSR_AWD1_MST_Msk                (0x1UL << ADC_CSR_AWD1_MST_Pos)         /*!< 0x00000080 */
#define ADC_CSR_AWD1_MST                    ADC_CSR_AWD1_MST_Msk                    /*!< ADC multimode master analog watchdog 1 flag */
#define ADC_CSR_AWD2_MST_Pos                (8UL)
#define ADC_CSR_AWD2_MST_Msk                (0x1UL << ADC_CSR_AWD2_MST_Pos)         /*!< 0x00000100 */
#define ADC_CSR_AWD2_MST                    ADC_CSR_AWD2_MST_Msk                    /*!< ADC multimode master analog watchdog 2 flag */
#define ADC_CSR_AWD3_MST_Pos                (9UL)
#define ADC_CSR_AWD3_MST_Msk                (0x1UL << ADC_CSR_AWD3_MST_Pos)         /*!< 0x00000200 */
#define ADC_CSR_AWD3_MST                    ADC_CSR_AWD3_MST_Msk                    /*!< ADC multimode master analog watchdog 3 flag */
#define ADC_CSR_JQOVF_MST_Pos               (10UL)
#define ADC_CSR_JQOVF_MST_Msk               (0x1UL << ADC_CSR_JQOVF_MST_Pos)        /*!< 0x00000400 */
#define ADC_CSR_JQOVF_MST                   ADC_CSR_JQOVF_MST_Msk                   /*!< ADC multimode master group injected contexts queue overflow flag */
#define ADC_CSR_LDORDY_MST_Pos              (12UL)
#define ADC_CSR_LDORDY_MST_Msk              (0x1UL << ADC_CSR_LDORDY_MST_Pos)       /*!< 0x00001000 */
#define ADC_CSR_LDORDY_MST                  ADC_CSR_LDORDY_MST_Msk                  /*!< ADC multimode master internal voltage regulator output ready flag */

#define ADC_CSR_ADRDY_SLV_Pos               (16UL)
#define ADC_CSR_ADRDY_SLV_Msk               (0x1UL << ADC_CSR_ADRDY_SLV_Pos)        /*!< 0x00010000 */
#define ADC_CSR_ADRDY_SLV                   ADC_CSR_ADRDY_SLV_Msk                   /*!< ADC multimode slave ready flag */
#define ADC_CSR_EOSMP_SLV_Pos               (17UL)
#define ADC_CSR_EOSMP_SLV_Msk               (0x1UL << ADC_CSR_EOSMP_SLV_Pos)        /*!< 0x00020000 */
#define ADC_CSR_EOSMP_SLV                   ADC_CSR_EOSMP_SLV_Msk                   /*!< ADC multimode slave group regular end of sampling flag */
#define ADC_CSR_EOC_SLV_Pos                 (18UL)
#define ADC_CSR_EOC_SLV_Msk                 (0x1UL << ADC_CSR_EOC_SLV_Pos)          /*!< 0x00040000 */
#define ADC_CSR_EOC_SLV                     ADC_CSR_EOC_SLV_Msk                     /*!< ADC multimode slave group regular end of unitary conversion flag */
#define ADC_CSR_EOS_SLV_Pos                 (19UL)
#define ADC_CSR_EOS_SLV_Msk                 (0x1UL << ADC_CSR_EOS_SLV_Pos)           /*!< 0x00080000 */
#define ADC_CSR_EOS_SLV                     ADC_CSR_EOS_SLV_Msk                     /*!< ADC multimode slave group regular end of sequence conversions flag */
#define ADC_CSR_OVR_SLV_Pos                 (20UL)
#define ADC_CSR_OVR_SLV_Msk                 (0x1UL << ADC_CSR_OVR_SLV_Pos)          /*!< 0x00100000 */
#define ADC_CSR_OVR_SLV                     ADC_CSR_OVR_SLV_Msk                     /*!< ADC multimode slave group regular overrun flag */
#define ADC_CSR_JEOC_SLV_Pos                (21UL)
#define ADC_CSR_JEOC_SLV_Msk                (0x1UL << ADC_CSR_JEOC_SLV_Pos)         /*!< 0x00200000 */
#define ADC_CSR_JEOC_SLV                    ADC_CSR_JEOC_SLV_Msk                    /*!< ADC multimode slave group injected end of unitary conversion flag */
#define ADC_CSR_JEOS_SLV_Pos                (22UL)
#define ADC_CSR_JEOS_SLV_Msk                (0x1UL << ADC_CSR_JEOS_SLV_Pos)         /*!< 0x00400000 */
#define ADC_CSR_JEOS_SLV                    ADC_CSR_JEOS_SLV_Msk                    /*!< ADC multimode slave group injected end of sequence conversions flag */
#define ADC_CSR_AWD1_SLV_Pos                (23UL)
#define ADC_CSR_AWD1_SLV_Msk                (0x1UL << ADC_CSR_AWD1_SLV_Pos)         /*!< 0x00800000 */
#define ADC_CSR_AWD1_SLV                    ADC_CSR_AWD1_SLV_Msk                    /*!< ADC multimode slave analog watchdog 1 flag */
#define ADC_CSR_AWD2_SLV_Pos                (24UL)
#define ADC_CSR_AWD2_SLV_Msk                (0x1UL << ADC_CSR_AWD2_SLV_Pos)         /*!< 0x01000000 */
#define ADC_CSR_AWD2_SLV                    ADC_CSR_AWD2_SLV_Msk                    /*!< ADC multimode slave analog watchdog 2 flag */
#define ADC_CSR_AWD3_SLV_Pos                (25UL)
#define ADC_CSR_AWD3_SLV_Msk                (0x1UL << ADC_CSR_AWD3_SLV_Pos)         /*!< 0x02000000 */
#define ADC_CSR_AWD3_SLV                    ADC_CSR_AWD3_SLV_Msk                    /*!< ADC multimode slave analog watchdog 3 flag */
#define ADC_CSR_JQOVF_SLV_Pos               (26UL)
#define ADC_CSR_JQOVF_SLV_Msk               (0x1UL << ADC_CSR_JQOVF_SLV_Pos)        /*!< 0x04000000 */
#define ADC_CSR_JQOVF_SLV                   ADC_CSR_JQOVF_SLV_Msk                   /*!< ADC multimode slave group injected contexts queue overflow flag */
#define ADC_CSR_LDORDY_SLV_Pos              (28UL)
#define ADC_CSR_LDORDY_SLV_Msk              (0x1UL << ADC_CSR_LDORDY_SLV_Pos)       /*!< 0x10000000 */
#define ADC_CSR_LDORDY_SLV                  ADC_CSR_LDORDY_SLV_Msk                  /*!< ADC multimode slave internal voltage regulator output ready flag */

/********************  Bit definition for ADC_CCR register  *******************/
#define ADC_CCR_DUAL_Pos                    (0UL)
#define ADC_CCR_DUAL_Msk                    (0x1FUL << ADC_CCR_DUAL_Pos)            /*!< 0x0000001F */
#define ADC_CCR_DUAL                        ADC_CCR_DUAL_Msk                        /*!< ADC multimode mode selection */
#define ADC_CCR_DUAL_0                      (0x01UL << ADC_CCR_DUAL_Pos)            /*!< 0x00000001 */
#define ADC_CCR_DUAL_1                      (0x02UL << ADC_CCR_DUAL_Pos)            /*!< 0x00000002 */
#define ADC_CCR_DUAL_2                      (0x04UL << ADC_CCR_DUAL_Pos)            /*!< 0x00000004 */
#define ADC_CCR_DUAL_3                      (0x08UL << ADC_CCR_DUAL_Pos)            /*!< 0x00000008 */
#define ADC_CCR_DUAL_4                      (0x10UL << ADC_CCR_DUAL_Pos)            /*!< 0x00000010 */

#define ADC_CCR_DELAY_Pos                   (8UL)
#define ADC_CCR_DELAY_Msk                   (0xFUL << ADC_CCR_DELAY_Pos)            /*!< 0x00000F00 */
#define ADC_CCR_DELAY                       ADC_CCR_DELAY_Msk                       /*!< ADC multimode delay between 2 sampling phases */
#define ADC_CCR_DELAY_0                     (0x1UL << ADC_CCR_DELAY_Pos)            /*!< 0x00000100 */
#define ADC_CCR_DELAY_1                     (0x2UL << ADC_CCR_DELAY_Pos)            /*!< 0x00000200 */
#define ADC_CCR_DELAY_2                     (0x4UL << ADC_CCR_DELAY_Pos)            /*!< 0x00000400 */
#define ADC_CCR_DELAY_3                     (0x8UL << ADC_CCR_DELAY_Pos)            /*!< 0x00000800 */

#define ADC_CCR_DAMDF_Pos                   (14UL)
#define ADC_CCR_DAMDF_Msk                   (0x3UL << ADC_CCR_DAMDF_Pos)            /*!< 0x0000C000 */
#define ADC_CCR_DAMDF                       ADC_CCR_DAMDF_Msk                       /*!< ADC multimode data format */
#define ADC_CCR_DAMDF_0                     (0x1UL << ADC_CCR_DAMDF_Pos)            /*!< 0x00004000 */
#define ADC_CCR_DAMDF_1                     (0x2UL << ADC_CCR_DAMDF_Pos)            /*!< 0x00008000 */

#define ADC_CCR_PRESC_Pos                   (18UL)
#define ADC_CCR_PRESC_Msk                   (0xFUL << ADC_CCR_PRESC_Pos)            /*!< 0x003C0000 */
#define ADC_CCR_PRESC                       ADC_CCR_PRESC_Msk                       /*!< ADC common clock prescaler */
#define ADC_CCR_PRESC_0                     (0x1UL << ADC_CCR_PRESC_Pos)            /*!< 0x00040000 */
#define ADC_CCR_PRESC_1                     (0x2UL << ADC_CCR_PRESC_Pos)            /*!< 0x00080000 */
#define ADC_CCR_PRESC_2                     (0x4UL << ADC_CCR_PRESC_Pos)            /*!< 0x00100000 */
#define ADC_CCR_PRESC_3                     (0x8UL << ADC_CCR_PRESC_Pos)            /*!< 0x00200000 */

#define ADC_CCR_VREFEN_Pos                  (22UL)
#define ADC_CCR_VREFEN_Msk                  (0x1UL << ADC_CCR_VREFEN_Pos)           /*!< 0x00400000 */
#define ADC_CCR_VREFEN                      ADC_CCR_VREFEN_Msk                      /*!< ADC internal path to VrefInt enable */

#define ADC_CCR_TSEN_Pos                    (23UL)
#define ADC_CCR_TSEN_Msk                    (0x1UL << ADC_CCR_TSEN_Pos)             /*!< 0x00800000 */
#define ADC_CCR_TSEN                        ADC_CCR_TSEN_Msk                        /*!< ADC internal path to Temperature sensor voltage enable */

#define ADC_CCR_VBATEN_Pos                  (24UL)
#define ADC_CCR_VBATEN_Msk                  (0x1UL << ADC_CCR_VBATEN_Pos)           /*!< 0x01000000 */
#define ADC_CCR_VBATEN                      ADC_CCR_VBATEN_Msk                      /*!< ADC internal path to battery voltage enable */

/********************  Bit definition for ADC_CDR register  *******************/
#define ADC_CDR_RDATA_MST_Pos               (0UL)
#define ADC_CDR_RDATA_MST_Msk               (0xFFFFUL << ADC_CDR_RDATA_MST_Pos)     /*!< 0x0000FFFF */
#define ADC_CDR_RDATA_MST                   ADC_CDR_RDATA_MST_Msk                   /*!< ADC multimode master group regular conversion data */

#define ADC_CDR_RDATA_SLV_Pos               (16UL)
#define ADC_CDR_RDATA_SLV_Msk               (0xFFFFUL << ADC_CDR_RDATA_SLV_Pos)     /*!< 0xFFFF0000 */
#define ADC_CDR_RDATA_SLV                   ADC_CDR_RDATA_SLV_Msk                   /*!< ADC multimode slave group regular conversion data */

/********************  Bit definition for ADC_CDR2 register  ******************/
#define ADC_CDR2_RDATA_ALT_Pos              (0UL)
#define ADC_CDR2_RDATA_ALT_Msk              (0xFFFFFFFFUL << ADC_CDR2_RDATA_ALT_Pos) /*!< 0xFFFFFFFF */
#define ADC_CDR2_RDATA_ALT                  ADC_CDR2_RDATA_ALT_Msk                   /*!< ADC multimode master or slave (alternated) group regular conversion data */

/******************************************************************************/
/*                                                                            */
/*                       Advanced Encryption Standard (AES)                   */
/*                                                                            */
/******************************************************************************/
/*******************  Bit definition for AES_CR register  *********************/
#define AES_CR_EN_Pos                       (0UL)
#define AES_CR_EN_Msk                       (0x1UL << AES_CR_EN_Pos)                /*!< 0x00000001 */
#define AES_CR_EN                           AES_CR_EN_Msk                           /*!< AES Enable */
#define AES_CR_DATATYPE_Pos                 (1UL)
#define AES_CR_DATATYPE_Msk                 (0x3UL << AES_CR_DATATYPE_Pos)          /*!< 0x00000006 */
#define AES_CR_DATATYPE                     AES_CR_DATATYPE_Msk                     /*!< Data type selection */
#define AES_CR_DATATYPE_0                   (0x1UL << AES_CR_DATATYPE_Pos)          /*!< 0x00000002 */
#define AES_CR_DATATYPE_1                   (0x2UL << AES_CR_DATATYPE_Pos)          /*!< 0x00000004 */
#define AES_CR_MODE_Pos                     (3UL)
#define AES_CR_MODE_Msk                     (0x3UL << AES_CR_MODE_Pos)              /*!< 0x00000018 */
#define AES_CR_MODE                         AES_CR_MODE_Msk                         /*!< AES Mode Of Operation */
#define AES_CR_MODE_0                       (0x1UL << AES_CR_MODE_Pos)              /*!< 0x00000008 */
#define AES_CR_MODE_1                       (0x2UL << AES_CR_MODE_Pos)              /*!< 0x00000010 */
#define AES_CR_CHMOD_Pos                    (5UL)
#define AES_CR_CHMOD_Msk                    (0x803UL << AES_CR_CHMOD_Pos)           /*!< 0x00010060 */
#define AES_CR_CHMOD                        AES_CR_CHMOD_Msk                        /*!< AES Chaining Mode */
#define AES_CR_CHMOD_0                      (0x001UL << AES_CR_CHMOD_Pos)           /*!< 0x00000020 */
#define AES_CR_CHMOD_1                      (0x002UL << AES_CR_CHMOD_Pos)           /*!< 0x00000040 */
#define AES_CR_CHMOD_2                      (0x800UL << AES_CR_CHMOD_Pos)           /*!< 0x00010000 */
#define AES_CR_DMAINEN_Pos                  (11UL)
#define AES_CR_DMAINEN_Msk                  (0x1UL << AES_CR_DMAINEN_Pos)           /*!< 0x00000800 */
#define AES_CR_DMAINEN                      AES_CR_DMAINEN_Msk                      /*!< Enable data input phase DMA management  */
#define AES_CR_DMAOUTEN_Pos                 (12UL)
#define AES_CR_DMAOUTEN_Msk                 (0x1UL << AES_CR_DMAOUTEN_Pos)          /*!< 0x00001000 */
#define AES_CR_DMAOUTEN                     AES_CR_DMAOUTEN_Msk                     /*!< Enable data output phase DMA management */
#define AES_CR_GCMPH_Pos                    (13UL)
#define AES_CR_GCMPH_Msk                    (0x3UL << AES_CR_GCMPH_Pos)             /*!< 0x00006000 */
#define AES_CR_GCMPH                        AES_CR_GCMPH_Msk                        /*!< GCM Phase */
#define AES_CR_GCMPH_0                      (0x1UL << AES_CR_GCMPH_Pos)             /*!< 0x00002000 */
#define AES_CR_GCMPH_1                      (0x2UL << AES_CR_GCMPH_Pos)             /*!< 0x00004000 */
#define AES_CR_KEYSIZE_Pos                  (18UL)
#define AES_CR_KEYSIZE_Msk                  (0x1UL << AES_CR_KEYSIZE_Pos)           /*!< 0x00040000 */
#define AES_CR_KEYSIZE                      AES_CR_KEYSIZE_Msk                      /*!< Key size selection */
#define AES_CR_KEYPROT_Pos                 (19UL)
#define AES_CR_KEYPROT_Msk                 (0x1UL << AES_CR_KEYPROT_Pos)          /*!< 0x00040000 */
#define AES_CR_KEYPROT                     AES_CR_KEYPROT_Msk                     /*!<  Key protection */
#define AES_CR_NPBLB_Pos                    (20UL)
#define AES_CR_NPBLB_Msk                    (0xFUL << AES_CR_NPBLB_Pos)             /*!< 0x00F00000 */
#define AES_CR_NPBLB                        AES_CR_NPBLB_Msk                        /*!< Number of padding bytes in payload last block */
#define AES_CR_NPBLB_0                      (0x1UL << AES_CR_NPBLB_Pos)             /*!< 0x00100000 */
#define AES_CR_NPBLB_1                      (0x2UL << AES_CR_NPBLB_Pos)             /*!< 0x00200000 */
#define AES_CR_NPBLB_2                      (0x4UL << AES_CR_NPBLB_Pos)             /*!< 0x00400000 */
#define AES_CR_NPBLB_3                      (0x8UL << AES_CR_NPBLB_Pos)             /*!< 0x00800000 */
#define AES_CR_KMOD_Pos                     (24UL)
#define AES_CR_KMOD_Msk                     (0x3UL << AES_CR_KMOD_Pos)              /*!< 0x03000000 */
#define AES_CR_KMOD                         AES_CR_KMOD_Msk                         /*!< Key mode selection */
#define AES_CR_KMOD_0                       (0x1UL << AES_CR_KMOD_Pos)             /*!< 0x01000000 */
#define AES_CR_KMOD_1                       (0x2UL << AES_CR_KMOD_Pos)              /*!< 0x02000000 */
#define AES_CR_KSHAREID_Pos                (26UL)
#define AES_CR_KSHAREID_Msk                (0x3UL << AES_CR_KSHAREID_Pos)         /*!< 0x0C000000 */
#define AES_CR_KSHAREID                    AES_CR_KSHAREID_Msk                    /*!< Key Shared ID */
#define AES_CR_KEYSEL_Pos                  (28UL)
#define AES_CR_KEYSEL_Msk                  (0x7UL << AES_CR_KEYSEL_Pos)           /*!< 0x70000000 */
#define AES_CR_KEYSEL                      AES_CR_KEYSEL_Msk                      /*!< Key Selection */
#define AES_CR_KEYSEL_0                    (0x1UL << AES_CR_KEYSEL_Pos)           /*!< 0x10000000 */
#define AES_CR_KEYSEL_1                    (0x2UL << AES_CR_KEYSEL_Pos)           /*!< 0x20000000 */
#define AES_CR_KEYSEL_2                    (0x4UL << AES_CR_KEYSEL_Pos)           /*!< 0x40000000 */
#define AES_CR_IPRST_Pos                    (31UL)
#define AES_CR_IPRST_Msk                    (0x1UL << AES_CR_IPRST_Pos)             /*!< 0x80000000 */
#define AES_CR_IPRST                        AES_CR_IPRST_Msk                        /*!< AES IP software reset */

/*******************  Bit definition for AES_SR register  *********************/
#define AES_SR_CCF_Pos                      (0UL)
#define AES_SR_CCF_Msk                      (0x1UL << AES_SR_CCF_Pos)               /*!< 0x00000001 */
#define AES_SR_CCF                          AES_SR_CCF_Msk                          /*!< Computation Complete Flag */
#define AES_SR_RDERR_Pos                    (1UL)
#define AES_SR_RDERR_Msk                    (0x1UL << AES_SR_RDERR_Pos)             /*!< 0x00000002 */
#define AES_SR_RDERR                        AES_SR_RDERR_Msk                        /*!< Read Error Flag */
#define AES_SR_WRERR_Pos                    (2UL)
#define AES_SR_WRERR_Msk                    (0x1UL << AES_SR_WRERR_Pos)             /*!< 0x00000004 */
#define AES_SR_WRERR                        AES_SR_WRERR_Msk                        /*!< Write Error Flag */
#define AES_SR_BUSY_Pos                     (3UL)
#define AES_SR_BUSY_Msk                     (0x1UL << AES_SR_BUSY_Pos)              /*!< 0x00000008 */
#define AES_SR_BUSY                         AES_SR_BUSY_Msk                         /*!< Busy Flag */
#define AES_SR_KEYVALID_Pos                 (7UL)
#define AES_SR_KEYVALID_Msk                 (0x1UL << AES_SR_KEYVALID_Pos)          /*!< 0x00000080 */
#define AES_SR_KEYVALID                     AES_SR_KEYVALID_Msk                     /*!< KEYVALID Flag */

/*******************  Bit definition for AES_DINR register  *******************/
#define AES_DINR_Pos                        (0UL)
#define AES_DINR_Msk                        (0xFFFFFFFFUL << AES_DINR_Pos)          /*!< 0xFFFFFFFF */
#define AES_DINR                            AES_DINR_Msk                            /*!< AES Data Input Register */

/*******************  Bit definition for AES_DOUTR register  ******************/
#define AES_DOUTR_Pos                       (0UL)
#define AES_DOUTR_Msk                       (0xFFFFFFFFUL << AES_DOUTR_Pos)         /*!< 0xFFFFFFFF */
#define AES_DOUTR                           AES_DOUTR_Msk                           /*!< AES Data Output Register */

/*******************  Bit definition for AES_KEYR0 register  ******************/
#define AES_KEYR0_Pos                       (0UL)
#define AES_KEYR0_Msk                       (0xFFFFFFFFUL << AES_KEYR0_Pos)         /*!< 0xFFFFFFFF */
#define AES_KEYR0                           AES_KEYR0_Msk                           /*!< AES Key Register 0 */

/*******************  Bit definition for AES_KEYR1 register  ******************/
#define AES_KEYR1_Pos                       (0UL)
#define AES_KEYR1_Msk                       (0xFFFFFFFFUL << AES_KEYR1_Pos)         /*!< 0xFFFFFFFF */
#define AES_KEYR1                           AES_KEYR1_Msk                           /*!< AES Key Register 1 */

/*******************  Bit definition for AES_KEYR2 register  ******************/
#define AES_KEYR2_Pos                       (0UL)
#define AES_KEYR2_Msk                       (0xFFFFFFFFUL << AES_KEYR2_Pos)         /*!< 0xFFFFFFFF */
#define AES_KEYR2                           AES_KEYR2_Msk                           /*!< AES Key Register 2 */

/*******************  Bit definition for AES_KEYR3 register  ******************/
#define AES_KEYR3_Pos                       (0UL)
#define AES_KEYR3_Msk                       (0xFFFFFFFFUL << AES_KEYR3_Pos)         /*!< 0xFFFFFFFF */
#define AES_KEYR3                           AES_KEYR3_Msk                           /*!< AES Key Register 3 */

/*******************  Bit definition for AES_KEYR4 register  ******************/
#define AES_KEYR4_Pos                       (0UL)
#define AES_KEYR4_Msk                       (0xFFFFFFFFUL << AES_KEYR4_Pos)         /*!< 0xFFFFFFFF */
#define AES_KEYR4                           AES_KEYR4_Msk                           /*!< AES Key Register 4 */

/*******************  Bit definition for AES_KEYR5 register  ******************/
#define AES_KEYR5_Pos                       (0UL)
#define AES_KEYR5_Msk                       (0xFFFFFFFFUL << AES_KEYR5_Pos)         /*!< 0xFFFFFFFF */
#define AES_KEYR5                           AES_KEYR5_Msk                           /*!< AES Key Register 5 */

/*******************  Bit definition for AES_KEYR6 register  ******************/
#define AES_KEYR6_Pos                       (0UL)
#define AES_KEYR6_Msk                       (0xFFFFFFFFUL << AES_KEYR6_Pos)         /*!< 0xFFFFFFFF */
#define AES_KEYR6                           AES_KEYR6_Msk                           /*!< AES Key Register 6 */

/*******************  Bit definition for AES_KEYR7 register  ******************/
#define AES_KEYR7_Pos                       (0UL)
#define AES_KEYR7_Msk                       (0xFFFFFFFFUL << AES_KEYR7_Pos)         /*!< 0xFFFFFFFF */
#define AES_KEYR7                           AES_KEYR7_Msk                           /*!< AES Key Register 7 */

/*******************  Bit definition for AES_IVR0 register   ******************/
#define AES_IVR0_Pos                        (0UL)
#define AES_IVR0_Msk                        (0xFFFFFFFFUL << AES_IVR0_Pos)          /*!< 0xFFFFFFFF */
#define AES_IVR0                            AES_IVR0_Msk                            /*!< AES Initialization Vector Register 0 */

/*******************  Bit definition for AES_IVR1 register   ******************/
#define AES_IVR1_Pos                        (0UL)
#define AES_IVR1_Msk                        (0xFFFFFFFFUL << AES_IVR1_Pos)          /*!< 0xFFFFFFFF */
#define AES_IVR1                            AES_IVR1_Msk                            /*!< AES Initialization Vector Register 1 */

/*******************  Bit definition for AES_IVR2 register   ******************/
#define AES_IVR2_Pos                        (0UL)
#define AES_IVR2_Msk                        (0xFFFFFFFFUL << AES_IVR2_Pos)          /*!< 0xFFFFFFFF */
#define AES_IVR2                            AES_IVR2_Msk                            /*!< AES Initialization Vector Register 2 */

/*******************  Bit definition for AES_IVR3 register   ******************/
#define AES_IVR3_Pos                        (0UL)
#define AES_IVR3_Msk                        (0xFFFFFFFFUL << AES_IVR3_Pos)          /*!< 0xFFFFFFFF */
#define AES_IVR3                            AES_IVR3_Msk                            /*!< AES Initialization Vector Register 3 */

/*******************  Bit definition for AES_SUSP0R register  ******************/
#define AES_SUSP0R_Pos                      (0UL)
#define AES_SUSP0R_Msk                      (0xFFFFFFFFUL << AES_SUSP0R_Pos)        /*!< 0xFFFFFFFF */
#define AES_SUSP0R                          AES_SUSP0R_Msk                          /*!< AES Suspend registers 0 */

/*******************  Bit definition for AES_SUSP1R register  ******************/
#define AES_SUSP1R_Pos                      (0UL)
#define AES_SUSP1R_Msk                      (0xFFFFFFFFUL << AES_SUSP1R_Pos)        /*!< 0xFFFFFFFF */
#define AES_SUSP1R                          AES_SUSP1R_Msk                          /*!< AES Suspend registers 1 */

/*******************  Bit definition for AES_SUSP2R register  ******************/
#define AES_SUSP2R_Pos                      (0UL)
#define AES_SUSP2R_Msk                      (0xFFFFFFFFUL << AES_SUSP2R_Pos)        /*!< 0xFFFFFFFF */
#define AES_SUSP2R                          AES_SUSP2R_Msk                          /*!< AES Suspend registers 2 */

/*******************  Bit definition for AES_SUSP3R register  ******************/
#define AES_SUSP3R_Pos                      (0UL)
#define AES_SUSP3R_Msk                      (0xFFFFFFFFUL << AES_SUSP3R_Pos)        /*!< 0xFFFFFFFF */
#define AES_SUSP3R                          AES_SUSP3R_Msk                          /*!< AES Suspend registers 3 */

/*******************  Bit definition for AES_SUSP4R register  ******************/
#define AES_SUSP4R_Pos                      (0UL)
#define AES_SUSP4R_Msk                      (0xFFFFFFFFUL << AES_SUSP4R_Pos)        /*!< 0xFFFFFFFF */
#define AES_SUSP4R                          AES_SUSP4R_Msk                          /*!< AES Suspend registers 4 */

/*******************  Bit definition for AES_SUSP5R register  ******************/
#define AES_SUSP5R_Pos                      (0UL)
#define AES_SUSP5R_Msk                      (0xFFFFFFFFUL << AES_SUSP5R_Pos)        /*!< 0xFFFFFFFF */
#define AES_SUSP5R                          AES_SUSP5R_Msk                          /*!< AES Suspend registers 5 */

/*******************  Bit definition for AES_SUSP6R register  ******************/
#define AES_SUSP6R_Pos                      (0UL)
#define AES_SUSP6R_Msk                      (0xFFFFFFFFUL << AES_SUSP6R_Pos)        /*!< 0xFFFFFFFF */
#define AES_SUSP6R                          AES_SUSP6R_Msk                          /*!< AES Suspend registers 6 */

/*******************  Bit definition for AES_SUSP7R register  ******************/
#define AES_SUSP7R_Pos                      (0UL)
#define AES_SUSP7R_Msk                      (0xFFFFFFFFUL << AES_SUSP7R_Pos)        /*!< 0xFFFFFFFF */
#define AES_SUSP7R                          AES_SUSP7R_Msk                          /*!< AES Suspend registers 7 */

/*******************  Bit definition for AES_IER register     ******************/
#define AES_IER_CCFIE_Pos                   (0UL)
#define AES_IER_CCFIE_Msk                   (0x1UL << AES_IER_CCFIE_Pos)            /*!< 0x00000001 */
#define AES_IER_CCFIE                       AES_IER_CCFIE_Msk                       /*!< Computation complete flag interrupt enable */
#define AES_IER_RWEIE_Pos                   (1UL)
#define AES_IER_RWEIE_Msk                   (0x1UL << AES_IER_RWEIE_Pos)            /*!< 0x00000002 */
#define AES_IER_RWEIE                       AES_IER_RWEIE_Msk                       /*!< Read or write error Interrupt Enable */
#define AES_IER_KEIE_Pos                    (2UL)
#define AES_IER_KEIE_Msk                    (0x1UL << AES_IER_KEIE_Pos)             /*!< 0x00000004 */
#define AES_IER_KEIE                        AES_IER_KEIE_Msk                        /*!< Key error interrupt enable */
#define AES_IER_RNGEIE_Pos                  (3UL)
#define AES_IER_RNGEIE_Msk                  (0x1UL << AES_IER_RNGEIE_Pos)           /*!< 0x00000008 */
#define AES_IER_RNGEIE                      AES_IER_RNGEIE_Msk                      /*!< Rng error interrupt enable */

/*******************  Bit definition for AES_ISR register     ******************/
#define AES_ISR_CCF_Pos                     (0UL)
#define AES_ISR_CCF_Msk                     (0x1UL << AES_ISR_CCF_Pos)              /*!< 0x00000001 */
#define AES_ISR_CCF                         AES_ISR_CCF_Msk                         /*!< Computation complete flag */
#define AES_ISR_RWEIF_Pos                   (1UL)
#define AES_ISR_RWEIF_Msk                   (0x1UL << AES_ISR_RWEIF_Pos)            /*!< 0x00000002 */
#define AES_ISR_RWEIF                       AES_ISR_RWEIF_Msk                       /*!< Read or write error Interrupt flag */
#define AES_ISR_KEIF_Pos                    (2UL)
#define AES_ISR_KEIF_Msk                    (0x1UL << AES_ISR_KEIF_Pos)             /*!< 0x00000004 */
#define AES_ISR_KEIF                        AES_ISR_KEIF_Msk                        /*!< Key error interrupt flag */
#define AES_ISR_RNGEIF_Pos                  (3UL)
#define AES_ISR_RNGEIF_Msk                  (0x1UL << AES_ISR_RNGEIF_Pos)           /*!< 0x00000008 */
#define AES_ISR_RNGEIF                      AES_ISR_RNGEIF_Msk                      /*!< Rng error interrupt flag */

/*******************  Bit definition for AES_ICR register     ******************/
#define AES_ICR_CCF_Pos                     (0UL)
#define AES_ICR_CCF_Msk                     (0x1UL << AES_ICR_CCF_Pos)              /*!< 0x00000001 */
#define AES_ICR_CCF                         AES_ICR_CCF_Msk                         /*!< Computation complete flag clear */
#define AES_ICR_RWEIF_Pos                   (1UL)
#define AES_ICR_RWEIF_Msk                   (0x1UL << AES_ICR_RWEIF_Pos)            /*!< 0x00000002 */
#define AES_ICR_RWEIF                       AES_ICR_RWEIF_Msk                       /*!< Read or write error Interrupt flag clear */
#define AES_ICR_KEIF_Pos                    (2UL)
#define AES_ICR_KEIF_Msk                    (0x1UL << AES_ICR_KEIF_Pos)             /*!< 0x00000004 */
#define AES_ICR_KEIF                        AES_ICR_KEIF_Msk                        /*!< Key error interrupt flag clear */
#define AES_ICR_RNGEIF_Pos                  (3UL)
#define AES_ICR_RNGEIF_Msk                  (0x1UL << AES_ICR_RNGEIF_Pos)           /*!< 0x00000008 */
#define AES_ICR_RNGEIF                       AES_ICR_RNGEIF_Msk                     /*!< Rng error interrupt flag clear */

/******************************************************************************/
/*                                                                            */
/*                       Coupling and chaining bridge (CCB)                   */
/*                                                                            */
/******************************************************************************/

/*******************  Bit definition for CCB_CR register     ******************/
#define CCB_CR_CCOP_Pos                     (0UL)
#define CCB_CR_CCOP_Msk                     (0xFFUL << CCB_CR_CCOP_Pos)             /*!< 0x000000FF */
#define CCB_CR_CCOP                         CCB_CR_CCOP_Msk                         /*!< Coupling and chaining operation */
#define CCB_CR_IPRST_Pos                    (31UL)
#define CCB_CR_IPRST_Msk                    (0x1UL << CCB_CR_IPRST_Pos)             /*!< 0x80000000 */
#define CCB_CR_IPRST                        CCB_CR_IPRST_Msk                        /*!< CCB reset */

/*******************  Bit definition for CCB_SR register     ******************/
#define CCB_SR_OPSTEP_Pos                    (0UL)
#define CCB_SR_OPSTEP_Msk                    (0x1FUL << CCB_SR_OPSTEP_Pos)          /*!< 0x0000001F */
#define CCB_SR_OPSTEP                        CCB_SR_OPSTEP_Msk                      /*!< Operation step */
#define CCB_SR_OPERR_Pos                     (8UL)
#define CCB_SR_OPERR_Msk                     (0x1FUL << CCB_SR_OPERR_Pos)           /*!< 0x00001F00     */
#define CCB_SR_OPERR                         CCB_SR_OPERR_Msk                       /*!< Operation error */
#define CCB_SR_BUSY_Pos                      (16UL)
#define CCB_SR_BUSY_Msk                      (0x1UL << CCB_SR_BUSY_Pos)             /*!< 0x00010000 */
#define CCB_SR_BUSY                          CCB_SR_BUSY_Msk                        /*!< CCB busy */
#define CCB_SR_TAMP_EVT0_Pos                 (24UL)
#define CCB_SR_TAMP_EVT0_Msk                 (0x1UL << CCB_SR_TAMP_EVT0_Pos)        /*!< 0x01000000 */
#define CCB_SR_TAMP_EVT0                     CCB_SR_TAMP_EVT0_Msk                   /*!< Tamper event 0 flag */
#define CCB_SR_TAMP_EVT1_Pos                 (25UL)
#define CCB_SR_TAMP_EVT1_Msk                 (0x1UL << CCB_SR_TAMP_EVT1_Pos)        /*!< 0x02000000 */
#define CCB_SR_TAMP_EVT1                     CCB_SR_TAMP_EVT1_Msk                   /*!< Tamper event 1 flag */
#define CCB_SR_TAMP_EVT2_Pos                 (26UL)
#define CCB_SR_TAMP_EVT2_Msk                 (0x1UL << CCB_SR_TAMP_EVT2_Pos)        /*!< 0x04000000 */
#define CCB_SR_TAMP_EVT2                     CCB_SR_TAMP_EVT2_Msk                   /*!< Tamper event 2 flag */
#define CCB_SR_TAMP_EVT3_Pos                 (27UL)
#define CCB_SR_TAMP_EVT3_Msk                 (0x1UL << CCB_SR_TAMP_EVT3_Pos)        /*!< 0x08000000 */
#define CCB_SR_TAMP_EVT3                     CCB_SR_TAMP_EVT3_Msk                   /*!< Tamper event 3 flag */
#define CCB_SR_TAMP_EVT4_Pos                 (28UL)
#define CCB_SR_TAMP_EVT4_Msk                 (0x1UL << CCB_SR_TAMP_EVT4_Pos)        /*!< 0x10000000 */
#define CCB_SR_TAMP_EVT4                     CCB_SR_TAMP_EVT4_Msk                   /*!< Tamper event 4 flag */

/******************************************************************************/
/*                                                                            */
/*                          CRC calculation unit                              */
/*                                                                            */
/******************************************************************************/
/*******************  Bit definition for CRC_DR register  *********************/
#define CRC_DR_DR_Pos                       (0UL)
#define CRC_DR_DR_Msk                       (0xFFFFFFFFUL << CRC_DR_DR_Pos)         /*!< 0xFFFFFFFF */
#define CRC_DR_DR                           CRC_DR_DR_Msk                           /*!< Data register bits */

/*******************  Bit definition for CRC_IDR register  ********************/
#define CRC_IDR_IDR_Pos                     (0UL)
#define CRC_IDR_IDR_Msk                     (0xFFFFFFFFUL << CRC_IDR_IDR_Pos)       /*!< 0xFFFFFFFF */
#define CRC_IDR_IDR                         CRC_IDR_IDR_Msk                         /*!< General-purpose 32-bits data register bits */

/********************  Bit definition for CRC_CR register  ********************/
#define CRC_CR_RESET_Pos                    (0UL)
#define CRC_CR_RESET_Msk                    (0x1UL << CRC_CR_RESET_Pos)             /*!< 0x00000001 */
#define CRC_CR_RESET                        CRC_CR_RESET_Msk                        /*!< RESET the CRC computation unit bit */
#define CRC_CR_POLYSIZE_Pos                 (3UL)
#define CRC_CR_POLYSIZE_Msk                 (0x3UL << CRC_CR_POLYSIZE_Pos)          /*!< 0x00000018 */
#define CRC_CR_POLYSIZE                     CRC_CR_POLYSIZE_Msk                     /*!< Polynomial size bits */
#define CRC_CR_POLYSIZE_0                   (0x1UL << CRC_CR_POLYSIZE_Pos)          /*!< 0x00000008 */
#define CRC_CR_POLYSIZE_1                   (0x2UL << CRC_CR_POLYSIZE_Pos)          /*!< 0x00000010 */
#define CRC_CR_REV_IN_Pos                   (5UL)
#define CRC_CR_REV_IN_Msk                   (0x3UL << CRC_CR_REV_IN_Pos)            /*!< 0x00000060 */
#define CRC_CR_REV_IN                       CRC_CR_REV_IN_Msk                       /*!< REV_IN Reverse Input Data bits */
#define CRC_CR_REV_IN_0                     (0x1UL << CRC_CR_REV_IN_Pos)            /*!< 0x00000020 */
#define CRC_CR_REV_IN_1                     (0x2UL << CRC_CR_REV_IN_Pos)            /*!< 0x00000040 */
#define CRC_CR_REV_OUT_Pos                  (7UL)
#define CRC_CR_REV_OUT_Msk                  (0x3UL << CRC_CR_REV_OUT_Pos)           /*!< 0x00000180 */
#define CRC_CR_REV_OUT                      CRC_CR_REV_OUT_Msk                      /*!< REV_OUT Reverse Output Data bits */
#define CRC_CR_REV_OUT_0                    (0x1UL << CRC_CR_REV_OUT_Pos)           /*!< 0x00000080 */
#define CRC_CR_REV_OUT_1                    (0x2UL << CRC_CR_REV_OUT_Pos)           /*!< 0x00000100 */
#define CRC_CR_RTYPE_IN_Pos                 (9UL)
#define CRC_CR_RTYPE_IN_Msk                 (0x1UL << CRC_CR_RTYPE_IN_Pos)          /*!< 0x00000200 */
#define CRC_CR_RTYPE_IN                     CRC_CR_RTYPE_IN_Msk                     /*!< RTYPE_IN Reverse Type Input bit */
#define CRC_CR_RTYPE_OUT_Pos                (10UL)
#define CRC_CR_RTYPE_OUT_Msk                (0x1UL << CRC_CR_RTYPE_OUT_Pos)         /*!< 0x00000400 */
#define CRC_CR_RTYPE_OUT                    CRC_CR_RTYPE_OUT_Msk                    /*!< RTYPE_OUT Reverse Type Output bit */

/*******************  Bit definition for CRC_INIT register  *******************/
#define CRC_INIT_INIT_Pos                   (0UL)
#define CRC_INIT_INIT_Msk                   (0xFFFFFFFFUL << CRC_INIT_INIT_Pos)     /*!< 0xFFFFFFFF */
#define CRC_INIT_INIT                       CRC_INIT_INIT_Msk                       /*!< Initial CRC value bits */

/*******************  Bit definition for CRC_POL register  ********************/
#define CRC_POL_POL_Pos                     (0UL)
#define CRC_POL_POL_Msk                     (0xFFFFFFFFUL << CRC_POL_POL_Pos)       /*!< 0xFFFFFFFF */
#define CRC_POL_POL                         CRC_POL_POL_Msk                         /*!< Coefficients of the polynomial */

/******************************************************************************/
/*                                                                            */
/*                          CRS Clock Recovery System                         */
/******************************************************************************/
/*******************  Bit definition for CRS_CR register  *********************/
#define CRS_CR_SYNCOKIE_Pos                 (0UL)
#define CRS_CR_SYNCOKIE_Msk                 (0x1UL << CRS_CR_SYNCOKIE_Pos)          /*!< 0x00000001 */
#define CRS_CR_SYNCOKIE                     CRS_CR_SYNCOKIE_Msk                     /*!< SYNC event OK interrupt enable */
#define CRS_CR_SYNCWARNIE_Pos               (1UL)
#define CRS_CR_SYNCWARNIE_Msk               (0x1UL << CRS_CR_SYNCWARNIE_Pos)        /*!< 0x00000002 */
#define CRS_CR_SYNCWARNIE                   CRS_CR_SYNCWARNIE_Msk                   /*!< SYNC warning interrupt enable */
#define CRS_CR_ERRIE_Pos                    (2UL)
#define CRS_CR_ERRIE_Msk                    (0x1UL << CRS_CR_ERRIE_Pos)             /*!< 0x00000004 */
#define CRS_CR_ERRIE                        CRS_CR_ERRIE_Msk                        /*!< SYNC error or trimming error interrupt enable */
#define CRS_CR_ESYNCIE_Pos                  (3UL)
#define CRS_CR_ESYNCIE_Msk                  (0x1UL << CRS_CR_ESYNCIE_Pos)           /*!< 0x00000008 */
#define CRS_CR_ESYNCIE                      CRS_CR_ESYNCIE_Msk                      /*!< Expected SYNC interrupt enable */
#define CRS_CR_CEN_Pos                      (5UL)
#define CRS_CR_CEN_Msk                      (0x1UL << CRS_CR_CEN_Pos)               /*!< 0x00000020 */
#define CRS_CR_CEN                          CRS_CR_CEN_Msk                          /*!< Frequency error counter enable */
#define CRS_CR_AUTOTRIMEN_Pos               (6UL)
#define CRS_CR_AUTOTRIMEN_Msk               (0x1UL << CRS_CR_AUTOTRIMEN_Pos)        /*!< 0x00000040 */
#define CRS_CR_AUTOTRIMEN                   CRS_CR_AUTOTRIMEN_Msk                   /*!< Automatic trimming enable */
#define CRS_CR_SWSYNC_Pos                   (7UL)
#define CRS_CR_SWSYNC_Msk                   (0x1UL << CRS_CR_SWSYNC_Pos)            /*!< 0x00000080 */
#define CRS_CR_SWSYNC                       CRS_CR_SWSYNC_Msk                       /*!< Generate software SYNC event */
#define CRS_CR_TRIM_Pos                     (8UL)
#define CRS_CR_TRIM_Msk                     (0x7FUL << CRS_CR_TRIM_Pos)             /*!< 0x00003F00 */
#define CRS_CR_TRIM                         CRS_CR_TRIM_Msk                         /*!< HSI48 oscillator smooth trimming */

/*******************  Bit definition for CRS_CFGR register  *********************/
#define CRS_CFGR_RELOAD_Pos                 (0UL)
#define CRS_CFGR_RELOAD_Msk                 (0xFFFFUL << CRS_CFGR_RELOAD_Pos)       /*!< 0x0000FFFF */
#define CRS_CFGR_RELOAD                     CRS_CFGR_RELOAD_Msk                     /*!< Counter reload value */
#define CRS_CFGR_FELIM_Pos                  (16UL)
#define CRS_CFGR_FELIM_Msk                  (0xFFUL << CRS_CFGR_FELIM_Pos)          /*!< 0x00FF0000 */
#define CRS_CFGR_FELIM                      CRS_CFGR_FELIM_Msk                      /*!< Frequency error limit */
#define CRS_CFGR_SYNCDIV_Pos                (24UL)
#define CRS_CFGR_SYNCDIV_Msk                (0x7UL << CRS_CFGR_SYNCDIV_Pos)         /*!< 0x07000000 */
#define CRS_CFGR_SYNCDIV                    CRS_CFGR_SYNCDIV_Msk                    /*!< SYNC divider */
#define CRS_CFGR_SYNCDIV_0                  (0x1UL << CRS_CFGR_SYNCDIV_Pos)         /*!< 0x01000000 */
#define CRS_CFGR_SYNCDIV_1                  (0x2UL << CRS_CFGR_SYNCDIV_Pos)         /*!< 0x02000000 */
#define CRS_CFGR_SYNCDIV_2                  (0x4UL << CRS_CFGR_SYNCDIV_Pos)         /*!< 0x04000000 */
#define CRS_CFGR_SYNCSRC_Pos                (28UL)
#define CRS_CFGR_SYNCSRC_Msk                (0x3UL << CRS_CFGR_SYNCSRC_Pos)         /*!< 0x30000000 */
#define CRS_CFGR_SYNCSRC                    CRS_CFGR_SYNCSRC_Msk                    /*!< SYNC signal source selection */
#define CRS_CFGR_SYNCSRC_0                  (0x1UL << CRS_CFGR_SYNCSRC_Pos)         /*!< 0x10000000 */
#define CRS_CFGR_SYNCSRC_1                  (0x2UL << CRS_CFGR_SYNCSRC_Pos)         /*!< 0x20000000 */
#define CRS_CFGR_SYNCPOL_Pos                (31UL)
#define CRS_CFGR_SYNCPOL_Msk                (0x1UL << CRS_CFGR_SYNCPOL_Pos)         /*!< 0x80000000 */
#define CRS_CFGR_SYNCPOL                    CRS_CFGR_SYNCPOL_Msk                    /*!< SYNC polarity selection */

/*******************  Bit definition for CRS_ISR register  *********************/
#define CRS_ISR_SYNCOKF_Pos                 (0UL)
#define CRS_ISR_SYNCOKF_Msk                 (0x1UL << CRS_ISR_SYNCOKF_Pos)          /*!< 0x00000001 */
#define CRS_ISR_SYNCOKF                     CRS_ISR_SYNCOKF_Msk                     /*!< SYNC event OK flag */
#define CRS_ISR_SYNCWARNF_Pos               (1UL)
#define CRS_ISR_SYNCWARNF_Msk               (0x1UL << CRS_ISR_SYNCWARNF_Pos)        /*!< 0x00000002 */
#define CRS_ISR_SYNCWARNF                   CRS_ISR_SYNCWARNF_Msk                   /*!< SYNC warning flag */
#define CRS_ISR_ERRF_Pos                    (2UL)
#define CRS_ISR_ERRF_Msk                    (0x1UL << CRS_ISR_ERRF_Pos)             /*!< 0x00000004 */
#define CRS_ISR_ERRF                        CRS_ISR_ERRF_Msk                        /*!< Error flag */
#define CRS_ISR_ESYNCF_Pos                  (3UL)
#define CRS_ISR_ESYNCF_Msk                  (0x1UL << CRS_ISR_ESYNCF_Pos)           /*!< 0x00000008 */
#define CRS_ISR_ESYNCF                      CRS_ISR_ESYNCF_Msk                      /*!< Expected SYNC flag */
#define CRS_ISR_SYNCERR_Pos                 (8UL)
#define CRS_ISR_SYNCERR_Msk                 (0x1UL << CRS_ISR_SYNCERR_Pos)          /*!< 0x00000100 */
#define CRS_ISR_SYNCERR                     CRS_ISR_SYNCERR_Msk                     /*!< SYNC error */
#define CRS_ISR_SYNCMISS_Pos                (9UL)
#define CRS_ISR_SYNCMISS_Msk                (0x1UL << CRS_ISR_SYNCMISS_Pos)         /*!< 0x00000200 */
#define CRS_ISR_SYNCMISS                    CRS_ISR_SYNCMISS_Msk                    /*!< SYNC missed */
#define CRS_ISR_TRIMOVF_Pos                 (10UL)
#define CRS_ISR_TRIMOVF_Msk                 (0x1UL << CRS_ISR_TRIMOVF_Pos)          /*!< 0x00000400 */
#define CRS_ISR_TRIMOVF                     CRS_ISR_TRIMOVF_Msk                     /*!< Trimming overflow or underflow */
#define CRS_ISR_FEDIR_Pos                   (15UL)
#define CRS_ISR_FEDIR_Msk                   (0x1UL << CRS_ISR_FEDIR_Pos)            /*!< 0x00008000 */
#define CRS_ISR_FEDIR                       CRS_ISR_FEDIR_Msk                       /*!< Frequency error direction */
#define CRS_ISR_FECAP_Pos                   (16UL)
#define CRS_ISR_FECAP_Msk                   (0xFFFFUL << CRS_ISR_FECAP_Pos)         /*!< 0xFFFF0000 */
#define CRS_ISR_FECAP                       CRS_ISR_FECAP_Msk                       /*!< Frequency error capture */

/*******************  Bit definition for CRS_ICR register  *********************/
#define CRS_ICR_SYNCOKC_Pos                 (0UL)
#define CRS_ICR_SYNCOKC_Msk                 (0x1UL << CRS_ICR_SYNCOKC_Pos)          /*!< 0x00000001 */
#define CRS_ICR_SYNCOKC                     CRS_ICR_SYNCOKC_Msk                     /*!< SYNC event OK clear flag */
#define CRS_ICR_SYNCWARNC_Pos               (1UL)
#define CRS_ICR_SYNCWARNC_Msk               (0x1UL << CRS_ICR_SYNCWARNC_Pos)        /*!< 0x00000002 */
#define CRS_ICR_SYNCWARNC                   CRS_ICR_SYNCWARNC_Msk                   /*!< SYNC warning clear flag */
#define CRS_ICR_ERRC_Pos                    (2UL)
#define CRS_ICR_ERRC_Msk                    (0x1UL << CRS_ICR_ERRC_Pos)             /*!< 0x00000004 */
#define CRS_ICR_ERRC                        CRS_ICR_ERRC_Msk                        /*!< Error clear flag */
#define CRS_ICR_ESYNCC_Pos                  (3UL)
#define CRS_ICR_ESYNCC_Msk                  (0x1UL << CRS_ICR_ESYNCC_Pos)           /*!< 0x00000008 */
#define CRS_ICR_ESYNCC                      CRS_ICR_ESYNCC_Msk                      /*!< Expected SYNC clear flag */

/******************************************************************************/
/*                                                                            */
/*                      Analog Comparators (COMP)                             */
/*                                                                            */
/******************************************************************************/
/*!< ******************  Bit definition for COMPx_CSR register  ********************/
#define COMP_CSR_EN_Pos                     (0UL)
#define COMP_CSR_EN_Msk                     (0x1UL << COMP_CSR_EN_Pos)              /*!< 0x00000001 */
#define COMP_CSR_EN                         COMP_CSR_EN_Msk                         /*!< COMPx enable bit */
#define COMP_CSR_INMSEL_Pos                 (4UL)
#define COMP_CSR_INMSEL_Msk                 (0xFUL << COMP_CSR_INMSEL_Pos)          /*!< 0x00070000 */
#define COMP_CSR_INMSEL                     COMP_CSR_INMSEL_Msk                     /*!< COMPx input minus selection bit  */
#define COMP_CSR_INMSEL_0                   (0x1UL << COMP_CSR_INMSEL_Pos)          /*!< 0x00010000 */
#define COMP_CSR_INMSEL_1                   (0x2UL << COMP_CSR_INMSEL_Pos)          /*!< 0x00020000 */
#define COMP_CSR_INMSEL_2                   (0x4UL << COMP_CSR_INMSEL_Pos)          /*!< 0x00040000 */
#define COMP_CSR_INMSEL_3                   (0x8UL << COMP_CSR_INMSEL_Pos)          /*!< 0x00080000 */
#define COMP_CSR_INPSEL_Pos                 (8UL)
#define COMP_CSR_INPSEL_Msk                 (0x3UL << COMP_CSR_INPSEL_Pos)          /*!< 0x00100000 */
#define COMP_CSR_INPSEL                     COMP_CSR_INPSEL_Msk                     /*!< COMPx input plus selection bit */
#define COMP_CSR_INPSEL_0                   (0x1UL << COMP_CSR_INPSEL_Pos)
#define COMP_CSR_INPSEL_1                   (0x2UL << COMP_CSR_INPSEL_Pos)
#define COMP_CSR_WINMODE_Pos                (11UL)
#define COMP_CSR_WINMODE_Msk                (0x1UL << COMP_CSR_WINMODE_Pos)         /*!< 0x00000010 */
#define COMP_CSR_WINMODE                    COMP_CSR_WINMODE_Msk                    /*!< COMPx Windows mode selection bit */
#define COMP_CSR_WINOUT_Pos                 (14UL)
#define COMP_CSR_WINOUT_Msk                 (0x1UL << COMP_CSR_WINOUT_Pos)          /*!< 0x00000008 */
#define COMP_CSR_WINOUT                     COMP_CSR_WINOUT_Msk                     /*!< COMPx polarity selection bit */
#define COMP_CSR_POLARITY_Pos               (15UL)
#define COMP_CSR_POLARITY_Msk               (0x1UL << COMP_CSR_POLARITY_Pos)        /*!< 0x00000008 */
#define COMP_CSR_POLARITY                   COMP_CSR_POLARITY_Msk                   /*!< COMPx polarity selection bit */
#define COMP_CSR_HYST_Pos                   (16UL)
#define COMP_CSR_HYST_Msk                   (0x3UL << COMP_CSR_HYST_Pos)            /*!< 0x00000300 */
#define COMP_CSR_HYST                       COMP_CSR_HYST_Msk                       /*!< COMPx hysteresis selection bits */
#define COMP_CSR_HYST_0                     (0x1UL << COMP_CSR_HYST_Pos)            /*!< 0x00000100 */
#define COMP_CSR_HYST_1                     (0x2UL << COMP_CSR_HYST_Pos)            /*!< 0x00000200 */
#define COMP_CSR_PWRMODE_Pos                (18UL)
#define COMP_CSR_PWRMODE_Msk                (0x3UL << COMP_CSR_PWRMODE_Pos)         /*!< 0x00003000 */
#define COMP_CSR_PWRMODE                    COMP_CSR_PWRMODE_Msk                    /*!< COMPx Power Mode of the comparator */
#define COMP_CSR_PWRMODE_0                  (0x1UL << COMP_CSR_PWRMODE_Pos)         /*!< 0x00001000 */
#define COMP_CSR_PWRMODE_1                  (0x2UL << COMP_CSR_PWRMODE_Pos)         /*!< 0x00002000 */
#define COMP_CSR_BLANKSEL_Pos               (20UL)
#define COMP_CSR_BLANKSEL_Msk               (0x1FUL << COMP_CSR_BLANKSEL_Pos)       /*!< 0x0F000000 */
#define COMP_CSR_BLANKSEL                   COMP_CSR_BLANKSEL_Msk                   /*!< COMPx blanking source selection bits */
#define COMP_CSR_BLANKSEL_0                 (0x1UL << COMP_CSR_BLANKSEL_Pos)        /*!< 0x01000000 */
#define COMP_CSR_BLANKSEL_1                 (0x2UL << COMP_CSR_BLANKSEL_Pos)        /*!< 0x02000000 */
#define COMP_CSR_BLANKSEL_2                 (0x4UL << COMP_CSR_BLANKSEL_Pos)        /*!< 0x04000000 */
#define COMP_CSR_BLANKSEL_3                 (0x8UL << COMP_CSR_BLANKSEL_Pos)        /*!< 0x08000000 */
#define COMP_CSR_BLANKSEL_4                 (0x10UL << COMP_CSR_BLANKSEL_Pos)       /*!< 0x01000000 */
#define COMP_CSR_VALUE_Pos                  (30UL)
#define COMP_CSR_VALUE_Msk                  (0x1UL << COMP_CSR_VALUE_Pos)           /*!< 0x00000001 */
#define COMP_CSR_VALUE                      COMP_CSR_VALUE_Msk                      /*!< COMPx enable bit */
#define COMP_CSR_LOCK_Pos                   (31UL)
#define COMP_CSR_LOCK_Msk                   (0x1UL << COMP_CSR_LOCK_Pos)            /*!< 0x80000000 */
#define COMP_CSR_LOCK                       COMP_CSR_LOCK_Msk                       /*!< COMPx Lock Bit */

/******************************************************************************/
/*                                                                            */
/*                      Digital to Analog Converter                           */
/*                                                                            */
/******************************************************************************/
#define DAC_CHANNEL2_SUPPORT                                                        /*!< DAC feature available only on specific devices: DAC channel 2 available */

/********************  Bit definition for DAC_CR register  ********************/
#define DAC_CR_EN1_Pos                      (0UL)
#define DAC_CR_EN1_Msk                      (0x1UL << DAC_CR_EN1_Pos)               /*!< 0x00000001 */
#define DAC_CR_EN1                          DAC_CR_EN1_Msk                          /*!<DAC channel1 enable */
#define DAC_CR_TEN1_Pos                     (1UL)
#define DAC_CR_TEN1_Msk                     (0x1UL << DAC_CR_TEN1_Pos)              /*!< 0x00000002 */
#define DAC_CR_TEN1                         DAC_CR_TEN1_Msk                         /*!<DAC channel1 Trigger enable */
#define DAC_CR_TSEL1_Pos                    (2UL)
#define DAC_CR_TSEL1_Msk                    (0xFUL << DAC_CR_TSEL1_Pos)             /*!< 0x0000003C */
#define DAC_CR_TSEL1                        DAC_CR_TSEL1_Msk                        /*!<TSEL1[3:0] (DAC channel1 Trigger selection) */
#define DAC_CR_TSEL1_0                      (0x1UL << DAC_CR_TSEL1_Pos)             /*!< 0x00000004 */
#define DAC_CR_TSEL1_1                      (0x2UL << DAC_CR_TSEL1_Pos)             /*!< 0x00000008 */
#define DAC_CR_TSEL1_2                      (0x4UL << DAC_CR_TSEL1_Pos)             /*!< 0x00000010 */
#define DAC_CR_TSEL1_3                      (0x8UL << DAC_CR_TSEL1_Pos)             /*!< 0x00000020 */
#define DAC_CR_WAVE1_Pos                    (6UL)
#define DAC_CR_WAVE1_Msk                    (0x3UL << DAC_CR_WAVE1_Pos)             /*!< 0x000000C0 */
#define DAC_CR_WAVE1                        DAC_CR_WAVE1_Msk                        /*!<WAVE1[1:0] (DAC channel1 noise/triangle wave generation enable) */
#define DAC_CR_WAVE1_0                      (0x1UL << DAC_CR_WAVE1_Pos)             /*!< 0x00000040 */
#define DAC_CR_WAVE1_1                      (0x2UL << DAC_CR_WAVE1_Pos)             /*!< 0x00000080 */
#define DAC_CR_MAMP1_Pos                    (8UL)
#define DAC_CR_MAMP1_Msk                    (0xFUL << DAC_CR_MAMP1_Pos)             /*!< 0x00000F00 */
#define DAC_CR_MAMP1                        DAC_CR_MAMP1_Msk                        /*!<MAMP1[3:0] (DAC channel1 Mask/Amplitude selector) */
#define DAC_CR_MAMP1_0                      (0x1UL << DAC_CR_MAMP1_Pos)             /*!< 0x00000100 */
#define DAC_CR_MAMP1_1                      (0x2UL << DAC_CR_MAMP1_Pos)             /*!< 0x00000200 */
#define DAC_CR_MAMP1_2                      (0x4UL << DAC_CR_MAMP1_Pos)             /*!< 0x00000400 */
#define DAC_CR_MAMP1_3                      (0x8UL << DAC_CR_MAMP1_Pos)             /*!< 0x00000800 */
#define DAC_CR_DMAEN1_Pos                   (12UL)
#define DAC_CR_DMAEN1_Msk                   (0x1UL << DAC_CR_DMAEN1_Pos)            /*!< 0x00001000 */
#define DAC_CR_DMAEN1                       DAC_CR_DMAEN1_Msk                       /*!<DAC channel1 DMA enable */
#define DAC_CR_DMAUDRIE1_Pos                (13UL)
#define DAC_CR_DMAUDRIE1_Msk                (0x1UL << DAC_CR_DMAUDRIE1_Pos)         /*!< 0x00002000 */
#define DAC_CR_DMAUDRIE1                    DAC_CR_DMAUDRIE1_Msk                    /*!<DAC channel 1 DMA underrun interrupt enable  >*/
#define DAC_CR_CEN1_Pos                     (14UL)
#define DAC_CR_CEN1_Msk                     (0x1UL << DAC_CR_CEN1_Pos)              /*!< 0x00004000 */
#define DAC_CR_CEN1                         DAC_CR_CEN1_Msk                         /*!<DAC channel 1 calibration enable >*/
#define DAC_CR_EN2_Pos                      (16UL)
#define DAC_CR_EN2_Msk                      (0x1UL << DAC_CR_EN2_Pos)               /*!< 0x00010000 */
#define DAC_CR_EN2                          DAC_CR_EN2_Msk                          /*!<DAC channel2 enable */
#define DAC_CR_TEN2_Pos                     (17UL)
#define DAC_CR_TEN2_Msk                     (0x1UL << DAC_CR_TEN2_Pos)              /*!< 0x00020000 */
#define DAC_CR_TEN2                         DAC_CR_TEN2_Msk                         /*!<DAC channel2 Trigger enable */
#define DAC_CR_TSEL2_Pos                    (18UL)
#define DAC_CR_TSEL2_Msk                    (0xFUL << DAC_CR_TSEL2_Pos)             /*!< 0x003C0000 */
#define DAC_CR_TSEL2                        DAC_CR_TSEL2_Msk                        /*!<TSEL2[3:0] (DAC channel2 Trigger selection) */
#define DAC_CR_TSEL2_0                      (0x1UL << DAC_CR_TSEL2_Pos)             /*!< 0x00040000 */
#define DAC_CR_TSEL2_1                      (0x2UL << DAC_CR_TSEL2_Pos)             /*!< 0x00080000 */
#define DAC_CR_TSEL2_2                      (0x4UL << DAC_CR_TSEL2_Pos)             /*!< 0x00100000 */
#define DAC_CR_TSEL2_3                      (0x8UL << DAC_CR_TSEL2_Pos)             /*!< 0x00200000 */
#define DAC_CR_WAVE2_Pos                    (22UL)
#define DAC_CR_WAVE2_Msk                    (0x3UL << DAC_CR_WAVE2_Pos)             /*!< 0x00C00000 */
#define DAC_CR_WAVE2                        DAC_CR_WAVE2_Msk                        /*!<WAVE2[1:0] (DAC channel2 noise/triangle wave generation enable) */
#define DAC_CR_WAVE2_0                      (0x1UL << DAC_CR_WAVE2_Pos)             /*!< 0x00400000 */
#define DAC_CR_WAVE2_1                      (0x2UL << DAC_CR_WAVE2_Pos)             /*!< 0x00800000 */
#define DAC_CR_MAMP2_Pos                    (24UL)
#define DAC_CR_MAMP2_Msk                    (0xFUL << DAC_CR_MAMP2_Pos)             /*!< 0x0F000000 */
#define DAC_CR_MAMP2                        DAC_CR_MAMP2_Msk                        /*!<MAMP2[3:0] (DAC channel2 Mask/Amplitude selector) */
#define DAC_CR_MAMP2_0                      (0x1UL << DAC_CR_MAMP2_Pos)             /*!< 0x01000000 */
#define DAC_CR_MAMP2_1                      (0x2UL << DAC_CR_MAMP2_Pos)             /*!< 0x02000000 */
#define DAC_CR_MAMP2_2                      (0x4UL << DAC_CR_MAMP2_Pos)             /*!< 0x04000000 */
#define DAC_CR_MAMP2_3                      (0x8UL << DAC_CR_MAMP2_Pos)             /*!< 0x08000000 */
#define DAC_CR_DMAEN2_Pos                   (28UL)
#define DAC_CR_DMAEN2_Msk                   (0x1UL << DAC_CR_DMAEN2_Pos)            /*!< 0x10000000 */
#define DAC_CR_DMAEN2                       DAC_CR_DMAEN2_Msk                       /*!<DAC channel2 DMA enabled */
#define DAC_CR_DMAUDRIE2_Pos                (29UL)
#define DAC_CR_DMAUDRIE2_Msk                (0x1UL << DAC_CR_DMAUDRIE2_Pos)         /*!< 0x20000000 */
#define DAC_CR_DMAUDRIE2                    DAC_CR_DMAUDRIE2_Msk                    /*!<DAC channel2 DMA underrun interrupt enable  >*/
#define DAC_CR_CEN2_Pos                     (30UL)
#define DAC_CR_CEN2_Msk                     (0x1UL << DAC_CR_CEN2_Pos)              /*!< 0x40000000 */
#define DAC_CR_CEN2                         DAC_CR_CEN2_Msk                         /*!<DAC channel2 calibration enable >*/

/*****************  Bit definition for DAC_SWTRIGR register  ******************/
#define DAC_SWTRIGR_SWTRIG1_Pos             (0UL)
#define DAC_SWTRIGR_SWTRIG1_Msk             (0x1UL << DAC_SWTRIGR_SWTRIG1_Pos)      /*!< 0x00000001 */
#define DAC_SWTRIGR_SWTRIG1                 DAC_SWTRIGR_SWTRIG1_Msk                 /*!<DAC channel1 software trigger */
#define DAC_SWTRIGR_SWTRIG2_Pos             (1UL)
#define DAC_SWTRIGR_SWTRIG2_Msk             (0x1UL << DAC_SWTRIGR_SWTRIG2_Pos)      /*!< 0x00000002 */
#define DAC_SWTRIGR_SWTRIG2                 DAC_SWTRIGR_SWTRIG2_Msk                 /*!<DAC channel2 software trigger */
#define DAC_SWTRIGR_SWTRIGB1_Pos            (16UL)
#define DAC_SWTRIGR_SWTRIGB1_Msk            (0x1UL << DAC_SWTRIGR_SWTRIGB1_Pos)     /*!< 0x00010000 */
#define DAC_SWTRIGR_SWTRIGB1                DAC_SWTRIGR_SWTRIGB1_Msk                /*!<DAC channel1 software trigger B */
#define DAC_SWTRIGR_SWTRIGB2_Pos            (17UL)
#define DAC_SWTRIGR_SWTRIGB2_Msk            (0x1UL << DAC_SWTRIGR_SWTRIGB2_Pos)     /*!< 0x00020000 */
#define DAC_SWTRIGR_SWTRIGB2                DAC_SWTRIGR_SWTRIGB2_Msk                /*!<DAC channel2 software trigger B */

/*****************  Bit definition for DAC_DHR12R1 register  ******************/
#define DAC_DHR12R1_DACC1DHR_Pos            (0UL)
#define DAC_DHR12R1_DACC1DHR_Msk            (0xFFFUL << DAC_DHR12R1_DACC1DHR_Pos)   /*!< 0x00000FFF */
#define DAC_DHR12R1_DACC1DHR                DAC_DHR12R1_DACC1DHR_Msk                /*!<DAC channel1 12-bit Right aligned data */
#define DAC_DHR12R1_DACC1DHRB_Pos           (16UL)
#define DAC_DHR12R1_DACC1DHRB_Msk           (0xFFFUL << DAC_DHR12R1_DACC1DHRB_Pos)  /*!< 0x0FFF0000 */
#define DAC_DHR12R1_DACC1DHRB               DAC_DHR12R1_DACC1DHRB_Msk               /*!<DAC channel1 12-bit Right-aligned data B */

/*****************  Bit definition for DAC_DHR12L1 register  ******************/
#define DAC_DHR12L1_DACC1DHR_Pos            (4UL)
#define DAC_DHR12L1_DACC1DHR_Msk            (0xFFFUL << DAC_DHR12L1_DACC1DHR_Pos)   /*!< 0x0000FFF0 */
#define DAC_DHR12L1_DACC1DHR                DAC_DHR12L1_DACC1DHR_Msk                /*!<DAC channel1 12-bit Left aligned data */
#define DAC_DHR12L1_DACC1DHRB_Pos           (20UL)
#define DAC_DHR12L1_DACC1DHRB_Msk           (0xFFFUL << DAC_DHR12L1_DACC1DHRB_Pos)  /*!< 0xFFF00000 */
#define DAC_DHR12L1_DACC1DHRB               DAC_DHR12L1_DACC1DHRB_Msk               /*!<DAC channel1 12-bit Left aligned data B */

/******************  Bit definition for DAC_DHR8R1 register  ******************/
#define DAC_DHR8R1_DACC1DHR_Pos             (0UL)
#define DAC_DHR8R1_DACC1DHR_Msk             (0xFFUL << DAC_DHR8R1_DACC1DHR_Pos)     /*!< 0x000000FF */
#define DAC_DHR8R1_DACC1DHR                 DAC_DHR8R1_DACC1DHR_Msk                 /*!<DAC channel1 8-bit Right aligned data */
#define DAC_DHR8R1_DACC1DHRB_Pos            (8UL)
#define DAC_DHR8R1_DACC1DHRB_Msk            (0xFFUL << DAC_DHR8R1_DACC1DHRB_Pos)    /*!< 0x0000FF00 */
#define DAC_DHR8R1_DACC1DHRB                DAC_DHR8R1_DACC1DHRB_Msk                /*!<DAC channel1 8-bit Right aligned data B */

/*****************  Bit definition for DAC_DHR12R2 register  ******************/
#define DAC_DHR12R2_DACC2DHR_Pos            (0UL)
#define DAC_DHR12R2_DACC2DHR_Msk            (0xFFFUL << DAC_DHR12R2_DACC2DHR_Pos)   /*!< 0x00000FFF */
#define DAC_DHR12R2_DACC2DHR                DAC_DHR12R2_DACC2DHR_Msk                /*!<DAC channel2 12-bit Right aligned data */
#define DAC_DHR12R2_DACC2DHRB_Pos           (16UL)
#define DAC_DHR12R2_DACC2DHRB_Msk           (0xFFFUL << DAC_DHR12R2_DACC2DHRB_Pos)  /*!< 0x0FFF0000 */
#define DAC_DHR12R2_DACC2DHRB               DAC_DHR12R2_DACC2DHRB_Msk               /*!<DAC channel2 12-bit Right-aligned data B */

/*****************  Bit definition for DAC_DHR12L2 register  ******************/
#define DAC_DHR12L2_DACC2DHR_Pos            (4UL)
#define DAC_DHR12L2_DACC2DHR_Msk            (0xFFFUL << DAC_DHR12L2_DACC2DHR_Pos)   /*!< 0x0000FFF0 */
#define DAC_DHR12L2_DACC2DHR                DAC_DHR12L2_DACC2DHR_Msk                /*!<DAC channel2 12-bit Left aligned data */
#define DAC_DHR12L2_DACC2DHRB_Pos           (20UL)
#define DAC_DHR12L2_DACC2DHRB_Msk           (0xFFFUL << DAC_DHR12L2_DACC2DHRB_Pos)  /*!< 0xFFF00000 */
#define DAC_DHR12L2_DACC2DHRB               DAC_DHR12L2_DACC2DHRB_Msk               /*!<DAC channel2 12-bit Left aligned data B */

/******************  Bit definition for DAC_DHR8R2 register  ******************/
#define DAC_DHR8R2_DACC2DHR_Pos             (0UL)
#define DAC_DHR8R2_DACC2DHR_Msk             (0xFFUL << DAC_DHR8R2_DACC2DHR_Pos)     /*!< 0x000000FF */
#define DAC_DHR8R2_DACC2DHR                 DAC_DHR8R2_DACC2DHR_Msk                 /*!<DAC channel2 8-bit Right aligned data */
#define DAC_DHR8R2_DACC2DHRB_Pos            (8UL)
#define DAC_DHR8R2_DACC2DHRB_Msk            (0xFFUL << DAC_DHR8R2_DACC2DHRB_Pos)    /*!< 0x0000FF00 */
#define DAC_DHR8R2_DACC2DHRB                DAC_DHR8R2_DACC2DHRB_Msk                /*!<DAC channel2 8-bit Right aligned data B */

/*****************  Bit definition for DAC_DHR12RD register  ******************/
#define DAC_DHR12RD_DACC1DHR_Pos            (0UL)
#define DAC_DHR12RD_DACC1DHR_Msk            (0xFFFUL << DAC_DHR12RD_DACC1DHR_Pos)   /*!< 0x00000FFF */
#define DAC_DHR12RD_DACC1DHR                DAC_DHR12RD_DACC1DHR_Msk                /*!<DAC channel1 12-bit Right aligned data */
#define DAC_DHR12RD_DACC2DHR_Pos            (16UL)
#define DAC_DHR12RD_DACC2DHR_Msk            (0xFFFUL << DAC_DHR12RD_DACC2DHR_Pos)   /*!< 0x0FFF0000 */
#define DAC_DHR12RD_DACC2DHR                DAC_DHR12RD_DACC2DHR_Msk                /*!<DAC channel2 12-bit Right aligned data */

/*****************  Bit definition for DAC_DHR12LD register  ******************/
#define DAC_DHR12LD_DACC1DHR_Pos            (4UL)
#define DAC_DHR12LD_DACC1DHR_Msk            (0xFFFUL << DAC_DHR12LD_DACC1DHR_Pos)   /*!< 0x0000FFF0 */
#define DAC_DHR12LD_DACC1DHR                DAC_DHR12LD_DACC1DHR_Msk                /*!<DAC channel1 12-bit Left aligned data */
#define DAC_DHR12LD_DACC2DHR_Pos            (20UL)
#define DAC_DHR12LD_DACC2DHR_Msk            (0xFFFUL << DAC_DHR12LD_DACC2DHR_Pos)   /*!< 0xFFF00000 */
#define DAC_DHR12LD_DACC2DHR                DAC_DHR12LD_DACC2DHR_Msk                /*!<DAC channel2 12-bit Left aligned data */

/******************  Bit definition for DAC_DHR8RD register  ******************/
#define DAC_DHR8RD_DACC1DHR_Pos             (0UL)
#define DAC_DHR8RD_DACC1DHR_Msk             (0xFFUL << DAC_DHR8RD_DACC1DHR_Pos)     /*!< 0x000000FF */
#define DAC_DHR8RD_DACC1DHR                 DAC_DHR8RD_DACC1DHR_Msk                 /*!<DAC channel1 8-bit Right aligned data */
#define DAC_DHR8RD_DACC2DHR_Pos             (8UL)
#define DAC_DHR8RD_DACC2DHR_Msk             (0xFFUL << DAC_DHR8RD_DACC2DHR_Pos)     /*!< 0x0000FF00 */
#define DAC_DHR8RD_DACC2DHR                 DAC_DHR8RD_DACC2DHR_Msk                 /*!<DAC channel2 8-bit Right aligned data */

/*******************  Bit definition for DAC_DOR1 register  *******************/
#define DAC_DOR1_DACC1DOR_Pos               (0UL)
#define DAC_DOR1_DACC1DOR_Msk               (0xFFFUL << DAC_DOR1_DACC1DOR_Pos)      /*!< 0x00000FFF */
#define DAC_DOR1_DACC1DOR                   DAC_DOR1_DACC1DOR_Msk                   /*!<DAC channel1 data output */
#define DAC_DOR1_DACC1DORB_Pos              (16UL)
#define DAC_DOR1_DACC1DORB_Msk              (0xFFFUL << DAC_DOR1_DACC1DORB_Pos)     /*!< 0x0FFF0000 */
#define DAC_DOR1_DACC1DORB                  DAC_DOR1_DACC1DORB_Msk                  /*!<DAC channel1 data output B */

/*******************  Bit definition for DAC_DOR2 register  *******************/
#define DAC_DOR2_DACC2DOR_Pos               (0UL)
#define DAC_DOR2_DACC2DOR_Msk               (0xFFFUL << DAC_DOR2_DACC2DOR_Pos)      /*!< 0x00000FFF */
#define DAC_DOR2_DACC2DOR                   DAC_DOR2_DACC2DOR_Msk                   /*!<DAC channel2 data output */
#define DAC_DOR2_DACC2DORB_Pos              (16UL)
#define DAC_DOR2_DACC2DORB_Msk              (0xFFFUL << DAC_DOR2_DACC2DORB_Pos)     /*!< 0x0FFF0000 */
#define DAC_DOR2_DACC2DORB                  DAC_DOR2_DACC2DORB_Msk                  /*!<DAC channel2 data output B */

/********************  Bit definition for DAC_SR register  ********************/
#define DAC_SR_DAC1RDY_Pos                  (11UL)
#define DAC_SR_DAC1RDY_Msk                  (0x1UL << DAC_SR_DAC1RDY_Pos)           /*!< 0x00000800 */
#define DAC_SR_DAC1RDY                      DAC_SR_DAC1RDY_Msk                      /*!<DAC channel 1 ready status bit */
#define DAC_SR_DORSTAT1_Pos                 (12UL)
#define DAC_SR_DORSTAT1_Msk                 (0x1UL << DAC_SR_DORSTAT1_Pos)          /*!< 0x00001000 */
#define DAC_SR_DORSTAT1                     DAC_SR_DORSTAT1_Msk                     /*!<DAC channel 1 output register status bit */
#define DAC_SR_DMAUDR1_Pos                  (13UL)
#define DAC_SR_DMAUDR1_Msk                  (0x1UL << DAC_SR_DMAUDR1_Pos)           /*!< 0x00002000 */
#define DAC_SR_DMAUDR1                      DAC_SR_DMAUDR1_Msk                      /*!<DAC channel1 DMA underrun flag */
#define DAC_SR_CAL_FLAG1_Pos                (14UL)
#define DAC_SR_CAL_FLAG1_Msk                (0x1UL << DAC_SR_CAL_FLAG1_Pos)         /*!< 0x00004000 */
#define DAC_SR_CAL_FLAG1                    DAC_SR_CAL_FLAG1_Msk                    /*!<DAC channel1 calibration offset status */
#define DAC_SR_BWST1_Pos                    (15UL)
#define DAC_SR_BWST1_Msk                    (0x1UL << DAC_SR_BWST1_Pos)             /*!< 0x00008000 */
#define DAC_SR_BWST1                        DAC_SR_BWST1_Msk                        /*!<DAC channel1 busy writing sample time flag */

#define DAC_SR_DAC2RDY_Pos                  (27UL)
#define DAC_SR_DAC2RDY_Msk                  (0x1UL << DAC_SR_DAC2RDY_Pos)           /*!< 0x08000000 */
#define DAC_SR_DAC2RDY                      DAC_SR_DAC2RDY_Msk                      /*!<DAC channel 2 ready status bit */
#define DAC_SR_DORSTAT2_Pos                 (28UL)
#define DAC_SR_DORSTAT2_Msk                 (0x1UL << DAC_SR_DORSTAT2_Pos)          /*!< 0x10000000 */
#define DAC_SR_DORSTAT2                     DAC_SR_DORSTAT2_Msk                     /*!<DAC channel 2 output register status bit */
#define DAC_SR_DMAUDR2_Pos                  (29UL)
#define DAC_SR_DMAUDR2_Msk                  (0x1UL << DAC_SR_DMAUDR2_Pos)           /*!< 0x20000000 */
#define DAC_SR_DMAUDR2                      DAC_SR_DMAUDR2_Msk                      /*!<DAC channel2 DMA underrun flag */
#define DAC_SR_CAL_FLAG2_Pos                (30UL)
#define DAC_SR_CAL_FLAG2_Msk                (0x1UL << DAC_SR_CAL_FLAG2_Pos)         /*!< 0x40000000 */
#define DAC_SR_CAL_FLAG2                    DAC_SR_CAL_FLAG2_Msk                    /*!<DAC channel2 calibration offset status */
#define DAC_SR_BWST2_Pos                    (31UL)
#define DAC_SR_BWST2_Msk                    (0x1UL << DAC_SR_BWST2_Pos)             /*!< 0x80000000 */
#define DAC_SR_BWST2                        DAC_SR_BWST2_Msk                        /*!<DAC channel2 busy writing sample time flag */

/*******************  Bit definition for DAC_CCR register  ********************/
#define DAC_CCR_OTRIM1_Pos                  (0UL)
#define DAC_CCR_OTRIM1_Msk                  (0x1FUL << DAC_CCR_OTRIM1_Pos)          /*!< 0x0000001F */
#define DAC_CCR_OTRIM1                      DAC_CCR_OTRIM1_Msk                      /*!<DAC channel1 offset trimming value */
#define DAC_CCR_OTRIM2_Pos                  (16UL)
#define DAC_CCR_OTRIM2_Msk                  (0x1FUL << DAC_CCR_OTRIM2_Pos)          /*!< 0x001F0000 */
#define DAC_CCR_OTRIM2                      DAC_CCR_OTRIM2_Msk                      /*!<DAC channel2 offset trimming value */

/*******************  Bit definition for DAC_MCR register  *******************/
#define DAC_MCR_MODE1_Pos                   (0UL)
#define DAC_MCR_MODE1_Msk                   (0x7UL << DAC_MCR_MODE1_Pos)            /*!< 0x00000007 */
#define DAC_MCR_MODE1                       DAC_MCR_MODE1_Msk                       /*!<MODE1[2:0] (DAC channel1 mode) */
#define DAC_MCR_MODE1_0                     (0x1UL << DAC_MCR_MODE1_Pos)            /*!< 0x00000001 */
#define DAC_MCR_MODE1_1                     (0x2UL << DAC_MCR_MODE1_Pos)            /*!< 0x00000002 */
#define DAC_MCR_MODE1_2                     (0x4UL << DAC_MCR_MODE1_Pos)            /*!< 0x00000004 */
#define DAC_MCR_DMADOUBLE1_Pos              (8UL)
#define DAC_MCR_DMADOUBLE1_Msk              (0x1UL << DAC_MCR_DMADOUBLE1_Pos)       /*!< 0x00000100 */
#define DAC_MCR_DMADOUBLE1                  DAC_MCR_DMADOUBLE1_Msk                  /*!<DAC Channel 1 DMA double data mode */
#define DAC_MCR_SINFORMAT1_Pos              (9UL)
#define DAC_MCR_SINFORMAT1_Msk              (0x1UL << DAC_MCR_SINFORMAT1_Pos)       /*!< 0x00000200 */
#define DAC_MCR_SINFORMAT1                  DAC_MCR_SINFORMAT1_Msk                  /*!<DAC Channel 1 enable signed format */
#define DAC_MCR_HFSEL_Pos                   (14UL)
#define DAC_MCR_HFSEL_Msk                   (0x3UL << DAC_MCR_HFSEL_Pos)            /*!< 0x0000C000 */
#define DAC_MCR_HFSEL                       DAC_MCR_HFSEL_Msk                       /*!<HFSEL[1:0] (High Frequency interface mode selection) */
#define DAC_MCR_HFSEL_0                     (0x1UL << DAC_MCR_HFSEL_Pos)            /*!< 0x00004000 */
#define DAC_MCR_HFSEL_1                     (0x2UL << DAC_MCR_HFSEL_Pos)            /*!< 0x00008000 */
#define DAC_MCR_MODE2_Pos                   (16UL)
#define DAC_MCR_MODE2_Msk                   (0x7UL << DAC_MCR_MODE2_Pos)            /*!< 0x00070000 */
#define DAC_MCR_MODE2                       DAC_MCR_MODE2_Msk                       /*!<MODE2[2:0] (DAC channel2 mode) */
#define DAC_MCR_MODE2_0                     (0x1UL << DAC_MCR_MODE2_Pos)            /*!< 0x00010000 */
#define DAC_MCR_MODE2_1                     (0x2UL << DAC_MCR_MODE2_Pos)            /*!< 0x00020000 */
#define DAC_MCR_MODE2_2                     (0x4UL << DAC_MCR_MODE2_Pos)            /*!< 0x00040000 */
#define DAC_MCR_DMADOUBLE2_Pos              (24UL)
#define DAC_MCR_DMADOUBLE2_Msk              (0x1UL << DAC_MCR_DMADOUBLE2_Pos)       /*!< 0x01000000 */
#define DAC_MCR_DMADOUBLE2                  DAC_MCR_DMADOUBLE2_Msk                  /*!<DAC Channel 2 DMA double data mode */
#define DAC_MCR_SINFORMAT2_Pos              (25UL)
#define DAC_MCR_SINFORMAT2_Msk              (0x1UL << DAC_MCR_SINFORMAT2_Pos)       /*!< 0x02000000 */
#define DAC_MCR_SINFORMAT2                  DAC_MCR_SINFORMAT2_Msk                  /*!<DAC Channel 2 enable signed format */

/******************  Bit definition for DAC_SHSR1 register  ******************/
#define DAC_SHSR1_TSAMPLE1_Pos              (0UL)
#define DAC_SHSR1_TSAMPLE1_Msk              (0x3FFUL << DAC_SHSR1_TSAMPLE1_Pos)     /*!< 0x000003FF */
#define DAC_SHSR1_TSAMPLE1                  DAC_SHSR1_TSAMPLE1_Msk                  /*!<DAC channel1 sample time */

/******************  Bit definition for DAC_SHSR2 register  ******************/
#define DAC_SHSR2_TSAMPLE2_Pos              (0UL)
#define DAC_SHSR2_TSAMPLE2_Msk              (0x3FFUL << DAC_SHSR2_TSAMPLE2_Pos)     /*!< 0x000003FF */
#define DAC_SHSR2_TSAMPLE2                  DAC_SHSR2_TSAMPLE2_Msk                  /*!<DAC channel2 sample time */

/******************  Bit definition for DAC_SHHR register  ******************/
#define DAC_SHHR_THOLD1_Pos                 (0UL)
#define DAC_SHHR_THOLD1_Msk                 (0x3FFUL << DAC_SHHR_THOLD1_Pos)        /*!< 0x000003FF */
#define DAC_SHHR_THOLD1                     DAC_SHHR_THOLD1_Msk                     /*!<DAC channel1 hold time */
#define DAC_SHHR_THOLD2_Pos                 (16UL)
#define DAC_SHHR_THOLD2_Msk                 (0x3FFUL << DAC_SHHR_THOLD2_Pos)        /*!< 0x03FF0000 */
#define DAC_SHHR_THOLD2                     DAC_SHHR_THOLD2_Msk                     /*!<DAC channel2 hold time */

/******************  Bit definition for DAC_SHRR register  ******************/
#define DAC_SHRR_TREFRESH1_Pos              (0UL)
#define DAC_SHRR_TREFRESH1_Msk              (0xFFUL << DAC_SHRR_TREFRESH1_Pos)      /*!< 0x000000FF */
#define DAC_SHRR_TREFRESH1                  DAC_SHRR_TREFRESH1_Msk                  /*!<DAC channel1 refresh time */
#define DAC_SHRR_TREFRESH2_Pos              (16UL)
#define DAC_SHRR_TREFRESH2_Msk              (0xFFUL << DAC_SHRR_TREFRESH2_Pos)      /*!< 0x00FF0000 */
#define DAC_SHRR_TREFRESH2                  DAC_SHRR_TREFRESH2_Msk                  /*!<DAC channel2 refresh time */

/******************  Bit definition for DAC_AUTOCR register  ******************/
#define DAC_AUTOCR_AUTOMODE_Pos             (22UL)
#define DAC_AUTOCR_AUTOMODE_Msk             (0x1UL << DAC_AUTOCR_AUTOMODE_Pos)      /*!< 0x00400000 */
#define DAC_AUTOCR_AUTOMODE                 DAC_AUTOCR_AUTOMODE_Msk                 /*!< AUTOCR Enable */

/******************************************************************************/
/*                                                                            */
/*                                 Debug MCU                                  */
/*                                                                            */
/******************************************************************************/
/********************  Bit definition for DBGMCU_IDCODE register  *************/
#define DBGMCU_IDCODE_DEV_ID_Pos            (0UL)
#define DBGMCU_IDCODE_DEV_ID_Msk            (0xFFFUL << DBGMCU_IDCODE_DEV_ID_Pos)   /*!< 0x00000FFF */
#define DBGMCU_IDCODE_DEV_ID                DBGMCU_IDCODE_DEV_ID_Msk
#define DBGMCU_IDCODE_REV_ID_Pos            (16UL)
#define DBGMCU_IDCODE_REV_ID_Msk            (0xFFFFUL << DBGMCU_IDCODE_REV_ID_Pos)  /*!< 0xFFFF0000 */
#define DBGMCU_IDCODE_REV_ID                DBGMCU_IDCODE_REV_ID_Msk

/********************  Bit definition for DBGMCU_CR register  *****************/
#define DBGMCU_CR_DBG_STOP_Pos              (1UL)
#define DBGMCU_CR_DBG_STOP_Msk              (0x1UL << DBGMCU_CR_DBG_STOP_Pos)       /*!< 0x00000002 */
#define DBGMCU_CR_DBG_STOP                  DBGMCU_CR_DBG_STOP_Msk
#define DBGMCU_CR_DBG_STANDBY_Pos           (2UL)
#define DBGMCU_CR_DBG_STANDBY_Msk           (0x1UL << DBGMCU_CR_DBG_STANDBY_Pos)    /*!< 0x00000004 */
#define DBGMCU_CR_DBG_STANDBY               DBGMCU_CR_DBG_STANDBY_Msk
#define DBGMCU_CR_TRACE_IOEN_Pos            (4UL)
#define DBGMCU_CR_TRACE_IOEN_Msk            (0x1UL << DBGMCU_CR_TRACE_IOEN_Pos)     /*!< 0x00000010 */
#define DBGMCU_CR_TRACE_IOEN                DBGMCU_CR_TRACE_IOEN_Msk
#define DBGMCU_CR_TRACE_EN_Pos              (5UL)
#define DBGMCU_CR_TRACE_EN_Msk              (0x1UL << DBGMCU_CR_TRACE_EN_Pos)       /*!< 0x00000020 */
#define DBGMCU_CR_TRACE_EN                  DBGMCU_CR_TRACE_EN_Msk
#define DBGMCU_CR_TRACE_MODE_Pos            (6UL)
#define DBGMCU_CR_TRACE_MODE_Msk            (0x3UL << DBGMCU_CR_TRACE_MODE_Pos)     /*!< 0x000000C0 */
#define DBGMCU_CR_TRACE_MODE                DBGMCU_CR_TRACE_MODE_Msk
#define DBGMCU_CR_TRACE_MODE_0              (0x1UL << DBGMCU_CR_TRACE_MODE_Pos)     /*!< 0x00000040 */
#define DBGMCU_CR_TRACE_MODE_1              (0x2UL << DBGMCU_CR_TRACE_MODE_Pos)     /*!< 0x00000080 */

/********************  Bit definition for DBGMCU_APB1FZR1 register  ***********/
#define DBGMCU_APB1FZR1_DBG_TIM2_STOP_Pos   (0UL)
#define DBGMCU_APB1FZR1_DBG_TIM2_STOP_Msk   (0x1UL << DBGMCU_APB1FZR1_DBG_TIM2_STOP_Pos)
#define DBGMCU_APB1FZR1_DBG_TIM2_STOP       DBGMCU_APB1FZR1_DBG_TIM2_STOP_Msk
#define DBGMCU_APB1FZR1_DBG_TIM3_STOP_Pos   (1UL)
#define DBGMCU_APB1FZR1_DBG_TIM3_STOP_Msk   (0x1UL << DBGMCU_APB1FZR1_DBG_TIM3_STOP_Pos)
#define DBGMCU_APB1FZR1_DBG_TIM3_STOP       DBGMCU_APB1FZR1_DBG_TIM3_STOP_Msk
#define DBGMCU_APB1FZR1_DBG_TIM4_STOP_Pos   (2UL)
#define DBGMCU_APB1FZR1_DBG_TIM4_STOP_Msk   (0x1UL << DBGMCU_APB1FZR1_DBG_TIM4_STOP_Pos)
#define DBGMCU_APB1FZR1_DBG_TIM4_STOP       DBGMCU_APB1FZR1_DBG_TIM4_STOP_Msk
#define DBGMCU_APB1FZR1_DBG_TIM6_STOP_Pos   (4UL)
#define DBGMCU_APB1FZR1_DBG_TIM6_STOP_Msk   (0x1UL << DBGMCU_APB1FZR1_DBG_TIM6_STOP_Pos)
#define DBGMCU_APB1FZR1_DBG_TIM6_STOP       DBGMCU_APB1FZR1_DBG_TIM6_STOP_Msk
#define DBGMCU_APB1FZR1_DBG_TIM7_STOP_Pos   (5UL)
#define DBGMCU_APB1FZR1_DBG_TIM7_STOP_Msk   (0x1UL << DBGMCU_APB1FZR1_DBG_TIM7_STOP_Pos)
#define DBGMCU_APB1FZR1_DBG_TIM7_STOP       DBGMCU_APB1FZR1_DBG_TIM7_STOP_Msk
#define DBGMCU_APB1FZR1_DBG_WWDG_STOP_Pos   (11UL)
#define DBGMCU_APB1FZR1_DBG_WWDG_STOP_Msk   (0x1UL << DBGMCU_APB1FZR1_DBG_WWDG_STOP_Pos)
#define DBGMCU_APB1FZR1_DBG_WWDG_STOP       DBGMCU_APB1FZR1_DBG_WWDG_STOP_Msk
#define DBGMCU_APB1FZR1_DBG_IWDG_STOP_Pos   (12UL)
#define DBGMCU_APB1FZR1_DBG_IWDG_STOP_Msk   (0x1UL << DBGMCU_APB1FZR1_DBG_IWDG_STOP_Pos)
#define DBGMCU_APB1FZR1_DBG_IWDG_STOP       DBGMCU_APB1FZR1_DBG_IWDG_STOP_Msk
#define DBGMCU_APB1FZR1_DBG_I2C1_STOP_Pos   (21UL)
#define DBGMCU_APB1FZR1_DBG_I2C1_STOP_Msk   (0x1UL << DBGMCU_APB1FZR1_DBG_I2C1_STOP_Pos)
#define DBGMCU_APB1FZR1_DBG_I2C1_STOP       DBGMCU_APB1FZR1_DBG_I2C1_STOP_Msk
#define DBGMCU_APB1FZR1_DBG_I2C2_STOP_Pos   (22UL)
#define DBGMCU_APB1FZR1_DBG_I2C2_STOP_Msk   (0x1UL << DBGMCU_APB1FZR1_DBG_I2C2_STOP_Pos)
#define DBGMCU_APB1FZR1_DBG_I2C2_STOP       DBGMCU_APB1FZR1_DBG_I2C2_STOP_Msk
#define DBGMCU_APB1FZR1_DBG_I3C1_STOP_Pos   (23UL)
#define DBGMCU_APB1FZR1_DBG_I3C1_STOP_Msk   (0x1UL << DBGMCU_APB1FZR1_DBG_I3C1_STOP_Pos)
#define DBGMCU_APB1FZR1_DBG_I3C1_STOP       DBGMCU_APB1FZR1_DBG_I3C1_STOP_Msk
#define DBGMCU_APB1FZR1_DBG_RTC_STOP_Pos    (30UL)
#define DBGMCU_APB1FZR1_DBG_RTC_STOP_Msk    (0x1UL << DBGMCU_APB1FZR1_DBG_RTC_STOP_Pos)
#define DBGMCU_APB1FZR1_DBG_RTC_STOP        DBGMCU_APB1FZR1_DBG_RTC_STOP_Msk

/********************  Bit definition for DBGMCU_APB1FZR2 register  ***********/
#define DBGMCU_APB1FZR2_DBG_LPTIM2_STOP_Pos (5UL)
#define DBGMCU_APB1FZR2_DBG_LPTIM2_STOP_Msk (0x1UL << DBGMCU_APB1FZR2_DBG_LPTIM2_STOP_Pos)
#define DBGMCU_APB1FZR2_DBG_LPTIM2_STOP     DBGMCU_APB1FZR2_DBG_LPTIM2_STOP_Msk

/********************  Bit definition for DBGMCU_APB2FZR register  ***********/
#define DBGMCU_APB2FZR_DBG_TIM1_STOP_Pos    (11UL)
#define DBGMCU_APB2FZR_DBG_TIM1_STOP_Msk    (0x1UL << DBGMCU_APB2FZR_DBG_TIM1_STOP_Pos)
#define DBGMCU_APB2FZR_DBG_TIM1_STOP        DBGMCU_APB2FZR_DBG_TIM1_STOP_Msk
#define DBGMCU_APB2FZR_DBG_TIM15_STOP_Pos   (16UL)
#define DBGMCU_APB2FZR_DBG_TIM15_STOP_Msk   (0x1UL << DBGMCU_APB2FZR_DBG_TIM15_STOP_Pos)
#define DBGMCU_APB2FZR_DBG_TIM15_STOP       DBGMCU_APB2FZR_DBG_TIM15_STOP_Msk
#define DBGMCU_APB2FZR_DBG_TIM16_STOP_Pos   (17UL)
#define DBGMCU_APB2FZR_DBG_TIM16_STOP_Msk   (0x1UL << DBGMCU_APB2FZR_DBG_TIM16_STOP_Pos)
#define DBGMCU_APB2FZR_DBG_TIM16_STOP       DBGMCU_APB2FZR_DBG_TIM16_STOP_Msk
#define DBGMCU_APB2FZR_DBG_TIM17_STOP_Pos   (18UL)
#define DBGMCU_APB2FZR_DBG_TIM17_STOP_Msk   (0x1UL << DBGMCU_APB2FZR_DBG_TIM17_STOP_Pos)
#define DBGMCU_APB2FZR_DBG_TIM17_STOP       DBGMCU_APB2FZR_DBG_TIM17_STOP_Msk
#define DBGMCU_APB2FZR_DBG_I3C2_STOP_Pos    (27UL)
#define DBGMCU_APB2FZR_DBG_I3C2_STOP_Msk    (0x1UL << DBGMCU_APB2FZR_DBG_I3C2_STOP_Pos)
#define DBGMCU_APB2FZR_DBG_I3C2_STOP        DBGMCU_APB2FZR_DBG_I3C2_STOP_Msk

/********************  Bit definition for DBGMCU_APB3FZR register  ***********/
#define DBGMCU_APB3FZR_DBG_I2C3_STOP_Pos    (10UL)
#define DBGMCU_APB3FZR_DBG_I2C3_STOP_Msk    (0x1UL << DBGMCU_APB3FZR_DBG_I2C3_STOP_Pos)
#define DBGMCU_APB3FZR_DBG_I2C3_STOP        DBGMCU_APB3FZR_DBG_I2C3_STOP_Msk
#define DBGMCU_APB3FZR_DBG_LPTIM1_STOP_Pos  (17UL)
#define DBGMCU_APB3FZR_DBG_LPTIM1_STOP_Msk  (0x1UL << DBGMCU_APB3FZR_DBG_LPTIM1_STOP_Pos)
#define DBGMCU_APB3FZR_DBG_LPTIM1_STOP      DBGMCU_APB3FZR_DBG_LPTIM1_STOP_Msk
#define DBGMCU_APB3FZR_DBG_LPTIM3_STOP_Pos  (18UL)
#define DBGMCU_APB3FZR_DBG_LPTIM3_STOP_Msk  (0x1UL << DBGMCU_APB3FZR_DBG_LPTIM3_STOP_Pos)
#define DBGMCU_APB3FZR_DBG_LPTIM3_STOP      DBGMCU_APB3FZR_DBG_LPTIM3_STOP_Msk
#define DBGMCU_APB3FZR_DBG_LPTIM4_STOP_Pos  (19UL)
#define DBGMCU_APB3FZR_DBG_LPTIM4_STOP_Msk  (0x1UL << DBGMCU_APB3FZR_DBG_LPTIM4_STOP_Pos)
#define DBGMCU_APB3FZR_DBG_LPTIM4_STOP      DBGMCU_APB3FZR_DBG_LPTIM4_STOP_Msk

/********************  Bit definition for DBGMCU_AHB1FZR register  ***********/
#define DBGMCU_AHB1FZR_DBG_GPDMA0_STOP_Pos  (0UL)
#define DBGMCU_AHB1FZR_DBG_GPDMA0_STOP_Msk  (0x1UL << DBGMCU_AHB1FZR_DBG_GPDMA0_STOP_Pos)
#define DBGMCU_AHB1FZR_DBG_GPDMA0_STOP      DBGMCU_AHB1FZR_DBG_GPDMA0_STOP_Msk
#define DBGMCU_AHB1FZR_DBG_GPDMA1_STOP_Pos  (1UL)
#define DBGMCU_AHB1FZR_DBG_GPDMA1_STOP_Msk  (0x1UL << DBGMCU_AHB1FZR_DBG_GPDMA1_STOP_Pos)
#define DBGMCU_AHB1FZR_DBG_GPDMA1_STOP      DBGMCU_AHB1FZR_DBG_GPDMA1_STOP_Msk
#define DBGMCU_AHB1FZR_DBG_GPDMA2_STOP_Pos  (2UL)
#define DBGMCU_AHB1FZR_DBG_GPDMA2_STOP_Msk  (0x1UL << DBGMCU_AHB1FZR_DBG_GPDMA2_STOP_Pos)
#define DBGMCU_AHB1FZR_DBG_GPDMA2_STOP      DBGMCU_AHB1FZR_DBG_GPDMA2_STOP_Msk
#define DBGMCU_AHB1FZR_DBG_GPDMA3_STOP_Pos  (3UL)
#define DBGMCU_AHB1FZR_DBG_GPDMA3_STOP_Msk  (0x1UL << DBGMCU_AHB1FZR_DBG_GPDMA3_STOP_Pos)
#define DBGMCU_AHB1FZR_DBG_GPDMA3_STOP      DBGMCU_AHB1FZR_DBG_GPDMA3_STOP_Msk
#define DBGMCU_AHB1FZR_DBG_GPDMA4_STOP_Pos  (4UL)
#define DBGMCU_AHB1FZR_DBG_GPDMA4_STOP_Msk  (0x1UL << DBGMCU_AHB1FZR_DBG_GPDMA4_STOP_Pos)
#define DBGMCU_AHB1FZR_DBG_GPDMA4_STOP      DBGMCU_AHB1FZR_DBG_GPDMA4_STOP_Msk
#define DBGMCU_AHB1FZR_DBG_GPDMA5_STOP_Pos  (5UL)
#define DBGMCU_AHB1FZR_DBG_GPDMA5_STOP_Msk  (0x1UL << DBGMCU_AHB1FZR_DBG_GPDMA5_STOP_Pos)
#define DBGMCU_AHB1FZR_DBG_GPDMA5_STOP      DBGMCU_AHB1FZR_DBG_GPDMA5_STOP_Msk
#define DBGMCU_AHB1FZR_DBG_GPDMA6_STOP_Pos  (6UL)
#define DBGMCU_AHB1FZR_DBG_GPDMA6_STOP_Msk  (0x1UL << DBGMCU_AHB1FZR_DBG_GPDMA6_STOP_Pos)
#define DBGMCU_AHB1FZR_DBG_GPDMA6_STOP      DBGMCU_AHB1FZR_DBG_GPDMA6_STOP_Msk
#define DBGMCU_AHB1FZR_DBG_GPDMA7_STOP_Pos  (7UL)
#define DBGMCU_AHB1FZR_DBG_GPDMA7_STOP_Msk  (0x1UL << DBGMCU_AHB1FZR_DBG_GPDMA7_STOP_Pos)
#define DBGMCU_AHB1FZR_DBG_GPDMA7_STOP      DBGMCU_AHB1FZR_DBG_GPDMA7_STOP_Msk
#define DBGMCU_AHB1FZR_DBG_GPDMA8_STOP_Pos  (8UL)
#define DBGMCU_AHB1FZR_DBG_GPDMA8_STOP_Msk  (0x1UL << DBGMCU_AHB1FZR_DBG_GPDMA8_STOP_Pos)
#define DBGMCU_AHB1FZR_DBG_GPDMA8_STOP      DBGMCU_AHB1FZR_DBG_GPDMA8_STOP_Msk
#define DBGMCU_AHB1FZR_DBG_GPDMA9_STOP_Pos  (9UL)
#define DBGMCU_AHB1FZR_DBG_GPDMA9_STOP_Msk  (0x1UL << DBGMCU_AHB1FZR_DBG_GPDMA9_STOP_Pos)
#define DBGMCU_AHB1FZR_DBG_GPDMA9_STOP      DBGMCU_AHB1FZR_DBG_GPDMA9_STOP_Msk
#define DBGMCU_AHB1FZR_DBG_GPDMA10_STOP_Pos (10UL)
#define DBGMCU_AHB1FZR_DBG_GPDMA10_STOP_Msk (0x1UL << DBGMCU_AHB1FZR_DBG_GPDMA10_STOP_Pos)
#define DBGMCU_AHB1FZR_DBG_GPDMA10_STOP     DBGMCU_AHB1FZR_DBG_GPDMA10_STOP_Msk
#define DBGMCU_AHB1FZR_DBG_GPDMA11_STOP_Pos (11UL)
#define DBGMCU_AHB1FZR_DBG_GPDMA11_STOP_Msk (0x1UL << DBGMCU_AHB1FZR_DBG_GPDMA11_STOP_Pos)
#define DBGMCU_AHB1FZR_DBG_GPDMA11_STOP     DBGMCU_AHB1FZR_DBG_GPDMA11_STOP_Msk

/******************************************************************************/
/*                                                                            */
/*                        Delay Block Interface (DLYB)                        */
/*                                                                            */
/******************************************************************************/
/*******************  Bit definition for DLYB_CR register  ********************/
#define DLYB_CR_DEN_Pos                     (0UL)
#define DLYB_CR_DEN_Msk                     (0x1UL << DLYB_CR_DEN_Pos)              /*!< 0x00000001 */
#define DLYB_CR_DEN                         DLYB_CR_DEN_Msk                         /*!<Delay Block enable */
#define DLYB_CR_SEN_Pos                     (1UL)
#define DLYB_CR_SEN_Msk                     (0x1UL << DLYB_CR_SEN_Pos)              /*!< 0x00000002 */
#define DLYB_CR_SEN                         DLYB_CR_SEN_Msk                         /*!<Sampler length enable */

/*******************  Bit definition for DLYB_CFGR register  ********************/
#define DLYB_CFGR_SEL_Pos                   (0UL)
#define DLYB_CFGR_SEL_Msk                   (0xFUL << DLYB_CFGR_SEL_Pos)            /*!< 0x0000000F */
#define DLYB_CFGR_SEL                       DLYB_CFGR_SEL_Msk                       /*!<Select the phase for the Output clock[3:0] */
#define DLYB_CFGR_SEL_0                     (0x1UL << DLYB_CFGR_SEL_Pos)            /*!< 0x00000001 */
#define DLYB_CFGR_SEL_1                     (0x2UL << DLYB_CFGR_SEL_Pos)            /*!< 0x00000002 */
#define DLYB_CFGR_SEL_2                     (0x3UL << DLYB_CFGR_SEL_Pos)            /*!< 0x00000003 */
#define DLYB_CFGR_SEL_3                     (0x8UL << DLYB_CFGR_SEL_Pos)            /*!< 0x00000008 */
#define DLYB_CFGR_UNIT_Pos                  (8UL)
#define DLYB_CFGR_UNIT_Msk                  (0x7FUL << DLYB_CFGR_UNIT_Pos)          /*!< 0x00007F00 */
#define DLYB_CFGR_UNIT                      DLYB_CFGR_UNIT_Msk                      /*!<Delay Defines the delay of a Unit delay cell[6:0] */
#define DLYB_CFGR_UNIT_0                    (0x01UL << DLYB_CFGR_UNIT_Pos)          /*!< 0x00000100 */
#define DLYB_CFGR_UNIT_1                    (0x02UL << DLYB_CFGR_UNIT_Pos)          /*!< 0x00000200 */
#define DLYB_CFGR_UNIT_2                    (0x04UL << DLYB_CFGR_UNIT_Pos)          /*!< 0x00000400 */
#define DLYB_CFGR_UNIT_3                    (0x08UL << DLYB_CFGR_UNIT_Pos)          /*!< 0x00000800 */
#define DLYB_CFGR_UNIT_4                    (0x10UL << DLYB_CFGR_UNIT_Pos)          /*!< 0x00001000 */
#define DLYB_CFGR_UNIT_5                    (0x20UL << DLYB_CFGR_UNIT_Pos)          /*!< 0x00002000 */
#define DLYB_CFGR_UNIT_6                    (0x40UL << DLYB_CFGR_UNIT_Pos)          /*!< 0x00004000 */
#define DLYB_CFGR_LNG_Pos                   (16UL)
#define DLYB_CFGR_LNG_Msk                   (0xFFFUL << DLYB_CFGR_LNG_Pos)          /*!< 0x0FFF0000 */
#define DLYB_CFGR_LNG                       DLYB_CFGR_LNG_Msk                       /*!<Delay line length value[11:0] */
#define DLYB_CFGR_LNG_0                     (0x001UL << DLYB_CFGR_LNG_Pos)          /*!< 0x00010000 */
#define DLYB_CFGR_LNG_1                     (0x002UL << DLYB_CFGR_LNG_Pos)          /*!< 0x00020000 */
#define DLYB_CFGR_LNG_2                     (0x004UL << DLYB_CFGR_LNG_Pos)          /*!< 0x00040000 */
#define DLYB_CFGR_LNG_3                     (0x008UL << DLYB_CFGR_LNG_Pos)          /*!< 0x00080000 */
#define DLYB_CFGR_LNG_4                     (0x010UL << DLYB_CFGR_LNG_Pos)          /*!< 0x00100000 */
#define DLYB_CFGR_LNG_5                     (0x020UL << DLYB_CFGR_LNG_Pos)          /*!< 0x00200000 */
#define DLYB_CFGR_LNG_6                     (0x040UL << DLYB_CFGR_LNG_Pos)          /*!< 0x00400000 */
#define DLYB_CFGR_LNG_7                     (0x080UL << DLYB_CFGR_LNG_Pos)          /*!< 0x00800000 */
#define DLYB_CFGR_LNG_8                     (0x100UL << DLYB_CFGR_LNG_Pos)          /*!< 0x01000000 */
#define DLYB_CFGR_LNG_9                     (0x200UL << DLYB_CFGR_LNG_Pos)          /*!< 0x02000000 */
#define DLYB_CFGR_LNG_10                    (0x400UL << DLYB_CFGR_LNG_Pos)          /*!< 0x04000000 */
#define DLYB_CFGR_LNG_11                    (0x800UL << DLYB_CFGR_LNG_Pos)          /*!< 0x08000000 */
#define DLYB_CFGR_LNGF_Pos                  (31UL)
#define DLYB_CFGR_LNGF_Msk                  (0x1UL << DLYB_CFGR_LNGF_Pos)            /*!< 0x80000000 */
#define DLYB_CFGR_LNGF                      DLYB_CFGR_LNGF_Msk                       /*!<Length valid flag */

/******************************************************************************/
/*                                                                            */
/*                           DMA Controller (DMA)                             */
/*                                                                            */
/******************************************************************************/
/*******************  Bit definition for DMA_SECCFGR register  ****************/
#define DMA_SECCFGR_SEC0_Pos                (0UL)
#define DMA_SECCFGR_SEC0_Msk                (0x1UL << DMA_SECCFGR_SEC0_Pos)         /*!< 0x00000001 */
#define DMA_SECCFGR_SEC0                    DMA_SECCFGR_SEC0_Msk                    /*!< Secure State of Channel 0  */
#define DMA_SECCFGR_SEC1_Pos                (1UL)
#define DMA_SECCFGR_SEC1_Msk                (0x1UL << DMA_SECCFGR_SEC1_Pos)         /*!< 0x00000002 */
#define DMA_SECCFGR_SEC1                    DMA_SECCFGR_SEC1_Msk                    /*!< Secure State of Channel 1  */
#define DMA_SECCFGR_SEC2_Pos                (2UL)
#define DMA_SECCFGR_SEC2_Msk                (0x1UL << DMA_SECCFGR_SEC2_Pos)         /*!< 0x00000004 */
#define DMA_SECCFGR_SEC2                    DMA_SECCFGR_SEC2_Msk                    /*!< Secure State of Channel 2  */
#define DMA_SECCFGR_SEC3_Pos                (3UL)
#define DMA_SECCFGR_SEC3_Msk                (0x1UL << DMA_SECCFGR_SEC3_Pos)         /*!< 0x00000008 */
#define DMA_SECCFGR_SEC3                    DMA_SECCFGR_SEC3_Msk                    /*!< Secure State of Channel 3  */
#define DMA_SECCFGR_SEC4_Pos                (4UL)
#define DMA_SECCFGR_SEC4_Msk                (0x1UL << DMA_SECCFGR_SEC4_Pos)         /*!< 0x00000010 */
#define DMA_SECCFGR_SEC4                    DMA_SECCFGR_SEC4_Msk                    /*!< Secure State of Channel 4  */
#define DMA_SECCFGR_SEC5_Pos                (5UL)
#define DMA_SECCFGR_SEC5_Msk                (0x1UL << DMA_SECCFGR_SEC5_Pos)         /*!< 0x00000020 */
#define DMA_SECCFGR_SEC5                    DMA_SECCFGR_SEC5_Msk                    /*!< Secure State of Channel 5  */
#define DMA_SECCFGR_SEC6_Pos                (6UL)
#define DMA_SECCFGR_SEC6_Msk                (0x1UL << DMA_SECCFGR_SEC6_Pos)         /*!< 0x00000040 */
#define DMA_SECCFGR_SEC6                    DMA_SECCFGR_SEC6_Msk                    /*!< Secure State of Channel 6  */
#define DMA_SECCFGR_SEC7_Pos                (7UL)
#define DMA_SECCFGR_SEC7_Msk                (0x1UL << DMA_SECCFGR_SEC7_Pos)         /*!< 0x00000080 */
#define DMA_SECCFGR_SEC7                    DMA_SECCFGR_SEC7_Msk                    /*!< Secure State of Channel 7  */
#define DMA_SECCFGR_SEC8_Pos                (8UL)
#define DMA_SECCFGR_SEC8_Msk                (0x1UL << DMA_SECCFGR_SEC8_Pos)         /*!< 0x00000100 */
#define DMA_SECCFGR_SEC8                    DMA_SECCFGR_SEC8_Msk                    /*!< Secure State of Channel 8  */
#define DMA_SECCFGR_SEC9_Pos                (9UL)
#define DMA_SECCFGR_SEC9_Msk                (0x1UL << DMA_SECCFGR_SEC9_Pos)         /*!< 0x00000200 */
#define DMA_SECCFGR_SEC9                    DMA_SECCFGR_SEC9_Msk                    /*!< Secure State of Channel 9  */
#define DMA_SECCFGR_SEC10_Pos               (10UL)
#define DMA_SECCFGR_SEC10_Msk               (0x1UL << DMA_SECCFGR_SEC10_Pos)        /*!< 0x00000400 */
#define DMA_SECCFGR_SEC10                   DMA_SECCFGR_SEC10_Msk                   /*!< Secure State of Channel 10 */
#define DMA_SECCFGR_SEC11_Pos               (11UL)
#define DMA_SECCFGR_SEC11_Msk               (0x1UL << DMA_SECCFGR_SEC11_Pos)        /*!< 0x00000800 */
#define DMA_SECCFGR_SEC11                   DMA_SECCFGR_SEC11_Msk                   /*!< Secure State of Channel 11 */

/*******************  Bit definition for DMA_PRIVCFGR register  ****************/
#define DMA_PRIVCFGR_PRIV0_Pos              (0UL)
#define DMA_PRIVCFGR_PRIV0_Msk              (0x1UL << DMA_PRIVCFGR_PRIV0_Pos)       /*!< 0x00000001 */
#define DMA_PRIVCFGR_PRIV0                  DMA_PRIVCFGR_PRIV0_Msk                  /*!< Privileged State of Channel 0  */
#define DMA_PRIVCFGR_PRIV1_Pos              (1UL)
#define DMA_PRIVCFGR_PRIV1_Msk              (0x1UL << DMA_PRIVCFGR_PRIV1_Pos)       /*!< 0x00000002 */
#define DMA_PRIVCFGR_PRIV1                  DMA_PRIVCFGR_PRIV1_Msk                  /*!< Privileged State of Channel 1  */
#define DMA_PRIVCFGR_PRIV2_Pos              (2UL)
#define DMA_PRIVCFGR_PRIV2_Msk              (0x1UL << DMA_PRIVCFGR_PRIV2_Pos)       /*!< 0x00000004 */
#define DMA_PRIVCFGR_PRIV2                  DMA_PRIVCFGR_PRIV2_Msk                  /*!< Privileged State of Channel 2  */
#define DMA_PRIVCFGR_PRIV3_Pos              (3UL)
#define DMA_PRIVCFGR_PRIV3_Msk              (0x1UL << DMA_PRIVCFGR_PRIV3_Pos)       /*!< 0x00000008 */
#define DMA_PRIVCFGR_PRIV3                  DMA_PRIVCFGR_PRIV3_Msk                  /*!< Privileged State of Channel 3  */
#define DMA_PRIVCFGR_PRIV4_Pos              (4UL)
#define DMA_PRIVCFGR_PRIV4_Msk              (0x1UL << DMA_PRIVCFGR_PRIV4_Pos)       /*!< 0x00000010 */
#define DMA_PRIVCFGR_PRIV4                  DMA_PRIVCFGR_PRIV4_Msk                  /*!< Privileged State of Channel 4  */
#define DMA_PRIVCFGR_PRIV5_Pos              (5UL)
#define DMA_PRIVCFGR_PRIV5_Msk              (0x1UL << DMA_PRIVCFGR_PRIV5_Pos)       /*!< 0x00000020 */
#define DMA_PRIVCFGR_PRIV5                  DMA_PRIVCFGR_PRIV5_Msk                  /*!< Privileged State of Channel 5  */
#define DMA_PRIVCFGR_PRIV6_Pos              (6UL)
#define DMA_PRIVCFGR_PRIV6_Msk              (0x1UL << DMA_PRIVCFGR_PRIV6_Pos)       /*!< 0x00000040 */
#define DMA_PRIVCFGR_PRIV6                  DMA_PRIVCFGR_PRIV6_Msk                  /*!< Privileged State of Channel 6  */
#define DMA_PRIVCFGR_PRIV7_Pos              (7UL)
#define DMA_PRIVCFGR_PRIV7_Msk              (0x1UL << DMA_PRIVCFGR_PRIV7_Pos)       /*!< 0x00000080 */
#define DMA_PRIVCFGR_PRIV7                  DMA_PRIVCFGR_PRIV7_Msk                  /*!< Privileged State of Channel 7  */
#define DMA_PRIVCFGR_PRIV8_Pos              (8UL)
#define DMA_PRIVCFGR_PRIV8_Msk              (0x1UL << DMA_PRIVCFGR_PRIV8_Pos)       /*!< 0x00000100 */
#define DMA_PRIVCFGR_PRIV8                  DMA_PRIVCFGR_PRIV8_Msk                  /*!< Privileged State of Channel 8  */
#define DMA_PRIVCFGR_PRIV9_Pos              (9UL)
#define DMA_PRIVCFGR_PRIV9_Msk              (0x1UL << DMA_PRIVCFGR_PRIV9_Pos)       /*!< 0x00000200 */
#define DMA_PRIVCFGR_PRIV9                  DMA_PRIVCFGR_PRIV9_Msk                  /*!< Privileged State of Channel 9  */
#define DMA_PRIVCFGR_PRIV10_Pos             (10UL)
#define DMA_PRIVCFGR_PRIV10_Msk             (0x1UL << DMA_PRIVCFGR_PRIV10_Pos)      /*!< 0x00000400 */
#define DMA_PRIVCFGR_PRIV10                 DMA_PRIVCFGR_PRIV10_Msk                 /*!< Privileged State of Channel 10 */
#define DMA_PRIVCFGR_PRIV11_Pos             (11UL)
#define DMA_PRIVCFGR_PRIV11_Msk             (0x1UL << DMA_PRIVCFGR_PRIV11_Pos)      /*!< 0x00000800 */
#define DMA_PRIVCFGR_PRIV11                 DMA_PRIVCFGR_PRIV11_Msk                 /*!< Privileged State of Channel 11 */

/*******************  Bit definition for DMA_RCFGLOCKR register  ****************/
#define DMA_RCFGLOCKR_LOCK0_Pos              (0UL)
#define DMA_RCFGLOCKR_LOCK0_Msk              (0x1UL << DMA_RCFGLOCKR_LOCK0_Pos)       /*!< 0x00000001 */
#define DMA_RCFGLOCKR_LOCK0                  DMA_RCFGLOCKR_LOCK0_Msk                  /*!< Lock the configuration of Channel 0  */
#define DMA_RCFGLOCKR_LOCK1_Pos              (1UL)
#define DMA_RCFGLOCKR_LOCK1_Msk              (0x1UL << DMA_RCFGLOCKR_LOCK1_Pos)       /*!< 0x00000002 */
#define DMA_RCFGLOCKR_LOCK1                  DMA_RCFGLOCKR_LOCK1_Msk                  /*!< Lock the configuration of Channel 1  */
#define DMA_RCFGLOCKR_LOCK2_Pos              (2UL)
#define DMA_RCFGLOCKR_LOCK2_Msk              (0x1UL << DMA_RCFGLOCKR_LOCK2_Pos)       /*!< 0x00000004 */
#define DMA_RCFGLOCKR_LOCK2                  DMA_RCFGLOCKR_LOCK2_Msk                  /*!< Lock the configuration of Channel 2  */
#define DMA_RCFGLOCKR_LOCK3_Pos              (3UL)
#define DMA_RCFGLOCKR_LOCK3_Msk              (0x1UL << DMA_RCFGLOCKR_LOCK3_Pos)       /*!< 0x00000008 */
#define DMA_RCFGLOCKR_LOCK3                  DMA_RCFGLOCKR_LOCK3_Msk                  /*!< Lock the configuration of Channel 3  */
#define DMA_RCFGLOCKR_LOCK4_Pos              (4UL)
#define DMA_RCFGLOCKR_LOCK4_Msk              (0x1UL << DMA_RCFGLOCKR_LOCK4_Pos)       /*!< 0x00000010 */
#define DMA_RCFGLOCKR_LOCK4                  DMA_RCFGLOCKR_LOCK4_Msk                  /*!< Lock the configuration of Channel 4  */
#define DMA_RCFGLOCKR_LOCK5_Pos              (5UL)
#define DMA_RCFGLOCKR_LOCK5_Msk              (0x1UL << DMA_RCFGLOCKR_LOCK5_Pos)       /*!< 0x00000020 */
#define DMA_RCFGLOCKR_LOCK5                  DMA_RCFGLOCKR_LOCK5_Msk                  /*!< Lock the configuration of Channel 5  */
#define DMA_RCFGLOCKR_LOCK6_Pos              (6UL)
#define DMA_RCFGLOCKR_LOCK6_Msk              (0x1UL << DMA_RCFGLOCKR_LOCK6_Pos)       /*!< 0x00000040 */
#define DMA_RCFGLOCKR_LOCK6                  DMA_RCFGLOCKR_LOCK6_Msk                  /*!< Lock the configuration of Channel 6  */
#define DMA_RCFGLOCKR_LOCK7_Pos              (7UL)
#define DMA_RCFGLOCKR_LOCK7_Msk              (0x1UL << DMA_RCFGLOCKR_LOCK7_Pos)       /*!< 0x00000080 */
#define DMA_RCFGLOCKR_LOCK7                  DMA_RCFGLOCKR_LOCK7_Msk                  /*!< Lock the configuration of Channel 7  */
#define DMA_RCFGLOCKR_LOCK8_Pos              (8UL)
#define DMA_RCFGLOCKR_LOCK8_Msk              (0x1UL << DMA_RCFGLOCKR_LOCK8_Pos)       /*!< 0x00000100 */
#define DMA_RCFGLOCKR_LOCK8                  DMA_RCFGLOCKR_LOCK8_Msk                  /*!< Lock the configuration of Channel 8  */
#define DMA_RCFGLOCKR_LOCK9_Pos              (9UL)
#define DMA_RCFGLOCKR_LOCK9_Msk              (0x1UL << DMA_RCFGLOCKR_LOCK9_Pos)       /*!< 0x00000200 */
#define DMA_RCFGLOCKR_LOCK9                  DMA_RCFGLOCKR_LOCK9_Msk                  /*!< Lock the configuration of Channel 9  */
#define DMA_RCFGLOCKR_LOCK10_Pos             (10UL)
#define DMA_RCFGLOCKR_LOCK10_Msk             (0x1UL << DMA_RCFGLOCKR_LOCK10_Pos)      /*!< 0x00000400 */
#define DMA_RCFGLOCKR_LOCK10                 DMA_RCFGLOCKR_LOCK10_Msk                 /*!< Lock the configuration of Channel 10 */
#define DMA_RCFGLOCKR_LOCK11_Pos             (11UL)
#define DMA_RCFGLOCKR_LOCK11_Msk             (0x1UL << DMA_RCFGLOCKR_LOCK11_Pos)      /*!< 0x00000800 */
#define DMA_RCFGLOCKR_LOCK11                 DMA_RCFGLOCKR_LOCK11_Msk                 /*!< Lock the configuration of Channel 11 */

/*******************  Bit definition for DMA_MISR register  ****************/
#define DMA_MISR_MIS0_Pos                   (0UL)
#define DMA_MISR_MIS0_Msk                   (0x1UL << DMA_MISR_MIS0_Pos)            /*!< 0x00000001 */
#define DMA_MISR_MIS0                       DMA_MISR_MIS0_Msk                       /*!< Masked Interrupt State of Non-Secure Channel 0  */
#define DMA_MISR_MIS1_Pos                   (1UL)
#define DMA_MISR_MIS1_Msk                   (0x1UL << DMA_MISR_MIS1_Pos)            /*!< 0x00000002 */
#define DMA_MISR_MIS1                       DMA_MISR_MIS1_Msk                       /*!< Masked Interrupt State of Non-Secure Channel 1  */
#define DMA_MISR_MIS2_Pos                   (2UL)
#define DMA_MISR_MIS2_Msk                   (0x1UL << DMA_MISR_MIS2_Pos)            /*!< 0x00000004 */
#define DMA_MISR_MIS2                       DMA_MISR_MIS2_Msk                       /*!< Masked Interrupt State of Non-Secure Channel 2  */
#define DMA_MISR_MIS3_Pos                   (3UL)
#define DMA_MISR_MIS3_Msk                   (0x1UL << DMA_MISR_MIS3_Pos)            /*!< 0x00000008 */
#define DMA_MISR_MIS3                       DMA_MISR_MIS3_Msk                       /*!< Masked Interrupt State of Non-Secure Channel 3  */
#define DMA_MISR_MIS4_Pos                   (4UL)
#define DMA_MISR_MIS4_Msk                   (0x1UL << DMA_MISR_MIS4_Pos)            /*!< 0x00000010 */
#define DMA_MISR_MIS4                       DMA_MISR_MIS4_Msk                       /*!< Masked Interrupt State of Non-Secure Channel 4  */
#define DMA_MISR_MIS5_Pos                   (5UL)
#define DMA_MISR_MIS5_Msk                   (0x1UL << DMA_MISR_MIS5_Pos)            /*!< 0x00000020 */
#define DMA_MISR_MIS5                       DMA_MISR_MIS5_Msk                       /*!< Masked Interrupt State of Non-Secure Channel 5  */
#define DMA_MISR_MIS6_Pos                   (6UL)
#define DMA_MISR_MIS6_Msk                   (0x1UL << DMA_MISR_MIS6_Pos)            /*!< 0x00000040 */
#define DMA_MISR_MIS6                       DMA_MISR_MIS6_Msk                       /*!< Masked Interrupt State of Non-Secure Channel 6  */
#define DMA_MISR_MIS7_Pos                   (7UL)
#define DMA_MISR_MIS7_Msk                   (0x1UL << DMA_MISR_MIS7_Pos)            /*!< 0x00000080 */
#define DMA_MISR_MIS7                       DMA_MISR_MIS7_Msk                       /*!< Masked Interrupt State of Non-Secure Channel 7  */
#define DMA_MISR_MIS8_Pos                   (8UL)
#define DMA_MISR_MIS8_Msk                   (0x1UL << DMA_MISR_MIS8_Pos)            /*!< 0x00000100 */
#define DMA_MISR_MIS8                       DMA_MISR_MIS8_Msk                       /*!< Masked Interrupt State of Non-Secure Channel 8  */
#define DMA_MISR_MIS9_Pos                   (9UL)
#define DMA_MISR_MIS9_Msk                   (0x1UL << DMA_MISR_MIS9_Pos)            /*!< 0x00000200 */
#define DMA_MISR_MIS9                       DMA_MISR_MIS9_Msk                       /*!< Masked Interrupt State of Non-Secure Channel 9  */
#define DMA_MISR_MIS10_Pos                  (10UL)
#define DMA_MISR_MIS10_Msk                  (0x1UL << DMA_MISR_MIS10_Pos)           /*!< 0x00000400 */
#define DMA_MISR_MIS10                      DMA_MISR_MIS10_Msk                      /*!< Masked Interrupt State of Non-Secure Channel 10 */
#define DMA_MISR_MIS11_Pos                  (11UL)
#define DMA_MISR_MIS11_Msk                  (0x1UL << DMA_MISR_MIS11_Pos)           /*!< 0x00000800 */
#define DMA_MISR_MIS11                      DMA_MISR_MIS11_Msk                      /*!< Masked Interrupt State of Non-Secure Channel 11 */

/*******************  Bit definition for DMA_SMISR register  ****************/
#define DMA_SMISR_MIS0_Pos                  (0UL)
#define DMA_SMISR_MIS0_Msk                  (0x1UL << DMA_SMISR_MIS0_Pos)           /*!< 0x00000001 */
#define DMA_SMISR_MIS0                      DMA_SMISR_MIS0_Msk                      /*!< Masked Interrupt State of Secure Channel 0  */
#define DMA_SMISR_MIS1_Pos                  (1UL)
#define DMA_SMISR_MIS1_Msk                  (0x1UL << DMA_SMISR_MIS1_Pos)           /*!< 0x00000002 */
#define DMA_SMISR_MIS1                      DMA_SMISR_MIS1_Msk                      /*!< Masked Interrupt State of Secure Channel 1  */
#define DMA_SMISR_MIS2_Pos                  (2UL)
#define DMA_SMISR_MIS2_Msk                  (0x1UL << DMA_SMISR_MIS2_Pos)           /*!< 0x00000004 */
#define DMA_SMISR_MIS2                      DMA_SMISR_MIS2_Msk                      /*!< Masked Interrupt State of Secure Channel 2  */
#define DMA_SMISR_MIS3_Pos                  (3UL)
#define DMA_SMISR_MIS3_Msk                  (0x1UL << DMA_SMISR_MIS3_Pos)           /*!< 0x00000008 */
#define DMA_SMISR_MIS3                      DMA_SMISR_MIS3_Msk                      /*!< Masked Interrupt State of Secure Channel 3  */
#define DMA_SMISR_MIS4_Pos                  (4UL)
#define DMA_SMISR_MIS4_Msk                  (0x1UL << DMA_SMISR_MIS4_Pos)           /*!< 0x00000010 */
#define DMA_SMISR_MIS4                      DMA_SMISR_MIS4_Msk                      /*!< Masked Interrupt State of Secure Channel 4  */
#define DMA_SMISR_MIS5_Pos                  (5UL)
#define DMA_SMISR_MIS5_Msk                  (0x1UL << DMA_SMISR_MIS5_Pos)           /*!< 0x00000020 */
#define DMA_SMISR_MIS5                      DMA_SMISR_MIS5_Msk                      /*!< Masked Interrupt State of Secure Channel 5  */
#define DMA_SMISR_MIS6_Pos                  (6UL)
#define DMA_SMISR_MIS6_Msk                  (0x1UL << DMA_SMISR_MIS6_Pos)           /*!< 0x00000040 */
#define DMA_SMISR_MIS6                      DMA_SMISR_MIS6_Msk                      /*!< Masked Interrupt State of Secure Channel 6  */
#define DMA_SMISR_MIS7_Pos                  (7UL)
#define DMA_SMISR_MIS7_Msk                  (0x1UL << DMA_SMISR_MIS7_Pos)           /*!< 0x00000080 */
#define DMA_SMISR_MIS7                      DMA_SMISR_MIS7_Msk                      /*!< Masked Interrupt State of Secure Channel 7  */
#define DMA_SMISR_MIS8_Pos                  (8UL)
#define DMA_SMISR_MIS8_Msk                  (0x1UL << DMA_SMISR_MIS8_Pos)           /*!< 0x00000100 */
#define DMA_SMISR_MIS8                      DMA_SMISR_MIS8_Msk                      /*!< Masked Interrupt State of Secure Channel 8  */
#define DMA_SMISR_MIS9_Pos                  (9UL)
#define DMA_SMISR_MIS9_Msk                  (0x1UL << DMA_SMISR_MIS9_Pos)           /*!< 0x00000200 */
#define DMA_SMISR_MIS9                      DMA_SMISR_MIS9_Msk                      /*!< Masked Interrupt State of Secure Channel 9  */
#define DMA_SMISR_MIS10_Pos                 (10UL)
#define DMA_SMISR_MIS10_Msk                 (0x1UL << DMA_SMISR_MIS10_Pos)          /*!< 0x00000400 */
#define DMA_SMISR_MIS10                     DMA_SMISR_MIS10_Msk                     /*!< Masked Interrupt State of Secure Channel 10 */
#define DMA_SMISR_MIS11_Pos                 (11UL)
#define DMA_SMISR_MIS11_Msk                 (0x1UL << DMA_SMISR_MIS11_Pos)          /*!< 0x00000800 */
#define DMA_SMISR_MIS11                     DMA_SMISR_MIS11_Msk                     /*!< Masked Interrupt State of Secure Channel 11 */

/*******************  Bit definition for DMA_CLBAR register  ****************/
#define DMA_CLBAR_LBA_Pos                   (16UL)
#define DMA_CLBAR_LBA_Msk                   (0xFFFFUL << DMA_CLBAR_LBA_Pos)         /*!< 0xFFFF0000 */
#define DMA_CLBAR_LBA                       DMA_CLBAR_LBA_Msk                       /*!< Linked-list Base Address of DMA channel x */

/*******************  Bit definition for DMA_CFCR register  *******************/
#define DMA_CFCR_TCF_Pos                    (8UL)
#define DMA_CFCR_TCF_Msk                    (0x1UL << DMA_CFCR_TCF_Pos)             /*!< 0x00000100 */
#define DMA_CFCR_TCF                        DMA_CFCR_TCF_Msk                        /*!< Transfer complete flag clear             */
#define DMA_CFCR_HTF_Pos                    (9UL)
#define DMA_CFCR_HTF_Msk                    (0x1UL << DMA_CFCR_HTF_Pos)             /*!< 0x00000200 */
#define DMA_CFCR_HTF                        DMA_CFCR_HTF_Msk                        /*!< Half transfer complete flag clear        */
#define DMA_CFCR_DTEF_Pos                   (10UL)
#define DMA_CFCR_DTEF_Msk                   (0x1UL << DMA_CFCR_DTEF_Pos)            /*!< 0x00000400 */
#define DMA_CFCR_DTEF                       DMA_CFCR_DTEF_Msk                       /*!< Data transfer error flag clear           */
#define DMA_CFCR_ULEF_Pos                   (11UL)
#define DMA_CFCR_ULEF_Msk                   (0x1UL << DMA_CFCR_ULEF_Pos)            /*!< 0x00000800 */
#define DMA_CFCR_ULEF                       DMA_CFCR_ULEF_Msk                       /*!< Update linked-list item error flag clear */
#define DMA_CFCR_USEF_Pos                   (12UL)
#define DMA_CFCR_USEF_Msk                   (0x1UL << DMA_CFCR_USEF_Pos)            /*!< 0x00001000 */
#define DMA_CFCR_USEF                       DMA_CFCR_USEF_Msk                       /*!< User setting error flag clear            */
#define DMA_CFCR_SUSPF_Pos                  (13UL)
#define DMA_CFCR_SUSPF_Msk                  (0x1UL << DMA_CFCR_SUSPF_Pos)           /*!< 0x00002000 */
#define DMA_CFCR_SUSPF                      DMA_CFCR_SUSPF_Msk                      /*!< Completed suspension flag clear          */
#define DMA_CFCR_TOF_Pos                    (14UL)
#define DMA_CFCR_TOF_Msk                    (0x1UL << DMA_CFCR_TOF_Pos)             /*!< 0x00004000 */
#define DMA_CFCR_TOF                        DMA_CFCR_TOF_Msk                        /*!< Trigger overrun flag clear               */

/*******************  Bit definition for DMA_CSR register  *******************/
#define DMA_CSR_IDLEF_Pos                   (0UL)
#define DMA_CSR_IDLEF_Msk                   (0x1UL << DMA_CSR_IDLEF_Pos)            /*!< 0x00000001 */
#define DMA_CSR_IDLEF                       DMA_CSR_IDLEF_Msk                       /*!< Idle flag                          */
#define DMA_CSR_TCF_Pos                     (8UL)
#define DMA_CSR_TCF_Msk                     (0x1UL << DMA_CSR_TCF_Pos)              /*!< 0x00000100 */
#define DMA_CSR_TCF                         DMA_CSR_TCF_Msk                         /*!< Transfer complete flag             */
#define DMA_CSR_HTF_Pos                     (9UL)
#define DMA_CSR_HTF_Msk                     (0x1UL << DMA_CSR_HTF_Pos)              /*!< 0x00000200 */
#define DMA_CSR_HTF                         DMA_CSR_HTF_Msk                         /*!< Half transfer complete flag        */
#define DMA_CSR_DTEF_Pos                    (10UL)
#define DMA_CSR_DTEF_Msk                    (0x1UL << DMA_CSR_DTEF_Pos)             /*!< 0x00000400 */
#define DMA_CSR_DTEF                        DMA_CSR_DTEF_Msk                        /*!< Data transfer error flag           */
#define DMA_CSR_ULEF_Pos                    (11UL)
#define DMA_CSR_ULEF_Msk                    (0x1UL << DMA_CSR_ULEF_Pos)             /*!< 0x00000800 */
#define DMA_CSR_ULEF                        DMA_CSR_ULEF_Msk                        /*!< Update linked-list item error flag */
#define DMA_CSR_USEF_Pos                    (12UL)
#define DMA_CSR_USEF_Msk                    (0x1UL << DMA_CSR_USEF_Pos)             /*!< 0x00001000 */
#define DMA_CSR_USEF                        DMA_CSR_USEF_Msk                        /*!< User setting error flag            */
#define DMA_CSR_SUSPF_Pos                   (13UL)
#define DMA_CSR_SUSPF_Msk                   (0x1UL << DMA_CSR_SUSPF_Pos)            /*!< 0x00002000 */
#define DMA_CSR_SUSPF                       DMA_CSR_SUSPF_Msk                       /*!< Completed suspension flag          */
#define DMA_CSR_TOF_Pos                     (14UL)
#define DMA_CSR_TOF_Msk                     (0x1UL << DMA_CSR_TOF_Pos)              /*!< 0x00004000 */
#define DMA_CSR_TOF                         DMA_CSR_TOF_Msk                         /*!< Trigger overrun flag               */
#define DMA_CSR_FIFOL_Pos                   (16UL)
#define DMA_CSR_FIFOL_Msk                   (0xFFUL << DMA_CSR_FIFOL_Pos)           /*!< 0x00FF0000 */
#define DMA_CSR_FIFOL                       DMA_CSR_FIFOL_Msk                       /*!< Monitored FIFO level in bytes      */

/*******************  Bit definition for DMA_CCR register  ********************/
#define DMA_CCR_EN_Pos                      (0UL)
#define DMA_CCR_EN_Msk                      (0x1UL << DMA_CCR_EN_Pos)               /*!< 0x00000001 */
#define DMA_CCR_EN                          DMA_CCR_EN_Msk                          /*!< Channel enable                                 */
#define DMA_CCR_RESET_Pos                   (1UL)
#define DMA_CCR_RESET_Msk                   (0x1UL << DMA_CCR_RESET_Pos)            /*!< 0x00000002 */
#define DMA_CCR_RESET                       DMA_CCR_RESET_Msk                       /*!< Channel reset                                  */
#define DMA_CCR_SUSP_Pos                    (2UL)
#define DMA_CCR_SUSP_Msk                    (0x1UL << DMA_CCR_SUSP_Pos)             /*!< 0x00000004 */
#define DMA_CCR_SUSP                        DMA_CCR_SUSP_Msk                        /*!< Channel suspend                                */
#define DMA_CCR_TCIE_Pos                    (8UL)
#define DMA_CCR_TCIE_Msk                    (0x1UL << DMA_CCR_TCIE_Pos)             /*!< 0x00000100 */
#define DMA_CCR_TCIE                        DMA_CCR_TCIE_Msk                        /*!< Transfer complete interrupt enable             */
#define DMA_CCR_HTIE_Pos                    (9UL)
#define DMA_CCR_HTIE_Msk                    (0x1UL << DMA_CCR_HTIE_Pos)             /*!< 0x00000200 */
#define DMA_CCR_HTIE                        DMA_CCR_HTIE_Msk                        /*!< Half transfer complete interrupt enable        */
#define DMA_CCR_DTEIE_Pos                   (10UL)
#define DMA_CCR_DTEIE_Msk                   (0x1UL << DMA_CCR_DTEIE_Pos)            /*!< 0x00000400 */
#define DMA_CCR_DTEIE                       DMA_CCR_DTEIE_Msk                       /*!< Data transfer error interrupt enable           */
#define DMA_CCR_ULEIE_Pos                   (11UL)
#define DMA_CCR_ULEIE_Msk                   (0x1UL << DMA_CCR_ULEIE_Pos)            /*!< 0x00000800 */
#define DMA_CCR_ULEIE                       DMA_CCR_ULEIE_Msk                       /*!< Update linked-list item error interrupt enable */
#define DMA_CCR_USEIE_Pos                   (12UL)
#define DMA_CCR_USEIE_Msk                   (0x1UL << DMA_CCR_USEIE_Pos)            /*!< 0x00001000 */
#define DMA_CCR_USEIE                       DMA_CCR_USEIE_Msk                       /*!< User setting error interrupt enable            */
#define DMA_CCR_SUSPIE_Pos                  (13UL)
#define DMA_CCR_SUSPIE_Msk                  (0x1UL << DMA_CCR_SUSPIE_Pos)           /*!< 0x00002000 */
#define DMA_CCR_SUSPIE                      DMA_CCR_SUSPIE_Msk                      /*!< Completed suspension interrupt enable          */
#define DMA_CCR_TOIE_Pos                    (14UL)
#define DMA_CCR_TOIE_Msk                    (0x1UL << DMA_CCR_TOIE_Pos)             /*!< 0x00004000 */
#define DMA_CCR_TOIE                        DMA_CCR_TOIE_Msk                        /*!< Trigger overrun interrupt enable               */
#define DMA_CCR_LSM_Pos                     (16UL)
#define DMA_CCR_LSM_Msk                     (0x1UL << DMA_CCR_LSM_Pos)              /*!< 0x00010000 */
#define DMA_CCR_LSM                         DMA_CCR_LSM_Msk                         /*!< Link step mode                                 */
#define DMA_CCR_LAP_Pos                     (17UL)
#define DMA_CCR_LAP_Msk                     (0x1UL << DMA_CCR_LAP_Pos)              /*!< 0x00020000 */
#define DMA_CCR_LAP                         DMA_CCR_LAP_Msk                         /*!< Linked-list allocated port                     */
#define DMA_CCR_PRIO_Pos                    (22UL)
#define DMA_CCR_PRIO_Msk                    (0x3UL << DMA_CCR_PRIO_Pos)             /*!< 0x00C00000 */
#define DMA_CCR_PRIO                        DMA_CCR_PRIO_Msk                        /*!< Priority level                                 */
#define DMA_CCR_PRIO_0                      (0x1UL << DMA_CCR_PRIO_Pos)             /*!< 0x00400000 */
#define DMA_CCR_PRIO_1                      (0x2UL << DMA_CCR_PRIO_Pos)             /*!< 0x00800000 */

/*******************  Bit definition for DMA_CTR1 register  *******************/
#define DMA_CTR1_SDW_LOG2_Pos               (0UL)
#define DMA_CTR1_SDW_LOG2_Msk               (0x3UL << DMA_CTR1_SDW_LOG2_Pos)        /*!< 0x00000003 */
#define DMA_CTR1_SDW_LOG2                   DMA_CTR1_SDW_LOG2_Msk                   /*!< Binary logarithm of the source data width of a burst                    */
#define DMA_CTR1_SDW_LOG2_0                 (0x1UL << DMA_CTR1_SDW_LOG2_Pos)        /*!< Bit 0 */
#define DMA_CTR1_SDW_LOG2_1                 (0x2UL << DMA_CTR1_SDW_LOG2_Pos)        /*!< Bit 1 */
#define DMA_CTR1_SINC_Pos                   (3UL)
#define DMA_CTR1_SINC_Msk                   (0x1UL << DMA_CTR1_SINC_Pos)            /*!< 0x00000008 */
#define DMA_CTR1_SINC                       DMA_CTR1_SINC_Msk                       /*!< Source incrementing burst                                               */
#define DMA_CTR1_SBL_1_Pos                  (4UL)
#define DMA_CTR1_SBL_1_Msk                  (0x3FUL << DMA_CTR1_SBL_1_Pos)          /*!< 0x000003F0 */
#define DMA_CTR1_SBL_1                      DMA_CTR1_SBL_1_Msk                      /*!< Source burst length minus 1                                             */
#define DMA_CTR1_PAM_Pos                    (11UL)
#define DMA_CTR1_PAM_Msk                    (0x3UL << DMA_CTR1_PAM_Pos)             /*!< 0x0001800 */
#define DMA_CTR1_PAM                        DMA_CTR1_PAM_Msk                        /*!< Padding / alignment mode                                                */
#define DMA_CTR1_PAM_0                      (0x1UL << DMA_CTR1_PAM_Pos)             /*!< Bit 0 */
#define DMA_CTR1_PAM_1                      (0x2UL << DMA_CTR1_PAM_Pos)             /*!< Bit 1 */
#define DMA_CTR1_SBX_Pos                    (13UL)
#define DMA_CTR1_SBX_Msk                    (0x1UL << DMA_CTR1_SBX_Pos)             /*!< 0x00002000 */
#define DMA_CTR1_SBX                        DMA_CTR1_SBX_Msk                        /*!< Source byte exchange within the unaligned half-word of each source word */
#define DMA_CTR1_SAP_Pos                    (14UL)
#define DMA_CTR1_SAP_Msk                    (0x1UL << DMA_CTR1_SAP_Pos)             /*!< 0x00004000 */
#define DMA_CTR1_SAP                        DMA_CTR1_SAP_Msk                        /*!< Source allocated port                                                   */
#define DMA_CTR1_SSEC_Pos                   (15UL)
#define DMA_CTR1_SSEC_Msk                   (0x1UL << DMA_CTR1_SSEC_Pos)            /*!< 0x00008000 */
#define DMA_CTR1_SSEC                       DMA_CTR1_SSEC_Msk                       /*!< Security attribute of the DMA transfer from the source                  */
#define DMA_CTR1_DDW_LOG2_Pos               (16UL)
#define DMA_CTR1_DDW_LOG2_Msk               (0x3UL << DMA_CTR1_DDW_LOG2_Pos)        /*!< 0x00030000 */
#define DMA_CTR1_DDW_LOG2                   DMA_CTR1_DDW_LOG2_Msk                   /*!< Binary logarithm of the destination data width of a burst               */
#define DMA_CTR1_DDW_LOG2_0                 (0x1UL << DMA_CTR1_DDW_LOG2_Pos)        /*!< Bit 0 */
#define DMA_CTR1_DDW_LOG2_1                 (0x2UL << DMA_CTR1_DDW_LOG2_Pos)        /*!< Bit 1 */
#define DMA_CTR1_DINC_Pos                   (19UL)
#define DMA_CTR1_DINC_Msk                   (0x1UL << DMA_CTR1_DINC_Pos)            /*!< 0x00080000 */
#define DMA_CTR1_DINC                       DMA_CTR1_DINC_Msk                       /*!< Destination incrementing burst                                          */
#define DMA_CTR1_DBL_1_Pos                  (20UL)
#define DMA_CTR1_DBL_1_Msk                  (0x3FUL << DMA_CTR1_DBL_1_Pos)          /*!< 0x03F00000 */
#define DMA_CTR1_DBL_1                      DMA_CTR1_DBL_1_Msk                      /*!< Destination burst length minus 1                                        */
#define DMA_CTR1_DBX_Pos                    (26UL)
#define DMA_CTR1_DBX_Msk                    (0x1UL << DMA_CTR1_DBX_Pos)             /*!< 0x04000000 */
#define DMA_CTR1_DBX                        DMA_CTR1_DBX_Msk                        /*!< Destination byte exchange                                               */
#define DMA_CTR1_DHX_Pos                    (27UL)
#define DMA_CTR1_DHX_Msk                    (0x1UL << DMA_CTR1_DHX_Pos)             /*!< 0x08000000 */
#define DMA_CTR1_DHX                        DMA_CTR1_DHX_Msk                        /*!< Destination half-word exchange                                          */
#define DMA_CTR1_DAP_Pos                    (30UL)
#define DMA_CTR1_DAP_Msk                    (0x1UL << DMA_CTR1_DAP_Pos)             /*!< 0x40000000 */
#define DMA_CTR1_DAP                        DMA_CTR1_DAP_Msk                        /*!< Destination allocated port                                              */
#define DMA_CTR1_DSEC_Pos                   (31UL)
#define DMA_CTR1_DSEC_Msk                   (0x1UL << DMA_CTR1_DSEC_Pos)            /*!< 0x80000000 */
#define DMA_CTR1_DSEC                       DMA_CTR1_DSEC_Msk                       /*!< Security attribute of the DMA transfer from the destination             */

/******************  Bit definition for DMA_CTR2 register  *******************/
#define DMA_CTR2_REQSEL_Pos                 (0UL)
#define DMA_CTR2_REQSEL_Msk                 (0x7FUL << DMA_CTR2_REQSEL_Pos)         /*!< 0x0000007F */
#define DMA_CTR2_REQSEL                     DMA_CTR2_REQSEL_Msk                     /*!< DMA hardware request selection */
#define DMA_CTR2_SWREQ_Pos                  (9UL)
#define DMA_CTR2_SWREQ_Msk                  (0x1UL << DMA_CTR2_SWREQ_Pos)           /*!< 0x00000200 */
#define DMA_CTR2_SWREQ                      DMA_CTR2_SWREQ_Msk                      /*!< Software request               */
#define DMA_CTR2_DREQ_Pos                   (10UL)
#define DMA_CTR2_DREQ_Msk                   (0x1UL << DMA_CTR2_DREQ_Pos)            /*!< 0x00000400 */
#define DMA_CTR2_DREQ                       DMA_CTR2_DREQ_Msk                       /*!< Destination hardware request   */
#define DMA_CTR2_BREQ_Pos                   (11UL)
#define DMA_CTR2_BREQ_Msk                   (0x1UL << DMA_CTR2_BREQ_Pos)            /*!< 0x00000800 */
#define DMA_CTR2_BREQ                       DMA_CTR2_BREQ_Msk                       /*!< Block hardware request         */
#define DMA_CTR2_PFREQ_Pos                  (12UL)
#define DMA_CTR2_PFREQ_Msk                  (0x1UL << DMA_CTR2_PFREQ_Pos)           /*!< 0x00001000 */
#define DMA_CTR2_PFREQ                      DMA_CTR2_PFREQ_Msk                      /*!< Hardware request in peripheral flow control mode */
#define DMA_CTR2_TRIGM_Pos                  (14UL)
#define DMA_CTR2_TRIGM_Msk                  (0x3UL << DMA_CTR2_TRIGM_Pos)           /*!< 0x0000C000 */
#define DMA_CTR2_TRIGM                      DMA_CTR2_TRIGM_Msk                      /*!< Trigger mode                   */
#define DMA_CTR2_TRIGM_0                    (0x1UL << DMA_CTR2_TRIGM_Pos)           /*!< Bit 0 */
#define DMA_CTR2_TRIGM_1                    (0x2UL << DMA_CTR2_TRIGM_Pos)           /*!< Bit 1 */
#define DMA_CTR2_TRIGSEL_Pos                (16UL)
#define DMA_CTR2_TRIGSEL_Msk                (0x3FUL << DMA_CTR2_TRIGSEL_Pos)        /*!< 0x003F0000 */
#define DMA_CTR2_TRIGSEL                    DMA_CTR2_TRIGSEL_Msk                    /*!< Trigger event input selection  */
#define DMA_CTR2_TRIGPOL_Pos                (24UL)
#define DMA_CTR2_TRIGPOL_Msk                (0x3UL << DMA_CTR2_TRIGPOL_Pos)         /*!< 0x03000000 */
#define DMA_CTR2_TRIGPOL                    DMA_CTR2_TRIGPOL_Msk                    /*!< Trigger event polarity         */
#define DMA_CTR2_TRIGPOL_0                  (0x1UL << DMA_CTR2_TRIGPOL_Pos)         /*!< Bit 0 */
#define DMA_CTR2_TRIGPOL_1                  (0x2UL << DMA_CTR2_TRIGPOL_Pos)         /*!< Bit 1 */
#define DMA_CTR2_TCEM_Pos                   (30UL)
#define DMA_CTR2_TCEM_Msk                   (0x3UL << DMA_CTR2_TCEM_Pos)            /*!< 0xC0000000 */
#define DMA_CTR2_TCEM                       DMA_CTR2_TCEM_Msk                       /*!< Transfer complete event mode   */
#define DMA_CTR2_TCEM_0                     (0x1UL << DMA_CTR2_TCEM_Pos)            /*!< Bit 0 */
#define DMA_CTR2_TCEM_1                     (0x2UL << DMA_CTR2_TCEM_Pos)            /*!< Bit 1 */

/******************  Bit definition for DMA_CBR1 register  *******************/
#define DMA_CBR1_BNDT_Pos                   (0UL)
#define DMA_CBR1_BNDT_Msk                   (0xFFFFUL << DMA_CBR1_BNDT_Pos)         /*!< 0x0000FFFF */
#define DMA_CBR1_BNDT                       DMA_CBR1_BNDT_Msk                       /*!< Block number of data bytes to transfer from the source */
#define DMA_CBR1_BRC_Pos                    (16UL)
#define DMA_CBR1_BRC_Msk                    (0x7FFUL << DMA_CBR1_BRC_Pos)           /*!< 0x07FF0000 */
#define DMA_CBR1_BRC                        DMA_CBR1_BRC_Msk                        /*!< Block repeat counter                                   */
#define DMA_CBR1_SDEC_Pos                   (28UL)
#define DMA_CBR1_SDEC_Msk                   (0x1UL << DMA_CBR1_SDEC_Pos)            /*!< 0x10000000 */
#define DMA_CBR1_SDEC                       DMA_CBR1_SDEC_Msk                       /*!< Source address decrement                               */
#define DMA_CBR1_DDEC_Pos                   (29UL)
#define DMA_CBR1_DDEC_Msk                   (0x1UL << DMA_CBR1_DDEC_Pos)            /*!< 0x20000000 */
#define DMA_CBR1_DDEC                       DMA_CBR1_DDEC_Msk                       /*!< Destination address decrement                          */
#define DMA_CBR1_BRSDEC_Pos                 (30UL)
#define DMA_CBR1_BRSDEC_Msk                 (0x1UL << DMA_CBR1_BRSDEC_Pos)          /*!< 0x40000000 */
#define DMA_CBR1_BRSDEC                     DMA_CBR1_BRSDEC_Msk                     /*!< Block repeat source address decrement                  */
#define DMA_CBR1_BRDDEC_Pos                 (31UL)
#define DMA_CBR1_BRDDEC_Msk                 (0x1UL << DMA_CBR1_BRDDEC_Pos)          /*!< 0x80000000 */
#define DMA_CBR1_BRDDEC                     DMA_CBR1_BRDDEC_Msk                     /*!< Block repeat destination address decrement             */

/******************  Bit definition for DMA_CSAR register  ********************/
#define DMA_CSAR_SA_Pos                     (0UL)
#define DMA_CSAR_SA_Msk                     (0xFFFFFFFFUL << DMA_CSAR_SA_Pos)       /*!< 0xFFFFFFFF */
#define DMA_CSAR_SA                         DMA_CSAR_SA_Msk                         /*!< Source Address */

/******************  Bit definition for DMA_CDAR register  *******************/
#define DMA_CDAR_DA_Pos                     (0UL)
#define DMA_CDAR_DA_Msk                     (0xFFFFFFFFUL << DMA_CDAR_DA_Pos)       /*!< 0xFFFFFFFF */
#define DMA_CDAR_DA                         DMA_CDAR_DA_Msk                         /*!< Destination address */

/******************  Bit definition for DMA_CTR3 register  *******************/
#define DMA_CTR3_SAO_Pos                    (0UL)
#define DMA_CTR3_SAO_Msk                    (0x1FFFUL << DMA_CTR3_SAO_Pos)          /*!< 0x00001FFF */
#define DMA_CTR3_SAO                        DMA_CTR3_SAO_Msk                        /*!< Source address offset increment      */
#define DMA_CTR3_DAO_Pos                    (16UL)
#define DMA_CTR3_DAO_Msk                    (0x1FFFUL << DMA_CTR3_DAO_Pos)          /*!< 0x1FFF0000 */
#define DMA_CTR3_DAO                        DMA_CTR3_DAO_Msk                        /*!< Destination address offset increment */

/******************  Bit definition for DMA_CBR2 register  *******************/
#define DMA_CBR2_BRSAO_Pos                  (0UL)
#define DMA_CBR2_BRSAO_Msk                  (0xFFFFUL << DMA_CBR2_BRSAO_Pos)        /*!< 0x0000FFFF */
#define DMA_CBR2_BRSAO                      DMA_CBR2_BRSAO_Msk                      /*!< Block repeated source address offset      */
#define DMA_CBR2_BRDAO_Pos                  (16UL)
#define DMA_CBR2_BRDAO_Msk                  (0xFFFFUL << DMA_CBR2_BRDAO_Pos)        /*!< 0xFFFF0000 */
#define DMA_CBR2_BRDAO                      DMA_CBR2_BRDAO_Msk                      /*!< Block repeated destination address offset */

/******************  Bit definition for DMA_CLLR register  *******************/
#define DMA_CLLR_LA_Pos                     (2UL)
#define DMA_CLLR_LA_Msk                     (0x3FFFUL << DMA_CLLR_LA_Pos)           /*!< 0x0000FFFC */
#define DMA_CLLR_LA                         DMA_CLLR_LA_Msk                         /*!< Pointer to the next linked-list data structure */
#define DMA_CLLR_ULL_Pos                    (16UL)
#define DMA_CLLR_ULL_Msk                    (0x1UL << DMA_CLLR_ULL_Pos)             /*!< 0x00010000 */
#define DMA_CLLR_ULL                        DMA_CLLR_ULL_Msk                        /*!< Update link address register from memory       */
#define DMA_CLLR_UB2_Pos                    (25UL)
#define DMA_CLLR_UB2_Msk                    (0x1UL << DMA_CLLR_UB2_Pos)             /*!< 0x02000000 */
#define DMA_CLLR_UB2                        DMA_CLLR_UB2_Msk                        /*!< Update block register 2 from memory            */
#define DMA_CLLR_UT3_Pos                    (26UL)
#define DMA_CLLR_UT3_Msk                    (0x1UL << DMA_CLLR_UT3_Pos)             /*!< 0x04000000 */
#define DMA_CLLR_UT3                        DMA_CLLR_UT3_Msk                        /*!< Update transfer register 3 from SRAM           */
#define DMA_CLLR_UDA_Pos                    (27UL)
#define DMA_CLLR_UDA_Msk                    (0x1UL << DMA_CLLR_UDA_Pos)             /*!< 0x08000000 */
#define DMA_CLLR_UDA                        DMA_CLLR_UDA_Msk                        /*!< Update destination address register from SRAM  */
#define DMA_CLLR_USA_Pos                    (28UL)
#define DMA_CLLR_USA_Msk                    (0x1UL << DMA_CLLR_USA_Pos)             /*!< 0x10000000 */
#define DMA_CLLR_USA                        DMA_CLLR_USA_Msk                        /*!< Update source address register from SRAM       */
#define DMA_CLLR_UB1_Pos                    (29UL)
#define DMA_CLLR_UB1_Msk                    (0x1UL << DMA_CLLR_UB1_Pos)             /*!< 0x20000000 */
#define DMA_CLLR_UB1                        DMA_CLLR_UB1_Msk                        /*!< Update block register 1 from SRAM              */
#define DMA_CLLR_UT2_Pos                    (30UL)
#define DMA_CLLR_UT2_Msk                    (0x1UL << DMA_CLLR_UT2_Pos)             /*!< 0x40000000 */
#define DMA_CLLR_UT2                        DMA_CLLR_UT2_Msk                        /*!< Update transfer register 2 from SRAM           */
#define DMA_CLLR_UT1_Pos                    (31UL)
#define DMA_CLLR_UT1_Msk                    (0x1UL << DMA_CLLR_UT1_Pos)             /*!< 0x80000000 */
#define DMA_CLLR_UT1                        DMA_CLLR_UT1_Msk                        /*!< Update transfer register 1 from SRAM           */

/******************************************************************************/
/*                                                                            */
/*                    External Interrupt/Event Controller                     */
/*                                                                            */
/******************************************************************************/
/******************  Bit definition for EXTI_RTSR1 register  ******************/
#define EXTI_RTSR1_RT0_Pos                  (0UL)
#define EXTI_RTSR1_RT0_Msk                  (0x1UL << EXTI_RTSR1_RT0_Pos)           /*!< 0x00000001 */
#define EXTI_RTSR1_RT0                      EXTI_RTSR1_RT0_Msk                      /*!< Rising trigger configuration for input line 0 */
#define EXTI_RTSR1_RT1_Pos                  (1UL)
#define EXTI_RTSR1_RT1_Msk                  (0x1UL << EXTI_RTSR1_RT1_Pos)           /*!< 0x00000002 */
#define EXTI_RTSR1_RT1                      EXTI_RTSR1_RT1_Msk                      /*!< Rising trigger configuration for input line 1 */
#define EXTI_RTSR1_RT2_Pos                  (2UL)
#define EXTI_RTSR1_RT2_Msk                  (0x1UL << EXTI_RTSR1_RT2_Pos)           /*!< 0x00000004 */
#define EXTI_RTSR1_RT2                      EXTI_RTSR1_RT2_Msk                      /*!< Rising trigger configuration for input line 2 */
#define EXTI_RTSR1_RT3_Pos                  (3UL)
#define EXTI_RTSR1_RT3_Msk                  (0x1UL << EXTI_RTSR1_RT3_Pos)           /*!< 0x00000008 */
#define EXTI_RTSR1_RT3                      EXTI_RTSR1_RT3_Msk                      /*!< Rising trigger configuration for input line 3 */
#define EXTI_RTSR1_RT4_Pos                  (4UL)
#define EXTI_RTSR1_RT4_Msk                  (0x1UL << EXTI_RTSR1_RT4_Pos)           /*!< 0x00000010 */
#define EXTI_RTSR1_RT4                      EXTI_RTSR1_RT4_Msk                      /*!< Rising trigger configuration for input line 4 */
#define EXTI_RTSR1_RT5_Pos                  (5UL)
#define EXTI_RTSR1_RT5_Msk                  (0x1UL << EXTI_RTSR1_RT5_Pos)           /*!< 0x00000020 */
#define EXTI_RTSR1_RT5                      EXTI_RTSR1_RT5_Msk                      /*!< Rising trigger configuration for input line 5 */
#define EXTI_RTSR1_RT6_Pos                  (6UL)
#define EXTI_RTSR1_RT6_Msk                  (0x1UL << EXTI_RTSR1_RT6_Pos)           /*!< 0x00000040 */
#define EXTI_RTSR1_RT6                      EXTI_RTSR1_RT6_Msk                      /*!< Rising trigger configuration for input line 6 */
#define EXTI_RTSR1_RT7_Pos                  (7UL)
#define EXTI_RTSR1_RT7_Msk                  (0x1UL << EXTI_RTSR1_RT7_Pos)           /*!< 0x00000080 */
#define EXTI_RTSR1_RT7                      EXTI_RTSR1_RT7_Msk                      /*!< Rising trigger configuration for input line 7 */
#define EXTI_RTSR1_RT8_Pos                  (8UL)
#define EXTI_RTSR1_RT8_Msk                  (0x1UL << EXTI_RTSR1_RT8_Pos)           /*!< 0x00000100 */
#define EXTI_RTSR1_RT8                      EXTI_RTSR1_RT8_Msk                      /*!< Rising trigger configuration for input line 8 */
#define EXTI_RTSR1_RT9_Pos                  (9UL)
#define EXTI_RTSR1_RT9_Msk                  (0x1UL << EXTI_RTSR1_RT9_Pos)           /*!< 0x00000200 */
#define EXTI_RTSR1_RT9                      EXTI_RTSR1_RT9_Msk                      /*!< Rising trigger configuration for input line 9 */
#define EXTI_RTSR1_RT10_Pos                 (10UL)
#define EXTI_RTSR1_RT10_Msk                 (0x1UL << EXTI_RTSR1_RT10_Pos)          /*!< 0x00000400 */
#define EXTI_RTSR1_RT10                     EXTI_RTSR1_RT10_Msk                     /*!< Rising trigger configuration for input line 10 */
#define EXTI_RTSR1_RT11_Pos                 (11UL)
#define EXTI_RTSR1_RT11_Msk                 (0x1UL << EXTI_RTSR1_RT11_Pos)          /*!< 0x00000800 */
#define EXTI_RTSR1_RT11                     EXTI_RTSR1_RT11_Msk                     /*!< Rising trigger configuration for input line 11 */
#define EXTI_RTSR1_RT12_Pos                 (12UL)
#define EXTI_RTSR1_RT12_Msk                 (0x1UL << EXTI_RTSR1_RT12_Pos)          /*!< 0x00001000 */
#define EXTI_RTSR1_RT12                     EXTI_RTSR1_RT12_Msk                     /*!< Rising trigger configuration for input line 12 */
#define EXTI_RTSR1_RT13_Pos                 (13UL)
#define EXTI_RTSR1_RT13_Msk                 (0x1UL << EXTI_RTSR1_RT13_Pos)          /*!< 0x00002000 */
#define EXTI_RTSR1_RT13                     EXTI_RTSR1_RT13_Msk                     /*!< Rising trigger configuration for input line 13 */
#define EXTI_RTSR1_RT14_Pos                 (14UL)
#define EXTI_RTSR1_RT14_Msk                 (0x1UL << EXTI_RTSR1_RT14_Pos)          /*!< 0x00004000 */
#define EXTI_RTSR1_RT14                     EXTI_RTSR1_RT14_Msk                     /*!< Rising trigger configuration for input line 14 */
#define EXTI_RTSR1_RT15_Pos                 (15UL)
#define EXTI_RTSR1_RT15_Msk                 (0x1UL << EXTI_RTSR1_RT15_Pos)          /*!< 0x00008000 */
#define EXTI_RTSR1_RT15                     EXTI_RTSR1_RT15_Msk                     /*!< Rising trigger configuration for input line 15 */
#define EXTI_RTSR1_RT16_Pos                 (16UL)
#define EXTI_RTSR1_RT16_Msk                 (0x1UL << EXTI_RTSR1_RT16_Pos)          /*!< 0x00010000 */
#define EXTI_RTSR1_RT16                     EXTI_RTSR1_RT16_Msk                     /*!< Rising trigger configuration for input line 16 */
#define EXTI_RTSR1_RT17_Pos                 (17UL)
#define EXTI_RTSR1_RT17_Msk                 (0x1UL << EXTI_RTSR1_RT17_Pos)          /*!< 0x00020000 */
#define EXTI_RTSR1_RT17                     EXTI_RTSR1_RT17_Msk                     /*!< Rising trigger configuration for input line 17 */
#define EXTI_RTSR1_RT18_Pos                 (18UL)
#define EXTI_RTSR1_RT18_Msk                 (0x1UL << EXTI_RTSR1_RT18_Pos)          /*!< 0x00040000 */
#define EXTI_RTSR1_RT18                     EXTI_RTSR1_RT18_Msk                     /*!< Rising trigger configuration for input line 18 */
#define EXTI_RTSR1_RT19_Pos                 (19UL)
#define EXTI_RTSR1_RT19_Msk                 (0x1UL << EXTI_RTSR1_RT19_Pos)          /*!< 0x00080000 */
#define EXTI_RTSR1_RT19                     EXTI_RTSR1_RT19_Msk                     /*!< Rising trigger configuration for input line 19 */
#define EXTI_RTSR1_RT20_Pos                 (20UL)
#define EXTI_RTSR1_RT20_Msk                 (0x1UL << EXTI_RTSR1_RT20_Pos)          /*!< 0x00100000 */
#define EXTI_RTSR1_RT20                     EXTI_RTSR1_RT20_Msk                     /*!< Rising trigger configuration for input line 20 */
#define EXTI_RTSR1_RT21_Pos                 (21UL)
#define EXTI_RTSR1_RT21_Msk                 (0x1UL << EXTI_RTSR1_RT21_Pos)          /*!< 0x00200000 */
#define EXTI_RTSR1_RT21                     EXTI_RTSR1_RT21_Msk                     /*!< Rising trigger configuration for input line 21 */
#define EXTI_RTSR1_RT22_Pos                 (22UL)
#define EXTI_RTSR1_RT22_Msk                 (0x1UL << EXTI_RTSR1_RT22_Pos)          /*!< 0x00400000 */
#define EXTI_RTSR1_RT22                     EXTI_RTSR1_RT22_Msk                     /*!< Rising trigger configuration for input line 22 */

/******************  Bit definition for EXTI_FTSR1 register  ******************/
#define EXTI_FTSR1_FT0_Pos                  (0UL)
#define EXTI_FTSR1_FT0_Msk                  (0x1UL << EXTI_FTSR1_FT0_Pos)           /*!< 0x00000001 */
#define EXTI_FTSR1_FT0                      EXTI_FTSR1_FT0_Msk                      /*!< Falling trigger configuration for input line 0 */
#define EXTI_FTSR1_FT1_Pos                  (1UL)
#define EXTI_FTSR1_FT1_Msk                  (0x1UL << EXTI_FTSR1_FT1_Pos)           /*!< 0x00000002 */
#define EXTI_FTSR1_FT1                      EXTI_FTSR1_FT1_Msk                      /*!< Falling trigger configuration for input line 1 */
#define EXTI_FTSR1_FT2_Pos                  (2UL)
#define EXTI_FTSR1_FT2_Msk                  (0x1UL << EXTI_FTSR1_FT2_Pos)           /*!< 0x00000004 */
#define EXTI_FTSR1_FT2                      EXTI_FTSR1_FT2_Msk                      /*!< Falling trigger configuration for input line 2 */
#define EXTI_FTSR1_FT3_Pos                  (3UL)
#define EXTI_FTSR1_FT3_Msk                  (0x1UL << EXTI_FTSR1_FT3_Pos)           /*!< 0x00000008 */
#define EXTI_FTSR1_FT3                      EXTI_FTSR1_FT3_Msk                      /*!< Falling trigger configuration for input line 3 */
#define EXTI_FTSR1_FT4_Pos                  (4UL)
#define EXTI_FTSR1_FT4_Msk                  (0x1UL << EXTI_FTSR1_FT4_Pos)           /*!< 0x00000010 */
#define EXTI_FTSR1_FT4                      EXTI_FTSR1_FT4_Msk                      /*!< Falling trigger configuration for input line 4 */
#define EXTI_FTSR1_FT5_Pos                  (5UL)
#define EXTI_FTSR1_FT5_Msk                  (0x1UL << EXTI_FTSR1_FT5_Pos)           /*!< 0x00000020 */
#define EXTI_FTSR1_FT5                      EXTI_FTSR1_FT5_Msk                      /*!< Falling trigger configuration for input line 5 */
#define EXTI_FTSR1_FT6_Pos                  (6UL)
#define EXTI_FTSR1_FT6_Msk                  (0x1UL << EXTI_FTSR1_FT6_Pos)           /*!< 0x00000040 */
#define EXTI_FTSR1_FT6                      EXTI_FTSR1_FT6_Msk                      /*!< Falling trigger configuration for input line 6 */
#define EXTI_FTSR1_FT7_Pos                  (7UL)
#define EXTI_FTSR1_FT7_Msk                  (0x1UL << EXTI_FTSR1_FT7_Pos)           /*!< 0x00000080 */
#define EXTI_FTSR1_FT7                      EXTI_FTSR1_FT7_Msk                      /*!< Falling trigger configuration for input line 7 */
#define EXTI_FTSR1_FT8_Pos                  (8UL)
#define EXTI_FTSR1_FT8_Msk                  (0x1UL << EXTI_FTSR1_FT8_Pos)           /*!< 0x00000100 */
#define EXTI_FTSR1_FT8                      EXTI_FTSR1_FT8_Msk                      /*!< Falling trigger configuration for input line 8 */
#define EXTI_FTSR1_FT9_Pos                  (9UL)
#define EXTI_FTSR1_FT9_Msk                  (0x1UL << EXTI_FTSR1_FT9_Pos)           /*!< 0x00000200 */
#define EXTI_FTSR1_FT9                      EXTI_FTSR1_FT9_Msk                      /*!< Falling trigger configuration for input line 9 */
#define EXTI_FTSR1_FT10_Pos                 (10UL)
#define EXTI_FTSR1_FT10_Msk                 (0x1UL << EXTI_FTSR1_FT10_Pos)          /*!< 0x00000400 */
#define EXTI_FTSR1_FT10                     EXTI_FTSR1_FT10_Msk                     /*!< Falling trigger configuration for input line 10 */
#define EXTI_FTSR1_FT11_Pos                 (11UL)
#define EXTI_FTSR1_FT11_Msk                 (0x1UL << EXTI_FTSR1_FT11_Pos)          /*!< 0x00000800 */
#define EXTI_FTSR1_FT11                     EXTI_FTSR1_FT11_Msk                     /*!< Falling trigger configuration for input line 11 */
#define EXTI_FTSR1_FT12_Pos                 (12UL)
#define EXTI_FTSR1_FT12_Msk                 (0x1UL << EXTI_FTSR1_FT12_Pos)          /*!< 0x00001000 */
#define EXTI_FTSR1_FT12                     EXTI_FTSR1_FT12_Msk                     /*!< Falling trigger configuration for input line 12 */
#define EXTI_FTSR1_FT13_Pos                 (13UL)
#define EXTI_FTSR1_FT13_Msk                 (0x1UL << EXTI_FTSR1_FT13_Pos)          /*!< 0x00002000 */
#define EXTI_FTSR1_FT13                     EXTI_FTSR1_FT13_Msk                     /*!< Falling trigger configuration for input line 13 */
#define EXTI_FTSR1_FT14_Pos                 (14UL)
#define EXTI_FTSR1_FT14_Msk                 (0x1UL << EXTI_FTSR1_FT14_Pos)          /*!< 0x00004000 */
#define EXTI_FTSR1_FT14                     EXTI_FTSR1_FT14_Msk                     /*!< Falling trigger configuration for input line 14 */
#define EXTI_FTSR1_FT15_Pos                 (15UL)
#define EXTI_FTSR1_FT15_Msk                 (0x1UL << EXTI_FTSR1_FT15_Pos)          /*!< 0x00008000 */
#define EXTI_FTSR1_FT15                     EXTI_FTSR1_FT15_Msk                     /*!< Falling trigger configuration for input line 15 */
#define EXTI_FTSR1_FT16_Pos                 (16UL)
#define EXTI_FTSR1_FT16_Msk                 (0x1UL << EXTI_FTSR1_FT16_Pos)          /*!< 0x00010000 */
#define EXTI_FTSR1_FT16                     EXTI_FTSR1_FT16_Msk                     /*!< Falling trigger configuration for input line 16 */
#define EXTI_FTSR1_FT17_Pos                 (17UL)
#define EXTI_FTSR1_FT17_Msk                 (0x1UL << EXTI_FTSR1_FT17_Pos)          /*!< 0x00020000 */
#define EXTI_FTSR1_FT17                     EXTI_FTSR1_FT17_Msk                     /*!< Falling trigger configuration for input line 17 */
#define EXTI_FTSR1_FT18_Pos                 (18UL)
#define EXTI_FTSR1_FT18_Msk                 (0x1UL << EXTI_FTSR1_FT18_Pos)          /*!< 0x00040000 */
#define EXTI_FTSR1_FT18                     EXTI_FTSR1_FT18_Msk                     /*!< Falling trigger configuration for input line 18 */
#define EXTI_FTSR1_FT19_Pos                 (19UL)
#define EXTI_FTSR1_FT19_Msk                 (0x1UL << EXTI_FTSR1_FT19_Pos)          /*!< 0x00080000 */
#define EXTI_FTSR1_FT19                     EXTI_FTSR1_FT19_Msk                     /*!< Falling trigger configuration for input line 19 */
#define EXTI_FTSR1_FT20_Pos                 (20UL)
#define EXTI_FTSR1_FT20_Msk                 (0x1UL << EXTI_FTSR1_FT20_Pos)          /*!< 0x00100000 */
#define EXTI_FTSR1_FT20                     EXTI_FTSR1_FT20_Msk                     /*!< Falling trigger configuration for input line 20 */
#define EXTI_FTSR1_FT21_Pos                 (21UL)
#define EXTI_FTSR1_FT21_Msk                 (0x1UL << EXTI_FTSR1_FT21_Pos)          /*!< 0x00200000 */
#define EXTI_FTSR1_FT21                     EXTI_FTSR1_FT21_Msk                     /*!< Falling trigger configuration for input line 21 */
#define EXTI_FTSR1_FT22_Pos                 (22UL)
#define EXTI_FTSR1_FT22_Msk                 (0x1UL << EXTI_FTSR1_FT22_Pos)          /*!< 0x00400000 */
#define EXTI_FTSR1_FT22                     EXTI_FTSR1_FT22_Msk                     /*!< Falling trigger configuration for input line 22 */

/******************  Bit definition for EXTI_SWIER1 register  *****************/
#define EXTI_SWIER1_SWI0_Pos                (0UL)
#define EXTI_SWIER1_SWI0_Msk                (0x1UL << EXTI_SWIER1_SWI0_Pos)         /*!< 0x00000001 */
#define EXTI_SWIER1_SWI0                    EXTI_SWIER1_SWI0_Msk                    /*!< Software Interrupt on line 0 */
#define EXTI_SWIER1_SWI1_Pos                (1UL)
#define EXTI_SWIER1_SWI1_Msk                (0x1UL << EXTI_SWIER1_SWI1_Pos)         /*!< 0x00000002 */
#define EXTI_SWIER1_SWI1                    EXTI_SWIER1_SWI1_Msk                    /*!< Software Interrupt on line 1 */
#define EXTI_SWIER1_SWI2_Pos                (2UL)
#define EXTI_SWIER1_SWI2_Msk                (0x1UL << EXTI_SWIER1_SWI2_Pos)         /*!< 0x00000004 */
#define EXTI_SWIER1_SWI2                    EXTI_SWIER1_SWI2_Msk                    /*!< Software Interrupt on line 2 */
#define EXTI_SWIER1_SWI3_Pos                (3UL)
#define EXTI_SWIER1_SWI3_Msk                (0x1UL << EXTI_SWIER1_SWI3_Pos)         /*!< 0x00000008 */
#define EXTI_SWIER1_SWI3                    EXTI_SWIER1_SWI3_Msk                    /*!< Software Interrupt on line 3 */
#define EXTI_SWIER1_SWI4_Pos                (4UL)
#define EXTI_SWIER1_SWI4_Msk                (0x1UL << EXTI_SWIER1_SWI4_Pos)         /*!< 0x00000010 */
#define EXTI_SWIER1_SWI4                    EXTI_SWIER1_SWI4_Msk                    /*!< Software Interrupt on line 4 */
#define EXTI_SWIER1_SWI5_Pos                (5UL)
#define EXTI_SWIER1_SWI5_Msk                (0x1UL << EXTI_SWIER1_SWI5_Pos)         /*!< 0x00000020 */
#define EXTI_SWIER1_SWI5                    EXTI_SWIER1_SWI5_Msk                    /*!< Software Interrupt on line 5 */
#define EXTI_SWIER1_SWI6_Pos                (6UL)
#define EXTI_SWIER1_SWI6_Msk                (0x1UL << EXTI_SWIER1_SWI6_Pos)         /*!< 0x00000040 */
#define EXTI_SWIER1_SWI6                    EXTI_SWIER1_SWI6_Msk                    /*!< Software Interrupt on line 6 */
#define EXTI_SWIER1_SWI7_Pos                (7UL)
#define EXTI_SWIER1_SWI7_Msk                (0x1UL << EXTI_SWIER1_SWI7_Pos)         /*!< 0x00000080 */
#define EXTI_SWIER1_SWI7                    EXTI_SWIER1_SWI7_Msk                    /*!< Software Interrupt on line 7 */
#define EXTI_SWIER1_SWI8_Pos                (8UL)
#define EXTI_SWIER1_SWI8_Msk                (0x1UL << EXTI_SWIER1_SWI8_Pos)         /*!< 0x00000100 */
#define EXTI_SWIER1_SWI8                    EXTI_SWIER1_SWI8_Msk                    /*!< Software Interrupt on line 8 */
#define EXTI_SWIER1_SWI9_Pos                (9UL)
#define EXTI_SWIER1_SWI9_Msk                (0x1UL << EXTI_SWIER1_SWI9_Pos)         /*!< 0x00000200 */
#define EXTI_SWIER1_SWI9                    EXTI_SWIER1_SWI9_Msk                    /*!< Software Interrupt on line 9 */
#define EXTI_SWIER1_SWI10_Pos               (10UL)
#define EXTI_SWIER1_SWI10_Msk               (0x1UL << EXTI_SWIER1_SWI10_Pos)        /*!< 0x00000400 */
#define EXTI_SWIER1_SWI10                   EXTI_SWIER1_SWI10_Msk                   /*!< Software Interrupt on line 10 */
#define EXTI_SWIER1_SWI11_Pos               (11UL)
#define EXTI_SWIER1_SWI11_Msk               (0x1UL << EXTI_SWIER1_SWI11_Pos)        /*!< 0x00000800 */
#define EXTI_SWIER1_SWI11                   EXTI_SWIER1_SWI11_Msk                   /*!< Software Interrupt on line 11 */
#define EXTI_SWIER1_SWI12_Pos               (12UL)
#define EXTI_SWIER1_SWI12_Msk               (0x1UL << EXTI_SWIER1_SWI12_Pos)        /*!< 0x00001000 */
#define EXTI_SWIER1_SWI12                   EXTI_SWIER1_SWI12_Msk                   /*!< Software Interrupt on line 12 */
#define EXTI_SWIER1_SWI13_Pos               (13UL)
#define EXTI_SWIER1_SWI13_Msk               (0x1UL << EXTI_SWIER1_SWI13_Pos)        /*!< 0x00002000 */
#define EXTI_SWIER1_SWI13                   EXTI_SWIER1_SWI13_Msk                   /*!< Software Interrupt on line 13 */
#define EXTI_SWIER1_SWI14_Pos               (14UL)
#define EXTI_SWIER1_SWI14_Msk               (0x1UL << EXTI_SWIER1_SWI14_Pos)        /*!< 0x00004000 */
#define EXTI_SWIER1_SWI14                   EXTI_SWIER1_SWI14_Msk                   /*!< Software Interrupt on line 14 */
#define EXTI_SWIER1_SWI15_Pos               (15UL)
#define EXTI_SWIER1_SWI15_Msk               (0x1UL << EXTI_SWIER1_SWI15_Pos)        /*!< 0x00008000 */
#define EXTI_SWIER1_SWI15                   EXTI_SWIER1_SWI15_Msk                   /*!< Software Interrupt on line 15 */
#define EXTI_SWIER1_SWI16_Pos               (16UL)
#define EXTI_SWIER1_SWI16_Msk               (0x1UL << EXTI_SWIER1_SWI16_Pos)        /*!< 0x00010000 */
#define EXTI_SWIER1_SWI16                   EXTI_SWIER1_SWI16_Msk                   /*!< Software Interrupt on line 16 */
#define EXTI_SWIER1_SWI17_Pos               (17UL)
#define EXTI_SWIER1_SWI17_Msk               (0x1UL << EXTI_SWIER1_SWI17_Pos)        /*!< 0x00020000 */
#define EXTI_SWIER1_SWI17                   EXTI_SWIER1_SWI17_Msk                   /*!< Software Interrupt on line 17 */
#define EXTI_SWIER1_SWI18_Pos               (18UL)
#define EXTI_SWIER1_SWI18_Msk               (0x1UL << EXTI_SWIER1_SWI18_Pos)        /*!< 0x00040000 */
#define EXTI_SWIER1_SWI18                   EXTI_SWIER1_SWI18_Msk                   /*!< Software Interrupt on line 18 */
#define EXTI_SWIER1_SWI19_Pos               (19UL)
#define EXTI_SWIER1_SWI19_Msk               (0x1UL << EXTI_SWIER1_SWI19_Pos)        /*!< 0x00080000 */
#define EXTI_SWIER1_SWI19                   EXTI_SWIER1_SWI19_Msk                   /*!< Software Interrupt on line 19 */
#define EXTI_SWIER1_SWI20_Pos               (20UL)
#define EXTI_SWIER1_SWI20_Msk               (0x1UL << EXTI_SWIER1_SWI20_Pos)        /*!< 0x00100000 */
#define EXTI_SWIER1_SWI20                   EXTI_SWIER1_SWI20_Msk                   /*!< Software Interrupt on line 20 */
#define EXTI_SWIER1_SWI21_Pos               (21UL)
#define EXTI_SWIER1_SWI21_Msk               (0x1UL << EXTI_SWIER1_SWI21_Pos)        /*!< 0x00200000 */
#define EXTI_SWIER1_SWI21                   EXTI_SWIER1_SWI21_Msk                   /*!< Software Interrupt on line 21 */
#define EXTI_SWIER1_SWI22_Pos               (22UL)
#define EXTI_SWIER1_SWI22_Msk               (0x1UL << EXTI_SWIER1_SWI22_Pos)        /*!< 0x00400000 */
#define EXTI_SWIER1_SWI22                   EXTI_SWIER1_SWI22_Msk                   /*!< Software Interrupt on line 22 */

/*******************  Bit definition for EXTI_RPR1 register  ******************/
#define EXTI_RPR1_RPIF0_Pos                 (0UL)
#define EXTI_RPR1_RPIF0_Msk                 (0x1UL << EXTI_RPR1_RPIF0_Pos)          /*!< 0x00000001 */
#define EXTI_RPR1_RPIF0                     EXTI_RPR1_RPIF0_Msk                     /*!< Rising Pending Interrupt Flag on line 0 */
#define EXTI_RPR1_RPIF1_Pos                 (1UL)
#define EXTI_RPR1_RPIF1_Msk                 (0x1UL << EXTI_RPR1_RPIF1_Pos)          /*!< 0x00000002 */
#define EXTI_RPR1_RPIF1                     EXTI_RPR1_RPIF1_Msk                     /*!< Rising Pending Interrupt Flag on line 1 */
#define EXTI_RPR1_RPIF2_Pos                 (2UL)
#define EXTI_RPR1_RPIF2_Msk                 (0x1UL << EXTI_RPR1_RPIF2_Pos)          /*!< 0x00000004 */
#define EXTI_RPR1_RPIF2                     EXTI_RPR1_RPIF2_Msk                     /*!< Rising Pending Interrupt Flag on line 2 */
#define EXTI_RPR1_RPIF3_Pos                 (3UL)
#define EXTI_RPR1_RPIF3_Msk                 (0x1UL << EXTI_RPR1_RPIF3_Pos)          /*!< 0x00000008 */
#define EXTI_RPR1_RPIF3                     EXTI_RPR1_RPIF3_Msk                     /*!< Rising Pending Interrupt Flag on line 3 */
#define EXTI_RPR1_RPIF4_Pos                 (4UL)
#define EXTI_RPR1_RPIF4_Msk                 (0x1UL << EXTI_RPR1_RPIF4_Pos)          /*!< 0x00000010 */
#define EXTI_RPR1_RPIF4                     EXTI_RPR1_RPIF4_Msk                     /*!< Rising Pending Interrupt Flag on line 4 */
#define EXTI_RPR1_RPIF5_Pos                 (5UL)
#define EXTI_RPR1_RPIF5_Msk                 (0x1UL << EXTI_RPR1_RPIF5_Pos)          /*!< 0x00000020 */
#define EXTI_RPR1_RPIF5                     EXTI_RPR1_RPIF5_Msk                     /*!< Rising Pending Interrupt Flag on line 5 */
#define EXTI_RPR1_RPIF6_Pos                 (6UL)
#define EXTI_RPR1_RPIF6_Msk                 (0x1UL << EXTI_RPR1_RPIF6_Pos)          /*!< 0x00000040 */
#define EXTI_RPR1_RPIF6                     EXTI_RPR1_RPIF6_Msk                     /*!< Rising Pending Interrupt Flag on line 6 */
#define EXTI_RPR1_RPIF7_Pos                 (7UL)
#define EXTI_RPR1_RPIF7_Msk                 (0x1UL << EXTI_RPR1_RPIF7_Pos)          /*!< 0x00000080 */
#define EXTI_RPR1_RPIF7                     EXTI_RPR1_RPIF7_Msk                     /*!< Rising Pending Interrupt Flag on line 7 */
#define EXTI_RPR1_RPIF8_Pos                 (8UL)
#define EXTI_RPR1_RPIF8_Msk                 (0x1UL << EXTI_RPR1_RPIF8_Pos)          /*!< 0x00000100 */
#define EXTI_RPR1_RPIF8                     EXTI_RPR1_RPIF8_Msk                     /*!< Rising Pending Interrupt Flag on line 8 */
#define EXTI_RPR1_RPIF9_Pos                 (9UL)
#define EXTI_RPR1_RPIF9_Msk                 (0x1UL << EXTI_RPR1_RPIF9_Pos)          /*!< 0x00000200 */
#define EXTI_RPR1_RPIF9                     EXTI_RPR1_RPIF9_Msk                     /*!< Rising Pending Interrupt Flag on line 9 */
#define EXTI_RPR1_RPIF10_Pos                (10UL)
#define EXTI_RPR1_RPIF10_Msk                (0x1UL << EXTI_RPR1_RPIF10_Pos)         /*!< 0x00000400 */
#define EXTI_RPR1_RPIF10                    EXTI_RPR1_RPIF10_Msk                    /*!< Rising Pending Interrupt Flag on line 10 */
#define EXTI_RPR1_RPIF11_Pos                (11UL)
#define EXTI_RPR1_RPIF11_Msk                (0x1UL << EXTI_RPR1_RPIF11_Pos)         /*!< 0x00000800 */
#define EXTI_RPR1_RPIF11                    EXTI_RPR1_RPIF11_Msk                    /*!< Rising Pending Interrupt Flag on line 11 */
#define EXTI_RPR1_RPIF12_Pos                (12UL)
#define EXTI_RPR1_RPIF12_Msk                (0x1UL << EXTI_RPR1_RPIF12_Pos)         /*!< 0x00001000 */
#define EXTI_RPR1_RPIF12                    EXTI_RPR1_RPIF12_Msk                    /*!< Rising Pending Interrupt Flag on line 12 */
#define EXTI_RPR1_RPIF13_Pos                (13UL)
#define EXTI_RPR1_RPIF13_Msk                (0x1UL << EXTI_RPR1_RPIF13_Pos)         /*!< 0x00002000 */
#define EXTI_RPR1_RPIF13                    EXTI_RPR1_RPIF13_Msk                    /*!< Rising Pending Interrupt Flag on line 13 */
#define EXTI_RPR1_RPIF14_Pos                (14UL)
#define EXTI_RPR1_RPIF14_Msk                (0x1UL << EXTI_RPR1_RPIF14_Pos)         /*!< 0x00004000 */
#define EXTI_RPR1_RPIF14                    EXTI_RPR1_RPIF14_Msk                    /*!< Rising Pending Interrupt Flag on line 14 */
#define EXTI_RPR1_RPIF15_Pos                (15UL)
#define EXTI_RPR1_RPIF15_Msk                (0x1UL << EXTI_RPR1_RPIF15_Pos)         /*!< 0x00008000 */
#define EXTI_RPR1_RPIF15                    EXTI_RPR1_RPIF15_Msk                    /*!< Rising Pending Interrupt Flag on line 15 */
#define EXTI_RPR1_RPIF16_Pos                (16UL)
#define EXTI_RPR1_RPIF16_Msk                (0x1UL << EXTI_RPR1_RPIF16_Pos)         /*!< 0x00010000 */
#define EXTI_RPR1_RPIF16                    EXTI_RPR1_RPIF16_Msk                    /*!< Rising Pending Interrupt Flag on line 16 */
#define EXTI_RPR1_RPIF17_Pos                (17UL)
#define EXTI_RPR1_RPIF17_Msk                (0x1UL << EXTI_RPR1_RPIF17_Pos)         /*!< 0x00020000 */
#define EXTI_RPR1_RPIF17                    EXTI_RPR1_RPIF17_Msk                    /*!< Rising Pending Interrupt Flag on line 17 */
#define EXTI_RPR1_RPIF18_Pos                (18UL)
#define EXTI_RPR1_RPIF18_Msk                (0x1UL << EXTI_RPR1_RPIF18_Pos)         /*!< 0x00040000 */
#define EXTI_RPR1_RPIF18                    EXTI_RPR1_RPIF18_Msk                    /*!< Rising Pending Interrupt Flag on line 18 */
#define EXTI_RPR1_RPIF19_Pos                (19UL)
#define EXTI_RPR1_RPIF19_Msk                (0x1UL << EXTI_RPR1_RPIF19_Pos)         /*!< 0x00080000 */
#define EXTI_RPR1_RPIF19                    EXTI_RPR1_RPIF19_Msk                    /*!< Rising Pending Interrupt Flag on line 19 */
#define EXTI_RPR1_RPIF20_Pos                (20UL)
#define EXTI_RPR1_RPIF20_Msk                (0x1UL << EXTI_RPR1_RPIF20_Pos)         /*!< 0x00100000 */
#define EXTI_RPR1_RPIF20                    EXTI_RPR1_RPIF20_Msk                    /*!< Rising Pending Interrupt Flag on line 20 */
#define EXTI_RPR1_RPIF21_Pos                (21UL)
#define EXTI_RPR1_RPIF21_Msk                (0x1UL << EXTI_RPR1_RPIF21_Pos)         /*!< 0x00200000 */
#define EXTI_RPR1_RPIF21                    EXTI_RPR1_RPIF21_Msk                    /*!< Rising Pending Interrupt Flag on line 21 */
#define EXTI_RPR1_RPIF22_Pos                (22UL)
#define EXTI_RPR1_RPIF22_Msk                (0x1UL << EXTI_RPR1_RPIF22_Pos)         /*!< 0x00400000 */
#define EXTI_RPR1_RPIF22                    EXTI_RPR1_RPIF22_Msk                    /*!< Rising Pending Interrupt Flag on line 22 */

/*******************  Bit definition for EXTI_FPR1 register  ******************/
#define EXTI_FPR1_FPIF0_Pos                 (0UL)
#define EXTI_FPR1_FPIF0_Msk                 (0x1UL << EXTI_FPR1_FPIF0_Pos)          /*!< 0x00000001 */
#define EXTI_FPR1_FPIF0                     EXTI_FPR1_FPIF0_Msk                     /*!< Falling Pending Interrupt Flag on line 0 */
#define EXTI_FPR1_FPIF1_Pos                 (1UL)
#define EXTI_FPR1_FPIF1_Msk                 (0x1UL << EXTI_FPR1_FPIF1_Pos)          /*!< 0x00000002 */
#define EXTI_FPR1_FPIF1                     EXTI_FPR1_FPIF1_Msk                     /*!< Falling Pending Interrupt Flag on line 1 */
#define EXTI_FPR1_FPIF2_Pos                 (2UL)
#define EXTI_FPR1_FPIF2_Msk                 (0x1UL << EXTI_FPR1_FPIF2_Pos)          /*!< 0x00000004 */
#define EXTI_FPR1_FPIF2                     EXTI_FPR1_FPIF2_Msk                     /*!< Falling Pending Interrupt Flag on line 2 */
#define EXTI_FPR1_FPIF3_Pos                 (3UL)
#define EXTI_FPR1_FPIF3_Msk                 (0x1UL << EXTI_FPR1_FPIF3_Pos)          /*!< 0x00000008 */
#define EXTI_FPR1_FPIF3                     EXTI_FPR1_FPIF3_Msk                     /*!< Falling Pending Interrupt Flag on line 3 */
#define EXTI_FPR1_FPIF4_Pos                 (4UL)
#define EXTI_FPR1_FPIF4_Msk                 (0x1UL << EXTI_FPR1_FPIF4_Pos)          /*!< 0x00000010 */
#define EXTI_FPR1_FPIF4                     EXTI_FPR1_FPIF4_Msk                     /*!< Falling Pending Interrupt Flag on line 4 */
#define EXTI_FPR1_FPIF5_Pos                 (5UL)
#define EXTI_FPR1_FPIF5_Msk                 (0x1UL << EXTI_FPR1_FPIF5_Pos)          /*!< 0x00000020 */
#define EXTI_FPR1_FPIF5                     EXTI_FPR1_FPIF5_Msk                     /*!< Falling Pending Interrupt Flag on line 5 */
#define EXTI_FPR1_FPIF6_Pos                 (6UL)
#define EXTI_FPR1_FPIF6_Msk                 (0x1UL << EXTI_FPR1_FPIF6_Pos)          /*!< 0x00000040 */
#define EXTI_FPR1_FPIF6                     EXTI_FPR1_FPIF6_Msk                     /*!< Falling Pending Interrupt Flag on line 6 */
#define EXTI_FPR1_FPIF7_Pos                 (7UL)
#define EXTI_FPR1_FPIF7_Msk                 (0x1UL << EXTI_FPR1_FPIF7_Pos)          /*!< 0x00000080 */
#define EXTI_FPR1_FPIF7                     EXTI_FPR1_FPIF7_Msk                     /*!< Falling Pending Interrupt Flag on line 7 */
#define EXTI_FPR1_FPIF8_Pos                 (8UL)
#define EXTI_FPR1_FPIF8_Msk                 (0x1UL << EXTI_FPR1_FPIF8_Pos)          /*!< 0x00000100 */
#define EXTI_FPR1_FPIF8                     EXTI_FPR1_FPIF8_Msk                     /*!< Falling Pending Interrupt Flag on line 8 */
#define EXTI_FPR1_FPIF9_Pos                 (9UL)
#define EXTI_FPR1_FPIF9_Msk                 (0x1UL << EXTI_FPR1_FPIF9_Pos)          /*!< 0x00000200 */
#define EXTI_FPR1_FPIF9                     EXTI_FPR1_FPIF9_Msk                     /*!< Falling Pending Interrupt Flag on line 9 */
#define EXTI_FPR1_FPIF10_Pos                (10UL)
#define EXTI_FPR1_FPIF10_Msk                (0x1UL << EXTI_FPR1_FPIF10_Pos)         /*!< 0x00000400 */
#define EXTI_FPR1_FPIF10                    EXTI_FPR1_FPIF10_Msk                    /*!< Falling Pending Interrupt Flag on line 10 */
#define EXTI_FPR1_FPIF11_Pos                (11UL)
#define EXTI_FPR1_FPIF11_Msk                (0x1UL << EXTI_FPR1_FPIF11_Pos)         /*!< 0x00000800 */
#define EXTI_FPR1_FPIF11                    EXTI_FPR1_FPIF11_Msk                    /*!< Falling Pending Interrupt Flag on line 11 */
#define EXTI_FPR1_FPIF12_Pos                (12UL)
#define EXTI_FPR1_FPIF12_Msk                (0x1UL << EXTI_FPR1_FPIF12_Pos)         /*!< 0x00001000 */
#define EXTI_FPR1_FPIF12                    EXTI_FPR1_FPIF12_Msk                    /*!< Falling Pending Interrupt Flag on line 12 */
#define EXTI_FPR1_FPIF13_Pos                (13UL)
#define EXTI_FPR1_FPIF13_Msk                (0x1UL << EXTI_FPR1_FPIF13_Pos)         /*!< 0x00002000 */
#define EXTI_FPR1_FPIF13                    EXTI_FPR1_FPIF13_Msk                    /*!< Falling Pending Interrupt Flag on line 13 */
#define EXTI_FPR1_FPIF14_Pos                (14UL)
#define EXTI_FPR1_FPIF14_Msk                (0x1UL << EXTI_FPR1_FPIF14_Pos)         /*!< 0x00004000 */
#define EXTI_FPR1_FPIF14                    EXTI_FPR1_FPIF14_Msk                    /*!< Falling Pending Interrupt Flag on line 14 */
#define EXTI_FPR1_FPIF15_Pos                (15UL)
#define EXTI_FPR1_FPIF15_Msk                (0x1UL << EXTI_FPR1_FPIF15_Pos)         /*!< 0x00008000 */
#define EXTI_FPR1_FPIF15                    EXTI_FPR1_FPIF15_Msk                    /*!< Falling Pending Interrupt Flag on line 15 */
#define EXTI_FPR1_FPIF16_Pos                (16UL)
#define EXTI_FPR1_FPIF16_Msk                (0x1UL << EXTI_FPR1_FPIF16_Pos)         /*!< 0x00010000 */
#define EXTI_FPR1_FPIF16                    EXTI_FPR1_FPIF16_Msk                    /*!< Falling Pending Interrupt Flag on line 16 */
#define EXTI_FPR1_FPIF17_Pos                (17UL)
#define EXTI_FPR1_FPIF17_Msk                (0x1UL << EXTI_FPR1_FPIF17_Pos)         /*!< 0x00020000 */
#define EXTI_FPR1_FPIF17                    EXTI_FPR1_FPIF17_Msk                    /*!< Falling Pending Interrupt Flag on line 17 */
#define EXTI_FPR1_FPIF18_Pos                (18UL)
#define EXTI_FPR1_FPIF18_Msk                (0x1UL << EXTI_FPR1_FPIF18_Pos)         /*!< 0x00040000 */
#define EXTI_FPR1_FPIF18                    EXTI_FPR1_FPIF18_Msk                    /*!< Falling Pending Interrupt Flag on line 18 */
#define EXTI_FPR1_FPIF19_Pos                (19UL)
#define EXTI_FPR1_FPIF19_Msk                (0x1UL << EXTI_FPR1_FPIF19_Pos)         /*!< 0x00080000 */
#define EXTI_FPR1_FPIF19                    EXTI_FPR1_FPIF19_Msk                    /*!< Falling Pending Interrupt Flag on line 19 */
#define EXTI_FPR1_FPIF20_Pos                (20UL)
#define EXTI_FPR1_FPIF20_Msk                (0x1UL << EXTI_FPR1_FPIF20_Pos)         /*!< 0x00100000 */
#define EXTI_FPR1_FPIF20                    EXTI_FPR1_FPIF20_Msk                    /*!< Falling Pending Interrupt Flag on line 20 */
#define EXTI_FPR1_FPIF21_Pos                (21UL)
#define EXTI_FPR1_FPIF21_Msk                (0x1UL << EXTI_FPR1_FPIF21_Pos)         /*!< 0x00200000 */
#define EXTI_FPR1_FPIF21                    EXTI_FPR1_FPIF21_Msk                    /*!< Falling Pending Interrupt Flag on line 21 */
#define EXTI_FPR1_FPIF22_Pos                (22UL)
#define EXTI_FPR1_FPIF22_Msk                (0x1UL << EXTI_FPR1_FPIF22_Pos)         /*!< 0x00400000 */
#define EXTI_FPR1_FPIF22                    EXTI_FPR1_FPIF22_Msk                    /*!< Falling Pending Interrupt Flag on line 22 */

/*******************  Bit definition for EXTI_SECENR1 register  ******************/
#define EXTI_SECCFGR1_RPIF0_Pos             (0UL)
#define EXTI_SECCFGR1_RPIF0_Msk             (0x1UL << EXTI_SECCFGR1_RPIF0_Pos)      /*!< 0x00000001 */
#define EXTI_SECCFGR1_RPIF0                 EXTI_SECCFGR1_RPIF0_Msk                 /*!< Security enable on line 0 */
#define EXTI_SECCFGR1_RPIF1_Pos             (1UL)
#define EXTI_SECCFGR1_RPIF1_Msk             (0x1UL << EXTI_SECCFGR1_RPIF1_Pos)      /*!< 0x00000002 */
#define EXTI_SECCFGR1_RPIF1                 EXTI_SECCFGR1_RPIF1_Msk                 /*!< Security enable on line 1 */
#define EXTI_SECCFGR1_RPIF2_Pos             (2UL)
#define EXTI_SECCFGR1_RPIF2_Msk             (0x1UL << EXTI_SECCFGR1_RPIF2_Pos)      /*!< 0x00000004 */
#define EXTI_SECCFGR1_RPIF2                 EXTI_SECCFGR1_RPIF2_Msk                 /*!< Security enable on line 2 */
#define EXTI_SECCFGR1_RPIF3_Pos             (3UL)
#define EXTI_SECCFGR1_RPIF3_Msk             (0x1UL << EXTI_SECCFGR1_RPIF3_Pos)      /*!< 0x00000008 */
#define EXTI_SECCFGR1_RPIF3                 EXTI_SECCFGR1_RPIF3_Msk                 /*!< Security enable on line 3 */
#define EXTI_SECCFGR1_RPIF4_Pos             (4UL)
#define EXTI_SECCFGR1_RPIF4_Msk             (0x1UL << EXTI_SECCFGR1_RPIF4_Pos)      /*!< 0x00000010 */
#define EXTI_SECCFGR1_RPIF4                 EXTI_SECCFGR1_RPIF4_Msk                 /*!< Security enable on line 4 */
#define EXTI_SECCFGR1_RPIF5_Pos             (5UL)
#define EXTI_SECCFGR1_RPIF5_Msk             (0x1UL << EXTI_SECCFGR1_RPIF5_Pos)      /*!< 0x00000020 */
#define EXTI_SECCFGR1_RPIF5                 EXTI_SECCFGR1_RPIF5_Msk                 /*!< Security enable on line 5 */
#define EXTI_SECCFGR1_RPIF6_Pos             (6UL)
#define EXTI_SECCFGR1_RPIF6_Msk             (0x1UL << EXTI_SECCFGR1_RPIF6_Pos)      /*!< 0x00000040 */
#define EXTI_SECCFGR1_RPIF6                 EXTI_SECCFGR1_RPIF6_Msk                 /*!< Security enable on line 6 */
#define EXTI_SECCFGR1_RPIF7_Pos             (7UL)
#define EXTI_SECCFGR1_RPIF7_Msk             (0x1UL << EXTI_SECCFGR1_RPIF7_Pos)      /*!< 0x00000080 */
#define EXTI_SECCFGR1_RPIF7                 EXTI_SECCFGR1_RPIF7_Msk                 /*!< Security enable on line 7 */
#define EXTI_SECCFGR1_RPIF8_Pos             (8UL)
#define EXTI_SECCFGR1_RPIF8_Msk             (0x1UL << EXTI_SECCFGR1_RPIF8_Pos)      /*!< 0x00000100 */
#define EXTI_SECCFGR1_RPIF8                 EXTI_SECCFGR1_RPIF8_Msk                 /*!< Security enable on line 8 */
#define EXTI_SECCFGR1_RPIF9_Pos             (9UL)
#define EXTI_SECCFGR1_RPIF9_Msk             (0x1UL << EXTI_SECCFGR1_RPIF9_Pos)      /*!< 0x00000200 */
#define EXTI_SECCFGR1_RPIF9                 EXTI_SECCFGR1_RPIF9_Msk                 /*!< Security enable on line 9 */
#define EXTI_SECCFGR1_RPIF10_Pos            (10UL)
#define EXTI_SECCFGR1_RPIF10_Msk            (0x1UL << EXTI_SECCFGR1_RPIF10_Pos)     /*!< 0x00000400 */
#define EXTI_SECCFGR1_RPIF10                EXTI_SECCFGR1_RPIF10_Msk                /*!< Security enable on line 10 */
#define EXTI_SECCFGR1_RPIF11_Pos            (11UL)
#define EXTI_SECCFGR1_RPIF11_Msk            (0x1UL << EXTI_SECCFGR1_RPIF11_Pos)     /*!< 0x00000800 */
#define EXTI_SECCFGR1_RPIF11                EXTI_SECCFGR1_RPIF11_Msk                /*!< Security enable on line 11 */
#define EXTI_SECCFGR1_RPIF12_Pos            (12UL)
#define EXTI_SECCFGR1_RPIF12_Msk            (0x1UL << EXTI_SECCFGR1_RPIF12_Pos)     /*!< 0x00001000 */
#define EXTI_SECCFGR1_RPIF12                EXTI_SECCFGR1_RPIF12_Msk                /*!< Security enable on line 12 */
#define EXTI_SECCFGR1_RPIF13_Pos            (13UL)
#define EXTI_SECCFGR1_RPIF13_Msk            (0x1UL << EXTI_SECCFGR1_RPIF13_Pos)     /*!< 0x00002000 */
#define EXTI_SECCFGR1_RPIF13                EXTI_SECCFGR1_RPIF13_Msk                /*!< Security enable on line 13 */
#define EXTI_SECCFGR1_RPIF14_Pos            (14UL)
#define EXTI_SECCFGR1_RPIF14_Msk            (0x1UL << EXTI_SECCFGR1_RPIF14_Pos)     /*!< 0x00004000 */
#define EXTI_SECCFGR1_RPIF14                EXTI_SECCFGR1_RPIF14_Msk                /*!< Security enable on line 14 */
#define EXTI_SECCFGR1_RPIF15_Pos            (15UL)
#define EXTI_SECCFGR1_RPIF15_Msk            (0x1UL << EXTI_SECCFGR1_RPIF15_Pos)     /*!< 0x00008000 */
#define EXTI_SECCFGR1_RPIF15                EXTI_SECCFGR1_RPIF15_Msk                /*!< Security enable on line 15 */
#define EXTI_SECCFGR1_RPIF16_Pos            (16UL)
#define EXTI_SECCFGR1_RPIF16_Msk            (0x1UL << EXTI_SECCFGR1_RPIF16_Pos)     /*!< 0x00010000 */
#define EXTI_SECCFGR1_RPIF16                EXTI_SECCFGR1_RPIF16_Msk                /*!< Security enable on line 16 */
#define EXTI_SECCFGR1_RPIF17_Pos            (17UL)
#define EXTI_SECCFGR1_RPIF17_Msk            (0x1UL << EXTI_SECCFGR1_RPIF17_Pos)     /*!< 0x00020000 */
#define EXTI_SECCFGR1_RPIF17                EXTI_SECCFGR1_RPIF17_Msk                /*!< Security enable on line 17 */
#define EXTI_SECCFGR1_RPIF18_Pos            (18UL)
#define EXTI_SECCFGR1_RPIF18_Msk            (0x1UL << EXTI_SECCFGR1_RPIF18_Pos)     /*!< 0x00040000 */
#define EXTI_SECCFGR1_RPIF18                EXTI_SECCFGR1_RPIF18_Msk                /*!< Security enable on line 18 */
#define EXTI_SECCFGR1_RPIF19_Pos            (19UL)
#define EXTI_SECCFGR1_RPIF19_Msk            (0x1UL << EXTI_SECCFGR1_RPIF19_Pos)     /*!< 0x00080000 */
#define EXTI_SECCFGR1_RPIF19                EXTI_SECCFGR1_RPIF19_Msk                /*!< Security enable on line 19 */
#define EXTI_SECCFGR1_RPIF20_Pos            (20UL)
#define EXTI_SECCFGR1_RPIF20_Msk            (0x1UL << EXTI_SECCFGR1_RPIF20_Pos)     /*!< 0x00100000 */
#define EXTI_SECCFGR1_RPIF20                EXTI_SECCFGR1_RPIF20_Msk                /*!< Security enable on line 20 */
#define EXTI_SECCFGR1_RPIF21_Pos            (21UL)
#define EXTI_SECCFGR1_RPIF21_Msk            (0x1UL << EXTI_SECCFGR1_RPIF21_Pos)     /*!< 0x00200000 */
#define EXTI_SECCFGR1_RPIF21                EXTI_SECCFGR1_RPIF21_Msk                /*!< Security enable on line 21 */
#define EXTI_SECCFGR1_RPIF22_Pos            (22UL)
#define EXTI_SECCFGR1_RPIF22_Msk            (0x1UL << EXTI_SECCFGR1_RPIF22_Pos)     /*!< 0x00400000 */
#define EXTI_SECCFGR1_RPIF22                EXTI_SECCFGR1_RPIF22_Msk                /*!< Security enable on line 22 */

/*******************  Bit definition for EXTI_PRIVENR1 register  ******************/
#define EXTI_PRIVCFGR1_RPIF0_Pos            (0UL)
#define EXTI_PRIVCFGR1_RPIF0_Msk            (0x1UL << EXTI_PRIVCFGR1_RPIF0_Pos)     /*!< 0x00000001 */
#define EXTI_PRIVCFGR1_RPIF0                EXTI_PRIVCFGR1_RPIF0_Msk                /*!< Privilege enable on line 0 */
#define EXTI_PRIVCFGR1_RPIF1_Pos            (1UL)
#define EXTI_PRIVCFGR1_RPIF1_Msk            (0x1UL << EXTI_PRIVCFGR1_RPIF1_Pos)     /*!< 0x00000002 */
#define EXTI_PRIVCFGR1_RPIF1                EXTI_PRIVCFGR1_RPIF1_Msk                /*!< Privilege enable on line 1 */
#define EXTI_PRIVCFGR1_RPIF2_Pos            (2UL)
#define EXTI_PRIVCFGR1_RPIF2_Msk            (0x1UL << EXTI_PRIVCFGR1_RPIF2_Pos)     /*!< 0x00000004 */
#define EXTI_PRIVCFGR1_RPIF2                EXTI_PRIVCFGR1_RPIF2_Msk                /*!< Privilege enable on line 2 */
#define EXTI_PRIVCFGR1_RPIF3_Pos            (3UL)
#define EXTI_PRIVCFGR1_RPIF3_Msk            (0x1UL << EXTI_PRIVCFGR1_RPIF3_Pos)     /*!< 0x00000008 */
#define EXTI_PRIVCFGR1_RPIF3                EXTI_PRIVCFGR1_RPIF3_Msk                /*!< Privilege enable on line 3 */
#define EXTI_PRIVCFGR1_RPIF4_Pos            (4UL)
#define EXTI_PRIVCFGR1_RPIF4_Msk            (0x1UL << EXTI_PRIVCFGR1_RPIF4_Pos)     /*!< 0x00000010 */
#define EXTI_PRIVCFGR1_RPIF4                EXTI_PRIVCFGR1_RPIF4_Msk                /*!< Privilege enable on line 4 */
#define EXTI_PRIVCFGR1_RPIF5_Pos            (5UL)
#define EXTI_PRIVCFGR1_RPIF5_Msk            (0x1UL << EXTI_PRIVCFGR1_RPIF5_Pos)     /*!< 0x00000020 */
#define EXTI_PRIVCFGR1_RPIF5                EXTI_PRIVCFGR1_RPIF5_Msk                /*!< Privilege enable on line 5 */
#define EXTI_PRIVCFGR1_RPIF6_Pos            (6UL)
#define EXTI_PRIVCFGR1_RPIF6_Msk            (0x1UL << EXTI_PRIVCFGR1_RPIF6_Pos)     /*!< 0x00000040 */
#define EXTI_PRIVCFGR1_RPIF6                EXTI_PRIVCFGR1_RPIF6_Msk                /*!< Privilege enable on line 6 */
#define EXTI_PRIVCFGR1_RPIF7_Pos            (7UL)
#define EXTI_PRIVCFGR1_RPIF7_Msk            (0x1UL << EXTI_PRIVCFGR1_RPIF7_Pos)     /*!< 0x00000080 */
#define EXTI_PRIVCFGR1_RPIF7                EXTI_PRIVCFGR1_RPIF7_Msk                /*!< Privilege enable on line 7 */
#define EXTI_PRIVCFGR1_RPIF8_Pos            (8UL)
#define EXTI_PRIVCFGR1_RPIF8_Msk            (0x1UL << EXTI_PRIVCFGR1_RPIF8_Pos)     /*!< 0x00000100 */
#define EXTI_PRIVCFGR1_RPIF8                EXTI_PRIVCFGR1_RPIF8_Msk                /*!< Privilege enable on line 8 */
#define EXTI_PRIVCFGR1_RPIF9_Pos            (9UL)
#define EXTI_PRIVCFGR1_RPIF9_Msk            (0x1UL << EXTI_PRIVCFGR1_RPIF9_Pos)     /*!< 0x00000200 */
#define EXTI_PRIVCFGR1_RPIF9                EXTI_PRIVCFGR1_RPIF9_Msk                /*!< Privilege enable on line 9 */
#define EXTI_PRIVCFGR1_RPIF10_Pos           (10UL)
#define EXTI_PRIVCFGR1_RPIF10_Msk           (0x1UL << EXTI_PRIVCFGR1_RPIF10_Pos)    /*!< 0x00000400 */
#define EXTI_PRIVCFGR1_RPIF10               EXTI_PRIVCFGR1_RPIF10_Msk               /*!< Privilege enable on line 10 */
#define EXTI_PRIVCFGR1_RPIF11_Pos           (11UL)
#define EXTI_PRIVCFGR1_RPIF11_Msk           (0x1UL << EXTI_PRIVCFGR1_RPIF11_Pos)    /*!< 0x00000800 */
#define EXTI_PRIVCFGR1_RPIF11               EXTI_PRIVCFGR1_RPIF11_Msk               /*!< Privilege enable on line 11 */
#define EXTI_PRIVCFGR1_RPIF12_Pos           (12UL)
#define EXTI_PRIVCFGR1_RPIF12_Msk           (0x1UL << EXTI_PRIVCFGR1_RPIF12_Pos)    /*!< 0x00001000 */
#define EXTI_PRIVCFGR1_RPIF12               EXTI_PRIVCFGR1_RPIF12_Msk               /*!< Privilege enable on line 12 */
#define EXTI_PRIVCFGR1_RPIF13_Pos           (13UL)
#define EXTI_PRIVCFGR1_RPIF13_Msk           (0x1UL << EXTI_PRIVCFGR1_RPIF13_Pos)    /*!< 0x00002000 */
#define EXTI_PRIVCFGR1_RPIF13               EXTI_PRIVCFGR1_RPIF13_Msk               /*!< Privilege enable on line 13 */
#define EXTI_PRIVCFGR1_RPIF14_Pos           (14UL)
#define EXTI_PRIVCFGR1_RPIF14_Msk           (0x1UL << EXTI_PRIVCFGR1_RPIF14_Pos)    /*!< 0x00004000 */
#define EXTI_PRIVCFGR1_RPIF14               EXTI_PRIVCFGR1_RPIF14_Msk               /*!< Privilege enable on line 14 */
#define EXTI_PRIVCFGR1_RPIF15_Pos           (15UL)
#define EXTI_PRIVCFGR1_RPIF15_Msk           (0x1UL << EXTI_PRIVCFGR1_RPIF15_Pos)    /*!< 0x00008000 */
#define EXTI_PRIVCFGR1_RPIF15               EXTI_PRIVCFGR1_RPIF15_Msk               /*!< Privilege enable on line 15 */
#define EXTI_PRIVCFGR1_RPIF16_Pos           (16UL)
#define EXTI_PRIVCFGR1_RPIF16_Msk           (0x1UL << EXTI_PRIVCFGR1_RPIF16_Pos)    /*!< 0x00010000 */
#define EXTI_PRIVCFGR1_RPIF16               EXTI_PRIVCFGR1_RPIF16_Msk               /*!< Privilege enable on line 16 */
#define EXTI_PRIVCFGR1_RPIF17_Pos           (17UL)
#define EXTI_PRIVCFGR1_RPIF17_Msk           (0x1UL << EXTI_PRIVCFGR1_RPIF17_Pos)    /*!< 0x00020000 */
#define EXTI_PRIVCFGR1_RPIF17               EXTI_PRIVCFGR1_RPIF17_Msk               /*!< Privilege enable on line 17 */
#define EXTI_PRIVCFGR1_RPIF18_Pos           (18UL)
#define EXTI_PRIVCFGR1_RPIF18_Msk           (0x1UL << EXTI_PRIVCFGR1_RPIF18_Pos)    /*!< 0x00040000 */
#define EXTI_PRIVCFGR1_RPIF18               EXTI_PRIVCFGR1_RPIF18_Msk               /*!< Privilege enable on line 18 */
#define EXTI_PRIVCFGR1_RPIF19_Pos           (19UL)
#define EXTI_PRIVCFGR1_RPIF19_Msk           (0x1UL << EXTI_PRIVCFGR1_RPIF19_Pos)    /*!< 0x00080000 */
#define EXTI_PRIVCFGR1_RPIF19               EXTI_PRIVCFGR1_RPIF19_Msk               /*!< Privilege enable on line 19 */
#define EXTI_PRIVCFGR1_RPIF20_Pos           (20UL)
#define EXTI_PRIVCFGR1_RPIF20_Msk           (0x1UL << EXTI_PRIVCFGR1_RPIF20_Pos)    /*!< 0x00100000 */
#define EXTI_PRIVCFGR1_RPIF20               EXTI_PRIVCFGR1_RPIF20_Msk               /*!< Privilege enable on line 20 */
#define EXTI_PRIVCFGR1_RPIF21_Pos           (21UL)
#define EXTI_PRIVCFGR1_RPIF21_Msk           (0x1UL << EXTI_PRIVCFGR1_RPIF21_Pos)    /*!< 0x00200000 */
#define EXTI_PRIVCFGR1_RPIF21               EXTI_PRIVCFGR1_RPIF21_Msk               /*!< Privilege enable on line 21 */
#define EXTI_PRIVCFGR1_RPIF22_Pos           (22UL)
#define EXTI_PRIVCFGR1_RPIF22_Msk           (0x1UL << EXTI_PRIVCFGR1_RPIF22_Pos)    /*!< 0x00400000 */
#define EXTI_PRIVCFGR1_RPIF22               EXTI_PRIVCFGR1_RPIF22_Msk               /*!< Privilege enable on line 22 */

/*****************  Bit definition for EXTI_EXTICR1 register  **************/
#define EXTI_EXTICR1_EXTI0_Pos              (0UL)
#define EXTI_EXTICR1_EXTI0_Msk              (0xFUL << EXTI_EXTICR1_EXTI0_Pos)       /*!< 0x00000007 */
#define EXTI_EXTICR1_EXTI0                  EXTI_EXTICR1_EXTI0_Msk                  /*!< EXTI 0 configuration */
#define EXTI_EXTICR1_EXTI0_0                (0x1UL << EXTI_EXTICR1_EXTI0_Pos)       /*!< 0x00000001 */
#define EXTI_EXTICR1_EXTI0_1                (0x2UL << EXTI_EXTICR1_EXTI0_Pos)       /*!< 0x00000002 */
#define EXTI_EXTICR1_EXTI0_2                (0x4UL << EXTI_EXTICR1_EXTI0_Pos)       /*!< 0x00000004 */
#define EXTI_EXTICR1_EXTI0_3                (0x8UL << EXTI_EXTICR1_EXTI0_Pos)       /*!< 0x00000008 */
#define EXTI_EXTICR1_EXTI1_Pos              (8UL)
#define EXTI_EXTICR1_EXTI1_Msk              (0xFUL << EXTI_EXTICR1_EXTI1_Pos)       /*!< 0x00000700 */
#define EXTI_EXTICR1_EXTI1                  EXTI_EXTICR1_EXTI1_Msk                  /*!< EXTI 1 configuration */
#define EXTI_EXTICR1_EXTI1_0                (0x1UL << EXTI_EXTICR1_EXTI1_Pos)       /*!< 0x00000100 */
#define EXTI_EXTICR1_EXTI1_1                (0x2UL << EXTI_EXTICR1_EXTI1_Pos)       /*!< 0x00000200 */
#define EXTI_EXTICR1_EXTI1_2                (0x4UL << EXTI_EXTICR1_EXTI1_Pos)       /*!< 0x00000400 */
#define EXTI_EXTICR1_EXTI1_3                (0x8UL << EXTI_EXTICR1_EXTI1_Pos)       /*!< 0x00000800 */
#define EXTI_EXTICR1_EXTI2_Pos              (16UL)
#define EXTI_EXTICR1_EXTI2_Msk              (0xFUL << EXTI_EXTICR1_EXTI2_Pos)       /*!< 0x00070000 */
#define EXTI_EXTICR1_EXTI2                  EXTI_EXTICR1_EXTI2_Msk                  /*!< EXTI 2 configuration */
#define EXTI_EXTICR1_EXTI2_0                (0x1UL << EXTI_EXTICR1_EXTI2_Pos)       /*!< 0x00010000 */
#define EXTI_EXTICR1_EXTI2_1                (0x2UL << EXTI_EXTICR1_EXTI2_Pos)       /*!< 0x00020000 */
#define EXTI_EXTICR1_EXTI2_2                (0x4UL << EXTI_EXTICR1_EXTI2_Pos)       /*!< 0x00040000 */
#define EXTI_EXTICR1_EXTI2_3                (0x8UL << EXTI_EXTICR1_EXTI2_Pos)       /*!< 0x00080000 */
#define EXTI_EXTICR1_EXTI3_Pos              (24UL)
#define EXTI_EXTICR1_EXTI3_Msk              (0xFUL << EXTI_EXTICR1_EXTI3_Pos)       /*!< 0x07000000 */
#define EXTI_EXTICR1_EXTI3                  EXTI_EXTICR1_EXTI3_Msk                  /*!< EXTI 3 configuration */
#define EXTI_EXTICR1_EXTI3_0                (0x1UL << EXTI_EXTICR1_EXTI3_Pos)       /*!< 0x01000000 */
#define EXTI_EXTICR1_EXTI3_1                (0x2UL << EXTI_EXTICR1_EXTI3_Pos)       /*!< 0x02000000 */
#define EXTI_EXTICR1_EXTI3_2                (0x4UL << EXTI_EXTICR1_EXTI3_Pos)       /*!< 0x04000000 */
#define EXTI_EXTICR1_EXTI3_3                (0x8UL << EXTI_EXTICR1_EXTI3_Pos)       /*!< 0x08000000 */

/*****************  Bit definition for EXTI_EXTICR2 register  **************/
#define EXTI_EXTICR2_EXTI4_Pos              (0UL)
#define EXTI_EXTICR2_EXTI4_Msk              (0xFUL << EXTI_EXTICR2_EXTI4_Pos)       /*!< 0x00000007 */
#define EXTI_EXTICR2_EXTI4                  EXTI_EXTICR2_EXTI4_Msk                  /*!< EXTI 4 configuration */
#define EXTI_EXTICR2_EXTI4_0                (0x1UL << EXTI_EXTICR2_EXTI4_Pos)       /*!< 0x00000001 */
#define EXTI_EXTICR2_EXTI4_1                (0x2UL << EXTI_EXTICR2_EXTI4_Pos)       /*!< 0x00000002 */
#define EXTI_EXTICR2_EXTI4_2                (0x4UL << EXTI_EXTICR2_EXTI4_Pos)       /*!< 0x00000004 */
#define EXTI_EXTICR2_EXTI4_3                (0x8UL << EXTI_EXTICR2_EXTI4_Pos)       /*!< 0x00000008 */
#define EXTI_EXTICR2_EXTI5_Pos              (8UL)
#define EXTI_EXTICR2_EXTI5_Msk              (0xFUL << EXTI_EXTICR2_EXTI5_Pos)       /*!< 0x00000700 */
#define EXTI_EXTICR2_EXTI5                  EXTI_EXTICR2_EXTI5_Msk                  /*!< EXTI 5 configuration */
#define EXTI_EXTICR2_EXTI5_0                (0x1UL << EXTI_EXTICR2_EXTI5_Pos)       /*!< 0x00000100 */
#define EXTI_EXTICR2_EXTI5_1                (0x2UL << EXTI_EXTICR2_EXTI5_Pos)       /*!< 0x00000200 */
#define EXTI_EXTICR2_EXTI5_2                (0x4UL << EXTI_EXTICR2_EXTI5_Pos)       /*!< 0x00000400 */
#define EXTI_EXTICR2_EXTI5_3                (0x8UL << EXTI_EXTICR2_EXTI5_Pos)       /*!< 0x00000800 */
#define EXTI_EXTICR2_EXTI6_Pos              (16UL)
#define EXTI_EXTICR2_EXTI6_Msk              (0xFUL << EXTI_EXTICR2_EXTI6_Pos)       /*!< 0x00070000 */
#define EXTI_EXTICR2_EXTI6                  EXTI_EXTICR2_EXTI6_Msk                  /*!< EXTI 6 configuration */
#define EXTI_EXTICR2_EXTI6_0                (0x1UL << EXTI_EXTICR2_EXTI6_Pos)       /*!< 0x00010000 */
#define EXTI_EXTICR2_EXTI6_1                (0x2UL << EXTI_EXTICR2_EXTI6_Pos)       /*!< 0x00020000 */
#define EXTI_EXTICR2_EXTI6_2                (0x4UL << EXTI_EXTICR2_EXTI6_Pos)       /*!< 0x00040000 */
#define EXTI_EXTICR2_EXTI6_3                (0x8UL << EXTI_EXTICR2_EXTI6_Pos)       /*!< 0x00080000 */
#define EXTI_EXTICR2_EXTI7_Pos              (24UL)
#define EXTI_EXTICR2_EXTI7_Msk              (0xFUL << EXTI_EXTICR2_EXTI7_Pos)       /*!< 0x07000000 */
#define EXTI_EXTICR2_EXTI7                  EXTI_EXTICR2_EXTI7_Msk                  /*!< EXTI 7 configuration */
#define EXTI_EXTICR2_EXTI7_0                (0x1UL << EXTI_EXTICR2_EXTI7_Pos)       /*!< 0x01000000 */
#define EXTI_EXTICR2_EXTI7_1                (0x2UL << EXTI_EXTICR2_EXTI7_Pos)       /*!< 0x02000000 */
#define EXTI_EXTICR2_EXTI7_2                (0x4UL << EXTI_EXTICR2_EXTI7_Pos)       /*!< 0x04000000 */
#define EXTI_EXTICR2_EXTI7_3                (0x8UL << EXTI_EXTICR2_EXTI7_Pos)       /*!< 0x08000000 */

/*****************  Bit definition for EXTI_EXTICR3 register  **************/
#define EXTI_EXTICR3_EXTI8_Pos              (0UL)
#define EXTI_EXTICR3_EXTI8_Msk              (0xFUL << EXTI_EXTICR3_EXTI8_Pos)       /*!< 0x00000007 */
#define EXTI_EXTICR3_EXTI8                  EXTI_EXTICR3_EXTI8_Msk                  /*!< EXTI 8 configuration */
#define EXTI_EXTICR3_EXTI8_0                (0x1UL << EXTI_EXTICR3_EXTI8_Pos)       /*!< 0x00000001 */
#define EXTI_EXTICR3_EXTI8_1                (0x2UL << EXTI_EXTICR3_EXTI8_Pos)       /*!< 0x00000002 */
#define EXTI_EXTICR3_EXTI8_2                (0x4UL << EXTI_EXTICR3_EXTI8_Pos)       /*!< 0x00000004 */
#define EXTI_EXTICR3_EXTI8_3                (0x8UL << EXTI_EXTICR3_EXTI8_Pos)       /*!< 0x00000008 */
#define EXTI_EXTICR3_EXTI9_Pos              (8UL)
#define EXTI_EXTICR3_EXTI9_Msk              (0xFUL << EXTI_EXTICR3_EXTI9_Pos)       /*!< 0x00000700 */
#define EXTI_EXTICR3_EXTI9                  EXTI_EXTICR3_EXTI9_Msk                  /*!< EXTI 9 configuration */
#define EXTI_EXTICR3_EXTI9_0                (0x1UL << EXTI_EXTICR3_EXTI9_Pos)       /*!< 0x00000100 */
#define EXTI_EXTICR3_EXTI9_1                (0x2UL << EXTI_EXTICR3_EXTI9_Pos)       /*!< 0x00000200 */
#define EXTI_EXTICR3_EXTI9_2                (0x4UL << EXTI_EXTICR3_EXTI9_Pos)       /*!< 0x00000400 */
#define EXTI_EXTICR3_EXTI9_3                (0x8UL << EXTI_EXTICR3_EXTI9_Pos)       /*!< 0x00000800 */
#define EXTI_EXTICR3_EXTI10_Pos             (16UL)
#define EXTI_EXTICR3_EXTI10_Msk             (0xFUL << EXTI_EXTICR3_EXTI10_Pos)      /*!< 0x00070000 */
#define EXTI_EXTICR3_EXTI10                 EXTI_EXTICR3_EXTI10_Msk                 /*!< EXTI 10 configuration */
#define EXTI_EXTICR3_EXTI10_0               (0x1UL << EXTI_EXTICR3_EXTI10_Pos)      /*!< 0x00010000 */
#define EXTI_EXTICR3_EXTI10_1               (0x2UL << EXTI_EXTICR3_EXTI10_Pos)      /*!< 0x00020000 */
#define EXTI_EXTICR3_EXTI10_2               (0x4UL << EXTI_EXTICR3_EXTI10_Pos)      /*!< 0x00040000 */
#define EXTI_EXTICR3_EXTI10_3               (0x8UL << EXTI_EXTICR3_EXTI10_Pos)      /*!< 0x00080000 */
#define EXTI_EXTICR3_EXTI11_Pos             (24UL)
#define EXTI_EXTICR3_EXTI11_Msk             (0xFUL << EXTI_EXTICR3_EXTI11_Pos)      /*!< 0x07000000 */
#define EXTI_EXTICR3_EXTI11                 EXTI_EXTICR3_EXTI11_Msk                 /*!< EXTI 11 configuration */
#define EXTI_EXTICR3_EXTI11_0               (0x1UL << EXTI_EXTICR3_EXTI11_Pos)      /*!< 0x01000000 */
#define EXTI_EXTICR3_EXTI11_1               (0x2UL << EXTI_EXTICR3_EXTI11_Pos)      /*!< 0x02000000 */
#define EXTI_EXTICR3_EXTI11_2               (0x4UL << EXTI_EXTICR3_EXTI11_Pos)      /*!< 0x04000000 */
#define EXTI_EXTICR3_EXTI11_3               (0x8UL << EXTI_EXTICR3_EXTI11_Pos)      /*!< 0x08000000 */

/*****************  Bit definition for EXTI_EXTICR4 register  **************/
#define EXTI_EXTICR4_EXTI12_Pos             (0UL)
#define EXTI_EXTICR4_EXTI12_Msk             (0xFUL << EXTI_EXTICR4_EXTI12_Pos)      /*!< 0x00000007 */
#define EXTI_EXTICR4_EXTI12                 EXTI_EXTICR4_EXTI12_Msk                 /*!< EXTI 12 configuration */
#define EXTI_EXTICR4_EXTI12_0               (0x1UL << EXTI_EXTICR4_EXTI12_Pos)      /*!< 0x00000001 */
#define EXTI_EXTICR4_EXTI12_1               (0x2UL << EXTI_EXTICR4_EXTI12_Pos)      /*!< 0x00000002 */
#define EXTI_EXTICR4_EXTI12_2               (0x4UL << EXTI_EXTICR4_EXTI12_Pos)      /*!< 0x00000004 */
#define EXTI_EXTICR4_EXTI12_3               (0x8UL << EXTI_EXTICR4_EXTI12_Pos)      /*!< 0x00000008 */
#define EXTI_EXTICR4_EXTI13_Pos             (8UL)
#define EXTI_EXTICR4_EXTI13_Msk             (0xFUL << EXTI_EXTICR4_EXTI13_Pos)      /*!< 0x00000700 */
#define EXTI_EXTICR4_EXTI13                 EXTI_EXTICR4_EXTI13_Msk                 /*!< EXTI 13 configuration */
#define EXTI_EXTICR4_EXTI13_0               (0x1UL << EXTI_EXTICR4_EXTI13_Pos)      /*!< 0x00000100 */
#define EXTI_EXTICR4_EXTI13_1               (0x2UL << EXTI_EXTICR4_EXTI13_Pos)      /*!< 0x00000200 */
#define EXTI_EXTICR4_EXTI13_2               (0x4UL << EXTI_EXTICR4_EXTI13_Pos)      /*!< 0x00000400 */
#define EXTI_EXTICR4_EXTI13_3               (0x8UL << EXTI_EXTICR4_EXTI13_Pos)      /*!< 0x00000800 */
#define EXTI_EXTICR4_EXTI14_Pos             (16UL)
#define EXTI_EXTICR4_EXTI14_Msk             (0xFUL << EXTI_EXTICR4_EXTI14_Pos)      /*!< 0x00070000 */
#define EXTI_EXTICR4_EXTI14                 EXTI_EXTICR4_EXTI14_Msk                 /*!< EXTI 14 configuration */
#define EXTI_EXTICR4_EXTI14_0               (0x1UL << EXTI_EXTICR4_EXTI14_Pos)      /*!< 0x00010000 */
#define EXTI_EXTICR4_EXTI14_1               (0x2UL << EXTI_EXTICR4_EXTI14_Pos)      /*!< 0x00020000 */
#define EXTI_EXTICR4_EXTI14_2               (0x4UL << EXTI_EXTICR4_EXTI14_Pos)      /*!< 0x00040000 */
#define EXTI_EXTICR4_EXTI14_3               (0x8UL << EXTI_EXTICR4_EXTI14_Pos)      /*!< 0x00080000 */
#define EXTI_EXTICR4_EXTI15_Pos             (24UL)
#define EXTI_EXTICR4_EXTI15_Msk             (0xFUL << EXTI_EXTICR4_EXTI15_Pos)      /*!< 0x07000000 */
#define EXTI_EXTICR4_EXTI15                 EXTI_EXTICR4_EXTI15_Msk                 /*!< EXTI 15 configuration */
#define EXTI_EXTICR4_EXTI15_0               (0x1UL << EXTI_EXTICR4_EXTI15_Pos)      /*!< 0x01000000 */
#define EXTI_EXTICR4_EXTI15_1               (0x2UL << EXTI_EXTICR4_EXTI15_Pos)      /*!< 0x02000000 */
#define EXTI_EXTICR4_EXTI15_2               (0x4UL << EXTI_EXTICR4_EXTI15_Pos)      /*!< 0x04000000 */
#define EXTI_EXTICR4_EXTI15_3               (0x8UL << EXTI_EXTICR4_EXTI15_Pos)      /*!< 0x08000000 */

/*******************  Bit definition for EXTI_LOCKR register  *****************/
#define EXTI_LOCKR_LOCK_Pos                 (0UL)
#define EXTI_LOCKR_LOCK_Msk                 (0x1UL << EXTI_LOCKR_LOCK_Pos)          /*!< 0x00000001 */
#define EXTI_LOCKR_LOCK                     EXTI_LOCKR_LOCK_Msk                     /*! Security and privilege lock */

/*******************  Bit definition for EXTI_IMR1 register  ******************/
#define EXTI_IMR1_IM0_Pos                   (0UL)
#define EXTI_IMR1_IM0_Msk                   (0x1UL << EXTI_IMR1_IM0_Pos)            /*!< 0x00000001 */
#define EXTI_IMR1_IM0                       EXTI_IMR1_IM0_Msk                       /*!< Interrupt Mask on line 0 */
#define EXTI_IMR1_IM1_Pos                   (1UL)
#define EXTI_IMR1_IM1_Msk                   (0x1UL << EXTI_IMR1_IM1_Pos)            /*!< 0x00000002 */
#define EXTI_IMR1_IM1                       EXTI_IMR1_IM1_Msk                       /*!< Interrupt Mask on line 1 */
#define EXTI_IMR1_IM2_Pos                   (2UL)
#define EXTI_IMR1_IM2_Msk                   (0x1UL << EXTI_IMR1_IM2_Pos)            /*!< 0x00000004 */
#define EXTI_IMR1_IM2                       EXTI_IMR1_IM2_Msk                       /*!< Interrupt Mask on line 2 */
#define EXTI_IMR1_IM3_Pos                   (3UL)
#define EXTI_IMR1_IM3_Msk                   (0x1UL << EXTI_IMR1_IM3_Pos)            /*!< 0x00000008 */
#define EXTI_IMR1_IM3                       EXTI_IMR1_IM3_Msk                       /*!< Interrupt Mask on line 3 */
#define EXTI_IMR1_IM4_Pos                   (4UL)
#define EXTI_IMR1_IM4_Msk                   (0x1UL << EXTI_IMR1_IM4_Pos)            /*!< 0x00000010 */
#define EXTI_IMR1_IM4                       EXTI_IMR1_IM4_Msk                       /*!< Interrupt Mask on line 4 */
#define EXTI_IMR1_IM5_Pos                   (5UL)
#define EXTI_IMR1_IM5_Msk                   (0x1UL << EXTI_IMR1_IM5_Pos)            /*!< 0x00000020 */
#define EXTI_IMR1_IM5                       EXTI_IMR1_IM5_Msk                       /*!< Interrupt Mask on line 5 */
#define EXTI_IMR1_IM6_Pos                   (6UL)
#define EXTI_IMR1_IM6_Msk                   (0x1UL << EXTI_IMR1_IM6_Pos)            /*!< 0x00000040 */
#define EXTI_IMR1_IM6                       EXTI_IMR1_IM6_Msk                       /*!< Interrupt Mask on line 6 */
#define EXTI_IMR1_IM7_Pos                   (7UL)
#define EXTI_IMR1_IM7_Msk                   (0x1UL << EXTI_IMR1_IM7_Pos)            /*!< 0x00000080 */
#define EXTI_IMR1_IM7                       EXTI_IMR1_IM7_Msk                       /*!< Interrupt Mask on line 7 */
#define EXTI_IMR1_IM8_Pos                   (8UL)
#define EXTI_IMR1_IM8_Msk                   (0x1UL << EXTI_IMR1_IM8_Pos)            /*!< 0x00000100 */
#define EXTI_IMR1_IM8                       EXTI_IMR1_IM8_Msk                       /*!< Interrupt Mask on line 8 */
#define EXTI_IMR1_IM9_Pos                   (9UL)
#define EXTI_IMR1_IM9_Msk                   (0x1UL << EXTI_IMR1_IM9_Pos)            /*!< 0x00000200 */
#define EXTI_IMR1_IM9                       EXTI_IMR1_IM9_Msk                       /*!< Interrupt Mask on line 9 */
#define EXTI_IMR1_IM10_Pos                  (10UL)
#define EXTI_IMR1_IM10_Msk                  (0x1UL << EXTI_IMR1_IM10_Pos)           /*!< 0x00000400 */
#define EXTI_IMR1_IM10                      EXTI_IMR1_IM10_Msk                      /*!< Interrupt Mask on line 10 */
#define EXTI_IMR1_IM11_Pos                  (11UL)
#define EXTI_IMR1_IM11_Msk                  (0x1UL << EXTI_IMR1_IM11_Pos)           /*!< 0x00000800 */
#define EXTI_IMR1_IM11                      EXTI_IMR1_IM11_Msk                      /*!< Interrupt Mask on line 11 */
#define EXTI_IMR1_IM12_Pos                  (12UL)
#define EXTI_IMR1_IM12_Msk                  (0x1UL << EXTI_IMR1_IM12_Pos)           /*!< 0x00001000 */
#define EXTI_IMR1_IM12                      EXTI_IMR1_IM12_Msk                      /*!< Interrupt Mask on line 12 */
#define EXTI_IMR1_IM13_Pos                  (13UL)
#define EXTI_IMR1_IM13_Msk                  (0x1UL << EXTI_IMR1_IM13_Pos)           /*!< 0x00002000 */
#define EXTI_IMR1_IM13                      EXTI_IMR1_IM13_Msk                      /*!< Interrupt Mask on line 13 */
#define EXTI_IMR1_IM14_Pos                  (14UL)
#define EXTI_IMR1_IM14_Msk                  (0x1UL << EXTI_IMR1_IM14_Pos)           /*!< 0x00004000 */
#define EXTI_IMR1_IM14                      EXTI_IMR1_IM14_Msk                      /*!< Interrupt Mask on line 14 */
#define EXTI_IMR1_IM15_Pos                  (15UL)
#define EXTI_IMR1_IM15_Msk                  (0x1UL << EXTI_IMR1_IM15_Pos)           /*!< 0x00008000 */
#define EXTI_IMR1_IM15                      EXTI_IMR1_IM15_Msk                      /*!< Interrupt Mask on line 15 */
#define EXTI_IMR1_IM16_Pos                  (16UL)
#define EXTI_IMR1_IM16_Msk                  (0x1UL << EXTI_IMR1_IM16_Pos)           /*!< 0x00010000 */
#define EXTI_IMR1_IM16                      EXTI_IMR1_IM16_Msk                      /*!< Interrupt Mask on line 16 */
#define EXTI_IMR1_IM17_Pos                  (17UL)
#define EXTI_IMR1_IM17_Msk                  (0x1UL << EXTI_IMR1_IM17_Pos)           /*!< 0x00020000 */
#define EXTI_IMR1_IM17                      EXTI_IMR1_IM17_Msk                      /*!< Interrupt Mask on line 17 */
#define EXTI_IMR1_IM18_Pos                  (18UL)
#define EXTI_IMR1_IM18_Msk                  (0x1UL << EXTI_IMR1_IM18_Pos)           /*!< 0x00040000 */
#define EXTI_IMR1_IM18                      EXTI_IMR1_IM18_Msk                      /*!< Interrupt Mask on line 18 */
#define EXTI_IMR1_IM19_Pos                  (19UL)
#define EXTI_IMR1_IM19_Msk                  (0x1UL << EXTI_IMR1_IM19_Pos)           /*!< 0x00080000 */
#define EXTI_IMR1_IM19                      EXTI_IMR1_IM19_Msk                      /*!< Interrupt Mask on line 19 */
#define EXTI_IMR1_IM20_Pos                  (20UL)
#define EXTI_IMR1_IM20_Msk                  (0x1UL << EXTI_IMR1_IM20_Pos)           /*!< 0x00100000 */
#define EXTI_IMR1_IM20                      EXTI_IMR1_IM20_Msk                      /*!< Interrupt Mask on line 20 */
#define EXTI_IMR1_IM21_Pos                  (21UL)
#define EXTI_IMR1_IM21_Msk                  (0x1UL << EXTI_IMR1_IM21_Pos)           /*!< 0x00200000 */
#define EXTI_IMR1_IM21                      EXTI_IMR1_IM21_Msk                      /*!< Interrupt Mask on line 21 */
#define EXTI_IMR1_IM22_Pos                  (22UL)
#define EXTI_IMR1_IM22_Msk                  (0x1UL << EXTI_IMR1_IM22_Pos)           /*!< 0x00400000 */
#define EXTI_IMR1_IM22                      EXTI_IMR1_IM22_Msk                      /*!< Interrupt Mask on line 22 */

/*******************  Bit definition for EXTI_EMR1 register  ******************/
#define EXTI_EMR1_EM0_Pos                   (0UL)
#define EXTI_EMR1_EM0_Msk                   (0x1UL << EXTI_EMR1_EM0_Pos)            /*!< 0x00000001 */
#define EXTI_EMR1_EM0                       EXTI_EMR1_EM0_Msk                       /*!< Event Mask on line 0 */
#define EXTI_EMR1_EM1_Pos                   (1UL)
#define EXTI_EMR1_EM1_Msk                   (0x1UL << EXTI_EMR1_EM1_Pos)            /*!< 0x00000002 */
#define EXTI_EMR1_EM1                       EXTI_EMR1_EM1_Msk                       /*!< Event Mask on line 1 */
#define EXTI_EMR1_EM2_Pos                   (2UL)
#define EXTI_EMR1_EM2_Msk                   (0x1UL << EXTI_EMR1_EM2_Pos)            /*!< 0x00000004 */
#define EXTI_EMR1_EM2                       EXTI_EMR1_EM2_Msk                       /*!< Event Mask on line 2 */
#define EXTI_EMR1_EM3_Pos                   (3UL)
#define EXTI_EMR1_EM3_Msk                   (0x1UL << EXTI_EMR1_EM3_Pos)            /*!< 0x00000008 */
#define EXTI_EMR1_EM3                       EXTI_EMR1_EM3_Msk                       /*!< Event Mask on line 3 */
#define EXTI_EMR1_EM4_Pos                   (4UL)
#define EXTI_EMR1_EM4_Msk                   (0x1UL << EXTI_EMR1_EM4_Pos)            /*!< 0x00000010 */
#define EXTI_EMR1_EM4                       EXTI_EMR1_EM4_Msk                       /*!< Event Mask on line 4 */
#define EXTI_EMR1_EM5_Pos                   (5UL)
#define EXTI_EMR1_EM5_Msk                   (0x1UL << EXTI_EMR1_EM5_Pos)            /*!< 0x00000020 */
#define EXTI_EMR1_EM5                       EXTI_EMR1_EM5_Msk                       /*!< Event Mask on line 5 */
#define EXTI_EMR1_EM6_Pos                   (6UL)
#define EXTI_EMR1_EM6_Msk                   (0x1UL << EXTI_EMR1_EM6_Pos)            /*!< 0x00000040 */
#define EXTI_EMR1_EM6                       EXTI_EMR1_EM6_Msk                       /*!< Event Mask on line 6 */
#define EXTI_EMR1_EM7_Pos                   (7UL)
#define EXTI_EMR1_EM7_Msk                   (0x1UL << EXTI_EMR1_EM7_Pos)            /*!< 0x00000080 */
#define EXTI_EMR1_EM7                       EXTI_EMR1_EM7_Msk                       /*!< Event Mask on line 7 */
#define EXTI_EMR1_EM8_Pos                   (8UL)
#define EXTI_EMR1_EM8_Msk                   (0x1UL << EXTI_EMR1_EM8_Pos)            /*!< 0x00000100 */
#define EXTI_EMR1_EM8                       EXTI_EMR1_EM8_Msk                       /*!< Event Mask on line 8 */
#define EXTI_EMR1_EM9_Pos                   (9UL)
#define EXTI_EMR1_EM9_Msk                   (0x1UL << EXTI_EMR1_EM9_Pos)            /*!< 0x00000200 */
#define EXTI_EMR1_EM9                       EXTI_EMR1_EM9_Msk                       /*!< Event Mask on line 9 */
#define EXTI_EMR1_EM10_Pos                  (10UL)
#define EXTI_EMR1_EM10_Msk                  (0x1UL << EXTI_EMR1_EM10_Pos)           /*!< 0x00000400 */
#define EXTI_EMR1_EM10                      EXTI_EMR1_EM10_Msk                      /*!< Event Mask on line 10 */
#define EXTI_EMR1_EM11_Pos                  (11UL)
#define EXTI_EMR1_EM11_Msk                  (0x1UL << EXTI_EMR1_EM11_Pos)           /*!< 0x00000800 */
#define EXTI_EMR1_EM11                      EXTI_EMR1_EM11_Msk                      /*!< Event Mask on line 11 */
#define EXTI_EMR1_EM12_Pos                  (12UL)
#define EXTI_EMR1_EM12_Msk                  (0x1UL << EXTI_EMR1_EM12_Pos)           /*!< 0x00001000 */
#define EXTI_EMR1_EM12                      EXTI_EMR1_EM12_Msk                      /*!< Event Mask on line 12 */
#define EXTI_EMR1_EM13_Pos                  (13UL)
#define EXTI_EMR1_EM13_Msk                  (0x1UL << EXTI_EMR1_EM13_Pos)           /*!< 0x00002000 */
#define EXTI_EMR1_EM13                      EXTI_EMR1_EM13_Msk                      /*!< Event Mask on line 13 */
#define EXTI_EMR1_EM14_Pos                  (14UL)
#define EXTI_EMR1_EM14_Msk                  (0x1UL << EXTI_EMR1_EM14_Pos)           /*!< 0x00004000 */
#define EXTI_EMR1_EM14                      EXTI_EMR1_EM14_Msk                      /*!< Event Mask on line 14 */
#define EXTI_EMR1_EM15_Pos                  (15UL)
#define EXTI_EMR1_EM15_Msk                  (0x1UL << EXTI_EMR1_EM15_Pos)           /*!< 0x00008000 */
#define EXTI_EMR1_EM15                      EXTI_EMR1_EM15_Msk                      /*!< Event Mask on line 15 */
#define EXTI_EMR1_EM16_Pos                  (16UL)
#define EXTI_EMR1_EM16_Msk                  (0x1UL << EXTI_EMR1_EM16_Pos)           /*!< 0x00010000 */
#define EXTI_EMR1_EM16                      EXTI_EMR1_EM16_Msk                      /*!< Event Mask on line 16 */
#define EXTI_EMR1_EM17_Pos                  (17UL)
#define EXTI_EMR1_EM17_Msk                  (0x1UL << EXTI_EMR1_EM17_Pos)           /*!< 0x00020000 */
#define EXTI_EMR1_EM17                      EXTI_EMR1_EM17_Msk                      /*!< Event Mask on line 17 */
#define EXTI_EMR1_EM18_Pos                  (18UL)
#define EXTI_EMR1_EM18_Msk                  (0x1UL << EXTI_EMR1_EM18_Pos)           /*!< 0x00040000 */
#define EXTI_EMR1_EM18                      EXTI_EMR1_EM18_Msk                      /*!< Event Mask on line 18 */
#define EXTI_EMR1_EM19_Pos                  (19UL)
#define EXTI_EMR1_EM19_Msk                  (0x1UL << EXTI_EMR1_EM19_Pos)           /*!< 0x00080000 */
#define EXTI_EMR1_EM19                      EXTI_EMR1_EM19_Msk                      /*!< Event Mask on line 19 */
#define EXTI_EMR1_EM20_Pos                  (20UL)
#define EXTI_EMR1_EM20_Msk                  (0x1UL << EXTI_EMR1_EM20_Pos)           /*!< 0x00100000 */
#define EXTI_EMR1_EM20                      EXTI_EMR1_EM20_Msk                      /*!< Event Mask on line 20 */
#define EXTI_EMR1_EM21_Pos                  (21UL)
#define EXTI_EMR1_EM21_Msk                  (0x1UL << EXTI_EMR1_EM21_Pos)           /*!< 0x00200000 */
#define EXTI_EMR1_EM21                      EXTI_EMR1_EM21_Msk                      /*!< Event Mask on line 21 */
#define EXTI_EMR1_EM22_Pos                  (22UL)
#define EXTI_EMR1_EM22_Msk                  (0x1UL << EXTI_EMR1_EM22_Pos)           /*!< 0x00400000 */
#define EXTI_EMR1_EM22                      EXTI_EMR1_EM22_Msk                      /*!< Event Mask on line 22 */

/******************************************************************************/
/*                                                                            */
/*                 Flexible Datarate Controller Area Network                  */
/*                                                                            */
/******************************************************************************/
/*!<FDCAN control and status registers */
/*****************  Bit definition for FDCAN_CREL register  *******************/
#define FDCAN_CREL_DAY_Pos                  (0UL)
#define FDCAN_CREL_DAY_Msk                  (0xFFUL << FDCAN_CREL_DAY_Pos)          /*!< 0x000000FF */
#define FDCAN_CREL_DAY                      FDCAN_CREL_DAY_Msk                      /*!<Timestamp Day                           */
#define FDCAN_CREL_MON_Pos                  (8UL)
#define FDCAN_CREL_MON_Msk                  (0xFFUL << FDCAN_CREL_MON_Pos)          /*!< 0x0000FF00 */
#define FDCAN_CREL_MON                      FDCAN_CREL_MON_Msk                      /*!<Timestamp Month                         */
#define FDCAN_CREL_YEAR_Pos                 (16UL)
#define FDCAN_CREL_YEAR_Msk                 (0xFUL << FDCAN_CREL_YEAR_Pos)          /*!< 0x000F0000 */
#define FDCAN_CREL_YEAR                     FDCAN_CREL_YEAR_Msk                     /*!<Timestamp Year                          */
#define FDCAN_CREL_SUBSTEP_Pos              (20UL)
#define FDCAN_CREL_SUBSTEP_Msk              (0xFUL << FDCAN_CREL_SUBSTEP_Pos)       /*!< 0x00F00000 */
#define FDCAN_CREL_SUBSTEP                  FDCAN_CREL_SUBSTEP_Msk                  /*!<Sub-step of Core release                */
#define FDCAN_CREL_STEP_Pos                 (24UL)
#define FDCAN_CREL_STEP_Msk                 (0xFUL << FDCAN_CREL_STEP_Pos)          /*!< 0x0F000000 */
#define FDCAN_CREL_STEP                     FDCAN_CREL_STEP_Msk                     /*!<Step of Core release                    */
#define FDCAN_CREL_REL_Pos                  (28UL)
#define FDCAN_CREL_REL_Msk                  (0xFUL << FDCAN_CREL_REL_Pos)           /*!< 0xF0000000 */
#define FDCAN_CREL_REL                      FDCAN_CREL_REL_Msk                      /*!<Core release                            */

/*****************  Bit definition for FDCAN_ENDN register  *******************/
#define FDCAN_ENDN_ETV_Pos                  (0UL)
#define FDCAN_ENDN_ETV_Msk                  (0xFFFFFFFFUL << FDCAN_ENDN_ETV_Pos)    /*!< 0xFFFFFFFF */
#define FDCAN_ENDN_ETV                      FDCAN_ENDN_ETV_Msk                      /*!<Endianness Test Value                    */

/*****************  Bit definition for FDCAN_DBTP register  *******************/
#define FDCAN_DBTP_DSJW_Pos                 (0UL)
#define FDCAN_DBTP_DSJW_Msk                 (0xFUL << FDCAN_DBTP_DSJW_Pos)          /*!< 0x0000000F */
#define FDCAN_DBTP_DSJW                     FDCAN_DBTP_DSJW_Msk                     /*!<Synchronization Jump Width              */
#define FDCAN_DBTP_DTSEG2_Pos               (4UL)
#define FDCAN_DBTP_DTSEG2_Msk               (0xFUL << FDCAN_DBTP_DTSEG2_Pos)        /*!< 0x000000F0 */
#define FDCAN_DBTP_DTSEG2                   FDCAN_DBTP_DTSEG2_Msk                   /*!<Data time segment after sample point    */
#define FDCAN_DBTP_DTSEG1_Pos               (8UL)
#define FDCAN_DBTP_DTSEG1_Msk               (0x1FUL << FDCAN_DBTP_DTSEG1_Pos)       /*!< 0x00001F00 */
#define FDCAN_DBTP_DTSEG1                   FDCAN_DBTP_DTSEG1_Msk                   /*!<Data time segment before sample point   */
#define FDCAN_DBTP_DBRP_Pos                 (16UL)
#define FDCAN_DBTP_DBRP_Msk                 (0x1FUL << FDCAN_DBTP_DBRP_Pos)         /*!< 0x001F0000 */
#define FDCAN_DBTP_DBRP                     FDCAN_DBTP_DBRP_Msk                     /*!<Data BIt Rate Prescaler                 */
#define FDCAN_DBTP_TDC_Pos                  (23UL)
#define FDCAN_DBTP_TDC_Msk                  (0x1UL << FDCAN_DBTP_TDC_Pos)           /*!< 0x00800000 */
#define FDCAN_DBTP_TDC                      FDCAN_DBTP_TDC_Msk                      /*!<Transceiver Delay Compensation          */

/*****************  Bit definition for FDCAN_TEST register  *******************/
#define FDCAN_TEST_LBCK_Pos                 (4UL)
#define FDCAN_TEST_LBCK_Msk                 (0x1UL << FDCAN_TEST_LBCK_Pos)          /*!< 0x00000010 */
#define FDCAN_TEST_LBCK                     FDCAN_TEST_LBCK_Msk                     /*!<Loop Back mode                           */
#define FDCAN_TEST_TX_Pos                   (5UL)
#define FDCAN_TEST_TX_Msk                   (0x3UL << FDCAN_TEST_TX_Pos)            /*!< 0x00000060 */
#define FDCAN_TEST_TX                       FDCAN_TEST_TX_Msk                       /*!<Control of Transmit Pin                  */
#define FDCAN_TEST_RX_Pos                   (7UL)
#define FDCAN_TEST_RX_Msk                   (0x1UL << FDCAN_TEST_RX_Pos)            /*!< 0x00000080 */
#define FDCAN_TEST_RX                       FDCAN_TEST_RX_Msk                       /*!<Receive Pin                              */

/*****************  Bit definition for FDCAN_RWD register  ********************/
#define FDCAN_RWD_WDC_Pos                   (0UL)
#define FDCAN_RWD_WDC_Msk                   (0xFFUL << FDCAN_RWD_WDC_Pos)           /*!< 0x000000FF */
#define FDCAN_RWD_WDC                       FDCAN_RWD_WDC_Msk                       /*!<Watchdog configuration                   */
#define FDCAN_RWD_WDV_Pos                   (8UL)
#define FDCAN_RWD_WDV_Msk                   (0xFFUL << FDCAN_RWD_WDV_Pos)           /*!< 0x0000FF00 */
#define FDCAN_RWD_WDV                       FDCAN_RWD_WDV_Msk                       /*!<Watchdog value                           */

/*****************  Bit definition for FDCAN_CCCR register  ********************/
#define FDCAN_CCCR_INIT_Pos                 (0UL)
#define FDCAN_CCCR_INIT_Msk                 (0x1UL << FDCAN_CCCR_INIT_Pos)          /*!< 0x00000001 */
#define FDCAN_CCCR_INIT                     FDCAN_CCCR_INIT_Msk                     /*!<Initialization                           */
#define FDCAN_CCCR_CCE_Pos                  (1UL)
#define FDCAN_CCCR_CCE_Msk                  (0x1UL << FDCAN_CCCR_CCE_Pos)           /*!< 0x00000002 */
#define FDCAN_CCCR_CCE                      FDCAN_CCCR_CCE_Msk                      /*!<Configuration Change Enable              */
#define FDCAN_CCCR_ASM_Pos                  (2UL)
#define FDCAN_CCCR_ASM_Msk                  (0x1UL << FDCAN_CCCR_ASM_Pos)           /*!< 0x00000004 */
#define FDCAN_CCCR_ASM                      FDCAN_CCCR_ASM_Msk                      /*!<ASM Restricted Operation Mode            */
#define FDCAN_CCCR_CSA_Pos                  (3UL)
#define FDCAN_CCCR_CSA_Msk                  (0x1UL << FDCAN_CCCR_CSA_Pos)           /*!< 0x00000008 */
#define FDCAN_CCCR_CSA                      FDCAN_CCCR_CSA_Msk                      /*!<Clock Stop Acknowledge                   */
#define FDCAN_CCCR_CSR_Pos                  (4UL)
#define FDCAN_CCCR_CSR_Msk                  (0x1UL << FDCAN_CCCR_CSR_Pos)           /*!< 0x00000010 */
#define FDCAN_CCCR_CSR                      FDCAN_CCCR_CSR_Msk                      /*!<Clock Stop Request                       */
#define FDCAN_CCCR_MON_Pos                  (5UL)
#define FDCAN_CCCR_MON_Msk                  (0x1UL << FDCAN_CCCR_MON_Pos)           /*!< 0x00000020 */
#define FDCAN_CCCR_MON                      FDCAN_CCCR_MON_Msk                      /*!<Bus Monitoring Mode                      */
#define FDCAN_CCCR_DAR_Pos                  (6UL)
#define FDCAN_CCCR_DAR_Msk                  (0x1UL << FDCAN_CCCR_DAR_Pos)           /*!< 0x00000040 */
#define FDCAN_CCCR_DAR                      FDCAN_CCCR_DAR_Msk                      /*!<Disable Automatic Retransmission         */
#define FDCAN_CCCR_TEST_Pos                 (7UL)
#define FDCAN_CCCR_TEST_Msk                 (0x1UL << FDCAN_CCCR_TEST_Pos)          /*!< 0x00000080 */
#define FDCAN_CCCR_TEST                     FDCAN_CCCR_TEST_Msk                     /*!<Test Mode Enable                         */
#define FDCAN_CCCR_FDOE_Pos                 (8UL)
#define FDCAN_CCCR_FDOE_Msk                 (0x1UL << FDCAN_CCCR_FDOE_Pos)          /*!< 0x00000100 */
#define FDCAN_CCCR_FDOE                     FDCAN_CCCR_FDOE_Msk                     /*!<FD Operation Enable                      */
#define FDCAN_CCCR_BRSE_Pos                 (9UL)
#define FDCAN_CCCR_BRSE_Msk                 (0x1UL << FDCAN_CCCR_BRSE_Pos)          /*!< 0x00000200 */
#define FDCAN_CCCR_BRSE                     FDCAN_CCCR_BRSE_Msk                     /*!<FDCAN Bit Rate Switching                 */
#define FDCAN_CCCR_PXHD_Pos                 (12UL)
#define FDCAN_CCCR_PXHD_Msk                 (0x1UL << FDCAN_CCCR_PXHD_Pos)          /*!< 0x00001000 */
#define FDCAN_CCCR_PXHD                     FDCAN_CCCR_PXHD_Msk                     /*!<Protocol Exception Handling Disable      */
#define FDCAN_CCCR_EFBI_Pos                 (13UL)
#define FDCAN_CCCR_EFBI_Msk                 (0x1UL << FDCAN_CCCR_EFBI_Pos)          /*!< 0x00002000 */
#define FDCAN_CCCR_EFBI                     FDCAN_CCCR_EFBI_Msk                     /*!<Edge Filtering during Bus Integration    */
#define FDCAN_CCCR_TXP_Pos                  (14UL)
#define FDCAN_CCCR_TXP_Msk                  (0x1UL << FDCAN_CCCR_TXP_Pos)           /*!< 0x00004000 */
#define FDCAN_CCCR_TXP                      FDCAN_CCCR_TXP_Msk                      /*!<Two CAN bit times Pause                  */
#define FDCAN_CCCR_NISO_Pos                 (15UL)
#define FDCAN_CCCR_NISO_Msk                 (0x1UL << FDCAN_CCCR_NISO_Pos)          /*!< 0x00008000 */
#define FDCAN_CCCR_NISO                     FDCAN_CCCR_NISO_Msk                     /*!<Non ISO Operation                        */

/*****************  Bit definition for FDCAN_NBTP register  ******************* */
#define FDCAN_NBTP_NTSEG2_Pos               (0UL)
#define FDCAN_NBTP_NTSEG2_Msk               (0x7FUL << FDCAN_NBTP_NTSEG2_Pos)       /*!< 0x0000007F */
#define FDCAN_NBTP_NTSEG2                   FDCAN_NBTP_NTSEG2_Msk                   /*!<Nominal Time segment after sample point  */
#define FDCAN_NBTP_NTSEG1_Pos               (8UL)
#define FDCAN_NBTP_NTSEG1_Msk               (0xFFUL << FDCAN_NBTP_NTSEG1_Pos)       /*!< 0x0000FF00 */
#define FDCAN_NBTP_NTSEG1                   FDCAN_NBTP_NTSEG1_Msk                   /*!<Nominal Time segment before sample point */
#define FDCAN_NBTP_NBRP_Pos                 (16UL)
#define FDCAN_NBTP_NBRP_Msk                 (0x1FFUL << FDCAN_NBTP_NBRP_Pos)        /*!< 0x01FF0000 */
#define FDCAN_NBTP_NBRP                     FDCAN_NBTP_NBRP_Msk                     /*!<Bit Rate Prescaler                       */
#define FDCAN_NBTP_NSJW_Pos                 (25UL)
#define FDCAN_NBTP_NSJW_Msk                 (0x7FUL << FDCAN_NBTP_NSJW_Pos)         /*!< 0xFE000000 */
#define FDCAN_NBTP_NSJW                     FDCAN_NBTP_NSJW_Msk                     /*!<Nominal (Re)Synchronization Jump Width   */

/*****************  Bit definition for FDCAN_TSCC register  ********************/
#define FDCAN_TSCC_TSS_Pos                  (0UL)
#define FDCAN_TSCC_TSS_Msk                  (0x3UL << FDCAN_TSCC_TSS_Pos)           /*!< 0x00000003 */
#define FDCAN_TSCC_TSS                      FDCAN_TSCC_TSS_Msk                      /*!<Timestamp Select                         */
#define FDCAN_TSCC_TCP_Pos                  (16UL)
#define FDCAN_TSCC_TCP_Msk                  (0xFUL << FDCAN_TSCC_TCP_Pos)           /*!< 0x000F0000 */
#define FDCAN_TSCC_TCP                      FDCAN_TSCC_TCP_Msk                      /*!<Timestamp Counter Prescaler              */

/*****************  Bit definition for FDCAN_TSCV register  ********************/
#define FDCAN_TSCV_TSC_Pos                  (0UL)
#define FDCAN_TSCV_TSC_Msk                  (0xFFFFUL << FDCAN_TSCV_TSC_Pos)        /*!< 0x0000FFFF */
#define FDCAN_TSCV_TSC                      FDCAN_TSCV_TSC_Msk                      /*!<Timestamp Counter                        */

/*****************  Bit definition for FDCAN_TOCC register  ********************/
#define FDCAN_TOCC_ETOC_Pos                 (0UL)
#define FDCAN_TOCC_ETOC_Msk                 (0x1UL << FDCAN_TOCC_ETOC_Pos)          /*!< 0x00000001 */
#define FDCAN_TOCC_ETOC                     FDCAN_TOCC_ETOC_Msk                     /*!<Enable Timeout Counter                   */
#define FDCAN_TOCC_TOS_Pos                  (1UL)
#define FDCAN_TOCC_TOS_Msk                  (0x3UL << FDCAN_TOCC_TOS_Pos)           /*!< 0x00000006 */
#define FDCAN_TOCC_TOS                      FDCAN_TOCC_TOS_Msk                      /*!<Timeout Select                           */
#define FDCAN_TOCC_TOP_Pos                  (16UL)
#define FDCAN_TOCC_TOP_Msk                  (0xFFFFUL << FDCAN_TOCC_TOP_Pos)        /*!< 0xFFFF0000 */
#define FDCAN_TOCC_TOP                      FDCAN_TOCC_TOP_Msk                      /*!<Timeout Period                           */

/*****************  Bit definition for FDCAN_TOCV register  ******************* */
#define FDCAN_TOCV_TOC_Pos                  (0UL)
#define FDCAN_TOCV_TOC_Msk                  (0xFFFFUL << FDCAN_TOCV_TOC_Pos)        /*!< 0x0000FFFF */
#define FDCAN_TOCV_TOC                      FDCAN_TOCV_TOC_Msk                      /*!<Timeout Counter                          */

/*****************  Bit definition for FDCAN_ECR register  ******************** */
#define FDCAN_ECR_TEC_Pos                   (0UL)
#define FDCAN_ECR_TEC_Msk                   (0xFFUL << FDCAN_ECR_TEC_Pos)           /*!< 0x000000FF */
#define FDCAN_ECR_TEC                       FDCAN_ECR_TEC_Msk                       /*!<Transmit Error Counter                   */
#define FDCAN_ECR_REC_Pos                   (8UL)
#define FDCAN_ECR_REC_Msk                   (0x7FUL << FDCAN_ECR_REC_Pos)           /*!< 0x00007F00 */
#define FDCAN_ECR_REC                       FDCAN_ECR_REC_Msk                       /*!<Receive Error Counter                    */
#define FDCAN_ECR_RP_Pos                    (15UL)
#define FDCAN_ECR_RP_Msk                    (0x1UL << FDCAN_ECR_RP_Pos)             /*!< 0x00008000 */
#define FDCAN_ECR_RP                        FDCAN_ECR_RP_Msk                        /*!<Receive Error Passive                    */
#define FDCAN_ECR_CEL_Pos                   (16UL)
#define FDCAN_ECR_CEL_Msk                   (0xFFUL << FDCAN_ECR_CEL_Pos)           /*!< 0x00FF0000 */
#define FDCAN_ECR_CEL                       FDCAN_ECR_CEL_Msk                       /*!<CAN Error Logging                        */

/*****************  Bit definition for FDCAN_PSR register  ******************** */
#define FDCAN_PSR_LEC_Pos                   (0UL)
#define FDCAN_PSR_LEC_Msk                   (0x7UL << FDCAN_PSR_LEC_Pos)            /*!< 0x00000007 */
#define FDCAN_PSR_LEC                       FDCAN_PSR_LEC_Msk                       /*!<Last Error Code                          */
#define FDCAN_PSR_ACT_Pos                   (3UL)
#define FDCAN_PSR_ACT_Msk                   (0x3UL << FDCAN_PSR_ACT_Pos)            /*!< 0x00000018 */
#define FDCAN_PSR_ACT                       FDCAN_PSR_ACT_Msk                       /*!<Activity                                 */
#define FDCAN_PSR_EP_Pos                    (5UL)
#define FDCAN_PSR_EP_Msk                    (0x1UL << FDCAN_PSR_EP_Pos)             /*!< 0x00000020 */
#define FDCAN_PSR_EP                        FDCAN_PSR_EP_Msk                        /*!<Error Passive                            */
#define FDCAN_PSR_EW_Pos                    (6UL)
#define FDCAN_PSR_EW_Msk                    (0x1UL << FDCAN_PSR_EW_Pos)             /*!< 0x00000040 */
#define FDCAN_PSR_EW                        FDCAN_PSR_EW_Msk                        /*!<Warning Status                           */
#define FDCAN_PSR_BO_Pos                    (7UL)
#define FDCAN_PSR_BO_Msk                    (0x1UL << FDCAN_PSR_BO_Pos)             /*!< 0x00000080 */
#define FDCAN_PSR_BO                        FDCAN_PSR_BO_Msk                        /*!<Bus_Off Status                           */
#define FDCAN_PSR_DLEC_Pos                  (8UL)
#define FDCAN_PSR_DLEC_Msk                  (0x7UL << FDCAN_PSR_DLEC_Pos)           /*!< 0x00000700 */
#define FDCAN_PSR_DLEC                      FDCAN_PSR_DLEC_Msk                      /*!<Data Last Error Code                     */
#define FDCAN_PSR_RESI_Pos                  (11UL)
#define FDCAN_PSR_RESI_Msk                  (0x1UL << FDCAN_PSR_RESI_Pos)           /*!< 0x00000800 */
#define FDCAN_PSR_RESI                      FDCAN_PSR_RESI_Msk                      /*!<ESI flag of last received FDCAN Message  */
#define FDCAN_PSR_RBRS_Pos                  (12UL)
#define FDCAN_PSR_RBRS_Msk                  (0x1UL << FDCAN_PSR_RBRS_Pos)           /*!< 0x00001000 */
#define FDCAN_PSR_RBRS                      FDCAN_PSR_RBRS_Msk                      /*!<BRS flag of last received FDCAN Message  */
#define FDCAN_PSR_REDL_Pos                  (13UL)
#define FDCAN_PSR_REDL_Msk                  (0x1UL << FDCAN_PSR_REDL_Pos)           /*!< 0x00002000 */
#define FDCAN_PSR_REDL                      FDCAN_PSR_REDL_Msk                      /*!<Received FDCAN Message                   */
#define FDCAN_PSR_PXE_Pos                   (14UL)
#define FDCAN_PSR_PXE_Msk                   (0x1UL << FDCAN_PSR_PXE_Pos)            /*!< 0x00004000 */
#define FDCAN_PSR_PXE                       FDCAN_PSR_PXE_Msk                       /*!<Protocol Exception Event                 */
#define FDCAN_PSR_TDCV_Pos                  (16UL)
#define FDCAN_PSR_TDCV_Msk                  (0x7FUL << FDCAN_PSR_TDCV_Pos)          /*!< 0x007F0000 */
#define FDCAN_PSR_TDCV                      FDCAN_PSR_TDCV_Msk                      /*!<Transmitter Delay Compensation Value     */

/*****************  Bit definition for FDCAN_TDCR register  ******************* */
#define FDCAN_TDCR_TDCF_Pos                 (0UL)
#define FDCAN_TDCR_TDCF_Msk                 (0x7FUL << FDCAN_TDCR_TDCF_Pos)         /*!< 0x0000007F */
#define FDCAN_TDCR_TDCF                     FDCAN_TDCR_TDCF_Msk                     /*!<Transmitter Delay Compensation Filter    */
#define FDCAN_TDCR_TDCO_Pos                 (8UL)
#define FDCAN_TDCR_TDCO_Msk                 (0x7FUL << FDCAN_TDCR_TDCO_Pos)         /*!< 0x00007F00 */
#define FDCAN_TDCR_TDCO                     FDCAN_TDCR_TDCO_Msk                     /*!<Transmitter Delay Compensation Offset    */

/*****************  Bit definition for FDCAN_IR register  ********************* */
#define FDCAN_IR_RF0N_Pos                   (0UL)
#define FDCAN_IR_RF0N_Msk                   (0x1UL << FDCAN_IR_RF0N_Pos)            /*!< 0x00000001 */
#define FDCAN_IR_RF0N                       FDCAN_IR_RF0N_Msk                       /*!<Rx FIFO 0 New Message                    */
#define FDCAN_IR_RF0F_Pos                   (1UL)
#define FDCAN_IR_RF0F_Msk                   (0x1UL << FDCAN_IR_RF0F_Pos)            /*!< 0x00000002 */
#define FDCAN_IR_RF0F                       FDCAN_IR_RF0F_Msk                       /*!<Rx FIFO 0 Full                           */
#define FDCAN_IR_RF0L_Pos                   (2UL)
#define FDCAN_IR_RF0L_Msk                   (0x1UL << FDCAN_IR_RF0L_Pos)            /*!< 0x00000004 */
#define FDCAN_IR_RF0L                       FDCAN_IR_RF0L_Msk                       /*!<Rx FIFO 0 Message Lost                   */
#define FDCAN_IR_RF1N_Pos                   (3UL)
#define FDCAN_IR_RF1N_Msk                   (0x1UL << FDCAN_IR_RF1N_Pos)            /*!< 0x00000008 */
#define FDCAN_IR_RF1N                       FDCAN_IR_RF1N_Msk                       /*!<Rx FIFO 1 New Message                    */
#define FDCAN_IR_RF1F_Pos                   (4UL)
#define FDCAN_IR_RF1F_Msk                   (0x1UL << FDCAN_IR_RF1F_Pos)            /*!< 0x00000010 */
#define FDCAN_IR_RF1F                       FDCAN_IR_RF1F_Msk                       /*!<Rx FIFO 1 Full                           */
#define FDCAN_IR_RF1L_Pos                   (5UL)
#define FDCAN_IR_RF1L_Msk                   (0x1UL << FDCAN_IR_RF1L_Pos)            /*!< 0x00000020 */
#define FDCAN_IR_RF1L                       FDCAN_IR_RF1L_Msk                       /*!<Rx FIFO 1 Message Lost                   */
#define FDCAN_IR_HPM_Pos                    (6UL)
#define FDCAN_IR_HPM_Msk                    (0x1UL << FDCAN_IR_HPM_Pos)             /*!< 0x00000040 */
#define FDCAN_IR_HPM                        FDCAN_IR_HPM_Msk                        /*!<High Priority Message                    */
#define FDCAN_IR_TC_Pos                     (7UL)
#define FDCAN_IR_TC_Msk                     (0x1UL << FDCAN_IR_TC_Pos)              /*!< 0x00000080 */
#define FDCAN_IR_TC                         FDCAN_IR_TC_Msk                         /*!<Transmission Completed                   */
#define FDCAN_IR_TCF_Pos                    (8UL)
#define FDCAN_IR_TCF_Msk                    (0x1UL << FDCAN_IR_TCF_Pos)             /*!< 0x00000100 */
#define FDCAN_IR_TCF                        FDCAN_IR_TCF_Msk                        /*!<Transmission Cancellation Finished       */
#define FDCAN_IR_TFE_Pos                    (9UL)
#define FDCAN_IR_TFE_Msk                    (0x1UL << FDCAN_IR_TFE_Pos)             /*!< 0x00000200 */
#define FDCAN_IR_TFE                        FDCAN_IR_TFE_Msk                        /*!<Tx FIFO Empty                            */
#define FDCAN_IR_TEFN_Pos                   (10UL)
#define FDCAN_IR_TEFN_Msk                   (0x1UL << FDCAN_IR_TEFN_Pos)            /*!< 0x00000400 */
#define FDCAN_IR_TEFN                       FDCAN_IR_TEFN_Msk                       /*!<Tx Event FIFO New Entry                  */
#define FDCAN_IR_TEFF_Pos                   (11UL)
#define FDCAN_IR_TEFF_Msk                   (0x1UL << FDCAN_IR_TEFF_Pos)            /*!< 0x00000800 */
#define FDCAN_IR_TEFF                       FDCAN_IR_TEFF_Msk                       /*!<Tx Event FIFO Full                       */
#define FDCAN_IR_TEFL_Pos                   (12UL)
#define FDCAN_IR_TEFL_Msk                   (0x1UL << FDCAN_IR_TEFL_Pos)            /*!< 0x00001000 */
#define FDCAN_IR_TEFL                       FDCAN_IR_TEFL_Msk                       /*!<Tx Event FIFO Element Lost               */
#define FDCAN_IR_TSW_Pos                    (13UL)
#define FDCAN_IR_TSW_Msk                    (0x1UL << FDCAN_IR_TSW_Pos)             /*!< 0x00002000 */
#define FDCAN_IR_TSW                        FDCAN_IR_TSW_Msk                        /*!<Timestamp Wraparound                     */
#define FDCAN_IR_MRAF_Pos                   (14UL)
#define FDCAN_IR_MRAF_Msk                   (0x1UL << FDCAN_IR_MRAF_Pos)            /*!< 0x00004000 */
#define FDCAN_IR_MRAF                       FDCAN_IR_MRAF_Msk                       /*!<Message RAM Access Failure               */
#define FDCAN_IR_TOO_Pos                    (15UL)
#define FDCAN_IR_TOO_Msk                    (0x1UL << FDCAN_IR_TOO_Pos)             /*!< 0x00008000 */
#define FDCAN_IR_TOO                        FDCAN_IR_TOO_Msk                        /*!<Timeout Occurred                         */
#define FDCAN_IR_ELO_Pos                    (16UL)
#define FDCAN_IR_ELO_Msk                    (0x1UL << FDCAN_IR_ELO_Pos)             /*!< 0x00010000 */
#define FDCAN_IR_ELO                        FDCAN_IR_ELO_Msk                        /*!<Error Logging Overflow                   */
#define FDCAN_IR_EP_Pos                     (17UL)
#define FDCAN_IR_EP_Msk                     (0x1UL << FDCAN_IR_EP_Pos)              /*!< 0x00020000 */
#define FDCAN_IR_EP                         FDCAN_IR_EP_Msk                         /*!<Error Passive                            */
#define FDCAN_IR_EW_Pos                     (18UL)
#define FDCAN_IR_EW_Msk                     (0x1UL << FDCAN_IR_EW_Pos)              /*!< 0x00040000 */
#define FDCAN_IR_EW                         FDCAN_IR_EW_Msk                         /*!<Warning Status                           */
#define FDCAN_IR_BO_Pos                     (19UL)
#define FDCAN_IR_BO_Msk                     (0x1UL << FDCAN_IR_BO_Pos)              /*!< 0x00080000 */
#define FDCAN_IR_BO                         FDCAN_IR_BO_Msk                         /*!<Bus_Off Status                           */
#define FDCAN_IR_WDI_Pos                    (20UL)
#define FDCAN_IR_WDI_Msk                    (0x1UL << FDCAN_IR_WDI_Pos)             /*!< 0x00100000 */
#define FDCAN_IR_WDI                        FDCAN_IR_WDI_Msk                        /*!<Watchdog Interrupt                       */
#define FDCAN_IR_PEA_Pos                    (21UL)
#define FDCAN_IR_PEA_Msk                    (0x1UL << FDCAN_IR_PEA_Pos)             /*!< 0x00200000 */
#define FDCAN_IR_PEA                        FDCAN_IR_PEA_Msk                        /*!<Protocol Error in Arbitration Phase      */
#define FDCAN_IR_PED_Pos                    (22UL)
#define FDCAN_IR_PED_Msk                    (0x1UL << FDCAN_IR_PED_Pos)             /*!< 0x00400000 */
#define FDCAN_IR_PED                        FDCAN_IR_PED_Msk                        /*!<Protocol Error in Data Phase             */
#define FDCAN_IR_ARA_Pos                    (23UL)
#define FDCAN_IR_ARA_Msk                    (0x1UL << FDCAN_IR_ARA_Pos)             /*!< 0x00800000 */
#define FDCAN_IR_ARA                        FDCAN_IR_ARA_Msk                        /*!<Access to Reserved Address               */

/*****************  Bit definition for FDCAN_IE register  ********************* */
#define FDCAN_IE_RF0NE_Pos                  (0UL)
#define FDCAN_IE_RF0NE_Msk                  (0x1UL << FDCAN_IE_RF0NE_Pos)           /*!< 0x00000001 */
#define FDCAN_IE_RF0NE                      FDCAN_IE_RF0NE_Msk                      /*!<Rx FIFO 0 New Message Enable             */
#define FDCAN_IE_RF0FE_Pos                  (1UL)
#define FDCAN_IE_RF0FE_Msk                  (0x1UL << FDCAN_IE_RF0FE_Pos)           /*!< 0x00000002 */
#define FDCAN_IE_RF0FE                      FDCAN_IE_RF0FE_Msk                      /*!<Rx FIFO 0 Full Enable                    */
#define FDCAN_IE_RF0LE_Pos                  (2UL)
#define FDCAN_IE_RF0LE_Msk                  (0x1UL << FDCAN_IE_RF0LE_Pos)           /*!< 0x00000004 */
#define FDCAN_IE_RF0LE                      FDCAN_IE_RF0LE_Msk                      /*!<Rx FIFO 0 Message Lost Enable            */
#define FDCAN_IE_RF1NE_Pos                  (3UL)
#define FDCAN_IE_RF1NE_Msk                  (0x1UL << FDCAN_IE_RF1NE_Pos)           /*!< 0x00000008 */
#define FDCAN_IE_RF1NE                      FDCAN_IE_RF1NE_Msk                      /*!<Rx FIFO 1 New Message Enable             */
#define FDCAN_IE_RF1FE_Pos                  (4UL)
#define FDCAN_IE_RF1FE_Msk                  (0x1UL << FDCAN_IE_RF1FE_Pos)           /*!< 0x00000010 */
#define FDCAN_IE_RF1FE                      FDCAN_IE_RF1FE_Msk                      /*!<Rx FIFO 1 Full Enable                    */
#define FDCAN_IE_RF1LE_Pos                  (5UL)
#define FDCAN_IE_RF1LE_Msk                  (0x1UL << FDCAN_IE_RF1LE_Pos)           /*!< 0x00000020 */
#define FDCAN_IE_RF1LE                      FDCAN_IE_RF1LE_Msk                      /*!<Rx FIFO 1 Message Lost Enable            */
#define FDCAN_IE_HPME_Pos                   (6UL)
#define FDCAN_IE_HPME_Msk                   (0x1UL << FDCAN_IE_HPME_Pos)            /*!< 0x00000040 */
#define FDCAN_IE_HPME                       FDCAN_IE_HPME_Msk                       /*!<High Priority Message Enable             */
#define FDCAN_IE_TCE_Pos                    (7UL)
#define FDCAN_IE_TCE_Msk                    (0x1UL << FDCAN_IE_TCE_Pos)             /*!< 0x00000080 */
#define FDCAN_IE_TCE                        FDCAN_IE_TCE_Msk                        /*!<Transmission Completed Enable            */
#define FDCAN_IE_TCFE_Pos                   (8UL)
#define FDCAN_IE_TCFE_Msk                   (0x1UL << FDCAN_IE_TCFE_Pos)            /*!< 0x00000100 */
#define FDCAN_IE_TCFE                       FDCAN_IE_TCFE_Msk                       /*!<Transmission Cancellation Finished Enable*/
#define FDCAN_IE_TFEE_Pos                   (9UL)
#define FDCAN_IE_TFEE_Msk                   (0x1UL << FDCAN_IE_TFEE_Pos)            /*!< 0x00000200 */
#define FDCAN_IE_TFEE                       FDCAN_IE_TFEE_Msk                       /*!<Tx FIFO Empty Enable                     */
#define FDCAN_IE_TEFNE_Pos                  (10UL)
#define FDCAN_IE_TEFNE_Msk                  (0x1UL << FDCAN_IE_TEFNE_Pos)           /*!< 0x00000400 */
#define FDCAN_IE_TEFNE                      FDCAN_IE_TEFNE_Msk                      /*!<Tx Event FIFO New Entry Enable           */
#define FDCAN_IE_TEFFE_Pos                  (11UL)
#define FDCAN_IE_TEFFE_Msk                  (0x1UL << FDCAN_IE_TEFFE_Pos)           /*!< 0x00000800 */
#define FDCAN_IE_TEFFE                      FDCAN_IE_TEFFE_Msk                      /*!<Tx Event FIFO Full Enable                */
#define FDCAN_IE_TEFLE_Pos                  (12UL)
#define FDCAN_IE_TEFLE_Msk                  (0x1UL << FDCAN_IE_TEFLE_Pos)           /*!< 0x00001000 */
#define FDCAN_IE_TEFLE                      FDCAN_IE_TEFLE_Msk                      /*!<Tx Event FIFO Element Lost Enable        */
#define FDCAN_IE_TSWE_Pos                   (13UL)
#define FDCAN_IE_TSWE_Msk                   (0x1UL << FDCAN_IE_TSWE_Pos)            /*!< 0x00002000 */
#define FDCAN_IE_TSWE                       FDCAN_IE_TSWE_Msk                       /*!<Timestamp Wraparound Enable              */
#define FDCAN_IE_MRAFE_Pos                  (14UL)
#define FDCAN_IE_MRAFE_Msk                  (0x1UL << FDCAN_IE_MRAFE_Pos)           /*!< 0x00004000 */
#define FDCAN_IE_MRAFE                      FDCAN_IE_MRAFE_Msk                      /*!<Message RAM Access Failure Enable        */
#define FDCAN_IE_TOOE_Pos                   (15UL)
#define FDCAN_IE_TOOE_Msk                   (0x1UL << FDCAN_IE_TOOE_Pos)            /*!< 0x00008000 */
#define FDCAN_IE_TOOE                       FDCAN_IE_TOOE_Msk                       /*!<Timeout Occurred Enable                  */
#define FDCAN_IE_ELOE_Pos                   (16UL)
#define FDCAN_IE_ELOE_Msk                   (0x1UL << FDCAN_IE_ELOE_Pos)            /*!< 0x00010000 */
#define FDCAN_IE_ELOE                       FDCAN_IE_ELOE_Msk                       /*!<Error Logging Overflow Enable            */
#define FDCAN_IE_EPE_Pos                    (17UL)
#define FDCAN_IE_EPE_Msk                    (0x1UL << FDCAN_IE_EPE_Pos)             /*!< 0x00020000 */
#define FDCAN_IE_EPE                        FDCAN_IE_EPE_Msk                        /*!<Error Passive Enable                     */
#define FDCAN_IE_EWE_Pos                    (18UL)
#define FDCAN_IE_EWE_Msk                    (0x1UL << FDCAN_IE_EWE_Pos)             /*!< 0x00040000 */
#define FDCAN_IE_EWE                        FDCAN_IE_EWE_Msk                        /*!<Warning Status Enable                    */
#define FDCAN_IE_BOE_Pos                    (19UL)
#define FDCAN_IE_BOE_Msk                    (0x1UL << FDCAN_IE_BOE_Pos)             /*!< 0x00080000 */
#define FDCAN_IE_BOE                        FDCAN_IE_BOE_Msk                        /*!<Bus_Off Status Enable                    */
#define FDCAN_IE_WDIE_Pos                   (20UL)
#define FDCAN_IE_WDIE_Msk                   (0x1UL << FDCAN_IE_WDIE_Pos)            /*!< 0x00100000 */
#define FDCAN_IE_WDIE                       FDCAN_IE_WDIE_Msk                       /*!<Watchdog Interrupt Enable                */
#define FDCAN_IE_PEAE_Pos                   (21UL)
#define FDCAN_IE_PEAE_Msk                   (0x1UL << FDCAN_IE_PEAE_Pos)            /*!< 0x00200000 */
#define FDCAN_IE_PEAE                       FDCAN_IE_PEAE_Msk                       /*!<Protocol Error in Arbitration Phase Enable*/
#define FDCAN_IE_PEDE_Pos                   (22UL)
#define FDCAN_IE_PEDE_Msk                   (0x1UL << FDCAN_IE_PEDE_Pos)            /*!< 0x00400000 */
#define FDCAN_IE_PEDE                       FDCAN_IE_PEDE_Msk                       /*!<Protocol Error in Data Phase Enable      */
#define FDCAN_IE_ARAE_Pos                   (23UL)
#define FDCAN_IE_ARAE_Msk                   (0x1UL << FDCAN_IE_ARAE_Pos)            /*!< 0x00800000 */
#define FDCAN_IE_ARAE                       FDCAN_IE_ARAE_Msk                       /*!<Access to Reserved Address Enable        */

/*****************  Bit definition for FDCAN_ILS register  ******************** **/
#define FDCAN_ILS_RXFIFO0_Pos               (0UL)
#define FDCAN_ILS_RXFIFO0_Msk               (0x1UL << FDCAN_ILS_RXFIFO0_Pos)        /*!< 0x00000001 */
#define FDCAN_ILS_RXFIFO0                   FDCAN_ILS_RXFIFO0_Msk                   /*!<Rx FIFO 0 Message Lost
                                                                                        Rx FIFO 0 is Full
                                                                                        Rx FIFO 0 Has New Message                */
#define FDCAN_ILS_RXFIFO1_Pos               (1UL)
#define FDCAN_ILS_RXFIFO1_Msk               (0x1UL << FDCAN_ILS_RXFIFO1_Pos)        /*!< 0x00000002 */
#define FDCAN_ILS_RXFIFO1                   FDCAN_ILS_RXFIFO1_Msk                   /*!<Rx FIFO 1 Message Lost
                                                                                        Rx FIFO 1 is Full
                                                                                        Rx FIFO 1 Has New Message                */
#define FDCAN_ILS_SMSG_Pos                  (2UL)
#define FDCAN_ILS_SMSG_Msk                  (0x1UL << FDCAN_ILS_SMSG_Pos)           /*!< 0x00000004 */
#define FDCAN_ILS_SMSG                      FDCAN_ILS_SMSG_Msk                      /*!<Transmission Cancellation Finished
                                                                                        Transmission Completed
                                                                                        High Priority Message                    */
#define FDCAN_ILS_TFERR_Pos                 (3UL)
#define FDCAN_ILS_TFERR_Msk                 (0x1UL << FDCAN_ILS_TFERR_Pos)          /*!< 0x00000008 */
#define FDCAN_ILS_TFERR                     FDCAN_ILS_TFERR_Msk                     /*!<Tx Event FIFO Element Lost
                                                                                        Tx Event FIFO Full
                                                                                        Tx Event FIFO New Entry
                                                                                        Tx FIFO Empty Interrupt Line             */
#define FDCAN_ILS_MISC_Pos                  (4UL)
#define FDCAN_ILS_MISC_Msk                  (0x1UL << FDCAN_ILS_MISC_Pos)           /*!< 0x00000010 */
#define FDCAN_ILS_MISC                      FDCAN_ILS_MISC_Msk                      /*!<Timeout Occurred
                                                                                        Message RAM Access Failure
                                                                                        Timestamp Wraparound                    */
#define FDCAN_ILS_BERR_Pos                  (5UL)
#define FDCAN_ILS_BERR_Msk                  (0x1UL << FDCAN_ILS_BERR_Pos)           /*!< 0x00000020 */
#define FDCAN_ILS_BERR                      FDCAN_ILS_BERR_Msk                      /*!<Error Passive
                                                                                        Error Logging Overflow                   */
#define FDCAN_ILS_PERR_Pos                  (6UL)
#define FDCAN_ILS_PERR_Msk                  (0x1UL << FDCAN_ILS_PERR_Pos)           /*!< 0x00000040 */
#define FDCAN_ILS_PERR                      FDCAN_ILS_PERR_Msk                      /*!<Access to Reserved Address Line
                                                                                        Protocol Error in Data Phase Line
                                                                                        Protocol Error in Arbitration Phase Line
                                                                                        Watchdog Interrupt Line
                                                                                        Bus_Off Status
                                                                                        Warning Status                           */

/*****************  Bit definition for FDCAN_ILE register  ******************** **/
#define FDCAN_ILE_EINT0_Pos                 (0UL)
#define FDCAN_ILE_EINT0_Msk                 (0x1UL << FDCAN_ILE_EINT0_Pos)          /*!< 0x00000001 */
#define FDCAN_ILE_EINT0                     FDCAN_ILE_EINT0_Msk                     /*!<Enable Interrupt Line 0                  */
#define FDCAN_ILE_EINT1_Pos                 (1UL)
#define FDCAN_ILE_EINT1_Msk                 (0x1UL << FDCAN_ILE_EINT1_Pos)          /*!< 0x00000002 */
#define FDCAN_ILE_EINT1                     FDCAN_ILE_EINT1_Msk                     /*!<Enable Interrupt Line 1                  */

/*****************  Bit definition for FDCAN_RXGFC register  ****************** **/
#define FDCAN_RXGFC_RRFE_Pos                (0UL)
#define FDCAN_RXGFC_RRFE_Msk                (0x1UL << FDCAN_RXGFC_RRFE_Pos)         /*!< 0x00000001 */
#define FDCAN_RXGFC_RRFE                    FDCAN_RXGFC_RRFE_Msk                    /*!<Reject Remote Frames Extended            */
#define FDCAN_RXGFC_RRFS_Pos                (1UL)
#define FDCAN_RXGFC_RRFS_Msk                (0x1UL << FDCAN_RXGFC_RRFS_Pos)         /*!< 0x00000002 */
#define FDCAN_RXGFC_RRFS                    FDCAN_RXGFC_RRFS_Msk                    /*!<Reject Remote Frames Standard            */
#define FDCAN_RXGFC_ANFE_Pos                (2UL)
#define FDCAN_RXGFC_ANFE_Msk                (0x3UL << FDCAN_RXGFC_ANFE_Pos)         /*!< 0x0000000C */
#define FDCAN_RXGFC_ANFE                    FDCAN_RXGFC_ANFE_Msk                    /*!<Accept Non-matching Frames Extended      */
#define FDCAN_RXGFC_ANFS_Pos                (4UL)
#define FDCAN_RXGFC_ANFS_Msk                (0x3UL << FDCAN_RXGFC_ANFS_Pos)         /*!< 0x00000030 */
#define FDCAN_RXGFC_ANFS                    FDCAN_RXGFC_ANFS_Msk                    /*!<Accept Non-matching Frames Standard      */
#define FDCAN_RXGFC_F1OM_Pos                (8UL)
#define FDCAN_RXGFC_F1OM_Msk                (0x1UL << FDCAN_RXGFC_F1OM_Pos)         /*!< 0x00000100 */
#define FDCAN_RXGFC_F1OM                    FDCAN_RXGFC_F1OM_Msk                    /*!<FIFO 1 operation mode                    */
#define FDCAN_RXGFC_F0OM_Pos                (9UL)
#define FDCAN_RXGFC_F0OM_Msk                (0x1UL << FDCAN_RXGFC_F0OM_Pos)         /*!< 0x00000200 */
#define FDCAN_RXGFC_F0OM                    FDCAN_RXGFC_F0OM_Msk                    /*!<FIFO 0 operation mode                    */
#define FDCAN_RXGFC_LSS_Pos                 (16UL)
#define FDCAN_RXGFC_LSS_Msk                 (0x1FUL << FDCAN_RXGFC_LSS_Pos)         /*!< 0x001F0000 */
#define FDCAN_RXGFC_LSS                     FDCAN_RXGFC_LSS_Msk                     /*!<List Size Standard                       */
#define FDCAN_RXGFC_LSE_Pos                 (24UL)
#define FDCAN_RXGFC_LSE_Msk                 (0xFUL << FDCAN_RXGFC_LSE_Pos)          /*!< 0x0F000000 */
#define FDCAN_RXGFC_LSE                     FDCAN_RXGFC_LSE_Msk                     /*!<List Size Extended                       */

/*****************  Bit definition for FDCAN_XIDAM register  ****************** **/
#define FDCAN_XIDAM_EIDM_Pos                (0UL)
#define FDCAN_XIDAM_EIDM_Msk                (0x1FFFFFFFUL << FDCAN_XIDAM_EIDM_Pos)  /*!< 0x1FFFFFFF */
#define FDCAN_XIDAM_EIDM                    FDCAN_XIDAM_EIDM_Msk                    /*!<Extended ID Mask                         */

/*****************  Bit definition for FDCAN_HPMS register  ******************* **/
#define FDCAN_HPMS_BIDX_Pos                 (0UL)
#define FDCAN_HPMS_BIDX_Msk                 (0x7UL << FDCAN_HPMS_BIDX_Pos)          /*!< 0x00000007 */
#define FDCAN_HPMS_BIDX                     FDCAN_HPMS_BIDX_Msk                     /*!<Buffer Index                             */
#define FDCAN_HPMS_MSI_Pos                  (6UL)
#define FDCAN_HPMS_MSI_Msk                  (0x3UL << FDCAN_HPMS_MSI_Pos)           /*!< 0x000000C0 */
#define FDCAN_HPMS_MSI                      FDCAN_HPMS_MSI_Msk                      /*!<Message Storage Indicator                */
#define FDCAN_HPMS_FIDX_Pos                 (8UL)
#define FDCAN_HPMS_FIDX_Msk                 (0x1FUL << FDCAN_HPMS_FIDX_Pos)         /*!< 0x00001F00 */
#define FDCAN_HPMS_FIDX                     FDCAN_HPMS_FIDX_Msk                     /*!<Filter Index                             */
#define FDCAN_HPMS_FLST_Pos                 (15UL)
#define FDCAN_HPMS_FLST_Msk                 (0x1UL << FDCAN_HPMS_FLST_Pos)          /*!< 0x00008000 */
#define FDCAN_HPMS_FLST                     FDCAN_HPMS_FLST_Msk                     /*!<Filter List                              */

/*****************  Bit definition for FDCAN_RXF0S register  ****************** **/
#define FDCAN_RXF0S_F0FL_Pos                (0UL)
#define FDCAN_RXF0S_F0FL_Msk                (0xFUL << FDCAN_RXF0S_F0FL_Pos)         /*!< 0x0000000F */
#define FDCAN_RXF0S_F0FL                    FDCAN_RXF0S_F0FL_Msk                    /*!<Rx FIFO 0 Fill Level                     */
#define FDCAN_RXF0S_F0GI_Pos                (8UL)
#define FDCAN_RXF0S_F0GI_Msk                (0x3UL << FDCAN_RXF0S_F0GI_Pos)         /*!< 0x00000300 */
#define FDCAN_RXF0S_F0GI                    FDCAN_RXF0S_F0GI_Msk                    /*!<Rx FIFO 0 Get Index                      */
#define FDCAN_RXF0S_F0PI_Pos                (16UL)
#define FDCAN_RXF0S_F0PI_Msk                (0x3UL << FDCAN_RXF0S_F0PI_Pos)         /*!< 0x00030000 */
#define FDCAN_RXF0S_F0PI                    FDCAN_RXF0S_F0PI_Msk                    /*!<Rx FIFO 0 Put Index                      */
#define FDCAN_RXF0S_F0F_Pos                 (24UL)
#define FDCAN_RXF0S_F0F_Msk                 (0x1UL << FDCAN_RXF0S_F0F_Pos)          /*!< 0x01000000 */
#define FDCAN_RXF0S_F0F                     FDCAN_RXF0S_F0F_Msk                     /*!<Rx FIFO 0 Full                           */
#define FDCAN_RXF0S_RF0L_Pos                (25UL)
#define FDCAN_RXF0S_RF0L_Msk                (0x1UL << FDCAN_RXF0S_RF0L_Pos)         /*!< 0x02000000 */
#define FDCAN_RXF0S_RF0L                    FDCAN_RXF0S_RF0L_Msk                    /*!<Rx FIFO 0 Message Lost                   */

/*****************  Bit definition for FDCAN_RXF0A register  ****************** **/
#define FDCAN_RXF0A_F0AI_Pos                (0UL)
#define FDCAN_RXF0A_F0AI_Msk                (0x7UL << FDCAN_RXF0A_F0AI_Pos)         /*!< 0x00000007 */
#define FDCAN_RXF0A_F0AI                    FDCAN_RXF0A_F0AI_Msk                    /*!<Rx FIFO 0 Acknowledge Index              */

/*****************  Bit definition for FDCAN_RXF1S register  ****************** **/
#define FDCAN_RXF1S_F1FL_Pos                (0UL)
#define FDCAN_RXF1S_F1FL_Msk                (0xFUL << FDCAN_RXF1S_F1FL_Pos)         /*!< 0x0000000F */
#define FDCAN_RXF1S_F1FL                    FDCAN_RXF1S_F1FL_Msk                    /*!<Rx FIFO 1 Fill Level                     */
#define FDCAN_RXF1S_F1GI_Pos                (8UL)
#define FDCAN_RXF1S_F1GI_Msk                (0x3UL << FDCAN_RXF1S_F1GI_Pos)         /*!< 0x00000300 */
#define FDCAN_RXF1S_F1GI                    FDCAN_RXF1S_F1GI_Msk                    /*!<Rx FIFO 1 Get Index                      */
#define FDCAN_RXF1S_F1PI_Pos                (16UL)
#define FDCAN_RXF1S_F1PI_Msk                (0x3UL << FDCAN_RXF1S_F1PI_Pos)         /*!< 0x00030000 */
#define FDCAN_RXF1S_F1PI                    FDCAN_RXF1S_F1PI_Msk                    /*!<Rx FIFO 1 Put Index                      */
#define FDCAN_RXF1S_F1F_Pos                 (24UL)
#define FDCAN_RXF1S_F1F_Msk                 (0x1UL << FDCAN_RXF1S_F1F_Pos)          /*!< 0x01000000 */
#define FDCAN_RXF1S_F1F                     FDCAN_RXF1S_F1F_Msk                     /*!<Rx FIFO 1 Full                           */
#define FDCAN_RXF1S_RF1L_Pos                (25UL)
#define FDCAN_RXF1S_RF1L_Msk                (0x1UL << FDCAN_RXF1S_RF1L_Pos)         /*!< 0x02000000 */
#define FDCAN_RXF1S_RF1L                    FDCAN_RXF1S_RF1L_Msk                    /*!<Rx FIFO 1 Message Lost                   */

/*****************  Bit definition for FDCAN_RXF1A register  ****************** **/
#define FDCAN_RXF1A_F1AI_Pos                (0UL)
#define FDCAN_RXF1A_F1AI_Msk                (0x7UL << FDCAN_RXF1A_F1AI_Pos)         /*!< 0x00000007 */
#define FDCAN_RXF1A_F1AI                    FDCAN_RXF1A_F1AI_Msk                    /*!<Rx FIFO 1 Acknowledge Index              */

/*****************  Bit definition for FDCAN_TXBC register  ******************* **/
#define FDCAN_TXBC_TFQM_Pos                 (24UL)
#define FDCAN_TXBC_TFQM_Msk                 (0x1UL << FDCAN_TXBC_TFQM_Pos)          /*!< 0x01000000 */
#define FDCAN_TXBC_TFQM                     FDCAN_TXBC_TFQM_Msk                     /*!<Tx FIFO/Queue Mode                       */

/*****************  Bit definition for FDCAN_TXFQS register  ****************** ***/
#define FDCAN_TXFQS_TFFL_Pos                (0UL)
#define FDCAN_TXFQS_TFFL_Msk                (0x7UL << FDCAN_TXFQS_TFFL_Pos)         /*!< 0x00000007 */
#define FDCAN_TXFQS_TFFL                    FDCAN_TXFQS_TFFL_Msk                    /*!<Tx FIFO Free Level                       */
#define FDCAN_TXFQS_TFGI_Pos                (8UL)
#define FDCAN_TXFQS_TFGI_Msk                (0x3UL << FDCAN_TXFQS_TFGI_Pos)         /*!< 0x00000300 */
#define FDCAN_TXFQS_TFGI                    FDCAN_TXFQS_TFGI_Msk                    /*!<Tx FIFO Get Index                        */
#define FDCAN_TXFQS_TFQPI_Pos               (16UL)
#define FDCAN_TXFQS_TFQPI_Msk               (0x3UL << FDCAN_TXFQS_TFQPI_Pos)        /*!< 0x00030000 */
#define FDCAN_TXFQS_TFQPI                   FDCAN_TXFQS_TFQPI_Msk                   /*!<Tx FIFO/Queue Put Index                  */
#define FDCAN_TXFQS_TFQF_Pos                (21UL)
#define FDCAN_TXFQS_TFQF_Msk                (0x1UL << FDCAN_TXFQS_TFQF_Pos)         /*!< 0x00200000 */
#define FDCAN_TXFQS_TFQF                    FDCAN_TXFQS_TFQF_Msk                    /*!<Tx FIFO/Queue Full                       */

/*****************  Bit definition for FDCAN_TXBRP register  ****************** ***/
#define FDCAN_TXBRP_TRP_Pos                 (0UL)
#define FDCAN_TXBRP_TRP_Msk                 (0x7UL << FDCAN_TXBRP_TRP_Pos)          /*!< 0x00000007 */
#define FDCAN_TXBRP_TRP                     FDCAN_TXBRP_TRP_Msk                     /*!<Transmission Request Pending             */

/*****************  Bit definition for FDCAN_TXBAR register  ****************** ***/
#define FDCAN_TXBAR_AR_Pos                  (0UL)
#define FDCAN_TXBAR_AR_Msk                  (0x7UL << FDCAN_TXBAR_AR_Pos)           /*!< 0x00000007 */
#define FDCAN_TXBAR_AR                      FDCAN_TXBAR_AR_Msk                      /*!<Add Request                              */

/*****************  Bit definition for FDCAN_TXBCR register  ****************** ***/
#define FDCAN_TXBCR_CR_Pos                  (0UL)
#define FDCAN_TXBCR_CR_Msk                  (0x7UL << FDCAN_TXBCR_CR_Pos)           /*!< 0x00000007 */
#define FDCAN_TXBCR_CR                      FDCAN_TXBCR_CR_Msk                      /*!<Cancellation Request                     */

/*****************  Bit definition for FDCAN_TXBTO register  ****************** ***/
#define FDCAN_TXBTO_TO_Pos                  (0UL)
#define FDCAN_TXBTO_TO_Msk                  (0x7UL << FDCAN_TXBTO_TO_Pos)           /*!< 0x00000007 */
#define FDCAN_TXBTO_TO                      FDCAN_TXBTO_TO_Msk                      /*!<Transmission Occurred                    */

/*****************  Bit definition for FDCAN_TXBCF register  ****************** ***/
#define FDCAN_TXBCF_CF_Pos                  (0UL)
#define FDCAN_TXBCF_CF_Msk                  (0x7UL << FDCAN_TXBCF_CF_Pos)           /*!< 0x00000007 */
#define FDCAN_TXBCF_CF                      FDCAN_TXBCF_CF_Msk                      /*!<Cancellation Finished                    */

/*****************  Bit definition for FDCAN_TXBTIE register  ***************** ***/
#define FDCAN_TXBTIE_TIE_Pos                (0UL)
#define FDCAN_TXBTIE_TIE_Msk                (0x7UL << FDCAN_TXBTIE_TIE_Pos)         /*!< 0x00000007 */
#define FDCAN_TXBTIE_TIE                    FDCAN_TXBTIE_TIE_Msk                    /*!<Transmission Interrupt Enable            */

/*****************  Bit definition for FDCAN_ TXBCIE register  **************** ***/
#define FDCAN_TXBCIE_CFIE_Pos               (0UL)
#define FDCAN_TXBCIE_CFIE_Msk               (0x7UL << FDCAN_TXBCIE_CFIE_Pos)        /*!< 0x00000007 */
#define FDCAN_TXBCIE_CFIE                   FDCAN_TXBCIE_CFIE_Msk                   /*!<Cancellation Finished Interrupt Enable   */

/*****************  Bit definition for FDCAN_TXEFS register  ****************** ***/
#define FDCAN_TXEFS_EFFL_Pos                (0UL)
#define FDCAN_TXEFS_EFFL_Msk                (0x7UL << FDCAN_TXEFS_EFFL_Pos)         /*!< 0x00000007 */
#define FDCAN_TXEFS_EFFL                    FDCAN_TXEFS_EFFL_Msk                    /*!<Event FIFO Fill Level                    */
#define FDCAN_TXEFS_EFGI_Pos                (8UL)
#define FDCAN_TXEFS_EFGI_Msk                (0x3UL << FDCAN_TXEFS_EFGI_Pos)         /*!< 0x00000300 */
#define FDCAN_TXEFS_EFGI                    FDCAN_TXEFS_EFGI_Msk                    /*!<Event FIFO Get Index                     */
#define FDCAN_TXEFS_EFPI_Pos                (16UL)
#define FDCAN_TXEFS_EFPI_Msk                (0x3UL << FDCAN_TXEFS_EFPI_Pos)         /*!< 0x00030000 */
#define FDCAN_TXEFS_EFPI                    FDCAN_TXEFS_EFPI_Msk                    /*!<Event FIFO Put Index                     */
#define FDCAN_TXEFS_EFF_Pos                 (24UL)
#define FDCAN_TXEFS_EFF_Msk                 (0x1UL << FDCAN_TXEFS_EFF_Pos)          /*!< 0x01000000 */
#define FDCAN_TXEFS_EFF                     FDCAN_TXEFS_EFF_Msk                     /*!<Event FIFO Full                          */
#define FDCAN_TXEFS_TEFL_Pos                (25UL)
#define FDCAN_TXEFS_TEFL_Msk                (0x1UL << FDCAN_TXEFS_TEFL_Pos)         /*!< 0x02000000 */
#define FDCAN_TXEFS_TEFL                    FDCAN_TXEFS_TEFL_Msk                    /*!<Tx Event FIFO Element Lost               */

/*****************  Bit definition for FDCAN_TXEFA register  ****************** ***/
#define FDCAN_TXEFA_EFAI_Pos                (0UL)
#define FDCAN_TXEFA_EFAI_Msk                (0x3UL << FDCAN_TXEFA_EFAI_Pos)         /*!< 0x00000003 */
#define FDCAN_TXEFA_EFAI                    FDCAN_TXEFA_EFAI_Msk                    /*!<Event FIFO Acknowledge Index             */

/*!<FDCAN config registers */
/*****************  Bit definition for FDCAN_CKDIV register  ****************** ***/
#define FDCAN_CKDIV_PDIV_Pos                (0UL)
#define FDCAN_CKDIV_PDIV_Msk                (0xFUL << FDCAN_CKDIV_PDIV_Pos)         /*!< 0x0000000F */
#define FDCAN_CKDIV_PDIV                    FDCAN_CKDIV_PDIV_Msk                    /*!<Input Clock Divider                      */

/******************************************************************************/
/*                                                                            */
/*                                    FLASH                                   */
/*                                                                            */
/******************************************************************************/
/*******************  Bits definition for FLASH_ACR register  *****************/
#define FLASH_ACR_LATENCY_Pos               (0UL)
#define FLASH_ACR_LATENCY_Msk               (0xFUL << FLASH_ACR_LATENCY_Pos)        /*!< 0x0000000F */
#define FLASH_ACR_LATENCY                   FLASH_ACR_LATENCY_Msk                   /*!< Latency    */
#define FLASH_ACR_LATENCY_0                 (0x1UL << FLASH_ACR_LATENCY_Pos)        /*!< 0x00000001 */
#define FLASH_ACR_LATENCY_1                 (0x2UL << FLASH_ACR_LATENCY_Pos)        /*!< 0x00000002 */
#define FLASH_ACR_LATENCY_2                 (0x4UL << FLASH_ACR_LATENCY_Pos)        /*!< 0x00000004 */
#define FLASH_ACR_LATENCY_3                 (0x8UL << FLASH_ACR_LATENCY_Pos)        /*!< 0x00000008 */
#define FLASH_ACR_PRFTEN_Pos                (8UL)
#define FLASH_ACR_PRFTEN_Msk                (0x1UL << FLASH_ACR_PRFTEN_Pos)         /*!< 0x00000100 */
#define FLASH_ACR_PRFTEN                    FLASH_ACR_PRFTEN_Msk                    /*!< Prefetch enable */
#define FLASH_ACR_LPM_Pos                   (11UL)
#define FLASH_ACR_LPM_Msk                   (0x1UL << FLASH_ACR_LPM_Pos)            /*!< 0x00000800 */
#define FLASH_ACR_LPM                       FLASH_ACR_LPM_Msk                       /*!< Low-Power read mode */
#define FLASH_ACR_PDREQ1_Pos                (12UL)
#define FLASH_ACR_PDREQ1_Msk                (0x1UL << FLASH_ACR_PDREQ1_Pos)         /*!< 0x00001000 */
#define FLASH_ACR_PDREQ1                    FLASH_ACR_PDREQ1_Msk                    /*!< Bank 1 power-down mode request */
#define FLASH_ACR_PDREQ2_Pos                (13UL)
#define FLASH_ACR_PDREQ2_Msk                (0x1UL << FLASH_ACR_PDREQ2_Pos)         /*!< 0x00002000 */
#define FLASH_ACR_PDREQ2                    FLASH_ACR_PDREQ2_Msk                    /*!< Bank 2 power-down mode request */
#define FLASH_ACR_SLEEP_PD_Pos              (14UL)
#define FLASH_ACR_SLEEP_PD_Msk              (0x1UL << FLASH_ACR_SLEEP_PD_Pos)       /*!< 0x00004000 */
#define FLASH_ACR_SLEEP_PD                  FLASH_ACR_SLEEP_PD_Msk                  /*!< Flash power-down mode during sleep */

/******************  Bits definition for FLASH_KEYR register  *****************/
#define FLASH_KEYR_KEY_Pos                  (0UL)
#define FLASH_KEYR_KEY_Msk                  (0xFFFFFFFFUL << FLASH_KEYR_KEY_Pos)    /*!< 0xFFFFFFFFF */
#define FLASH_KEYR_KEY                      FLASH_KEYR_KEY_Msk                      /*!< Flash non-secure key */

/*****************  Bits definition for FLASH_SKEYR register  *****************/
#define FLASH_SKEYR_KEY_Pos                 (0UL)
#define FLASH_SKEYR_KEY_Msk                 (0xFFFFFFFFUL << FLASH_SKEYR_KEY_Pos)   /*!< 0xFFFFFFFFF */
#define FLASH_SKEYR_KEY                     FLASH_SKEYR_KEY_Msk                     /*!< Flash secure key */

/****************  Bits definition for FLASH_OPTKEYR register  ****************/
#define FLASH_OPTKEYR_KEY_Pos               (0UL)
#define FLASH_OPTKEYR_KEY_Msk               (0xFFFFFFFFUL << FLASH_OPTKEYR_KEY_Pos) /*!< 0xFFFFFFFFF */
#define FLASH_OPTKEYR_KEY                   FLASH_OPTKEYR_KEY_Msk                   /*!< Option byte key */

/****************  Bits definition for FLASH_PDKEY1R register  ****************/
#define FLASH_PDKEY1R_KEY1_Pos              (0UL)
#define FLASH_PDKEY1R_KEY1_Msk              (0xFFFFFFFFUL << FLASH_PDKEY1R_KEY1_Pos) /*!< 0xFFFFFFFFF */
#define FLASH_PDKEY1R_KEY1                  FLASH_PDKEY1R_KEY1_Msk                   /*!< Bank 1 power-down key */

/****************  Bits definition for FLASH_PDKEY2R register  ****************/
#define FLASH_PDKEY2R_KEY2_Pos              (0UL)
#define FLASH_PDKEY2R_KEY2_Msk              (0xFFFFFFFFUL << FLASH_PDKEY2R_KEY2_Pos) /*!< 0xFFFFFFFFF */
#define FLASH_PDKEY2R_KEY2                  FLASH_PDKEY2R_KEY2_Msk                   /*!< Bank 2 power-down key */

/*******************  Bits definition for FLASH_SR register  ******************/
#define FLASH_SR_EOP_Pos                    (0UL)
#define FLASH_SR_EOP_Msk                    (0x1UL << FLASH_SR_EOP_Pos)             /*!< 0x00000001 */
#define FLASH_SR_EOP                        FLASH_SR_EOP_Msk                        /*!< Non-secure end of operation */
#define FLASH_SR_OPERR_Pos                  (1UL)
#define FLASH_SR_OPERR_Msk                  (0x1UL << FLASH_SR_OPERR_Pos)           /*!< 0x00000002 */
#define FLASH_SR_OPERR                      FLASH_SR_OPERR_Msk                      /*!< Non-secure operation error */
#define FLASH_SR_PROGERR_Pos                (3UL)
#define FLASH_SR_PROGERR_Msk                (0x1UL << FLASH_SR_PROGERR_Pos)         /*!< 0x00000008 */
#define FLASH_SR_PROGERR                    FLASH_SR_PROGERR_Msk                    /*!< Non-secure programming error */
#define FLASH_SR_WRPERR_Pos                 (4UL)
#define FLASH_SR_WRPERR_Msk                 (0x1UL << FLASH_SR_WRPERR_Pos)          /*!< 0x00000010 */
#define FLASH_SR_WRPERR                     FLASH_SR_WRPERR_Msk                     /*!< Non-secure write protection error */
#define FLASH_SR_PGAERR_Pos                 (5UL)
#define FLASH_SR_PGAERR_Msk                 (0x1UL << FLASH_SR_PGAERR_Pos)          /*!< 0x00000020 */
#define FLASH_SR_PGAERR                     FLASH_SR_PGAERR_Msk                     /*!< Non-secure programming alignment error */
#define FLASH_SR_SIZERR_Pos                 (6UL)
#define FLASH_SR_SIZERR_Msk                 (0x1UL << FLASH_SR_SIZERR_Pos)          /*!< 0x00000040 */
#define FLASH_SR_SIZERR                     FLASH_SR_SIZERR_Msk                     /*!< Non-secure size error */
#define FLASH_SR_PGSERR_Pos                 (7UL)
#define FLASH_SR_PGSERR_Msk                 (0x1UL << FLASH_SR_PGSERR_Pos)          /*!< 0x00000080 */
#define FLASH_SR_PGSERR                     FLASH_SR_PGSERR_Msk                     /*!< Non-secure programming sequence error */
#define FLASH_SR_OPTWERR_Pos                (13UL)
#define FLASH_SR_OPTWERR_Msk                (0x1UL << FLASH_SR_OPTWERR_Pos)         /*!< 0x00002000 */
#define FLASH_SR_OPTWERR                    FLASH_SR_OPTWERR_Msk                    /*!< Option write error */
#define FLASH_SR_BSY_Pos                    (16UL)
#define FLASH_SR_BSY_Msk                    (0x1UL << FLASH_SR_BSY_Pos)             /*!< 0x00010000 */
#define FLASH_SR_BSY                        FLASH_SR_BSY_Msk                        /*!< Non-secure busy */
#define FLASH_SR_WDW_Pos                    (17UL)
#define FLASH_SR_WDW_Msk                    (0x1UL << FLASH_SR_WDW_Pos)             /*!< 0x00020000 */
#define FLASH_SR_WDW                        FLASH_SR_WDW_Msk                        /*!< Non-secure wait data to write */
#define FLASH_SR_OEM1LOCK_Pos               (18UL)
#define FLASH_SR_OEM1LOCK_Msk               (0x1UL << FLASH_SR_OEM1LOCK_Pos)        /*!< 0x00040000 */
#define FLASH_SR_OEM1LOCK                   FLASH_SR_OEM1LOCK_Msk                   /*!< OEM1 lock */
#define FLASH_SR_OEM2LOCK_Pos               (19UL)
#define FLASH_SR_OEM2LOCK_Msk               (0x1UL << FLASH_SR_OEM2LOCK_Pos)        /*!< 0x00080000 */
#define FLASH_SR_OEM2LOCK                   FLASH_SR_OEM2LOCK_Msk                   /*!< OEM2 lock */
#define FLASH_SR_PD1_Pos                    (20UL)
#define FLASH_SR_PD1_Msk                    (0x1UL << FLASH_SR_PD1_Pos)             /*!< 0x00100000 */
#define FLASH_SR_PD1                        FLASH_SR_PD1_Msk                        /*!< Bank 1 in power-down mode */
#define FLASH_SR_PD2_Pos                    (21UL)
#define FLASH_SR_PD2_Msk                    (0x1UL << FLASH_SR_PD2_Pos)             /*!< 0x00200000 */
#define FLASH_SR_PD2                        FLASH_SR_PD2_Msk                        /*!< Bank 2 in power-down mode */

/*******************  Bits definition for FLASH_SSR register  *****************/
#define FLASH_SSR_EOP_Pos                   (0UL)
#define FLASH_SSR_EOP_Msk                   (0x1UL << FLASH_SSR_EOP_Pos)            /*!< 0x00000001 */
#define FLASH_SSR_EOP                       FLASH_SSR_EOP_Msk                       /*!< Secure end of operation */
#define FLASH_SSR_OPERR_Pos                 (1UL)
#define FLASH_SSR_OPERR_Msk                 (0x1UL << FLASH_SSR_OPERR_Pos)          /*!< 0x00000002 */
#define FLASH_SSR_OPERR                     FLASH_SSR_OPERR_Msk                     /*!< Secure operation error */
#define FLASH_SSR_PROGERR_Pos               (3UL)
#define FLASH_SSR_PROGERR_Msk               (0x1UL << FLASH_SSR_PROGERR_Pos)        /*!< 0x00000008 */
#define FLASH_SSR_PROGERR                   FLASH_SSR_PROGERR_Msk                   /*!< Secure programming error */
#define FLASH_SSR_WRPERR_Pos                (4UL)
#define FLASH_SSR_WRPERR_Msk                (0x1UL << FLASH_SSR_WRPERR_Pos)         /*!< 0x00000010 */
#define FLASH_SSR_WRPERR                    FLASH_SSR_WRPERR_Msk                    /*!< Secure write protection error */
#define FLASH_SSR_PGAERR_Pos                (5UL)
#define FLASH_SSR_PGAERR_Msk                (0x1UL << FLASH_SSR_PGAERR_Pos)         /*!< 0x00000020 */
#define FLASH_SSR_PGAERR                    FLASH_SSR_PGAERR_Msk                    /*!< Secure programming alignment error */
#define FLASH_SSR_SIZERR_Pos                (6UL)
#define FLASH_SSR_SIZERR_Msk                (0x1UL << FLASH_SSR_SIZERR_Pos)         /*!< 0x00000040 */
#define FLASH_SSR_SIZERR                    FLASH_SSR_SIZERR_Msk                    /*!< Secure size error */
#define FLASH_SSR_PGSERR_Pos                (7UL)
#define FLASH_SSR_PGSERR_Msk                (0x1UL << FLASH_SSR_PGSERR_Pos)         /*!< 0x00000080 */
#define FLASH_SSR_PGSERR                    FLASH_SSR_PGSERR_Msk                    /*!< Secure programming sequence error */
#define FLASH_SSR_BSY_Pos                   (16UL)
#define FLASH_SSR_BSY_Msk                   (0x1UL << FLASH_SSR_BSY_Pos)            /*!< 0x00010000 */
#define FLASH_SSR_BSY                       FLASH_SSR_BSY_Msk                       /*!< Secure busy */
#define FLASH_SSR_WDW_Pos                   (17UL)
#define FLASH_SSR_WDW_Msk                   (0x1UL << FLASH_SSR_WDW_Pos)            /*!< 0x00020000 */
#define FLASH_SSR_WDW                       FLASH_SSR_WDW_Msk                       /*!< Secure wait data to write */

/*******************  Bits definition for FLASH_CR register  ******************/
#define FLASH_CR_PG_Pos                     (0UL)
#define FLASH_CR_PG_Msk                     (0x1UL << FLASH_CR_PG_Pos)              /*!< 0x00000001 */
#define FLASH_CR_PG                         FLASH_CR_PG_Msk                         /*!< Non-secure programming */
#define FLASH_CR_PER_Pos                    (1UL)
#define FLASH_CR_PER_Msk                    (0x1UL << FLASH_CR_PER_Pos)             /*!< 0x00000002 */
#define FLASH_CR_PER                        FLASH_CR_PER_Msk                        /*!< Non-secure page erase */
#define FLASH_CR_MER1_Pos                   (2UL)
#define FLASH_CR_MER1_Msk                   (0x1UL << FLASH_CR_MER1_Pos)            /*!< 0x00000004 */
#define FLASH_CR_MER1                       FLASH_CR_MER1_Msk                       /*!< Non-secure bank 1 mass erase */
#define FLASH_CR_PNB_Pos                    (3UL)
#define FLASH_CR_PNB_Msk                    (0x7FUL << FLASH_CR_PNB_Pos)            /*!< 0x000003F8 */
#define FLASH_CR_PNB                        FLASH_CR_PNB_Msk                        /*!< Non-secure page number selection */
#define FLASH_CR_BKER_Pos                   (11UL)
#define FLASH_CR_BKER_Msk                   (0x1UL << FLASH_CR_BKER_Pos)            /*!< 0x00000800 */
#define FLASH_CR_BKER                       FLASH_CR_BKER_Msk                       /*!< Non-secure bank selection for page erase */
#define FLASH_CR_BWR_Pos                    (14UL)
#define FLASH_CR_BWR_Msk                    (0x1UL << FLASH_CR_BWR_Pos)             /*!< 0x00004000 */
#define FLASH_CR_BWR                        FLASH_CR_BWR_Msk                        /*!< Non-secure burst write programming mode */
#define FLASH_CR_MER2_Pos                   (15UL)
#define FLASH_CR_MER2_Msk                   (0x1UL << FLASH_CR_MER2_Pos)            /*!< 0x00008000 */
#define FLASH_CR_MER2                       FLASH_CR_MER2_Msk                       /*!< Non-secure bank 2 mass erase */
#define FLASH_CR_STRT_Pos                   (16UL)
#define FLASH_CR_STRT_Msk                   (0x1UL << FLASH_CR_STRT_Pos)            /*!< 0x00010000 */
#define FLASH_CR_STRT                       FLASH_CR_STRT_Msk                       /*!< Non-secure start */
#define FLASH_CR_OPTSTRT_Pos                (17UL)
#define FLASH_CR_OPTSTRT_Msk                (0x1UL << FLASH_CR_OPTSTRT_Pos)         /*!< 0x00020000 */
#define FLASH_CR_OPTSTRT                    FLASH_CR_OPTSTRT_Msk                    /*!< Option modification Start */
#define FLASH_CR_EOPIE_Pos                  (24UL)
#define FLASH_CR_EOPIE_Msk                  (0x1UL << FLASH_CR_EOPIE_Pos)           /*!< 0x01000000 */
#define FLASH_CR_EOPIE                      FLASH_CR_EOPIE_Msk                      /*!< Non-secure end of operation interrupt enable */
#define FLASH_CR_ERRIE_Pos                  (25UL)
#define FLASH_CR_ERRIE_Msk                  (0x1UL << FLASH_CR_ERRIE_Pos)           /*!< 0x02000000 */
#define FLASH_CR_ERRIE                      FLASH_CR_ERRIE_Msk                      /*!< Non-secure error interrupt enable */
#define FLASH_CR_OBL_LAUNCH_Pos             (27UL)
#define FLASH_CR_OBL_LAUNCH_Msk             (0x1UL << FLASH_CR_OBL_LAUNCH_Pos)      /*!< 0x08000000 */
#define FLASH_CR_OBL_LAUNCH                 FLASH_CR_OBL_LAUNCH_Msk                 /*!< Force the option byte loading */
#define FLASH_CR_OPTLOCK_Pos                (30UL)
#define FLASH_CR_OPTLOCK_Msk                (0x1UL << FLASH_CR_OPTLOCK_Pos)         /*!< 0x40000000 */
#define FLASH_CR_OPTLOCK                    FLASH_CR_OPTLOCK_Msk                    /*!< Option Lock */
#define FLASH_CR_LOCK_Pos                   (31UL)
#define FLASH_CR_LOCK_Msk                   (0x1UL << FLASH_CR_LOCK_Pos)            /*!< 0x80000000 */
#define FLASH_CR_LOCK                       FLASH_CR_LOCK_Msk                       /*!< Non-secure Lock */

/*******************  Bits definition for FLASH_SCR register  *****************/
#define FLASH_SCR_PG_Pos                    (0UL)
#define FLASH_SCR_PG_Msk                    (0x1UL << FLASH_SCR_PG_Pos)             /*!< 0x00000001 */
#define FLASH_SCR_PG                        FLASH_SCR_PG_Msk                        /*!< Secure programming */
#define FLASH_SCR_PER_Pos                   (1UL)
#define FLASH_SCR_PER_Msk                   (0x1UL << FLASH_SCR_PER_Pos)            /*!< 0x00000002 */
#define FLASH_SCR_PER                       FLASH_SCR_PER_Msk                       /*!< Secure page erase */
#define FLASH_SCR_MER1_Pos                  (2UL)
#define FLASH_SCR_MER1_Msk                  (0x1UL << FLASH_SCR_MER1_Pos)           /*!< 0x00000004 */
#define FLASH_SCR_MER1                      FLASH_SCR_MER1_Msk                      /*!< Secure bank 1 mass erase */
#define FLASH_SCR_PNB_Pos                   (3UL)
#define FLASH_SCR_PNB_Msk                   (0x7FUL << FLASH_SCR_PNB_Pos)           /*!< 0x000003F8 */
#define FLASH_SCR_PNB                       FLASH_SCR_PNB_Msk                       /*!< Secure page number selection */
#define FLASH_SCR_BKER_Pos                  (11UL)
#define FLASH_SCR_BKER_Msk                  (0x1UL << FLASH_SCR_BKER_Pos)           /*!< 0x00000800 */
#define FLASH_SCR_BKER                      FLASH_SCR_BKER_Msk                      /*!< Secure bank selection for page erase */
#define FLASH_SCR_BWR_Pos                   (14UL)
#define FLASH_SCR_BWR_Msk                   (0x1UL << FLASH_SCR_BWR_Pos)            /*!< 0x00004000 */
#define FLASH_SCR_BWR                       FLASH_SCR_BWR_Msk                       /*!< Secure burst write programming mode */
#define FLASH_SCR_MER2_Pos                  (15UL)
#define FLASH_SCR_MER2_Msk                  (0x1UL << FLASH_SCR_MER2_Pos)           /*!< 0x00008000 */
#define FLASH_SCR_MER2                      FLASH_SCR_MER2_Msk                      /*!< Secure bank 2 mass erase */
#define FLASH_SCR_STRT_Pos                  (16UL)
#define FLASH_SCR_STRT_Msk                  (0x1UL << FLASH_SCR_STRT_Pos)           /*!< 0x00010000 */
#define FLASH_SCR_STRT                      FLASH_SCR_STRT_Msk                      /*!< Secure start */
#define FLASH_SCR_EOPIE_Pos                 (24UL)
#define FLASH_SCR_EOPIE_Msk                 (0x1UL << FLASH_SCR_EOPIE_Pos)          /*!< 0x01000000 */
#define FLASH_SCR_EOPIE                     FLASH_SCR_EOPIE_Msk                     /*!< Secure end of operation interrupt enable */
#define FLASH_SCR_ERRIE_Pos                 (25UL)
#define FLASH_SCR_ERRIE_Msk                 (0x1UL << FLASH_SCR_ERRIE_Pos)          /*!< 0x02000000 */
#define FLASH_SCR_ERRIE                     FLASH_SCR_ERRIE_Msk                     /*!< Secure error interrupt enable */
#define FLASH_SCR_INV_Pos                   (29UL)
#define FLASH_SCR_INV_Msk                   (0x1UL << FLASH_SCR_INV_Pos)            /*!< 0x20000000 */
#define FLASH_SCR_INV                       FLASH_SCR_INV_Msk                       /*!< Flash security state invert */
#define FLASH_SCR_LOCK_Pos                  (31UL)
#define FLASH_SCR_LOCK_Msk                  (0x1UL << FLASH_SCR_LOCK_Pos)           /*!< 0x80000000 */
#define FLASH_SCR_LOCK                      FLASH_SCR_LOCK_Msk                      /*!< Secure lock */

/*******************  Bits definition for FLASH_ECCCR register  **************/
#define FLASH_ECCCR_ADDR_ECC_Pos            (0UL)
#define FLASH_ECCCR_ADDR_ECC_Msk            (0x7FFFFUL << FLASH_ECCCR_ADDR_ECC_Pos) /*!< 0x0007FFFF */
#define FLASH_ECCCR_ADDR_ECC                FLASH_ECCCR_ADDR_ECC_Msk                /*!< ECC fail address */
#define FLASH_ECCCR_BK_ECC_Pos              (21UL)
#define FLASH_ECCCR_BK_ECC_Msk              (0x1UL << FLASH_ECCCR_BK_ECC_Pos)       /*!< 0x00200000 */
#define FLASH_ECCCR_BK_ECC                  FLASH_ECCCR_BK_ECC_Msk                  /*!< ECC fail bank */
#define FLASH_ECCCR_SYSF_ECC_Pos            (22UL)
#define FLASH_ECCCR_SYSF_ECC_Msk            (0x1UL << FLASH_ECCCR_SYSF_ECC_Pos)     /*!< 0x00400000 */
#define FLASH_ECCCR_SYSF_ECC                FLASH_ECCCR_SYSF_ECC_Msk                /*!< System Flash ECC fail */
#define FLASH_ECCCR_ECCIE_Pos               (24UL)
#define FLASH_ECCCR_ECCIE_Msk               (0x1UL << FLASH_ECCCR_ECCIE_Pos)        /*!< 0x01000000 */
#define FLASH_ECCCR_ECCIE                   FLASH_ECCCR_ECCIE_Msk                   /*!< ECC correction interrupt enable */
#define FLASH_ECCCR_ECCC_Pos                (30UL)
#define FLASH_ECCCR_ECCC_Msk                (0x1UL << FLASH_ECCCR_ECCC_Pos)         /*!< 0x40000000 */
#define FLASH_ECCCR_ECCC                    FLASH_ECCCR_ECCC_Msk                    /*!< ECC correction */

/*******************  Bits definition for FLASH_ECCDR register  **************/
#define FLASH_ECCDR_ADDR_ECC_Pos            (0UL)
#define FLASH_ECCDR_ADDR_ECC_Msk            (0x7FFFFUL << FLASH_ECCDR_ADDR_ECC_Pos) /*!< 0x0007FFFF */
#define FLASH_ECCDR_ADDR_ECC                FLASH_ECCDR_ADDR_ECC_Msk                /*!< ECC fail address */
#define FLASH_ECCDR_BK_ECC_Pos              (21UL)
#define FLASH_ECCDR_BK_ECC_Msk              (0x1UL << FLASH_ECCDR_BK_ECC_Pos)       /*!< 0x00200000 */
#define FLASH_ECCDR_BK_ECC                  FLASH_ECCDR_BK_ECC_Msk                  /*!< ECC fail bank */
#define FLASH_ECCDR_SYSF_ECC_Pos            (22UL)
#define FLASH_ECCDR_SYSF_ECC_Msk            (0x1UL << FLASH_ECCDR_SYSF_ECC_Pos)     /*!< 0x00400000 */
#define FLASH_ECCDR_SYSF_ECC                FLASH_ECCDR_SYSF_ECC_Msk                /*!< System Flash ECC fail */
#define FLASH_ECCDR_ECCD_Pos                (31UL)
#define FLASH_ECCDR_ECCD_Msk                (0x1UL << FLASH_ECCDR_ECCD_Pos)         /*!< 0x80000000 */
#define FLASH_ECCDR_ECCD                    FLASH_ECCDR_ECCD_Msk                    /*!< ECC detection */

/*******************  Bits definition for FLASH_OPSR register  ***************/
#define FLASH_OPSR_ADDR_OP_Pos              (0UL)
#define FLASH_OPSR_ADDR_OP_Msk              (0x7FFFFUL << FLASH_OPSR_ADDR_OP_Pos)   /*!< 0x0007FFFF */
#define FLASH_OPSR_ADDR_OP                  FLASH_OPSR_ADDR_OP_Msk                  /*!< Interrupted operation address */
#define FLASH_OPSR_BK_OP_Pos                (21UL)
#define FLASH_OPSR_BK_OP_Msk                (0x1UL << FLASH_OPSR_BK_OP_Pos)         /*!< 0x00200000 */
#define FLASH_OPSR_BK_OP                    FLASH_OPSR_BK_OP_Msk                    /*!< Interrupted operation bank */
#define FLASH_OPSR_SYSF_OP_Pos              (22UL)
#define FLASH_OPSR_SYSF_OP_Msk              (0x1UL << FLASH_OPSR_SYSF_OP_Pos)       /*!< 0x00400000 */
#define FLASH_OPSR_SYSF_OP                  FLASH_OPSR_SYSF_OP_Msk                  /*!< Operation in System Flash interrupted */
#define FLASH_OPSR_CODE_OP_Pos              (29UL)
#define FLASH_OPSR_CODE_OP_Msk              (0x7UL << FLASH_OPSR_CODE_OP_Pos)       /*!< 0xE0000000 */
#define FLASH_OPSR_CODE_OP                  FLASH_OPSR_CODE_OP_Msk                  /*!< Flash operation code */
#define FLASH_OPSR_CODE_OP_0                (0x1UL << FLASH_OPSR_CODE_OP_Pos)       /*!< 0x20000000 */
#define FLASH_OPSR_CODE_OP_1                (0x2UL << FLASH_OPSR_CODE_OP_Pos)       /*!< 0x40000000 */
#define FLASH_OPSR_CODE_OP_2                (0x4UL << FLASH_OPSR_CODE_OP_Pos)       /*!< 0x80000000 */

/*******************  Bits definition for FLASH_OPTR register  ***************/
#define FLASH_OPTR_RDP_Pos                  (0UL)
#define FLASH_OPTR_RDP_Msk                  (0xFFUL << FLASH_OPTR_RDP_Pos)          /*!< 0x000000FF */
#define FLASH_OPTR_RDP                      FLASH_OPTR_RDP_Msk                      /*!< Readout protection level */
#define FLASH_OPTR_BOR_LEV_Pos              (8UL)
#define FLASH_OPTR_BOR_LEV_Msk              (0x7UL << FLASH_OPTR_BOR_LEV_Pos)       /*!< 0x00000700 */
#define FLASH_OPTR_BOR_LEV                  FLASH_OPTR_BOR_LEV_Msk                  /*!< BOR reset level */
#define FLASH_OPTR_BOR_LEV_0                (0x1UL << FLASH_OPTR_BOR_LEV_Pos)       /*!< 0x00000100 */
#define FLASH_OPTR_BOR_LEV_1                (0x2UL << FLASH_OPTR_BOR_LEV_Pos)       /*!< 0x00000200 */
#define FLASH_OPTR_BOR_LEV_2                (0x4UL << FLASH_OPTR_BOR_LEV_Pos)       /*!< 0x00000400 */
#define FLASH_OPTR_BDRST_POR_Pos            (11UL)
#define FLASH_OPTR_BDRST_POR_Msk            (0x1UL << FLASH_OPTR_BDRST_POR_Pos)     /*!< 0x00000800 */
#define FLASH_OPTR_BDRST_POR                FLASH_OPTR_BDRST_POR_Msk                /*!< Backup domain reset with power on reset */
#define FLASH_OPTR_nRST_STOP_Pos            (12UL)
#define FLASH_OPTR_nRST_STOP_Msk            (0x1UL << FLASH_OPTR_nRST_STOP_Pos)     /*!< 0x00001000 */
#define FLASH_OPTR_nRST_STOP                FLASH_OPTR_nRST_STOP_Msk                /*!< Reset generation in stop mode */
#define FLASH_OPTR_nRST_STDBY_Pos           (13UL)
#define FLASH_OPTR_nRST_STDBY_Msk           (0x1UL << FLASH_OPTR_nRST_STDBY_Pos)    /*!< 0x00002000 */
#define FLASH_OPTR_nRST_STDBY               FLASH_OPTR_nRST_STDBY_Msk               /*!< Reset generation in standby mode */
#define FLASH_OPTR_nRST_SHDW_Pos            (14UL)
#define FLASH_OPTR_nRST_SHDW_Msk            (0x1UL << FLASH_OPTR_nRST_SHDW_Pos)     /*!< 0x00004000 */
#define FLASH_OPTR_nRST_SHDW                FLASH_OPTR_nRST_SHDW_Msk                /*!< Reset generation in shutdown mode */
#define FLASH_OPTR_SRAM1_RST_Pos            (15UL)
#define FLASH_OPTR_SRAM1_RST_Msk            (0x1UL << FLASH_OPTR_SRAM1_RST_Pos)     /*!< 0x00008000 */
#define FLASH_OPTR_SRAM1_RST                FLASH_OPTR_SRAM1_RST_Msk                /*!< SRAM1 erase upon system reset */
#define FLASH_OPTR_IWDG_SW_Pos              (16UL)
#define FLASH_OPTR_IWDG_SW_Msk              (0x1UL << FLASH_OPTR_IWDG_SW_Pos)       /*!< 0x00010000 */
#define FLASH_OPTR_IWDG_SW                  FLASH_OPTR_IWDG_SW_Msk                  /*!< Independent watchdog selection */
#define FLASH_OPTR_IWDG_STOP_Pos            (17UL)
#define FLASH_OPTR_IWDG_STOP_Msk            (0x1UL << FLASH_OPTR_IWDG_STOP_Pos)     /*!< 0x00020000 */
#define FLASH_OPTR_IWDG_STOP                FLASH_OPTR_IWDG_STOP_Msk                /*!< Independent watchdog counter freeze in stop mode */
#define FLASH_OPTR_IWDG_STDBY_Pos           (18UL)
#define FLASH_OPTR_IWDG_STDBY_Msk           (0x1UL << FLASH_OPTR_IWDG_STDBY_Pos)    /*!< 0x00040000 */
#define FLASH_OPTR_IWDG_STDBY               FLASH_OPTR_IWDG_STDBY_Msk               /*!< Independent watchdog counter freeze in standby mode */
#define FLASH_OPTR_WWDG_SW_Pos              (19UL)
#define FLASH_OPTR_WWDG_SW_Msk              (0x1UL << FLASH_OPTR_WWDG_SW_Pos)       /*!< 0x00080000 */
#define FLASH_OPTR_WWDG_SW                  FLASH_OPTR_WWDG_SW_Msk                  /*!< Window watchdog selection */
#define FLASH_OPTR_SWAP_BANK_Pos            (20UL)
#define FLASH_OPTR_SWAP_BANK_Msk            (0x1UL << FLASH_OPTR_SWAP_BANK_Pos)     /*!< 0x00100000 */
#define FLASH_OPTR_SWAP_BANK                FLASH_OPTR_SWAP_BANK_Msk                /*!< Swap banks */
#define FLASH_OPTR_DUALBANK_Pos             (21UL)
#define FLASH_OPTR_DUALBANK_Msk             (0x1UL << FLASH_OPTR_DUALBANK_Pos)      /*!< 0x00200000 */
#define FLASH_OPTR_DUALBANK                 FLASH_OPTR_DUALBANK_Msk                 /*!< Dual-bank on 1Mbyte Flash memory devices */
#define FLASH_OPTR_SRAM3_PE_Pos             (23UL)
#define FLASH_OPTR_SRAM3_PE_Msk             (0x1UL << FLASH_OPTR_SRAM3_PE_Pos)      /*!< 0x00800000 */
#define FLASH_OPTR_SRAM3_PE                 FLASH_OPTR_SRAM3_PE_Msk                 /*!< SRAM3 parity check enable*/
#define FLASH_OPTR_SRAM2_PE_Pos             (24UL)
#define FLASH_OPTR_SRAM2_PE_Msk             (0x1UL << FLASH_OPTR_SRAM2_PE_Pos)      /*!< 0x01000000 */
#define FLASH_OPTR_SRAM2_PE                 FLASH_OPTR_SRAM2_PE_Msk                 /*!< SRAM2 parity check enable*/
#define FLASH_OPTR_SRAM2_RST_Pos            (25UL)
#define FLASH_OPTR_SRAM2_RST_Msk            (0x1UL << FLASH_OPTR_SRAM2_RST_Pos)     /*!< 0x02000000 */
#define FLASH_OPTR_SRAM2_RST                FLASH_OPTR_SRAM2_RST_Msk                /*!< SRAM2 erase when system reset */
#define FLASH_OPTR_nSWBOOT0_Pos             (26UL)
#define FLASH_OPTR_nSWBOOT0_Msk             (0x1UL << FLASH_OPTR_nSWBOOT0_Pos)      /*!< 0x04000000 */
#define FLASH_OPTR_nSWBOOT0                 FLASH_OPTR_nSWBOOT0_Msk                 /*!< Software BOOT0 */
#define FLASH_OPTR_nBOOT0_Pos               (27UL)
#define FLASH_OPTR_nBOOT0_Msk               (0x1UL << FLASH_OPTR_nBOOT0_Pos)        /*!< 0x08000000 */
#define FLASH_OPTR_nBOOT0                   FLASH_OPTR_nBOOT0_Msk                   /*!< nBOOT0 option bit */
#define FLASH_OPTR_IO_VDD_HSLV_Pos          (29UL)
#define FLASH_OPTR_IO_VDD_HSLV_Msk          (0x1UL << FLASH_OPTR_IO_VDD_HSLV_Pos)   /*!< 0x20000000 */
#define FLASH_OPTR_IO_VDD_HSLV              FLASH_OPTR_IO_VDD_HSLV_Msk              /*!< High speed IO at low VDD voltage configuration bit */
#define FLASH_OPTR_IO_VDDIO2_HSLV_Pos       (30UL)
#define FLASH_OPTR_IO_VDDIO2_HSLV_Msk       (0x1UL << FLASH_OPTR_IO_VDDIO2_HSLV_Pos) /*!< 0x40000000 */
#define FLASH_OPTR_IO_VDDIO2_HSLV           FLASH_OPTR_IO_VDDIO2_HSLV_Msk            /*!< High speed IO at low VDDIO2 voltage configuration bit */
#define FLASH_OPTR_TZEN_Pos                 (31UL)
#define FLASH_OPTR_TZEN_Msk                 (0x1UL << FLASH_OPTR_TZEN_Pos)          /*!< 0x80000000 */
#define FLASH_OPTR_TZEN                     FLASH_OPTR_TZEN_Msk                     /*!< Global TrustZone security enable */

/******************  Bits definition for FLASH_BOOT0R register  ***************/
#define FLASH_BOOT0R_ADD_Pos                (7UL)
#define FLASH_BOOT0R_ADD_Msk                (0x1FFFFFFUL << FLASH_BOOT0R_ADD_Pos)   /*!< 0xFFFFFF80 */
#define FLASH_BOOT0R_ADD                    FLASH_BOOT0R_ADD_Msk                    /*!< Non-secure boot base address 0 */

/******************  Bits definition for FLASH_BOOT1R register  ***************/
#define FLASH_BOOT1R_ADD_Pos                (7UL)
#define FLASH_BOOT1R_ADD_Msk                (0x1FFFFFFUL << FLASH_BOOT1R_ADD_Pos)   /*!< 0xFFFFFF80 */
#define FLASH_BOOT1R_ADD                    FLASH_BOOT1R_ADD_Msk                    /*!< Non-secure boot base address 1 */

/******************  Bits definition for FLASH_SBOOT0R register  **************/
#define FLASH_SBOOT0R_BOOT_LOCK_Pos         (0UL)
#define FLASH_SBOOT0R_BOOT_LOCK_Msk         (0x1UL << FLASH_SBOOT0R_BOOT_LOCK_Pos)  /*!< 0x00000001 */
#define FLASH_SBOOT0R_BOOT_LOCK             FLASH_SBOOT0R_BOOT_LOCK_Msk             /*!< Boot Lock */
#define FLASH_SBOOT0R_ADD_Pos               (7UL)
#define FLASH_SBOOT0R_ADD_Msk               (0x1FFFFFFUL << FLASH_SBOOT0R_ADD_Pos)  /*!< 0xFFFFFF80 */
#define FLASH_SBOOT0R_ADD                   FLASH_SBOOT0R_ADD_Msk                   /*!< Secure boot base address 0 */

/*****************  Bits definition for FLASH_SECWM1R1 register  **************/
#define FLASH_SECWM1R1_SECWM1_STRT_Pos      (0UL)
#define FLASH_SECWM1R1_SECWM1_STRT_Msk      (0x7FUL << FLASH_SECWM1R1_SECWM1_STRT_Pos) /*!< 0x0000007F */
#define FLASH_SECWM1R1_SECWM1_STRT          FLASH_SECWM1R1_SECWM1_STRT_Msk             /*!< Start page of first secure area */
#define FLASH_SECWM1R1_SECWM1_END_Pos       (16UL)
#define FLASH_SECWM1R1_SECWM1_END_Msk       (0x7FUL << FLASH_SECWM1R1_SECWM1_END_Pos)  /*!< 0x007F0000 */
#define FLASH_SECWM1R1_SECWM1_END           FLASH_SECWM1R1_SECWM1_END_Msk              /*!< End page of first secure area */

/*****************  Bits definition for FLASH_SECWM1R2 register  **************/
#define FLASH_SECWM1R2_HDP1_END_Pos         (16UL)
#define FLASH_SECWM1R2_HDP1_END_Msk         (0x7FUL << FLASH_SECWM1R2_HDP1_END_Pos) /*!< 0x007F0000 */
#define FLASH_SECWM1R2_HDP1_END             FLASH_SECWM1R2_HDP1_END_Msk             /*!< End page of first hide protection area */
#define FLASH_SECWM1R2_HDP1EN_Pos           (24UL)
#define FLASH_SECWM1R2_HDP1EN_Msk           (0xFFUL << FLASH_SECWM1R2_HDP1EN_Pos)   /*!< 0xFF000000 */
#define FLASH_SECWM1R2_HDP1EN               FLASH_SECWM1R2_HDP1EN_Msk               /*!< Hide protection first area enable */

/******************  Bits definition for FLASH_WRP1AR register  ***************/
#define FLASH_WRP1AR_STRT_Pos               (0UL)
#define FLASH_WRP1AR_STRT_Msk               (0x7FUL << FLASH_WRP1AR_STRT_Pos)       /*!< 0x0000007F */
#define FLASH_WRP1AR_STRT                   FLASH_WRP1AR_STRT_Msk                   /*!< Bank 1 WRP first area A start page */
#define FLASH_WRP1AR_END_Pos                (16UL)
#define FLASH_WRP1AR_END_Msk                (0x7FUL << FLASH_WRP1AR_END_Pos)        /*!< 0x007F0000 */
#define FLASH_WRP1AR_END                    FLASH_WRP1AR_END_Msk                    /*!< Bank 1 WRP first area A end page */
#define FLASH_WRP1AR_UNLOCK_Pos             (31UL)
#define FLASH_WRP1AR_UNLOCK_Msk             (0x1UL << FLASH_WRP1AR_UNLOCK_Pos)      /*!< 0x80000000 */
#define FLASH_WRP1AR_UNLOCK                 FLASH_WRP1AR_UNLOCK_Msk                 /*!< Bank 1 WRP first area A unlock */

/******************  Bits definition for FLASH_WRP1BR register  ***************/
#define FLASH_WRP1BR_STRT_Pos               (0UL)
#define FLASH_WRP1BR_STRT_Msk               (0x7FUL << FLASH_WRP1BR_STRT_Pos)       /*!< 0x0000007F */
#define FLASH_WRP1BR_STRT                   FLASH_WRP1BR_STRT_Msk                   /*!< Bank 1 WRP second area B start page */
#define FLASH_WRP1BR_END_Pos                (16UL)
#define FLASH_WRP1BR_END_Msk                (0x7FUL << FLASH_WRP1BR_END_Pos)        /*!< 0x007F0000 */
#define FLASH_WRP1BR_END                    FLASH_WRP1BR_END_Msk                    /*!< Bank 1 WRP second area B end page */
#define FLASH_WRP1BR_UNLOCK_Pos             (31UL)
#define FLASH_WRP1BR_UNLOCK_Msk             (0x1UL << FLASH_WRP1BR_UNLOCK_Pos)      /*!< 0x80000000 */
#define FLASH_WRP1BR_UNLOCK                 FLASH_WRP1BR_UNLOCK_Msk                 /*!< Bank 1 WRP second area B unlock */

/*****************  Bits definition for FLASH_SECWM2R1 register  **************/
#define FLASH_SECWM2R1_SECWM2_STRT_Pos      (0UL)
#define FLASH_SECWM2R1_SECWM2_STRT_Msk      (0x7FUL << FLASH_SECWM2R1_SECWM2_STRT_Pos) /*!< 0x0000007F */
#define FLASH_SECWM2R1_SECWM2_STRT          FLASH_SECWM2R1_SECWM2_STRT_Msk             /*!< Start page of second secure area */
#define FLASH_SECWM2R1_SECWM2_END_Pos       (16UL)
#define FLASH_SECWM2R1_SECWM2_END_Msk       (0x7FUL << FLASH_SECWM2R1_SECWM2_END_Pos)  /*!< 0x007F0000 */
#define FLASH_SECWM2R1_SECWM2_END           FLASH_SECWM2R1_SECWM2_END_Msk              /*!< End page of second secure area */

/*****************  Bits definition for FLASH_SECWM2R2 register  **************/
#define FLASH_SECWM2R2_HDP2_END_Pos         (16UL)
#define FLASH_SECWM2R2_HDP2_END_Msk         (0x7FUL << FLASH_SECWM2R2_HDP2_END_Pos) /*!< 0x007F0000 */
#define FLASH_SECWM2R2_HDP2_END             FLASH_SECWM2R2_HDP2_END_Msk             /*!< End page of hide protection second area */
#define FLASH_SECWM2R2_HDP2EN_Pos           (24UL)
#define FLASH_SECWM2R2_HDP2EN_Msk           (0xFFUL << FLASH_SECWM2R2_HDP2EN_Pos)   /*!< 0xFF000000 */
#define FLASH_SECWM2R2_HDP2EN               FLASH_SECWM2R2_HDP2EN_Msk               /*!< Hide protection second area enable */

/******************  Bits definition for FLASH_WRP2AR register  ***************/
#define FLASH_WRP2AR_STRT_Pos               (0UL)
#define FLASH_WRP2AR_STRT_Msk               (0x7FUL << FLASH_WRP2AR_STRT_Pos)       /*!< 0x0000007F */
#define FLASH_WRP2AR_STRT                   FLASH_WRP2AR_STRT_Msk                   /*!< Bank 2 WPR first area A start page */
#define FLASH_WRP2AR_END_Pos                (16UL)
#define FLASH_WRP2AR_END_Msk                (0x7FUL << FLASH_WRP2AR_END_Pos)        /*!< 0x007F0000 */
#define FLASH_WRP2AR_END                    FLASH_WRP2AR_END_Msk                    /*!< Bank 2 WPR first area A end page */
#define FLASH_WRP2AR_UNLOCK_Pos             (31UL)
#define FLASH_WRP2AR_UNLOCK_Msk             (0x1UL << FLASH_WRP2AR_UNLOCK_Pos)      /*!< 0x80000000 */
#define FLASH_WRP2AR_UNLOCK                 FLASH_WRP2AR_UNLOCK_Msk                 /*!< Bank 2 WPR first area A unlock */

/******************  Bits definition for FLASH_WRP2BR register  ***************/
#define FLASH_WRP2BR_STRT_Pos               (0UL)
#define FLASH_WRP2BR_STRT_Msk               (0x7FUL << FLASH_WRP2BR_STRT_Pos)       /*!< 0x0000007F */
#define FLASH_WRP2BR_STRT                   FLASH_WRP2BR_STRT_Msk                   /*!< Bank 2 WPR second area B start page */
#define FLASH_WRP2BR_END_Pos                (16UL)
#define FLASH_WRP2BR_END_Msk                (0x7FUL << FLASH_WRP2BR_END_Pos)        /*!< 0x007F0000 */
#define FLASH_WRP2BR_END                    FLASH_WRP2BR_END_Msk                    /*!< Bank 2 WPR second area B end page */
#define FLASH_WRP2BR_UNLOCK_Pos             (31UL)
#define FLASH_WRP2BR_UNLOCK_Msk             (0x1UL << FLASH_WRP2BR_UNLOCK_Pos)      /*!< 0x80000000 */
#define FLASH_WRP2BR_UNLOCK                 FLASH_WRP2BR_UNLOCK_Msk                 /*!< Bank 2 WPR second area B unlock */

/*******************  Bit definition for FLASH_SECBB1R1 register  ******************/
#define FLASH_SECBB1R1_SEC0_Pos                   (0UL)
#define FLASH_SECBB1R1_SEC0_Msk                   (0x1UL << FLASH_SECBB1R1_SEC0_Pos)            /*!< 0x00000001 */
#define FLASH_SECBB1R1_SEC0                       FLASH_SECBB1R1_SEC0_Msk                       /*!< Page 0 in bank 1 block-based secure */
#define FLASH_SECBB1R1_SEC1_Pos                   (1UL)
#define FLASH_SECBB1R1_SEC1_Msk                   (0x1UL << FLASH_SECBB1R1_SEC1_Pos)            /*!< 0x00000002 */
#define FLASH_SECBB1R1_SEC1                       FLASH_SECBB1R1_SEC1_Msk                       /*!< Page 1 in bank 1 block-based secure */
#define FLASH_SECBB1R1_SEC2_Pos                   (2UL)
#define FLASH_SECBB1R1_SEC2_Msk                   (0x1UL << FLASH_SECBB1R1_SEC2_Pos)            /*!< 0x00000004 */
#define FLASH_SECBB1R1_SEC2                       FLASH_SECBB1R1_SEC2_Msk                       /*!< Page 2 in bank 1 block-based secure */
#define FLASH_SECBB1R1_SEC3_Pos                   (3UL)
#define FLASH_SECBB1R1_SEC3_Msk                   (0x1UL << FLASH_SECBB1R1_SEC3_Pos)            /*!< 0x00000008 */
#define FLASH_SECBB1R1_SEC3                       FLASH_SECBB1R1_SEC3_Msk                       /*!< Page 3 in bank 1 block-based secure */
#define FLASH_SECBB1R1_SEC4_Pos                   (4UL)
#define FLASH_SECBB1R1_SEC4_Msk                   (0x1UL << FLASH_SECBB1R1_SEC4_Pos)            /*!< 0x00000010 */
#define FLASH_SECBB1R1_SEC4                       FLASH_SECBB1R1_SEC4_Msk                       /*!< Page 4 in bank 1 block-based secure */
#define FLASH_SECBB1R1_SEC5_Pos                   (5UL)
#define FLASH_SECBB1R1_SEC5_Msk                   (0x1UL << FLASH_SECBB1R1_SEC5_Pos)            /*!< 0x00000020 */
#define FLASH_SECBB1R1_SEC5                       FLASH_SECBB1R1_SEC5_Msk                       /*!< Page 5 in bank 1 block-based secure */
#define FLASH_SECBB1R1_SEC6_Pos                   (6UL)
#define FLASH_SECBB1R1_SEC6_Msk                   (0x1UL << FLASH_SECBB1R1_SEC6_Pos)            /*!< 0x00000040 */
#define FLASH_SECBB1R1_SEC6                       FLASH_SECBB1R1_SEC6_Msk                       /*!< Page 6 in bank 1 block-based secure */
#define FLASH_SECBB1R1_SEC7_Pos                   (7UL)
#define FLASH_SECBB1R1_SEC7_Msk                   (0x1UL << FLASH_SECBB1R1_SEC7_Pos)            /*!< 0x00000080 */
#define FLASH_SECBB1R1_SEC7                       FLASH_SECBB1R1_SEC7_Msk                       /*!< Page 7 in bank 1 block-based secure */
#define FLASH_SECBB1R1_SEC8_Pos                   (8UL)
#define FLASH_SECBB1R1_SEC8_Msk                   (0x1UL << FLASH_SECBB1R1_SEC8_Pos)            /*!< 0x00000100 */
#define FLASH_SECBB1R1_SEC8                       FLASH_SECBB1R1_SEC8_Msk                       /*!< Page 8 in bank 1 block-based secure */
#define FLASH_SECBB1R1_SEC9_Pos                   (9UL)
#define FLASH_SECBB1R1_SEC9_Msk                   (0x1UL << FLASH_SECBB1R1_SEC9_Pos)            /*!< 0x00000200 */
#define FLASH_SECBB1R1_SEC9                       FLASH_SECBB1R1_SEC9_Msk                       /*!< Page 9 in bank 1 block-based secure */
#define FLASH_SECBB1R1_SEC10_Pos                  (10UL)
#define FLASH_SECBB1R1_SEC10_Msk                  (0x1UL << FLASH_SECBB1R1_SEC10_Pos)           /*!< 0x00000400 */
#define FLASH_SECBB1R1_SEC10                      FLASH_SECBB1R1_SEC10_Msk                      /*!< Page 10 in bank 1 block-based secure */
#define FLASH_SECBB1R1_SEC11_Pos                  (11UL)
#define FLASH_SECBB1R1_SEC11_Msk                  (0x1UL << FLASH_SECBB1R1_SEC11_Pos)           /*!< 0x00000800 */
#define FLASH_SECBB1R1_SEC11                      FLASH_SECBB1R1_SEC11_Msk                      /*!< Page 11 in bank 1 block-based secure */
#define FLASH_SECBB1R1_SEC12_Pos                  (12UL)
#define FLASH_SECBB1R1_SEC12_Msk                  (0x1UL << FLASH_SECBB1R1_SEC12_Pos)           /*!< 0x00001000 */
#define FLASH_SECBB1R1_SEC12                      FLASH_SECBB1R1_SEC12_Msk                      /*!< Page 12 in bank 1 block-based secure */
#define FLASH_SECBB1R1_SEC13_Pos                  (13UL)
#define FLASH_SECBB1R1_SEC13_Msk                  (0x1UL << FLASH_SECBB1R1_SEC13_Pos)           /*!< 0x00002000 */
#define FLASH_SECBB1R1_SEC13                      FLASH_SECBB1R1_SEC13_Msk                      /*!< Page 13 in bank 1 block-based secure */
#define FLASH_SECBB1R1_SEC14_Pos                  (14UL)
#define FLASH_SECBB1R1_SEC14_Msk                  (0x1UL << FLASH_SECBB1R1_SEC14_Pos)           /*!< 0x00004000 */
#define FLASH_SECBB1R1_SEC14                      FLASH_SECBB1R1_SEC14_Msk                      /*!< Page 14 in bank 1 block-based secure */
#define FLASH_SECBB1R1_SEC15_Pos                  (15UL)
#define FLASH_SECBB1R1_SEC15_Msk                  (0x1UL << FLASH_SECBB1R1_SEC15_Pos)           /*!< 0x00008000 */
#define FLASH_SECBB1R1_SEC15                      FLASH_SECBB1R1_SEC15_Msk                      /*!< Page 15 in bank 1 block-based secure */
#define FLASH_SECBB1R1_SEC16_Pos                  (16UL)
#define FLASH_SECBB1R1_SEC16_Msk                  (0x1UL << FLASH_SECBB1R1_SEC16_Pos)           /*!< 0x00010000 */
#define FLASH_SECBB1R1_SEC16                      FLASH_SECBB1R1_SEC16_Msk                      /*!< Page 16 in bank 1 block-based secure */
#define FLASH_SECBB1R1_SEC17_Pos                  (17UL)
#define FLASH_SECBB1R1_SEC17_Msk                  (0x1UL << FLASH_SECBB1R1_SEC17_Pos)           /*!< 0x00020000 */
#define FLASH_SECBB1R1_SEC17                      FLASH_SECBB1R1_SEC17_Msk                      /*!< Page 17 in bank 1 block-based secure */
#define FLASH_SECBB1R1_SEC18_Pos                  (18UL)
#define FLASH_SECBB1R1_SEC18_Msk                  (0x1UL << FLASH_SECBB1R1_SEC18_Pos)           /*!< 0x00040000 */
#define FLASH_SECBB1R1_SEC18                      FLASH_SECBB1R1_SEC18_Msk                      /*!< Page 18 in bank 1 block-based secure */
#define FLASH_SECBB1R1_SEC19_Pos                  (19UL)
#define FLASH_SECBB1R1_SEC19_Msk                  (0x1UL << FLASH_SECBB1R1_SEC19_Pos)           /*!< 0x00080000 */
#define FLASH_SECBB1R1_SEC19                      FLASH_SECBB1R1_SEC19_Msk                      /*!< Page 19 in bank 1 block-based secure */
#define FLASH_SECBB1R1_SEC20_Pos                  (20UL)
#define FLASH_SECBB1R1_SEC20_Msk                  (0x1UL << FLASH_SECBB1R1_SEC20_Pos)           /*!< 0x00100000 */
#define FLASH_SECBB1R1_SEC20                      FLASH_SECBB1R1_SEC20_Msk                      /*!< Page 20 in bank 1 block-based secure */
#define FLASH_SECBB1R1_SEC21_Pos                  (21UL)
#define FLASH_SECBB1R1_SEC21_Msk                  (0x1UL << FLASH_SECBB1R1_SEC21_Pos)           /*!< 0x00200000 */
#define FLASH_SECBB1R1_SEC21                      FLASH_SECBB1R1_SEC21_Msk                      /*!< Page 21 in bank 1 block-based secure */
#define FLASH_SECBB1R1_SEC22_Pos                  (22UL)
#define FLASH_SECBB1R1_SEC22_Msk                  (0x1UL << FLASH_SECBB1R1_SEC22_Pos)           /*!< 0x00400000 */
#define FLASH_SECBB1R1_SEC22                      FLASH_SECBB1R1_SEC22_Msk                      /*!< Page 22 in bank 1 block-based secure */
#define FLASH_SECBB1R1_SEC23_Pos                  (23UL)
#define FLASH_SECBB1R1_SEC23_Msk                  (0x1UL << FLASH_SECBB1R1_SEC23_Pos)           /*!< 0x00800000 */
#define FLASH_SECBB1R1_SEC23                      FLASH_SECBB1R1_SEC23_Msk                      /*!< Page 23 in bank 1 block-based secure */
#define FLASH_SECBB1R1_SEC24_Pos                  (24UL)
#define FLASH_SECBB1R1_SEC24_Msk                  (0x1UL << FLASH_SECBB1R1_SEC24_Pos)           /*!< 0x01000000 */
#define FLASH_SECBB1R1_SEC24                      FLASH_SECBB1R1_SEC24_Msk                      /*!< Page 24 in bank 1 block-based secure */
#define FLASH_SECBB1R1_SEC25_Pos                  (25UL)
#define FLASH_SECBB1R1_SEC25_Msk                  (0x1UL << FLASH_SECBB1R1_SEC25_Pos)           /*!< 0x02000000 */
#define FLASH_SECBB1R1_SEC25                      FLASH_SECBB1R1_SEC25_Msk                      /*!< Page 25 in bank 1 block-based secure */
#define FLASH_SECBB1R1_SEC26_Pos                  (26UL)
#define FLASH_SECBB1R1_SEC26_Msk                  (0x1UL << FLASH_SECBB1R1_SEC26_Pos)           /*!< 0x04000000 */
#define FLASH_SECBB1R1_SEC26                      FLASH_SECBB1R1_SEC26_Msk                      /*!< Page 26 in bank 1 block-based secure */
#define FLASH_SECBB1R1_SEC27_Pos                  (27UL)
#define FLASH_SECBB1R1_SEC27_Msk                  (0x1UL << FLASH_SECBB1R1_SEC27_Pos)           /*!< 0x08000000 */
#define FLASH_SECBB1R1_SEC27                      FLASH_SECBB1R1_SEC27_Msk                      /*!< Page 27 in bank 1 block-based secure */
#define FLASH_SECBB1R1_SEC28_Pos                  (28UL)
#define FLASH_SECBB1R1_SEC28_Msk                  (0x1UL << FLASH_SECBB1R1_SEC28_Pos)           /*!< 0x10000000 */
#define FLASH_SECBB1R1_SEC28                      FLASH_SECBB1R1_SEC28_Msk                      /*!< Page 28 in bank 1 block-based secure */
#define FLASH_SECBB1R1_SEC29_Pos                  (29UL)
#define FLASH_SECBB1R1_SEC29_Msk                  (0x1UL << FLASH_SECBB1R1_SEC29_Pos)           /*!< 0x20000000 */
#define FLASH_SECBB1R1_SEC29                      FLASH_SECBB1R1_SEC29_Msk                      /*!< Page 29 in bank 1 block-based secure */
#define FLASH_SECBB1R1_SEC30_Pos                  (30UL)
#define FLASH_SECBB1R1_SEC30_Msk                  (0x1UL << FLASH_SECBB1R1_SEC30_Pos)           /*!< 0x40000000 */
#define FLASH_SECBB1R1_SEC30                      FLASH_SECBB1R1_SEC30_Msk                      /*!< Page 30 in bank 1 block-based secure */
#define FLASH_SECBB1R1_SEC31_Pos                  (31UL)
#define FLASH_SECBB1R1_SEC31_Msk                  (0x1UL << FLASH_SECBB1R1_SEC31_Pos)           /*!< 0x80000000 */
#define FLASH_SECBB1R1_SEC31                      FLASH_SECBB1R1_SEC31_Msk                      /*!< Page 31 in bank 1 block-based secure */

/*******************  Bit definition for FLASH_SECBB1R2 register  ******************/
#define FLASH_SECBB1R2_SEC0_Pos                   (0UL)
#define FLASH_SECBB1R2_SEC0_Msk                   (0x1UL << FLASH_SECBB1R2_SEC0_Pos)            /*!< 0x00000001 */
#define FLASH_SECBB1R2_SEC0                       FLASH_SECBB1R2_SEC0_Msk                       /*!< Page 32 in bank 1 block-based secure */
#define FLASH_SECBB1R2_SEC1_Pos                   (1UL)
#define FLASH_SECBB1R2_SEC1_Msk                   (0x1UL << FLASH_SECBB1R2_SEC1_Pos)            /*!< 0x00000002 */
#define FLASH_SECBB1R2_SEC1                       FLASH_SECBB1R2_SEC1_Msk                       /*!< Page 33 in bank 1 block-based secure */
#define FLASH_SECBB1R2_SEC2_Pos                   (2UL)
#define FLASH_SECBB1R2_SEC2_Msk                   (0x1UL << FLASH_SECBB1R2_SEC2_Pos)            /*!< 0x00000004 */
#define FLASH_SECBB1R2_SEC2                       FLASH_SECBB1R2_SEC2_Msk                       /*!< Page 34 in bank 1 block-based secure */
#define FLASH_SECBB1R2_SEC3_Pos                   (3UL)
#define FLASH_SECBB1R2_SEC3_Msk                   (0x1UL << FLASH_SECBB1R2_SEC3_Pos)            /*!< 0x00000008 */
#define FLASH_SECBB1R2_SEC3                       FLASH_SECBB1R2_SEC3_Msk                       /*!< Page 35 in bank 1 block-based secure */
#define FLASH_SECBB1R2_SEC4_Pos                   (4UL)
#define FLASH_SECBB1R2_SEC4_Msk                   (0x1UL << FLASH_SECBB1R2_SEC4_Pos)            /*!< 0x00000010 */
#define FLASH_SECBB1R2_SEC4                       FLASH_SECBB1R2_SEC4_Msk                       /*!< Page 36 in bank 1 block-based secure */
#define FLASH_SECBB1R2_SEC5_Pos                   (5UL)
#define FLASH_SECBB1R2_SEC5_Msk                   (0x1UL << FLASH_SECBB1R2_SEC5_Pos)            /*!< 0x00000020 */
#define FLASH_SECBB1R2_SEC5                       FLASH_SECBB1R2_SEC5_Msk                       /*!< Page 37 in bank 1 block-based secure */
#define FLASH_SECBB1R2_SEC6_Pos                   (6UL)
#define FLASH_SECBB1R2_SEC6_Msk                   (0x1UL << FLASH_SECBB1R2_SEC6_Pos)            /*!< 0x00000040 */
#define FLASH_SECBB1R2_SEC6                       FLASH_SECBB1R2_SEC6_Msk                       /*!< Page 38 in bank 1 block-based secure */
#define FLASH_SECBB1R2_SEC7_Pos                   (7UL)
#define FLASH_SECBB1R2_SEC7_Msk                   (0x1UL << FLASH_SECBB1R2_SEC7_Pos)            /*!< 0x00000080 */
#define FLASH_SECBB1R2_SEC7                       FLASH_SECBB1R2_SEC7_Msk                       /*!< Page 39 in bank 1 block-based secure */
#define FLASH_SECBB1R2_SEC8_Pos                   (8UL)
#define FLASH_SECBB1R2_SEC8_Msk                   (0x1UL << FLASH_SECBB1R2_SEC8_Pos)            /*!< 0x00000100 */
#define FLASH_SECBB1R2_SEC8                       FLASH_SECBB1R2_SEC8_Msk                       /*!< Page 40 in bank 1 block-based secure */
#define FLASH_SECBB1R2_SEC9_Pos                   (9UL)
#define FLASH_SECBB1R2_SEC9_Msk                   (0x1UL << FLASH_SECBB1R2_SEC9_Pos)            /*!< 0x00000200 */
#define FLASH_SECBB1R2_SEC9                       FLASH_SECBB1R2_SEC9_Msk                       /*!< Page 41 in bank 1 block-based secure */
#define FLASH_SECBB1R2_SEC10_Pos                  (10UL)
#define FLASH_SECBB1R2_SEC10_Msk                  (0x1UL << FLASH_SECBB1R2_SEC10_Pos)           /*!< 0x00000400 */
#define FLASH_SECBB1R2_SEC10                      FLASH_SECBB1R2_SEC10_Msk                      /*!< Page 42 in bank 1 block-based secure */
#define FLASH_SECBB1R2_SEC11_Pos                  (11UL)
#define FLASH_SECBB1R2_SEC11_Msk                  (0x1UL << FLASH_SECBB1R2_SEC11_Pos)           /*!< 0x00000800 */
#define FLASH_SECBB1R2_SEC11                      FLASH_SECBB1R2_SEC11_Msk                      /*!< Page 43 in bank 1 block-based secure */
#define FLASH_SECBB1R2_SEC12_Pos                  (12UL)
#define FLASH_SECBB1R2_SEC12_Msk                  (0x1UL << FLASH_SECBB1R2_SEC12_Pos)           /*!< 0x00001000 */
#define FLASH_SECBB1R2_SEC12                      FLASH_SECBB1R2_SEC12_Msk                      /*!< Page 44 in bank 1 block-based secure */
#define FLASH_SECBB1R2_SEC13_Pos                  (13UL)
#define FLASH_SECBB1R2_SEC13_Msk                  (0x1UL << FLASH_SECBB1R2_SEC13_Pos)           /*!< 0x00002000 */
#define FLASH_SECBB1R2_SEC13                      FLASH_SECBB1R2_SEC13_Msk                      /*!< Page 45 in bank 1 block-based secure */
#define FLASH_SECBB1R2_SEC14_Pos                  (14UL)
#define FLASH_SECBB1R2_SEC14_Msk                  (0x1UL << FLASH_SECBB1R2_SEC14_Pos)           /*!< 0x00004000 */
#define FLASH_SECBB1R2_SEC14                      FLASH_SECBB1R2_SEC14_Msk                      /*!< Page 46 in bank 1 block-based secure */
#define FLASH_SECBB1R2_SEC15_Pos                  (15UL)
#define FLASH_SECBB1R2_SEC15_Msk                  (0x1UL << FLASH_SECBB1R2_SEC15_Pos)           /*!< 0x00008000 */
#define FLASH_SECBB1R2_SEC15                      FLASH_SECBB1R2_SEC15_Msk                      /*!< Page 47 in bank 1 block-based secure */
#define FLASH_SECBB1R2_SEC16_Pos                  (16UL)
#define FLASH_SECBB1R2_SEC16_Msk                  (0x1UL << FLASH_SECBB1R2_SEC16_Pos)           /*!< 0x00010000 */
#define FLASH_SECBB1R2_SEC16                      FLASH_SECBB1R2_SEC16_Msk                      /*!< Page 48 in bank 1 block-based secure */
#define FLASH_SECBB1R2_SEC17_Pos                  (17UL)
#define FLASH_SECBB1R2_SEC17_Msk                  (0x1UL << FLASH_SECBB1R2_SEC17_Pos)           /*!< 0x00020000 */
#define FLASH_SECBB1R2_SEC17                      FLASH_SECBB1R2_SEC17_Msk                      /*!< Page 49 in bank 1 block-based secure */
#define FLASH_SECBB1R2_SEC18_Pos                  (18UL)
#define FLASH_SECBB1R2_SEC18_Msk                  (0x1UL << FLASH_SECBB1R2_SEC18_Pos)           /*!< 0x00040000 */
#define FLASH_SECBB1R2_SEC18                      FLASH_SECBB1R2_SEC18_Msk                      /*!< Page 50 in bank 1 block-based secure */
#define FLASH_SECBB1R2_SEC19_Pos                  (19UL)
#define FLASH_SECBB1R2_SEC19_Msk                  (0x1UL << FLASH_SECBB1R2_SEC19_Pos)           /*!< 0x00080000 */
#define FLASH_SECBB1R2_SEC19                      FLASH_SECBB1R2_SEC19_Msk                      /*!< Page 51 in bank 1 block-based secure */
#define FLASH_SECBB1R2_SEC20_Pos                  (20UL)
#define FLASH_SECBB1R2_SEC20_Msk                  (0x1UL << FLASH_SECBB1R2_SEC20_Pos)           /*!< 0x00100000 */
#define FLASH_SECBB1R2_SEC20                      FLASH_SECBB1R2_SEC20_Msk                      /*!< Page 52 in bank 1 block-based secure */
#define FLASH_SECBB1R2_SEC21_Pos                  (21UL)
#define FLASH_SECBB1R2_SEC21_Msk                  (0x1UL << FLASH_SECBB1R2_SEC21_Pos)           /*!< 0x00200000 */
#define FLASH_SECBB1R2_SEC21                      FLASH_SECBB1R2_SEC21_Msk                      /*!< Page 53 in bank 1 block-based secure */
#define FLASH_SECBB1R2_SEC22_Pos                  (22UL)
#define FLASH_SECBB1R2_SEC22_Msk                  (0x1UL << FLASH_SECBB1R2_SEC22_Pos)           /*!< 0x00400000 */
#define FLASH_SECBB1R2_SEC22                      FLASH_SECBB1R2_SEC22_Msk                      /*!< Page 54 in bank 1 block-based secure */
#define FLASH_SECBB1R2_SEC23_Pos                  (23UL)
#define FLASH_SECBB1R2_SEC23_Msk                  (0x1UL << FLASH_SECBB1R2_SEC23_Pos)           /*!< 0x00800000 */
#define FLASH_SECBB1R2_SEC23                      FLASH_SECBB1R2_SEC23_Msk                      /*!< Page 55 in bank 1 block-based secure */
#define FLASH_SECBB1R2_SEC24_Pos                  (24UL)
#define FLASH_SECBB1R2_SEC24_Msk                  (0x1UL << FLASH_SECBB1R2_SEC24_Pos)           /*!< 0x01000000 */
#define FLASH_SECBB1R2_SEC24                      FLASH_SECBB1R2_SEC24_Msk                      /*!< Page 56 in bank 1 block-based secure */
#define FLASH_SECBB1R2_SEC25_Pos                  (25UL)
#define FLASH_SECBB1R2_SEC25_Msk                  (0x1UL << FLASH_SECBB1R2_SEC25_Pos)           /*!< 0x02000000 */
#define FLASH_SECBB1R2_SEC25                      FLASH_SECBB1R2_SEC25_Msk                      /*!< Page 57 in bank 1 block-based secure */
#define FLASH_SECBB1R2_SEC26_Pos                  (26UL)
#define FLASH_SECBB1R2_SEC26_Msk                  (0x1UL << FLASH_SECBB1R2_SEC26_Pos)           /*!< 0x04000000 */
#define FLASH_SECBB1R2_SEC26                      FLASH_SECBB1R2_SEC26_Msk                      /*!< Page 58 in bank 1 block-based secure */
#define FLASH_SECBB1R2_SEC27_Pos                  (27UL)
#define FLASH_SECBB1R2_SEC27_Msk                  (0x1UL << FLASH_SECBB1R2_SEC27_Pos)           /*!< 0x08000000 */
#define FLASH_SECBB1R2_SEC27                      FLASH_SECBB1R2_SEC27_Msk                      /*!< Page 59 in bank 1 block-based secure */
#define FLASH_SECBB1R2_SEC28_Pos                  (28UL)
#define FLASH_SECBB1R2_SEC28_Msk                  (0x1UL << FLASH_SECBB1R2_SEC28_Pos)           /*!< 0x10000000 */
#define FLASH_SECBB1R2_SEC28                      FLASH_SECBB1R2_SEC28_Msk                      /*!< Page 60 in bank 1 block-based secure */
#define FLASH_SECBB1R2_SEC29_Pos                  (29UL)
#define FLASH_SECBB1R2_SEC29_Msk                  (0x1UL << FLASH_SECBB1R2_SEC29_Pos)           /*!< 0x20000000 */
#define FLASH_SECBB1R2_SEC29                      FLASH_SECBB1R2_SEC29_Msk                      /*!< Page 61 in bank 1 block-based secure */
#define FLASH_SECBB1R2_SEC30_Pos                  (30UL)
#define FLASH_SECBB1R2_SEC30_Msk                  (0x1UL << FLASH_SECBB1R2_SEC30_Pos)           /*!< 0x40000000 */
#define FLASH_SECBB1R2_SEC30                      FLASH_SECBB1R2_SEC30_Msk                      /*!< Page 62 in bank 1 block-based secure */
#define FLASH_SECBB1R2_SEC31_Pos                  (31UL)
#define FLASH_SECBB1R2_SEC31_Msk                  (0x1UL << FLASH_SECBB1R2_SEC31_Pos)           /*!< 0x80000000 */
#define FLASH_SECBB1R2_SEC31                      FLASH_SECBB1R2_SEC31_Msk                      /*!< Page 63 in bank 1 block-based secure */

/*******************  Bit definition for FLASH_SECBB1R3 register  ******************/
#define FLASH_SECBB1R3_SEC0_Pos                   (0UL)
#define FLASH_SECBB1R3_SEC0_Msk                   (0x1UL << FLASH_SECBB1R3_SEC0_Pos)            /*!< 0x00000001 */
#define FLASH_SECBB1R3_SEC0                       FLASH_SECBB1R3_SEC0_Msk                       /*!< Page 64 in bank 1 block-based secure */
#define FLASH_SECBB1R3_SEC1_Pos                   (1UL)
#define FLASH_SECBB1R3_SEC1_Msk                   (0x1UL << FLASH_SECBB1R3_SEC1_Pos)            /*!< 0x00000002 */
#define FLASH_SECBB1R3_SEC1                       FLASH_SECBB1R3_SEC1_Msk                       /*!< Page 65 in bank 1 block-based secure */
#define FLASH_SECBB1R3_SEC2_Pos                   (2UL)
#define FLASH_SECBB1R3_SEC2_Msk                   (0x1UL << FLASH_SECBB1R3_SEC2_Pos)            /*!< 0x00000004 */
#define FLASH_SECBB1R3_SEC2                       FLASH_SECBB1R3_SEC2_Msk                       /*!< Page 66 in bank 1 block-based secure */
#define FLASH_SECBB1R3_SEC3_Pos                   (3UL)
#define FLASH_SECBB1R3_SEC3_Msk                   (0x1UL << FLASH_SECBB1R3_SEC3_Pos)            /*!< 0x00000008 */
#define FLASH_SECBB1R3_SEC3                       FLASH_SECBB1R3_SEC3_Msk                       /*!< Page 67 in bank 1 block-based secure */
#define FLASH_SECBB1R3_SEC4_Pos                   (4UL)
#define FLASH_SECBB1R3_SEC4_Msk                   (0x1UL << FLASH_SECBB1R3_SEC4_Pos)            /*!< 0x00000010 */
#define FLASH_SECBB1R3_SEC4                       FLASH_SECBB1R3_SEC4_Msk                       /*!< Page 68 in bank 1 block-based secure */
#define FLASH_SECBB1R3_SEC5_Pos                   (5UL)
#define FLASH_SECBB1R3_SEC5_Msk                   (0x1UL << FLASH_SECBB1R3_SEC5_Pos)            /*!< 0x00000020 */
#define FLASH_SECBB1R3_SEC5                       FLASH_SECBB1R3_SEC5_Msk                       /*!< Page 69 in bank 1 block-based secure */
#define FLASH_SECBB1R3_SEC6_Pos                   (6UL)
#define FLASH_SECBB1R3_SEC6_Msk                   (0x1UL << FLASH_SECBB1R3_SEC6_Pos)            /*!< 0x00000040 */
#define FLASH_SECBB1R3_SEC6                       FLASH_SECBB1R3_SEC6_Msk                       /*!< Page 70 in bank 1 block-based secure */
#define FLASH_SECBB1R3_SEC7_Pos                   (7UL)
#define FLASH_SECBB1R3_SEC7_Msk                   (0x1UL << FLASH_SECBB1R3_SEC7_Pos)            /*!< 0x00000080 */
#define FLASH_SECBB1R3_SEC7                       FLASH_SECBB1R3_SEC7_Msk                       /*!< Page 71 in bank 1 block-based secure */
#define FLASH_SECBB1R3_SEC8_Pos                   (8UL)
#define FLASH_SECBB1R3_SEC8_Msk                   (0x1UL << FLASH_SECBB1R3_SEC8_Pos)            /*!< 0x00000100 */
#define FLASH_SECBB1R3_SEC8                       FLASH_SECBB1R3_SEC8_Msk                       /*!< Page 72 in bank 1 block-based secure */
#define FLASH_SECBB1R3_SEC9_Pos                   (9UL)
#define FLASH_SECBB1R3_SEC9_Msk                   (0x1UL << FLASH_SECBB1R3_SEC9_Pos)            /*!< 0x00000200 */
#define FLASH_SECBB1R3_SEC9                       FLASH_SECBB1R3_SEC9_Msk                       /*!< Page 73 in bank 1 block-based secure */
#define FLASH_SECBB1R3_SEC10_Pos                  (10UL)
#define FLASH_SECBB1R3_SEC10_Msk                  (0x1UL << FLASH_SECBB1R3_SEC10_Pos)           /*!< 0x00000400 */
#define FLASH_SECBB1R3_SEC10                      FLASH_SECBB1R3_SEC10_Msk                      /*!< Page 74 in bank 1 block-based secure */
#define FLASH_SECBB1R3_SEC11_Pos                  (11UL)
#define FLASH_SECBB1R3_SEC11_Msk                  (0x1UL << FLASH_SECBB1R3_SEC11_Pos)           /*!< 0x00000800 */
#define FLASH_SECBB1R3_SEC11                      FLASH_SECBB1R3_SEC11_Msk                      /*!< Page 75 in bank 1 block-based secure */
#define FLASH_SECBB1R3_SEC12_Pos                  (12UL)
#define FLASH_SECBB1R3_SEC12_Msk                  (0x1UL << FLASH_SECBB1R3_SEC12_Pos)           /*!< 0x00001000 */
#define FLASH_SECBB1R3_SEC12                      FLASH_SECBB1R3_SEC12_Msk                      /*!< Page 76 in bank 1 block-based secure */
#define FLASH_SECBB1R3_SEC13_Pos                  (13UL)
#define FLASH_SECBB1R3_SEC13_Msk                  (0x1UL << FLASH_SECBB1R3_SEC13_Pos)           /*!< 0x00002000 */
#define FLASH_SECBB1R3_SEC13                      FLASH_SECBB1R3_SEC13_Msk                      /*!< Page 77 in bank 1 block-based secure */
#define FLASH_SECBB1R3_SEC14_Pos                  (14UL)
#define FLASH_SECBB1R3_SEC14_Msk                  (0x1UL << FLASH_SECBB1R3_SEC14_Pos)           /*!< 0x00004000 */
#define FLASH_SECBB1R3_SEC14                      FLASH_SECBB1R3_SEC14_Msk                      /*!< Page 78 in bank 1 block-based secure */
#define FLASH_SECBB1R3_SEC15_Pos                  (15UL)
#define FLASH_SECBB1R3_SEC15_Msk                  (0x1UL << FLASH_SECBB1R3_SEC15_Pos)           /*!< 0x00008000 */
#define FLASH_SECBB1R3_SEC15                      FLASH_SECBB1R3_SEC15_Msk                      /*!< Page 79 in bank 1 block-based secure */
#define FLASH_SECBB1R3_SEC16_Pos                  (16UL)
#define FLASH_SECBB1R3_SEC16_Msk                  (0x1UL << FLASH_SECBB1R3_SEC16_Pos)           /*!< 0x00010000 */
#define FLASH_SECBB1R3_SEC16                      FLASH_SECBB1R3_SEC16_Msk                      /*!< Page 80 in bank 1 block-based secure */
#define FLASH_SECBB1R3_SEC17_Pos                  (17UL)
#define FLASH_SECBB1R3_SEC17_Msk                  (0x1UL << FLASH_SECBB1R3_SEC17_Pos)           /*!< 0x00020000 */
#define FLASH_SECBB1R3_SEC17                      FLASH_SECBB1R3_SEC17_Msk                      /*!< Page 81 in bank 1 block-based secure */
#define FLASH_SECBB1R3_SEC18_Pos                  (18UL)
#define FLASH_SECBB1R3_SEC18_Msk                  (0x1UL << FLASH_SECBB1R3_SEC18_Pos)           /*!< 0x00040000 */
#define FLASH_SECBB1R3_SEC18                      FLASH_SECBB1R3_SEC18_Msk                      /*!< Page 82 in bank 1 block-based secure */
#define FLASH_SECBB1R3_SEC19_Pos                  (19UL)
#define FLASH_SECBB1R3_SEC19_Msk                  (0x1UL << FLASH_SECBB1R3_SEC19_Pos)           /*!< 0x00080000 */
#define FLASH_SECBB1R3_SEC19                      FLASH_SECBB1R3_SEC19_Msk                      /*!< Page 83 in bank 1 block-based secure */
#define FLASH_SECBB1R3_SEC20_Pos                  (20UL)
#define FLASH_SECBB1R3_SEC20_Msk                  (0x1UL << FLASH_SECBB1R3_SEC20_Pos)           /*!< 0x00100000 */
#define FLASH_SECBB1R3_SEC20                      FLASH_SECBB1R3_SEC20_Msk                      /*!< Page 84 in bank 1 block-based secure */
#define FLASH_SECBB1R3_SEC21_Pos                  (21UL)
#define FLASH_SECBB1R3_SEC21_Msk                  (0x1UL << FLASH_SECBB1R3_SEC21_Pos)           /*!< 0x00200000 */
#define FLASH_SECBB1R3_SEC21                      FLASH_SECBB1R3_SEC21_Msk                      /*!< Page 85 in bank 1 block-based secure */
#define FLASH_SECBB1R3_SEC22_Pos                  (22UL)
#define FLASH_SECBB1R3_SEC22_Msk                  (0x1UL << FLASH_SECBB1R3_SEC22_Pos)           /*!< 0x00400000 */
#define FLASH_SECBB1R3_SEC22                      FLASH_SECBB1R3_SEC22_Msk                      /*!< Page 86 in bank 1 block-based secure */
#define FLASH_SECBB1R3_SEC23_Pos                  (23UL)
#define FLASH_SECBB1R3_SEC23_Msk                  (0x1UL << FLASH_SECBB1R3_SEC23_Pos)           /*!< 0x00800000 */
#define FLASH_SECBB1R3_SEC23                      FLASH_SECBB1R3_SEC23_Msk                      /*!< Page 87 in bank 1 block-based secure */
#define FLASH_SECBB1R3_SEC24_Pos                  (24UL)
#define FLASH_SECBB1R3_SEC24_Msk                  (0x1UL << FLASH_SECBB1R3_SEC24_Pos)           /*!< 0x01000000 */
#define FLASH_SECBB1R3_SEC24                      FLASH_SECBB1R3_SEC24_Msk                      /*!< Page 88 in bank 1 block-based secure */
#define FLASH_SECBB1R3_SEC25_Pos                  (25UL)
#define FLASH_SECBB1R3_SEC25_Msk                  (0x1UL << FLASH_SECBB1R3_SEC25_Pos)           /*!< 0x02000000 */
#define FLASH_SECBB1R3_SEC25                      FLASH_SECBB1R3_SEC25_Msk                      /*!< Page 89 in bank 1 block-based secure */
#define FLASH_SECBB1R3_SEC26_Pos                  (26UL)
#define FLASH_SECBB1R3_SEC26_Msk                  (0x1UL << FLASH_SECBB1R3_SEC26_Pos)           /*!< 0x04000000 */
#define FLASH_SECBB1R3_SEC26                      FLASH_SECBB1R3_SEC26_Msk                      /*!< Page 90 in bank 1 block-based secure */
#define FLASH_SECBB1R3_SEC27_Pos                  (27UL)
#define FLASH_SECBB1R3_SEC27_Msk                  (0x1UL << FLASH_SECBB1R3_SEC27_Pos)           /*!< 0x08000000 */
#define FLASH_SECBB1R3_SEC27                      FLASH_SECBB1R3_SEC27_Msk                      /*!< Page 91 in bank 1 block-based secure */
#define FLASH_SECBB1R3_SEC28_Pos                  (28UL)
#define FLASH_SECBB1R3_SEC28_Msk                  (0x1UL << FLASH_SECBB1R3_SEC28_Pos)           /*!< 0x10000000 */
#define FLASH_SECBB1R3_SEC28                      FLASH_SECBB1R3_SEC28_Msk                      /*!< Page 92 in bank 1 block-based secure */
#define FLASH_SECBB1R3_SEC29_Pos                  (29UL)
#define FLASH_SECBB1R3_SEC29_Msk                  (0x1UL << FLASH_SECBB1R3_SEC29_Pos)           /*!< 0x20000000 */
#define FLASH_SECBB1R3_SEC29                      FLASH_SECBB1R3_SEC29_Msk                      /*!< Page 93 in bank 1 block-based secure */
#define FLASH_SECBB1R3_SEC30_Pos                  (30UL)
#define FLASH_SECBB1R3_SEC30_Msk                  (0x1UL << FLASH_SECBB1R3_SEC30_Pos)           /*!< 0x40000000 */
#define FLASH_SECBB1R3_SEC30                      FLASH_SECBB1R3_SEC30_Msk                      /*!< Page 94 in bank 1 block-based secure */
#define FLASH_SECBB1R3_SEC31_Pos                  (31UL)
#define FLASH_SECBB1R3_SEC31_Msk                  (0x1UL << FLASH_SECBB1R3_SEC31_Pos)           /*!< 0x80000000 */
#define FLASH_SECBB1R3_SEC31                      FLASH_SECBB1R3_SEC31_Msk                      /*!< Page 95 in bank 1 block-based secure */

/*******************  Bit definition for FLASH_SECBB1R4 register  ******************/
#define FLASH_SECBB1R4_SEC0_Pos                   (0UL)
#define FLASH_SECBB1R4_SEC0_Msk                   (0x1UL << FLASH_SECBB1R4_SEC0_Pos)            /*!< 0x00000001 */
#define FLASH_SECBB1R4_SEC0                       FLASH_SECBB1R4_SEC0_Msk                       /*!< Page 96 in bank 1 block-based secure */
#define FLASH_SECBB1R4_SEC1_Pos                   (1UL)
#define FLASH_SECBB1R4_SEC1_Msk                   (0x1UL << FLASH_SECBB1R4_SEC1_Pos)            /*!< 0x00000002 */
#define FLASH_SECBB1R4_SEC1                       FLASH_SECBB1R4_SEC1_Msk                       /*!< Page 97 in bank 1 block-based secure */
#define FLASH_SECBB1R4_SEC2_Pos                   (2UL)
#define FLASH_SECBB1R4_SEC2_Msk                   (0x1UL << FLASH_SECBB1R4_SEC2_Pos)            /*!< 0x00000004 */
#define FLASH_SECBB1R4_SEC2                       FLASH_SECBB1R4_SEC2_Msk                       /*!< Page 98 in bank 1 block-based secure */
#define FLASH_SECBB1R4_SEC3_Pos                   (3UL)
#define FLASH_SECBB1R4_SEC3_Msk                   (0x1UL << FLASH_SECBB1R4_SEC3_Pos)            /*!< 0x00000008 */
#define FLASH_SECBB1R4_SEC3                       FLASH_SECBB1R4_SEC3_Msk                       /*!< Page 99 in bank 1 block-based secure */
#define FLASH_SECBB1R4_SEC4_Pos                   (4UL)
#define FLASH_SECBB1R4_SEC4_Msk                   (0x1UL << FLASH_SECBB1R4_SEC4_Pos)            /*!< 0x00000010 */
#define FLASH_SECBB1R4_SEC4                       FLASH_SECBB1R4_SEC4_Msk                       /*!< Page 100 in bank 1 block-based secure */
#define FLASH_SECBB1R4_SEC5_Pos                   (5UL)
#define FLASH_SECBB1R4_SEC5_Msk                   (0x1UL << FLASH_SECBB1R4_SEC5_Pos)            /*!< 0x00000020 */
#define FLASH_SECBB1R4_SEC5                       FLASH_SECBB1R4_SEC5_Msk                       /*!< Page 101 in bank 1 block-based secure */
#define FLASH_SECBB1R4_SEC6_Pos                   (6UL)
#define FLASH_SECBB1R4_SEC6_Msk                   (0x1UL << FLASH_SECBB1R4_SEC6_Pos)            /*!< 0x00000040 */
#define FLASH_SECBB1R4_SEC6                       FLASH_SECBB1R4_SEC6_Msk                       /*!< Page 102 in bank 1 block-based secure */
#define FLASH_SECBB1R4_SEC7_Pos                   (7UL)
#define FLASH_SECBB1R4_SEC7_Msk                   (0x1UL << FLASH_SECBB1R4_SEC7_Pos)            /*!< 0x00000080 */
#define FLASH_SECBB1R4_SEC7                       FLASH_SECBB1R4_SEC7_Msk                       /*!< Page 103 in bank 1 block-based secure */
#define FLASH_SECBB1R4_SEC8_Pos                   (8UL)
#define FLASH_SECBB1R4_SEC8_Msk                   (0x1UL << FLASH_SECBB1R4_SEC8_Pos)            /*!< 0x00000100 */
#define FLASH_SECBB1R4_SEC8                       FLASH_SECBB1R4_SEC8_Msk                       /*!< Page 104 in bank 1 block-based secure */
#define FLASH_SECBB1R4_SEC9_Pos                   (9UL)
#define FLASH_SECBB1R4_SEC9_Msk                   (0x1UL << FLASH_SECBB1R4_SEC9_Pos)            /*!< 0x00000200 */
#define FLASH_SECBB1R4_SEC9                       FLASH_SECBB1R4_SEC9_Msk                       /*!< Page 105 in bank 1 block-based secure */
#define FLASH_SECBB1R4_SEC10_Pos                  (10UL)
#define FLASH_SECBB1R4_SEC10_Msk                  (0x1UL << FLASH_SECBB1R4_SEC10_Pos)           /*!< 0x00000400 */
#define FLASH_SECBB1R4_SEC10                      FLASH_SECBB1R4_SEC10_Msk                      /*!< Page 106 in bank 1 block-based secure */
#define FLASH_SECBB1R4_SEC11_Pos                  (11UL)
#define FLASH_SECBB1R4_SEC11_Msk                  (0x1UL << FLASH_SECBB1R4_SEC11_Pos)           /*!< 0x00000800 */
#define FLASH_SECBB1R4_SEC11                      FLASH_SECBB1R4_SEC11_Msk                      /*!< Page 107 in bank 1 block-based secure */
#define FLASH_SECBB1R4_SEC12_Pos                  (12UL)
#define FLASH_SECBB1R4_SEC12_Msk                  (0x1UL << FLASH_SECBB1R4_SEC12_Pos)           /*!< 0x00001000 */
#define FLASH_SECBB1R4_SEC12                      FLASH_SECBB1R4_SEC12_Msk                      /*!< Page 108 in bank 1 block-based secure */
#define FLASH_SECBB1R4_SEC13_Pos                  (13UL)
#define FLASH_SECBB1R4_SEC13_Msk                  (0x1UL << FLASH_SECBB1R4_SEC13_Pos)           /*!< 0x00002000 */
#define FLASH_SECBB1R4_SEC13                      FLASH_SECBB1R4_SEC13_Msk                      /*!< Page 109 in bank 1 block-based secure */
#define FLASH_SECBB1R4_SEC14_Pos                  (14UL)
#define FLASH_SECBB1R4_SEC14_Msk                  (0x1UL << FLASH_SECBB1R4_SEC14_Pos)           /*!< 0x00004000 */
#define FLASH_SECBB1R4_SEC14                      FLASH_SECBB1R4_SEC14_Msk                      /*!< Page 110 in bank 1 block-based secure */
#define FLASH_SECBB1R4_SEC15_Pos                  (15UL)
#define FLASH_SECBB1R4_SEC15_Msk                  (0x1UL << FLASH_SECBB1R4_SEC15_Pos)           /*!< 0x00008000 */
#define FLASH_SECBB1R4_SEC15                      FLASH_SECBB1R4_SEC15_Msk                      /*!< Page 111 in bank 1 block-based secure */
#define FLASH_SECBB1R4_SEC16_Pos                  (16UL)
#define FLASH_SECBB1R4_SEC16_Msk                  (0x1UL << FLASH_SECBB1R4_SEC16_Pos)           /*!< 0x00010000 */
#define FLASH_SECBB1R4_SEC16                      FLASH_SECBB1R4_SEC16_Msk                      /*!< Page 112 in bank 1 block-based secure */
#define FLASH_SECBB1R4_SEC17_Pos                  (17UL)
#define FLASH_SECBB1R4_SEC17_Msk                  (0x1UL << FLASH_SECBB1R4_SEC17_Pos)           /*!< 0x00020000 */
#define FLASH_SECBB1R4_SEC17                      FLASH_SECBB1R4_SEC17_Msk                      /*!< Page 113 in bank 1 block-based secure */
#define FLASH_SECBB1R4_SEC18_Pos                  (18UL)
#define FLASH_SECBB1R4_SEC18_Msk                  (0x1UL << FLASH_SECBB1R4_SEC18_Pos)           /*!< 0x00040000 */
#define FLASH_SECBB1R4_SEC18                      FLASH_SECBB1R4_SEC18_Msk                      /*!< Page 114 in bank 1 block-based secure */
#define FLASH_SECBB1R4_SEC19_Pos                  (19UL)
#define FLASH_SECBB1R4_SEC19_Msk                  (0x1UL << FLASH_SECBB1R4_SEC19_Pos)           /*!< 0x00080000 */
#define FLASH_SECBB1R4_SEC19                      FLASH_SECBB1R4_SEC19_Msk                      /*!< Page 115 in bank 1 block-based secure */
#define FLASH_SECBB1R4_SEC20_Pos                  (20UL)
#define FLASH_SECBB1R4_SEC20_Msk                  (0x1UL << FLASH_SECBB1R4_SEC20_Pos)           /*!< 0x00100000 */
#define FLASH_SECBB1R4_SEC20                      FLASH_SECBB1R4_SEC20_Msk                      /*!< Page 116 in bank 1 block-based secure */
#define FLASH_SECBB1R4_SEC21_Pos                  (21UL)
#define FLASH_SECBB1R4_SEC21_Msk                  (0x1UL << FLASH_SECBB1R4_SEC21_Pos)           /*!< 0x00200000 */
#define FLASH_SECBB1R4_SEC21                      FLASH_SECBB1R4_SEC21_Msk                      /*!< Page 117 in bank 1 block-based secure */
#define FLASH_SECBB1R4_SEC22_Pos                  (22UL)
#define FLASH_SECBB1R4_SEC22_Msk                  (0x1UL << FLASH_SECBB1R4_SEC22_Pos)           /*!< 0x00400000 */
#define FLASH_SECBB1R4_SEC22                      FLASH_SECBB1R4_SEC22_Msk                      /*!< Page 118 in bank 1 block-based secure */
#define FLASH_SECBB1R4_SEC23_Pos                  (23UL)
#define FLASH_SECBB1R4_SEC23_Msk                  (0x1UL << FLASH_SECBB1R4_SEC23_Pos)           /*!< 0x00800000 */
#define FLASH_SECBB1R4_SEC23                      FLASH_SECBB1R4_SEC23_Msk                      /*!< Page 119 in bank 1 block-based secure */
#define FLASH_SECBB1R4_SEC24_Pos                  (24UL)
#define FLASH_SECBB1R4_SEC24_Msk                  (0x1UL << FLASH_SECBB1R4_SEC24_Pos)           /*!< 0x01000000 */
#define FLASH_SECBB1R4_SEC24                      FLASH_SECBB1R4_SEC24_Msk                      /*!< Page 120 in bank 1 block-based secure */
#define FLASH_SECBB1R4_SEC25_Pos                  (25UL)
#define FLASH_SECBB1R4_SEC25_Msk                  (0x1UL << FLASH_SECBB1R4_SEC25_Pos)           /*!< 0x02000000 */
#define FLASH_SECBB1R4_SEC25                      FLASH_SECBB1R4_SEC25_Msk                      /*!< Page 121 in bank 1 block-based secure */
#define FLASH_SECBB1R4_SEC26_Pos                  (26UL)
#define FLASH_SECBB1R4_SEC26_Msk                  (0x1UL << FLASH_SECBB1R4_SEC26_Pos)           /*!< 0x04000000 */
#define FLASH_SECBB1R4_SEC26                      FLASH_SECBB1R4_SEC26_Msk                      /*!< Page 122 in bank 1 block-based secure */
#define FLASH_SECBB1R4_SEC27_Pos                  (27UL)
#define FLASH_SECBB1R4_SEC27_Msk                  (0x1UL << FLASH_SECBB1R4_SEC27_Pos)           /*!< 0x08000000 */
#define FLASH_SECBB1R4_SEC27                      FLASH_SECBB1R4_SEC27_Msk                      /*!< Page 123 in bank 1 block-based secure */
#define FLASH_SECBB1R4_SEC28_Pos                  (28UL)
#define FLASH_SECBB1R4_SEC28_Msk                  (0x1UL << FLASH_SECBB1R4_SEC28_Pos)           /*!< 0x10000000 */
#define FLASH_SECBB1R4_SEC28                      FLASH_SECBB1R4_SEC28_Msk                      /*!< Page 124 in bank 1 block-based secure */
#define FLASH_SECBB1R4_SEC29_Pos                  (29UL)
#define FLASH_SECBB1R4_SEC29_Msk                  (0x1UL << FLASH_SECBB1R4_SEC29_Pos)           /*!< 0x20000000 */
#define FLASH_SECBB1R4_SEC29                      FLASH_SECBB1R4_SEC29_Msk                      /*!< Page 125 in bank 1 block-based secure */
#define FLASH_SECBB1R4_SEC30_Pos                  (30UL)
#define FLASH_SECBB1R4_SEC30_Msk                  (0x1UL << FLASH_SECBB1R4_SEC30_Pos)           /*!< 0x40000000 */
#define FLASH_SECBB1R4_SEC30                      FLASH_SECBB1R4_SEC30_Msk                      /*!< Page 126 in bank 1 block-based secure */
#define FLASH_SECBB1R4_SEC31_Pos                  (31UL)
#define FLASH_SECBB1R4_SEC31_Msk                  (0x1UL << FLASH_SECBB1R4_SEC31_Pos)           /*!< 0x80000000 */
#define FLASH_SECBB1R4_SEC31                      FLASH_SECBB1R4_SEC31_Msk                      /*!< Page 127 in bank 1 block-based secure */

/*******************  Bit definition for FLASH_SECBB2R1 register  ******************/
#define FLASH_SECBB2R1_SEC0_Pos                   (0UL)
#define FLASH_SECBB2R1_SEC0_Msk                   (0x1UL << FLASH_SECBB2R1_SEC0_Pos)            /*!< 0x00000001 */
#define FLASH_SECBB2R1_SEC0                       FLASH_SECBB2R1_SEC0_Msk                       /*!< Page 0 in bank 2 block-based secure */
#define FLASH_SECBB2R1_SEC1_Pos                   (1UL)
#define FLASH_SECBB2R1_SEC1_Msk                   (0x1UL << FLASH_SECBB2R1_SEC1_Pos)            /*!< 0x00000002 */
#define FLASH_SECBB2R1_SEC1                       FLASH_SECBB2R1_SEC1_Msk                       /*!< Page 1 in bank 2 block-based secure */
#define FLASH_SECBB2R1_SEC2_Pos                   (2UL)
#define FLASH_SECBB2R1_SEC2_Msk                   (0x1UL << FLASH_SECBB2R1_SEC2_Pos)            /*!< 0x00000004 */
#define FLASH_SECBB2R1_SEC2                       FLASH_SECBB2R1_SEC2_Msk                       /*!< Page 2 in bank 2 block-based secure */
#define FLASH_SECBB2R1_SEC3_Pos                   (3UL)
#define FLASH_SECBB2R1_SEC3_Msk                   (0x1UL << FLASH_SECBB2R1_SEC3_Pos)            /*!< 0x00000008 */
#define FLASH_SECBB2R1_SEC3                       FLASH_SECBB2R1_SEC3_Msk                       /*!< Page 3 in bank 2 block-based secure */
#define FLASH_SECBB2R1_SEC4_Pos                   (4UL)
#define FLASH_SECBB2R1_SEC4_Msk                   (0x1UL << FLASH_SECBB2R1_SEC4_Pos)            /*!< 0x00000010 */
#define FLASH_SECBB2R1_SEC4                       FLASH_SECBB2R1_SEC4_Msk                       /*!< Page 4 in bank 2 block-based secure */
#define FLASH_SECBB2R1_SEC5_Pos                   (5UL)
#define FLASH_SECBB2R1_SEC5_Msk                   (0x1UL << FLASH_SECBB2R1_SEC5_Pos)            /*!< 0x00000020 */
#define FLASH_SECBB2R1_SEC5                       FLASH_SECBB2R1_SEC5_Msk                       /*!< Page 5 in bank 2 block-based secure */
#define FLASH_SECBB2R1_SEC6_Pos                   (6UL)
#define FLASH_SECBB2R1_SEC6_Msk                   (0x1UL << FLASH_SECBB2R1_SEC6_Pos)            /*!< 0x00000040 */
#define FLASH_SECBB2R1_SEC6                       FLASH_SECBB2R1_SEC6_Msk                       /*!< Page 6 in bank 2 block-based secure */
#define FLASH_SECBB2R1_SEC7_Pos                   (7UL)
#define FLASH_SECBB2R1_SEC7_Msk                   (0x1UL << FLASH_SECBB2R1_SEC7_Pos)            /*!< 0x00000080 */
#define FLASH_SECBB2R1_SEC7                       FLASH_SECBB2R1_SEC7_Msk                       /*!< Page 7 in bank 2 block-based secure */
#define FLASH_SECBB2R1_SEC8_Pos                   (8UL)
#define FLASH_SECBB2R1_SEC8_Msk                   (0x1UL << FLASH_SECBB2R1_SEC8_Pos)            /*!< 0x00000100 */
#define FLASH_SECBB2R1_SEC8                       FLASH_SECBB2R1_SEC8_Msk                       /*!< Page 8 in bank 2 block-based secure */
#define FLASH_SECBB2R1_SEC9_Pos                   (9UL)
#define FLASH_SECBB2R1_SEC9_Msk                   (0x1UL << FLASH_SECBB2R1_SEC9_Pos)            /*!< 0x00000200 */
#define FLASH_SECBB2R1_SEC9                       FLASH_SECBB2R1_SEC9_Msk                       /*!< Page 9 in bank 2 block-based secure */
#define FLASH_SECBB2R1_SEC10_Pos                  (10UL)
#define FLASH_SECBB2R1_SEC10_Msk                  (0x1UL << FLASH_SECBB2R1_SEC10_Pos)           /*!< 0x00000400 */
#define FLASH_SECBB2R1_SEC10                      FLASH_SECBB2R1_SEC10_Msk                      /*!< Page 10 in bank 2 block-based secure */
#define FLASH_SECBB2R1_SEC11_Pos                  (11UL)
#define FLASH_SECBB2R1_SEC11_Msk                  (0x1UL << FLASH_SECBB2R1_SEC11_Pos)           /*!< 0x00000800 */
#define FLASH_SECBB2R1_SEC11                      FLASH_SECBB2R1_SEC11_Msk                      /*!< Page 11 in bank 2 block-based secure */
#define FLASH_SECBB2R1_SEC12_Pos                  (12UL)
#define FLASH_SECBB2R1_SEC12_Msk                  (0x1UL << FLASH_SECBB2R1_SEC12_Pos)           /*!< 0x00001000 */
#define FLASH_SECBB2R1_SEC12                      FLASH_SECBB2R1_SEC12_Msk                      /*!< Page 12 in bank 2 block-based secure */
#define FLASH_SECBB2R1_SEC13_Pos                  (13UL)
#define FLASH_SECBB2R1_SEC13_Msk                  (0x1UL << FLASH_SECBB2R1_SEC13_Pos)           /*!< 0x00002000 */
#define FLASH_SECBB2R1_SEC13                      FLASH_SECBB2R1_SEC13_Msk                      /*!< Page 13 in bank 2 block-based secure */
#define FLASH_SECBB2R1_SEC14_Pos                  (14UL)
#define FLASH_SECBB2R1_SEC14_Msk                  (0x1UL << FLASH_SECBB2R1_SEC14_Pos)           /*!< 0x00004000 */
#define FLASH_SECBB2R1_SEC14                      FLASH_SECBB2R1_SEC14_Msk                      /*!< Page 14 in bank 2 block-based secure */
#define FLASH_SECBB2R1_SEC15_Pos                  (15UL)
#define FLASH_SECBB2R1_SEC15_Msk                  (0x1UL << FLASH_SECBB2R1_SEC15_Pos)           /*!< 0x00008000 */
#define FLASH_SECBB2R1_SEC15                      FLASH_SECBB2R1_SEC15_Msk                      /*!< Page 15 in bank 2 block-based secure */
#define FLASH_SECBB2R1_SEC16_Pos                  (16UL)
#define FLASH_SECBB2R1_SEC16_Msk                  (0x1UL << FLASH_SECBB2R1_SEC16_Pos)           /*!< 0x00010000 */
#define FLASH_SECBB2R1_SEC16                      FLASH_SECBB2R1_SEC16_Msk                      /*!< Page 16 in bank 2 block-based secure */
#define FLASH_SECBB2R1_SEC17_Pos                  (17UL)
#define FLASH_SECBB2R1_SEC17_Msk                  (0x1UL << FLASH_SECBB2R1_SEC17_Pos)           /*!< 0x00020000 */
#define FLASH_SECBB2R1_SEC17                      FLASH_SECBB2R1_SEC17_Msk                      /*!< Page 17 in bank 2 block-based secure */
#define FLASH_SECBB2R1_SEC18_Pos                  (18UL)
#define FLASH_SECBB2R1_SEC18_Msk                  (0x1UL << FLASH_SECBB2R1_SEC18_Pos)           /*!< 0x00040000 */
#define FLASH_SECBB2R1_SEC18                      FLASH_SECBB2R1_SEC18_Msk                      /*!< Page 18 in bank 2 block-based secure */
#define FLASH_SECBB2R1_SEC19_Pos                  (19UL)
#define FLASH_SECBB2R1_SEC19_Msk                  (0x1UL << FLASH_SECBB2R1_SEC19_Pos)           /*!< 0x00080000 */
#define FLASH_SECBB2R1_SEC19                      FLASH_SECBB2R1_SEC19_Msk                      /*!< Page 19 in bank 2 block-based secure */
#define FLASH_SECBB2R1_SEC20_Pos                  (20UL)
#define FLASH_SECBB2R1_SEC20_Msk                  (0x1UL << FLASH_SECBB2R1_SEC20_Pos)           /*!< 0x00100000 */
#define FLASH_SECBB2R1_SEC20                      FLASH_SECBB2R1_SEC20_Msk                      /*!< Page 20 in bank 2 block-based secure */
#define FLASH_SECBB2R1_SEC21_Pos                  (21UL)
#define FLASH_SECBB2R1_SEC21_Msk                  (0x1UL << FLASH_SECBB2R1_SEC21_Pos)           /*!< 0x00200000 */
#define FLASH_SECBB2R1_SEC21                      FLASH_SECBB2R1_SEC21_Msk                      /*!< Page 21 in bank 2 block-based secure */
#define FLASH_SECBB2R1_SEC22_Pos                  (22UL)
#define FLASH_SECBB2R1_SEC22_Msk                  (0x1UL << FLASH_SECBB2R1_SEC22_Pos)           /*!< 0x00400000 */
#define FLASH_SECBB2R1_SEC22                      FLASH_SECBB2R1_SEC22_Msk                      /*!< Page 22 in bank 2 block-based secure */
#define FLASH_SECBB2R1_SEC23_Pos                  (23UL)
#define FLASH_SECBB2R1_SEC23_Msk                  (0x1UL << FLASH_SECBB2R1_SEC23_Pos)           /*!< 0x00800000 */
#define FLASH_SECBB2R1_SEC23                      FLASH_SECBB2R1_SEC23_Msk                      /*!< Page 23 in bank 2 block-based secure */
#define FLASH_SECBB2R1_SEC24_Pos                  (24UL)
#define FLASH_SECBB2R1_SEC24_Msk                  (0x1UL << FLASH_SECBB2R1_SEC24_Pos)           /*!< 0x01000000 */
#define FLASH_SECBB2R1_SEC24                      FLASH_SECBB2R1_SEC24_Msk                      /*!< Page 24 in bank 2 block-based secure */
#define FLASH_SECBB2R1_SEC25_Pos                  (25UL)
#define FLASH_SECBB2R1_SEC25_Msk                  (0x1UL << FLASH_SECBB2R1_SEC25_Pos)           /*!< 0x02000000 */
#define FLASH_SECBB2R1_SEC25                      FLASH_SECBB2R1_SEC25_Msk                      /*!< Page 25 in bank 2 block-based secure */
#define FLASH_SECBB2R1_SEC26_Pos                  (26UL)
#define FLASH_SECBB2R1_SEC26_Msk                  (0x1UL << FLASH_SECBB2R1_SEC26_Pos)           /*!< 0x04000000 */
#define FLASH_SECBB2R1_SEC26                      FLASH_SECBB2R1_SEC26_Msk                      /*!< Page 26 in bank 2 block-based secure */
#define FLASH_SECBB2R1_SEC27_Pos                  (27UL)
#define FLASH_SECBB2R1_SEC27_Msk                  (0x1UL << FLASH_SECBB2R1_SEC27_Pos)           /*!< 0x08000000 */
#define FLASH_SECBB2R1_SEC27                      FLASH_SECBB2R1_SEC27_Msk                      /*!< Page 27 in bank 2 block-based secure */
#define FLASH_SECBB2R1_SEC28_Pos                  (28UL)
#define FLASH_SECBB2R1_SEC28_Msk                  (0x1UL << FLASH_SECBB2R1_SEC28_Pos)           /*!< 0x10000000 */
#define FLASH_SECBB2R1_SEC28                      FLASH_SECBB2R1_SEC28_Msk                      /*!< Page 28 in bank 2 block-based secure */
#define FLASH_SECBB2R1_SEC29_Pos                  (29UL)
#define FLASH_SECBB2R1_SEC29_Msk                  (0x1UL << FLASH_SECBB2R1_SEC29_Pos)           /*!< 0x20000000 */
#define FLASH_SECBB2R1_SEC29                      FLASH_SECBB2R1_SEC29_Msk                      /*!< Page 29 in bank 2 block-based secure */
#define FLASH_SECBB2R1_SEC30_Pos                  (30UL)
#define FLASH_SECBB2R1_SEC30_Msk                  (0x1UL << FLASH_SECBB2R1_SEC30_Pos)           /*!< 0x40000000 */
#define FLASH_SECBB2R1_SEC30                      FLASH_SECBB2R1_SEC30_Msk                      /*!< Page 30 in bank 2 block-based secure */
#define FLASH_SECBB2R1_SEC31_Pos                  (31UL)
#define FLASH_SECBB2R1_SEC31_Msk                  (0x1UL << FLASH_SECBB2R1_SEC31_Pos)           /*!< 0x80000000 */
#define FLASH_SECBB2R1_SEC31                      FLASH_SECBB2R1_SEC31_Msk                      /*!< Page 31 in bank 2 block-based secure */

/*******************  Bit definition for FLASH_SECBB2R2 register  ******************/
#define FLASH_SECBB2R2_SEC0_Pos                   (0UL)
#define FLASH_SECBB2R2_SEC0_Msk                   (0x1UL << FLASH_SECBB2R2_SEC0_Pos)            /*!< 0x00000001 */
#define FLASH_SECBB2R2_SEC0                       FLASH_SECBB2R2_SEC0_Msk                       /*!< Page 32 in bank 2 block-based secure */
#define FLASH_SECBB2R2_SEC1_Pos                   (1UL)
#define FLASH_SECBB2R2_SEC1_Msk                   (0x1UL << FLASH_SECBB2R2_SEC1_Pos)            /*!< 0x00000002 */
#define FLASH_SECBB2R2_SEC1                       FLASH_SECBB2R2_SEC1_Msk                       /*!< Page 33 in bank 2 block-based secure */
#define FLASH_SECBB2R2_SEC2_Pos                   (2UL)
#define FLASH_SECBB2R2_SEC2_Msk                   (0x1UL << FLASH_SECBB2R2_SEC2_Pos)            /*!< 0x00000004 */
#define FLASH_SECBB2R2_SEC2                       FLASH_SECBB2R2_SEC2_Msk                       /*!< Page 34 in bank 2 block-based secure */
#define FLASH_SECBB2R2_SEC3_Pos                   (3UL)
#define FLASH_SECBB2R2_SEC3_Msk                   (0x1UL << FLASH_SECBB2R2_SEC3_Pos)            /*!< 0x00000008 */
#define FLASH_SECBB2R2_SEC3                       FLASH_SECBB2R2_SEC3_Msk                       /*!< Page 35 in bank 2 block-based secure */
#define FLASH_SECBB2R2_SEC4_Pos                   (4UL)
#define FLASH_SECBB2R2_SEC4_Msk                   (0x1UL << FLASH_SECBB2R2_SEC4_Pos)            /*!< 0x00000010 */
#define FLASH_SECBB2R2_SEC4                       FLASH_SECBB2R2_SEC4_Msk                       /*!< Page 36 in bank 2 block-based secure */
#define FLASH_SECBB2R2_SEC5_Pos                   (5UL)
#define FLASH_SECBB2R2_SEC5_Msk                   (0x1UL << FLASH_SECBB2R2_SEC5_Pos)            /*!< 0x00000020 */
#define FLASH_SECBB2R2_SEC5                       FLASH_SECBB2R2_SEC5_Msk                       /*!< Page 37 in bank 2 block-based secure */
#define FLASH_SECBB2R2_SEC6_Pos                   (6UL)
#define FLASH_SECBB2R2_SEC6_Msk                   (0x1UL << FLASH_SECBB2R2_SEC6_Pos)            /*!< 0x00000040 */
#define FLASH_SECBB2R2_SEC6                       FLASH_SECBB2R2_SEC6_Msk                       /*!< Page 38 in bank 2 block-based secure */
#define FLASH_SECBB2R2_SEC7_Pos                   (7UL)
#define FLASH_SECBB2R2_SEC7_Msk                   (0x1UL << FLASH_SECBB2R2_SEC7_Pos)            /*!< 0x00000080 */
#define FLASH_SECBB2R2_SEC7                       FLASH_SECBB2R2_SEC7_Msk                       /*!< Page 39 in bank 2 block-based secure */
#define FLASH_SECBB2R2_SEC8_Pos                   (8UL)
#define FLASH_SECBB2R2_SEC8_Msk                   (0x1UL << FLASH_SECBB2R2_SEC8_Pos)            /*!< 0x00000100 */
#define FLASH_SECBB2R2_SEC8                       FLASH_SECBB2R2_SEC8_Msk                       /*!< Page 40 in bank 2 block-based secure */
#define FLASH_SECBB2R2_SEC9_Pos                   (9UL)
#define FLASH_SECBB2R2_SEC9_Msk                   (0x1UL << FLASH_SECBB2R2_SEC9_Pos)            /*!< 0x00000200 */
#define FLASH_SECBB2R2_SEC9                       FLASH_SECBB2R2_SEC9_Msk                       /*!< Page 41 in bank 2 block-based secure */
#define FLASH_SECBB2R2_SEC10_Pos                  (10UL)
#define FLASH_SECBB2R2_SEC10_Msk                  (0x1UL << FLASH_SECBB2R2_SEC10_Pos)           /*!< 0x00000400 */
#define FLASH_SECBB2R2_SEC10                      FLASH_SECBB2R2_SEC10_Msk                      /*!< Page 42 in bank 2 block-based secure */
#define FLASH_SECBB2R2_SEC11_Pos                  (11UL)
#define FLASH_SECBB2R2_SEC11_Msk                  (0x1UL << FLASH_SECBB2R2_SEC11_Pos)           /*!< 0x00000800 */
#define FLASH_SECBB2R2_SEC11                      FLASH_SECBB2R2_SEC11_Msk                      /*!< Page 43 in bank 2 block-based secure */
#define FLASH_SECBB2R2_SEC12_Pos                  (12UL)
#define FLASH_SECBB2R2_SEC12_Msk                  (0x1UL << FLASH_SECBB2R2_SEC12_Pos)           /*!< 0x00001000 */
#define FLASH_SECBB2R2_SEC12                      FLASH_SECBB2R2_SEC12_Msk                      /*!< Page 44 in bank 2 block-based secure */
#define FLASH_SECBB2R2_SEC13_Pos                  (13UL)
#define FLASH_SECBB2R2_SEC13_Msk                  (0x1UL << FLASH_SECBB2R2_SEC13_Pos)           /*!< 0x00002000 */
#define FLASH_SECBB2R2_SEC13                      FLASH_SECBB2R2_SEC13_Msk                      /*!< Page 45 in bank 2 block-based secure */
#define FLASH_SECBB2R2_SEC14_Pos                  (14UL)
#define FLASH_SECBB2R2_SEC14_Msk                  (0x1UL << FLASH_SECBB2R2_SEC14_Pos)           /*!< 0x00004000 */
#define FLASH_SECBB2R2_SEC14                      FLASH_SECBB2R2_SEC14_Msk                      /*!< Page 46 in bank 2 block-based secure */
#define FLASH_SECBB2R2_SEC15_Pos                  (15UL)
#define FLASH_SECBB2R2_SEC15_Msk                  (0x1UL << FLASH_SECBB2R2_SEC15_Pos)           /*!< 0x00008000 */
#define FLASH_SECBB2R2_SEC15                      FLASH_SECBB2R2_SEC15_Msk                      /*!< Page 47 in bank 2 block-based secure */
#define FLASH_SECBB2R2_SEC16_Pos                  (16UL)
#define FLASH_SECBB2R2_SEC16_Msk                  (0x1UL << FLASH_SECBB2R2_SEC16_Pos)           /*!< 0x00010000 */
#define FLASH_SECBB2R2_SEC16                      FLASH_SECBB2R2_SEC16_Msk                      /*!< Page 48 in bank 2 block-based secure */
#define FLASH_SECBB2R2_SEC17_Pos                  (17UL)
#define FLASH_SECBB2R2_SEC17_Msk                  (0x1UL << FLASH_SECBB2R2_SEC17_Pos)           /*!< 0x00020000 */
#define FLASH_SECBB2R2_SEC17                      FLASH_SECBB2R2_SEC17_Msk                      /*!< Page 49 in bank 2 block-based secure */
#define FLASH_SECBB2R2_SEC18_Pos                  (18UL)
#define FLASH_SECBB2R2_SEC18_Msk                  (0x1UL << FLASH_SECBB2R2_SEC18_Pos)           /*!< 0x00040000 */
#define FLASH_SECBB2R2_SEC18                      FLASH_SECBB2R2_SEC18_Msk                      /*!< Page 50 in bank 2 block-based secure */
#define FLASH_SECBB2R2_SEC19_Pos                  (19UL)
#define FLASH_SECBB2R2_SEC19_Msk                  (0x1UL << FLASH_SECBB2R2_SEC19_Pos)           /*!< 0x00080000 */
#define FLASH_SECBB2R2_SEC19                      FLASH_SECBB2R2_SEC19_Msk                      /*!< Page 51 in bank 2 block-based secure */
#define FLASH_SECBB2R2_SEC20_Pos                  (20UL)
#define FLASH_SECBB2R2_SEC20_Msk                  (0x1UL << FLASH_SECBB2R2_SEC20_Pos)           /*!< 0x00100000 */
#define FLASH_SECBB2R2_SEC20                      FLASH_SECBB2R2_SEC20_Msk                      /*!< Page 52 in bank 2 block-based secure */
#define FLASH_SECBB2R2_SEC21_Pos                  (21UL)
#define FLASH_SECBB2R2_SEC21_Msk                  (0x1UL << FLASH_SECBB2R2_SEC21_Pos)           /*!< 0x00200000 */
#define FLASH_SECBB2R2_SEC21                      FLASH_SECBB2R2_SEC21_Msk                      /*!< Page 53 in bank 2 block-based secure */
#define FLASH_SECBB2R2_SEC22_Pos                  (22UL)
#define FLASH_SECBB2R2_SEC22_Msk                  (0x1UL << FLASH_SECBB2R2_SEC22_Pos)           /*!< 0x00400000 */
#define FLASH_SECBB2R2_SEC22                      FLASH_SECBB2R2_SEC22_Msk                      /*!< Page 54 in bank 2 block-based secure */
#define FLASH_SECBB2R2_SEC23_Pos                  (23UL)
#define FLASH_SECBB2R2_SEC23_Msk                  (0x1UL << FLASH_SECBB2R2_SEC23_Pos)           /*!< 0x00800000 */
#define FLASH_SECBB2R2_SEC23                      FLASH_SECBB2R2_SEC23_Msk                      /*!< Page 55 in bank 2 block-based secure */
#define FLASH_SECBB2R2_SEC24_Pos                  (24UL)
#define FLASH_SECBB2R2_SEC24_Msk                  (0x1UL << FLASH_SECBB2R2_SEC24_Pos)           /*!< 0x01000000 */
#define FLASH_SECBB2R2_SEC24                      FLASH_SECBB2R2_SEC24_Msk                      /*!< Page 56 in bank 2 block-based secure */
#define FLASH_SECBB2R2_SEC25_Pos                  (25UL)
#define FLASH_SECBB2R2_SEC25_Msk                  (0x1UL << FLASH_SECBB2R2_SEC25_Pos)           /*!< 0x02000000 */
#define FLASH_SECBB2R2_SEC25                      FLASH_SECBB2R2_SEC25_Msk                      /*!< Page 57 in bank 2 block-based secure */
#define FLASH_SECBB2R2_SEC26_Pos                  (26UL)
#define FLASH_SECBB2R2_SEC26_Msk                  (0x1UL << FLASH_SECBB2R2_SEC26_Pos)           /*!< 0x04000000 */
#define FLASH_SECBB2R2_SEC26                      FLASH_SECBB2R2_SEC26_Msk                      /*!< Page 58 in bank 2 block-based secure */
#define FLASH_SECBB2R2_SEC27_Pos                  (27UL)
#define FLASH_SECBB2R2_SEC27_Msk                  (0x1UL << FLASH_SECBB2R2_SEC27_Pos)           /*!< 0x08000000 */
#define FLASH_SECBB2R2_SEC27                      FLASH_SECBB2R2_SEC27_Msk                      /*!< Page 59 in bank 2 block-based secure */
#define FLASH_SECBB2R2_SEC28_Pos                  (28UL)
#define FLASH_SECBB2R2_SEC28_Msk                  (0x1UL << FLASH_SECBB2R2_SEC28_Pos)           /*!< 0x10000000 */
#define FLASH_SECBB2R2_SEC28                      FLASH_SECBB2R2_SEC28_Msk                      /*!< Page 60 in bank 2 block-based secure */
#define FLASH_SECBB2R2_SEC29_Pos                  (29UL)
#define FLASH_SECBB2R2_SEC29_Msk                  (0x1UL << FLASH_SECBB2R2_SEC29_Pos)           /*!< 0x20000000 */
#define FLASH_SECBB2R2_SEC29                      FLASH_SECBB2R2_SEC29_Msk                      /*!< Page 61 in bank 2 block-based secure */
#define FLASH_SECBB2R2_SEC30_Pos                  (30UL)
#define FLASH_SECBB2R2_SEC30_Msk                  (0x1UL << FLASH_SECBB2R2_SEC30_Pos)           /*!< 0x40000000 */
#define FLASH_SECBB2R2_SEC30                      FLASH_SECBB2R2_SEC30_Msk                      /*!< Page 62 in bank 2 block-based secure */
#define FLASH_SECBB2R2_SEC31_Pos                  (31UL)
#define FLASH_SECBB2R2_SEC31_Msk                  (0x1UL << FLASH_SECBB2R2_SEC31_Pos)           /*!< 0x80000000 */
#define FLASH_SECBB2R2_SEC31                      FLASH_SECBB2R2_SEC31_Msk                      /*!< Page 63 in bank 2 block-based secure */

/*******************  Bit definition for FLASH_SECBB2R3 register  ******************/
#define FLASH_SECBB2R3_SEC0_Pos                   (0UL)
#define FLASH_SECBB2R3_SEC0_Msk                   (0x1UL << FLASH_SECBB2R3_SEC0_Pos)            /*!< 0x00000001 */
#define FLASH_SECBB2R3_SEC0                       FLASH_SECBB2R3_SEC0_Msk                       /*!< Page 64 in bank 2 block-based secure */
#define FLASH_SECBB2R3_SEC1_Pos                   (1UL)
#define FLASH_SECBB2R3_SEC1_Msk                   (0x1UL << FLASH_SECBB2R3_SEC1_Pos)            /*!< 0x00000002 */
#define FLASH_SECBB2R3_SEC1                       FLASH_SECBB2R3_SEC1_Msk                       /*!< Page 65 in bank 2 block-based secure */
#define FLASH_SECBB2R3_SEC2_Pos                   (2UL)
#define FLASH_SECBB2R3_SEC2_Msk                   (0x1UL << FLASH_SECBB2R3_SEC2_Pos)            /*!< 0x00000004 */
#define FLASH_SECBB2R3_SEC2                       FLASH_SECBB2R3_SEC2_Msk                       /*!< Page 66 in bank 2 block-based secure */
#define FLASH_SECBB2R3_SEC3_Pos                   (3UL)
#define FLASH_SECBB2R3_SEC3_Msk                   (0x1UL << FLASH_SECBB2R3_SEC3_Pos)            /*!< 0x00000008 */
#define FLASH_SECBB2R3_SEC3                       FLASH_SECBB2R3_SEC3_Msk                       /*!< Page 67 in bank 2 block-based secure */
#define FLASH_SECBB2R3_SEC4_Pos                   (4UL)
#define FLASH_SECBB2R3_SEC4_Msk                   (0x1UL << FLASH_SECBB2R3_SEC4_Pos)            /*!< 0x00000010 */
#define FLASH_SECBB2R3_SEC4                       FLASH_SECBB2R3_SEC4_Msk                       /*!< Page 68 in bank 2 block-based secure */
#define FLASH_SECBB2R3_SEC5_Pos                   (5UL)
#define FLASH_SECBB2R3_SEC5_Msk                   (0x1UL << FLASH_SECBB2R3_SEC5_Pos)            /*!< 0x00000020 */
#define FLASH_SECBB2R3_SEC5                       FLASH_SECBB2R3_SEC5_Msk                       /*!< Page 69 in bank 2 block-based secure */
#define FLASH_SECBB2R3_SEC6_Pos                   (6UL)
#define FLASH_SECBB2R3_SEC6_Msk                   (0x1UL << FLASH_SECBB2R3_SEC6_Pos)            /*!< 0x00000040 */
#define FLASH_SECBB2R3_SEC6                       FLASH_SECBB2R3_SEC6_Msk                       /*!< Page 70 in bank 2 block-based secure */
#define FLASH_SECBB2R3_SEC7_Pos                   (7UL)
#define FLASH_SECBB2R3_SEC7_Msk                   (0x1UL << FLASH_SECBB2R3_SEC7_Pos)            /*!< 0x00000080 */
#define FLASH_SECBB2R3_SEC7                       FLASH_SECBB2R3_SEC7_Msk                       /*!< Page 71 in bank 2 block-based secure */
#define FLASH_SECBB2R3_SEC8_Pos                   (8UL)
#define FLASH_SECBB2R3_SEC8_Msk                   (0x1UL << FLASH_SECBB2R3_SEC8_Pos)            /*!< 0x00000100 */
#define FLASH_SECBB2R3_SEC8                       FLASH_SECBB2R3_SEC8_Msk                       /*!< Page 72 in bank 2 block-based secure */
#define FLASH_SECBB2R3_SEC9_Pos                   (9UL)
#define FLASH_SECBB2R3_SEC9_Msk                   (0x1UL << FLASH_SECBB2R3_SEC9_Pos)            /*!< 0x00000200 */
#define FLASH_SECBB2R3_SEC9                       FLASH_SECBB2R3_SEC9_Msk                       /*!< Page 73 in bank 2 block-based secure */
#define FLASH_SECBB2R3_SEC10_Pos                  (10UL)
#define FLASH_SECBB2R3_SEC10_Msk                  (0x1UL << FLASH_SECBB2R3_SEC10_Pos)           /*!< 0x00000400 */
#define FLASH_SECBB2R3_SEC10                      FLASH_SECBB2R3_SEC10_Msk                      /*!< Page 74 in bank 2 block-based secure */
#define FLASH_SECBB2R3_SEC11_Pos                  (11UL)
#define FLASH_SECBB2R3_SEC11_Msk                  (0x1UL << FLASH_SECBB2R3_SEC11_Pos)           /*!< 0x00000800 */
#define FLASH_SECBB2R3_SEC11                      FLASH_SECBB2R3_SEC11_Msk                      /*!< Page 75 in bank 2 block-based secure */
#define FLASH_SECBB2R3_SEC12_Pos                  (12UL)
#define FLASH_SECBB2R3_SEC12_Msk                  (0x1UL << FLASH_SECBB2R3_SEC12_Pos)           /*!< 0x00001000 */
#define FLASH_SECBB2R3_SEC12                      FLASH_SECBB2R3_SEC12_Msk                      /*!< Page 76 in bank 2 block-based secure */
#define FLASH_SECBB2R3_SEC13_Pos                  (13UL)
#define FLASH_SECBB2R3_SEC13_Msk                  (0x1UL << FLASH_SECBB2R3_SEC13_Pos)           /*!< 0x00002000 */
#define FLASH_SECBB2R3_SEC13                      FLASH_SECBB2R3_SEC13_Msk                      /*!< Page 77 in bank 2 block-based secure */
#define FLASH_SECBB2R3_SEC14_Pos                  (14UL)
#define FLASH_SECBB2R3_SEC14_Msk                  (0x1UL << FLASH_SECBB2R3_SEC14_Pos)           /*!< 0x00004000 */
#define FLASH_SECBB2R3_SEC14                      FLASH_SECBB2R3_SEC14_Msk                      /*!< Page 78 in bank 2 block-based secure */
#define FLASH_SECBB2R3_SEC15_Pos                  (15UL)
#define FLASH_SECBB2R3_SEC15_Msk                  (0x1UL << FLASH_SECBB2R3_SEC15_Pos)           /*!< 0x00008000 */
#define FLASH_SECBB2R3_SEC15                      FLASH_SECBB2R3_SEC15_Msk                      /*!< Page 79 in bank 2 block-based secure */
#define FLASH_SECBB2R3_SEC16_Pos                  (16UL)
#define FLASH_SECBB2R3_SEC16_Msk                  (0x1UL << FLASH_SECBB2R3_SEC16_Pos)           /*!< 0x00010000 */
#define FLASH_SECBB2R3_SEC16                      FLASH_SECBB2R3_SEC16_Msk                      /*!< Page 80 in bank 2 block-based secure */
#define FLASH_SECBB2R3_SEC17_Pos                  (17UL)
#define FLASH_SECBB2R3_SEC17_Msk                  (0x1UL << FLASH_SECBB2R3_SEC17_Pos)           /*!< 0x00020000 */
#define FLASH_SECBB2R3_SEC17                      FLASH_SECBB2R3_SEC17_Msk                      /*!< Page 81 in bank 2 block-based secure */
#define FLASH_SECBB2R3_SEC18_Pos                  (18UL)
#define FLASH_SECBB2R3_SEC18_Msk                  (0x1UL << FLASH_SECBB2R3_SEC18_Pos)           /*!< 0x00040000 */
#define FLASH_SECBB2R3_SEC18                      FLASH_SECBB2R3_SEC18_Msk                      /*!< Page 82 in bank 2 block-based secure */
#define FLASH_SECBB2R3_SEC19_Pos                  (19UL)
#define FLASH_SECBB2R3_SEC19_Msk                  (0x1UL << FLASH_SECBB2R3_SEC19_Pos)           /*!< 0x00080000 */
#define FLASH_SECBB2R3_SEC19                      FLASH_SECBB2R3_SEC19_Msk                      /*!< Page 83 in bank 2 block-based secure */
#define FLASH_SECBB2R3_SEC20_Pos                  (20UL)
#define FLASH_SECBB2R3_SEC20_Msk                  (0x1UL << FLASH_SECBB2R3_SEC20_Pos)           /*!< 0x00100000 */
#define FLASH_SECBB2R3_SEC20                      FLASH_SECBB2R3_SEC20_Msk                      /*!< Page 84 in bank 2 block-based secure */
#define FLASH_SECBB2R3_SEC21_Pos                  (21UL)
#define FLASH_SECBB2R3_SEC21_Msk                  (0x1UL << FLASH_SECBB2R3_SEC21_Pos)           /*!< 0x00200000 */
#define FLASH_SECBB2R3_SEC21                      FLASH_SECBB2R3_SEC21_Msk                      /*!< Page 85 in bank 2 block-based secure */
#define FLASH_SECBB2R3_SEC22_Pos                  (22UL)
#define FLASH_SECBB2R3_SEC22_Msk                  (0x1UL << FLASH_SECBB2R3_SEC22_Pos)           /*!< 0x00400000 */
#define FLASH_SECBB2R3_SEC22                      FLASH_SECBB2R3_SEC22_Msk                      /*!< Page 86 in bank 2 block-based secure */
#define FLASH_SECBB2R3_SEC23_Pos                  (23UL)
#define FLASH_SECBB2R3_SEC23_Msk                  (0x1UL << FLASH_SECBB2R3_SEC23_Pos)           /*!< 0x00800000 */
#define FLASH_SECBB2R3_SEC23                      FLASH_SECBB2R3_SEC23_Msk                      /*!< Page 87 in bank 2 block-based secure */
#define FLASH_SECBB2R3_SEC24_Pos                  (24UL)
#define FLASH_SECBB2R3_SEC24_Msk                  (0x1UL << FLASH_SECBB2R3_SEC24_Pos)           /*!< 0x01000000 */
#define FLASH_SECBB2R3_SEC24                      FLASH_SECBB2R3_SEC24_Msk                      /*!< Page 88 in bank 2 block-based secure */
#define FLASH_SECBB2R3_SEC25_Pos                  (25UL)
#define FLASH_SECBB2R3_SEC25_Msk                  (0x1UL << FLASH_SECBB2R3_SEC25_Pos)           /*!< 0x02000000 */
#define FLASH_SECBB2R3_SEC25                      FLASH_SECBB2R3_SEC25_Msk                      /*!< Page 89 in bank 2 block-based secure */
#define FLASH_SECBB2R3_SEC26_Pos                  (26UL)
#define FLASH_SECBB2R3_SEC26_Msk                  (0x1UL << FLASH_SECBB2R3_SEC26_Pos)           /*!< 0x04000000 */
#define FLASH_SECBB2R3_SEC26                      FLASH_SECBB2R3_SEC26_Msk                      /*!< Page 90 in bank 2 block-based secure */
#define FLASH_SECBB2R3_SEC27_Pos                  (27UL)
#define FLASH_SECBB2R3_SEC27_Msk                  (0x1UL << FLASH_SECBB2R3_SEC27_Pos)           /*!< 0x08000000 */
#define FLASH_SECBB2R3_SEC27                      FLASH_SECBB2R3_SEC27_Msk                      /*!< Page 91 in bank 2 block-based secure */
#define FLASH_SECBB2R3_SEC28_Pos                  (28UL)
#define FLASH_SECBB2R3_SEC28_Msk                  (0x1UL << FLASH_SECBB2R3_SEC28_Pos)           /*!< 0x10000000 */
#define FLASH_SECBB2R3_SEC28                      FLASH_SECBB2R3_SEC28_Msk                      /*!< Page 92 in bank 2 block-based secure */
#define FLASH_SECBB2R3_SEC29_Pos                  (29UL)
#define FLASH_SECBB2R3_SEC29_Msk                  (0x1UL << FLASH_SECBB2R3_SEC29_Pos)           /*!< 0x20000000 */
#define FLASH_SECBB2R3_SEC29                      FLASH_SECBB2R3_SEC29_Msk                      /*!< Page 93 in bank 2 block-based secure */
#define FLASH_SECBB2R3_SEC30_Pos                  (30UL)
#define FLASH_SECBB2R3_SEC30_Msk                  (0x1UL << FLASH_SECBB2R3_SEC30_Pos)           /*!< 0x40000000 */
#define FLASH_SECBB2R3_SEC30                      FLASH_SECBB2R3_SEC30_Msk                      /*!< Page 94 in bank 2 block-based secure */
#define FLASH_SECBB2R3_SEC31_Pos                  (31UL)
#define FLASH_SECBB2R3_SEC31_Msk                  (0x1UL << FLASH_SECBB2R3_SEC31_Pos)           /*!< 0x80000000 */
#define FLASH_SECBB2R3_SEC31                      FLASH_SECBB2R3_SEC31_Msk                      /*!< Page 95 in bank 2 block-based secure */

/*******************  Bit definition for FLASH_SECBB2R4 register  ******************/
#define FLASH_SECBB2R4_SEC0_Pos                   (0UL)
#define FLASH_SECBB2R4_SEC0_Msk                   (0x1UL << FLASH_SECBB2R4_SEC0_Pos)            /*!< 0x00000001 */
#define FLASH_SECBB2R4_SEC0                       FLASH_SECBB2R4_SEC0_Msk                       /*!< Page 96 in bank 2 block-based secure */
#define FLASH_SECBB2R4_SEC1_Pos                   (1UL)
#define FLASH_SECBB2R4_SEC1_Msk                   (0x1UL << FLASH_SECBB2R4_SEC1_Pos)            /*!< 0x00000002 */
#define FLASH_SECBB2R4_SEC1                       FLASH_SECBB2R4_SEC1_Msk                       /*!< Page 97 in bank 2 block-based secure */
#define FLASH_SECBB2R4_SEC2_Pos                   (2UL)
#define FLASH_SECBB2R4_SEC2_Msk                   (0x1UL << FLASH_SECBB2R4_SEC2_Pos)            /*!< 0x00000004 */
#define FLASH_SECBB2R4_SEC2                       FLASH_SECBB2R4_SEC2_Msk                       /*!< Page 98 in bank 2 block-based secure */
#define FLASH_SECBB2R4_SEC3_Pos                   (3UL)
#define FLASH_SECBB2R4_SEC3_Msk                   (0x1UL << FLASH_SECBB2R4_SEC3_Pos)            /*!< 0x00000008 */
#define FLASH_SECBB2R4_SEC3                       FLASH_SECBB2R4_SEC3_Msk                       /*!< Page 99 in bank 2 block-based secure */
#define FLASH_SECBB2R4_SEC4_Pos                   (4UL)
#define FLASH_SECBB2R4_SEC4_Msk                   (0x1UL << FLASH_SECBB2R4_SEC4_Pos)            /*!< 0x00000010 */
#define FLASH_SECBB2R4_SEC4                       FLASH_SECBB2R4_SEC4_Msk                       /*!< Page 100 in bank 2 block-based secure */
#define FLASH_SECBB2R4_SEC5_Pos                   (5UL)
#define FLASH_SECBB2R4_SEC5_Msk                   (0x1UL << FLASH_SECBB2R4_SEC5_Pos)            /*!< 0x00000020 */
#define FLASH_SECBB2R4_SEC5                       FLASH_SECBB2R4_SEC5_Msk                       /*!< Page 101 in bank 2 block-based secure */
#define FLASH_SECBB2R4_SEC6_Pos                   (6UL)
#define FLASH_SECBB2R4_SEC6_Msk                   (0x1UL << FLASH_SECBB2R4_SEC6_Pos)            /*!< 0x00000040 */
#define FLASH_SECBB2R4_SEC6                       FLASH_SECBB2R4_SEC6_Msk                       /*!< Page 102 in bank 2 block-based secure */
#define FLASH_SECBB2R4_SEC7_Pos                   (7UL)
#define FLASH_SECBB2R4_SEC7_Msk                   (0x1UL << FLASH_SECBB2R4_SEC7_Pos)            /*!< 0x00000080 */
#define FLASH_SECBB2R4_SEC7                       FLASH_SECBB2R4_SEC7_Msk                       /*!< Page 103 in bank 2 block-based secure */
#define FLASH_SECBB2R4_SEC8_Pos                   (8UL)
#define FLASH_SECBB2R4_SEC8_Msk                   (0x1UL << FLASH_SECBB2R4_SEC8_Pos)            /*!< 0x00000100 */
#define FLASH_SECBB2R4_SEC8                       FLASH_SECBB2R4_SEC8_Msk                       /*!< Page 104 in bank 2 block-based secure */
#define FLASH_SECBB2R4_SEC9_Pos                   (9UL)
#define FLASH_SECBB2R4_SEC9_Msk                   (0x1UL << FLASH_SECBB2R4_SEC9_Pos)            /*!< 0x00000200 */
#define FLASH_SECBB2R4_SEC9                       FLASH_SECBB2R4_SEC9_Msk                       /*!< Page 105 in bank 2 block-based secure */
#define FLASH_SECBB2R4_SEC10_Pos                  (10UL)
#define FLASH_SECBB2R4_SEC10_Msk                  (0x1UL << FLASH_SECBB2R4_SEC10_Pos)           /*!< 0x00000400 */
#define FLASH_SECBB2R4_SEC10                      FLASH_SECBB2R4_SEC10_Msk                      /*!< Page 106 in bank 2 block-based secure */
#define FLASH_SECBB2R4_SEC11_Pos                  (11UL)
#define FLASH_SECBB2R4_SEC11_Msk                  (0x1UL << FLASH_SECBB2R4_SEC11_Pos)           /*!< 0x00000800 */
#define FLASH_SECBB2R4_SEC11                      FLASH_SECBB2R4_SEC11_Msk                      /*!< Page 107 in bank 2 block-based secure */
#define FLASH_SECBB2R4_SEC12_Pos                  (12UL)
#define FLASH_SECBB2R4_SEC12_Msk                  (0x1UL << FLASH_SECBB2R4_SEC12_Pos)           /*!< 0x00001000 */
#define FLASH_SECBB2R4_SEC12                      FLASH_SECBB2R4_SEC12_Msk                      /*!< Page 108 in bank 2 block-based secure */
#define FLASH_SECBB2R4_SEC13_Pos                  (13UL)
#define FLASH_SECBB2R4_SEC13_Msk                  (0x1UL << FLASH_SECBB2R4_SEC13_Pos)           /*!< 0x00002000 */
#define FLASH_SECBB2R4_SEC13                      FLASH_SECBB2R4_SEC13_Msk                      /*!< Page 109 in bank 2 block-based secure */
#define FLASH_SECBB2R4_SEC14_Pos                  (14UL)
#define FLASH_SECBB2R4_SEC14_Msk                  (0x1UL << FLASH_SECBB2R4_SEC14_Pos)           /*!< 0x00004000 */
#define FLASH_SECBB2R4_SEC14                      FLASH_SECBB2R4_SEC14_Msk                      /*!< Page 110 in bank 2 block-based secure */
#define FLASH_SECBB2R4_SEC15_Pos                  (15UL)
#define FLASH_SECBB2R4_SEC15_Msk                  (0x1UL << FLASH_SECBB2R4_SEC15_Pos)           /*!< 0x00008000 */
#define FLASH_SECBB2R4_SEC15                      FLASH_SECBB2R4_SEC15_Msk                      /*!< Page 111 in bank 2 block-based secure */
#define FLASH_SECBB2R4_SEC16_Pos                  (16UL)
#define FLASH_SECBB2R4_SEC16_Msk                  (0x1UL << FLASH_SECBB2R4_SEC16_Pos)           /*!< 0x00010000 */
#define FLASH_SECBB2R4_SEC16                      FLASH_SECBB2R4_SEC16_Msk                      /*!< Page 112 in bank 2 block-based secure */
#define FLASH_SECBB2R4_SEC17_Pos                  (17UL)
#define FLASH_SECBB2R4_SEC17_Msk                  (0x1UL << FLASH_SECBB2R4_SEC17_Pos)           /*!< 0x00020000 */
#define FLASH_SECBB2R4_SEC17                      FLASH_SECBB2R4_SEC17_Msk                      /*!< Page 113 in bank 2 block-based secure */
#define FLASH_SECBB2R4_SEC18_Pos                  (18UL)
#define FLASH_SECBB2R4_SEC18_Msk                  (0x1UL << FLASH_SECBB2R4_SEC18_Pos)           /*!< 0x00040000 */
#define FLASH_SECBB2R4_SEC18                      FLASH_SECBB2R4_SEC18_Msk                      /*!< Page 114 in bank 2 block-based secure */
#define FLASH_SECBB2R4_SEC19_Pos                  (19UL)
#define FLASH_SECBB2R4_SEC19_Msk                  (0x1UL << FLASH_SECBB2R4_SEC19_Pos)           /*!< 0x00080000 */
#define FLASH_SECBB2R4_SEC19                      FLASH_SECBB2R4_SEC19_Msk                      /*!< Page 115 in bank 2 block-based secure */
#define FLASH_SECBB2R4_SEC20_Pos                  (20UL)
#define FLASH_SECBB2R4_SEC20_Msk                  (0x1UL << FLASH_SECBB2R4_SEC20_Pos)           /*!< 0x00100000 */
#define FLASH_SECBB2R4_SEC20                      FLASH_SECBB2R4_SEC20_Msk                      /*!< Page 116 in bank 2 block-based secure */
#define FLASH_SECBB2R4_SEC21_Pos                  (21UL)
#define FLASH_SECBB2R4_SEC21_Msk                  (0x1UL << FLASH_SECBB2R4_SEC21_Pos)           /*!< 0x00200000 */
#define FLASH_SECBB2R4_SEC21                      FLASH_SECBB2R4_SEC21_Msk                      /*!< Page 117 in bank 2 block-based secure */
#define FLASH_SECBB2R4_SEC22_Pos                  (22UL)
#define FLASH_SECBB2R4_SEC22_Msk                  (0x1UL << FLASH_SECBB2R4_SEC22_Pos)           /*!< 0x00400000 */
#define FLASH_SECBB2R4_SEC22                      FLASH_SECBB2R4_SEC22_Msk                      /*!< Page 118 in bank 2 block-based secure */
#define FLASH_SECBB2R4_SEC23_Pos                  (23UL)
#define FLASH_SECBB2R4_SEC23_Msk                  (0x1UL << FLASH_SECBB2R4_SEC23_Pos)           /*!< 0x00800000 */
#define FLASH_SECBB2R4_SEC23                      FLASH_SECBB2R4_SEC23_Msk                      /*!< Page 119 in bank 2 block-based secure */
#define FLASH_SECBB2R4_SEC24_Pos                  (24UL)
#define FLASH_SECBB2R4_SEC24_Msk                  (0x1UL << FLASH_SECBB2R4_SEC24_Pos)           /*!< 0x01000000 */
#define FLASH_SECBB2R4_SEC24                      FLASH_SECBB2R4_SEC24_Msk                      /*!< Page 120 in bank 2 block-based secure */
#define FLASH_SECBB2R4_SEC25_Pos                  (25UL)
#define FLASH_SECBB2R4_SEC25_Msk                  (0x1UL << FLASH_SECBB2R4_SEC25_Pos)           /*!< 0x02000000 */
#define FLASH_SECBB2R4_SEC25                      FLASH_SECBB2R4_SEC25_Msk                      /*!< Page 121 in bank 2 block-based secure */
#define FLASH_SECBB2R4_SEC26_Pos                  (26UL)
#define FLASH_SECBB2R4_SEC26_Msk                  (0x1UL << FLASH_SECBB2R4_SEC26_Pos)           /*!< 0x04000000 */
#define FLASH_SECBB2R4_SEC26                      FLASH_SECBB2R4_SEC26_Msk                      /*!< Page 122 in bank 2 block-based secure */
#define FLASH_SECBB2R4_SEC27_Pos                  (27UL)
#define FLASH_SECBB2R4_SEC27_Msk                  (0x1UL << FLASH_SECBB2R4_SEC27_Pos)           /*!< 0x08000000 */
#define FLASH_SECBB2R4_SEC27                      FLASH_SECBB2R4_SEC27_Msk                      /*!< Page 123 in bank 2 block-based secure */
#define FLASH_SECBB2R4_SEC28_Pos                  (28UL)
#define FLASH_SECBB2R4_SEC28_Msk                  (0x1UL << FLASH_SECBB2R4_SEC28_Pos)           /*!< 0x10000000 */
#define FLASH_SECBB2R4_SEC28                      FLASH_SECBB2R4_SEC28_Msk                      /*!< Page 124 in bank 2 block-based secure */
#define FLASH_SECBB2R4_SEC29_Pos                  (29UL)
#define FLASH_SECBB2R4_SEC29_Msk                  (0x1UL << FLASH_SECBB2R4_SEC29_Pos)           /*!< 0x20000000 */
#define FLASH_SECBB2R4_SEC29                      FLASH_SECBB2R4_SEC29_Msk                      /*!< Page 125 in bank 2 block-based secure */
#define FLASH_SECBB2R4_SEC30_Pos                  (30UL)
#define FLASH_SECBB2R4_SEC30_Msk                  (0x1UL << FLASH_SECBB2R4_SEC30_Pos)           /*!< 0x40000000 */
#define FLASH_SECBB2R4_SEC30                      FLASH_SECBB2R4_SEC30_Msk                      /*!< Page 126 in bank 2 block-based secure */
#define FLASH_SECBB2R4_SEC31_Pos                  (31UL)
#define FLASH_SECBB2R4_SEC31_Msk                  (0x1UL << FLASH_SECBB2R4_SEC31_Pos)           /*!< 0x80000000 */
#define FLASH_SECBB2R4_SEC31                      FLASH_SECBB2R4_SEC31_Msk                      /*!< Page 127 in bank 2 block-based secure */

/**********************  Bits definition for FLASH_SECHDPCR register  ***************/
#define FLASH_SECHDPCR_HDP1_ACCDIS_Pos            (0UL)
#define FLASH_SECHDPCR_HDP1_ACCDIS_Msk            (0xFFUL << FLASH_SECHDPCR_HDP1_ACCDIS_Pos)    /*!< 0x000000FF */
#define FLASH_SECHDPCR_HDP1_ACCDIS                FLASH_SECHDPCR_HDP1_ACCDIS_Msk                /*!< HDP1 area access disable */
#define FLASH_SECHDPCR_HDP2_ACCDIS_Pos            (8UL)
#define FLASH_SECHDPCR_HDP2_ACCDIS_Msk            (0xFFUL << FLASH_SECHDPCR_HDP2_ACCDIS_Pos)    /*!< 0x0000FF00 */
#define FLASH_SECHDPCR_HDP2_ACCDIS                FLASH_SECHDPCR_HDP2_ACCDIS_Msk                /*!< HDP2 area access disable */
#define FLASH_SECHDPCR_HDP1EXT_ACCDIS_Pos         (16UL)
#define FLASH_SECHDPCR_HDP1EXT_ACCDIS_Msk         (0xFFUL << FLASH_SECHDPCR_HDP1EXT_ACCDIS_Pos) /*!< 0x00FF0000 */
#define FLASH_SECHDPCR_HDP1EXT_ACCDIS             FLASH_SECHDPCR_HDP1EXT_ACCDIS_Msk             /*!< HDP1 extension area access disable */
#define FLASH_SECHDPCR_HDP2EXT_ACCDIS_Pos         (24UL)
#define FLASH_SECHDPCR_HDP2EXT_ACCDIS_Msk         (0xFFUL << FLASH_SECHDPCR_HDP2EXT_ACCDIS_Pos) /*!< 0xFF000000 */
#define FLASH_SECHDPCR_HDP2EXT_ACCDIS             FLASH_SECHDPCR_HDP2EXT_ACCDIS_Msk             /*!< HDP2 extension area access disable */

/**********************  Bits definition for FLASH_PRIVCFGR register  ***************/
#define FLASH_PRIVCFGR_SPRIV_Pos                  (0UL)
#define FLASH_PRIVCFGR_SPRIV_Msk                  (0x1UL << FLASH_PRIVCFGR_SPRIV_Pos)           /*!< 0x00000001 */
#define FLASH_PRIVCFGR_SPRIV                      FLASH_PRIVCFGR_SPRIV_Msk                      /*!< Privilege protection for secure registers */
#define FLASH_PRIVCFGR_PRIV_Pos                   (1UL)
#define FLASH_PRIVCFGR_PRIV_Msk                   (0x1UL << FLASH_PRIVCFGR_PRIV_Pos)            /*!< 0x00000002 */
#define FLASH_PRIVCFGR_PRIV                       FLASH_PRIVCFGR_PRIV_Msk                       /*!< Privilege protection for non-secure registers */

/*********************  Bits definition for FLASH_SECHDPEXTR register  **************/
#define FLASH_SECHDPEXTR_HDP1_EXT_Pos             (0UL)
#define FLASH_SECHDPEXTR_HDP1_EXT_Msk             (0xFFUL << FLASH_SECHDPEXTR_HDP1_EXT_Pos)     /*!< 0x000000FF */
#define FLASH_SECHDPEXTR_HDP1_EXT                 FLASH_SECHDPEXTR_HDP1_EXT_Msk                 /*!< HDP area extension in 4Kbytes pages in bank 1 */
#define FLASH_SECHDPEXTR_HDP2_EXT_Pos             (16UL)
#define FLASH_SECHDPEXTR_HDP2_EXT_Msk             (0xFFUL << FLASH_SECHDPEXTR_HDP2_EXT_Pos)     /*!< 0x00FF0000 */
#define FLASH_SECHDPEXTR_HDP2_EXT                 FLASH_SECHDPEXTR_HDP2_EXT_Msk                 /*!< HDP area extension in 4Kbytes pages in bank 2 */

/*******************  Bit definition for FLASH_PRIVBB1R1 register  ******************/
#define FLASH_PRIVBB1R1_PRIV0_Pos                   (0UL)
#define FLASH_PRIVBB1R1_PRIV0_Msk                   (0x1UL << FLASH_PRIVBB1R1_PRIV0_Pos)            /*!< 0x00000001 */
#define FLASH_PRIVBB1R1_PRIV0                       FLASH_PRIVBB1R1_PRIV0_Msk                       /*!< Page 0 in bank 1 block-based privilege */
#define FLASH_PRIVBB1R1_PRIV1_Pos                   (1UL)
#define FLASH_PRIVBB1R1_PRIV1_Msk                   (0x1UL << FLASH_PRIVBB1R1_PRIV1_Pos)            /*!< 0x00000002 */
#define FLASH_PRIVBB1R1_PRIV1                       FLASH_PRIVBB1R1_PRIV1_Msk                       /*!< Page 1 in bank 1 block-based privilege */
#define FLASH_PRIVBB1R1_PRIV2_Pos                   (2UL)
#define FLASH_PRIVBB1R1_PRIV2_Msk                   (0x1UL << FLASH_PRIVBB1R1_PRIV2_Pos)            /*!< 0x00000004 */
#define FLASH_PRIVBB1R1_PRIV2                       FLASH_PRIVBB1R1_PRIV2_Msk                       /*!< Page 2 in bank 1 block-based privilege */
#define FLASH_PRIVBB1R1_PRIV3_Pos                   (3UL)
#define FLASH_PRIVBB1R1_PRIV3_Msk                   (0x1UL << FLASH_PRIVBB1R1_PRIV3_Pos)            /*!< 0x00000008 */
#define FLASH_PRIVBB1R1_PRIV3                       FLASH_PRIVBB1R1_PRIV3_Msk                       /*!< Page 3 in bank 1 block-based privilege */
#define FLASH_PRIVBB1R1_PRIV4_Pos                   (4UL)
#define FLASH_PRIVBB1R1_PRIV4_Msk                   (0x1UL << FLASH_PRIVBB1R1_PRIV4_Pos)            /*!< 0x00000010 */
#define FLASH_PRIVBB1R1_PRIV4                       FLASH_PRIVBB1R1_PRIV4_Msk                       /*!< Page 4 in bank 1 block-based privilege */
#define FLASH_PRIVBB1R1_PRIV5_Pos                   (5UL)
#define FLASH_PRIVBB1R1_PRIV5_Msk                   (0x1UL << FLASH_PRIVBB1R1_PRIV5_Pos)            /*!< 0x00000020 */
#define FLASH_PRIVBB1R1_PRIV5                       FLASH_PRIVBB1R1_PRIV5_Msk                       /*!< Page 5 in bank 1 block-based privilege */
#define FLASH_PRIVBB1R1_PRIV6_Pos                   (6UL)
#define FLASH_PRIVBB1R1_PRIV6_Msk                   (0x1UL << FLASH_PRIVBB1R1_PRIV6_Pos)            /*!< 0x00000040 */
#define FLASH_PRIVBB1R1_PRIV6                       FLASH_PRIVBB1R1_PRIV6_Msk                       /*!< Page 6 in bank 1 block-based privilege */
#define FLASH_PRIVBB1R1_PRIV7_Pos                   (7UL)
#define FLASH_PRIVBB1R1_PRIV7_Msk                   (0x1UL << FLASH_PRIVBB1R1_PRIV7_Pos)            /*!< 0x00000080 */
#define FLASH_PRIVBB1R1_PRIV7                       FLASH_PRIVBB1R1_PRIV7_Msk                       /*!< Page 7 in bank 1 block-based privilege */
#define FLASH_PRIVBB1R1_PRIV8_Pos                   (8UL)
#define FLASH_PRIVBB1R1_PRIV8_Msk                   (0x1UL << FLASH_PRIVBB1R1_PRIV8_Pos)            /*!< 0x00000100 */
#define FLASH_PRIVBB1R1_PRIV8                       FLASH_PRIVBB1R1_PRIV8_Msk                       /*!< Page 8 in bank 1 block-based privilege */
#define FLASH_PRIVBB1R1_PRIV9_Pos                   (9UL)
#define FLASH_PRIVBB1R1_PRIV9_Msk                   (0x1UL << FLASH_PRIVBB1R1_PRIV9_Pos)            /*!< 0x00000200 */
#define FLASH_PRIVBB1R1_PRIV9                       FLASH_PRIVBB1R1_PRIV9_Msk                       /*!< Page 9 in bank 1 block-based privilege */
#define FLASH_PRIVBB1R1_PRIV10_Pos                  (10UL)
#define FLASH_PRIVBB1R1_PRIV10_Msk                  (0x1UL << FLASH_PRIVBB1R1_PRIV10_Pos)           /*!< 0x00000400 */
#define FLASH_PRIVBB1R1_PRIV10                      FLASH_PRIVBB1R1_PRIV10_Msk                      /*!< Page 10 in bank 1 block-based privilege */
#define FLASH_PRIVBB1R1_PRIV11_Pos                  (11UL)
#define FLASH_PRIVBB1R1_PRIV11_Msk                  (0x1UL << FLASH_PRIVBB1R1_PRIV11_Pos)           /*!< 0x00000800 */
#define FLASH_PRIVBB1R1_PRIV11                      FLASH_PRIVBB1R1_PRIV11_Msk                      /*!< Page 11 in bank 1 block-based privilege */
#define FLASH_PRIVBB1R1_PRIV12_Pos                  (12UL)
#define FLASH_PRIVBB1R1_PRIV12_Msk                  (0x1UL << FLASH_PRIVBB1R1_PRIV12_Pos)           /*!< 0x00001000 */
#define FLASH_PRIVBB1R1_PRIV12                      FLASH_PRIVBB1R1_PRIV12_Msk                      /*!< Page 12 in bank 1 block-based privilege */
#define FLASH_PRIVBB1R1_PRIV13_Pos                  (13UL)
#define FLASH_PRIVBB1R1_PRIV13_Msk                  (0x1UL << FLASH_PRIVBB1R1_PRIV13_Pos)           /*!< 0x00002000 */
#define FLASH_PRIVBB1R1_PRIV13                      FLASH_PRIVBB1R1_PRIV13_Msk                      /*!< Page 13 in bank 1 block-based privilege */
#define FLASH_PRIVBB1R1_PRIV14_Pos                  (14UL)
#define FLASH_PRIVBB1R1_PRIV14_Msk                  (0x1UL << FLASH_PRIVBB1R1_PRIV14_Pos)           /*!< 0x00004000 */
#define FLASH_PRIVBB1R1_PRIV14                      FLASH_PRIVBB1R1_PRIV14_Msk                      /*!< Page 14 in bank 1 block-based privilege */
#define FLASH_PRIVBB1R1_PRIV15_Pos                  (15UL)
#define FLASH_PRIVBB1R1_PRIV15_Msk                  (0x1UL << FLASH_PRIVBB1R1_PRIV15_Pos)           /*!< 0x00008000 */
#define FLASH_PRIVBB1R1_PRIV15                      FLASH_PRIVBB1R1_PRIV15_Msk                      /*!< Page 15 in bank 1 block-based privilege */
#define FLASH_PRIVBB1R1_PRIV16_Pos                  (16UL)
#define FLASH_PRIVBB1R1_PRIV16_Msk                  (0x1UL << FLASH_PRIVBB1R1_PRIV16_Pos)           /*!< 0x00010000 */
#define FLASH_PRIVBB1R1_PRIV16                      FLASH_PRIVBB1R1_PRIV16_Msk                      /*!< Page 16 in bank 1 block-based privilege */
#define FLASH_PRIVBB1R1_PRIV17_Pos                  (17UL)
#define FLASH_PRIVBB1R1_PRIV17_Msk                  (0x1UL << FLASH_PRIVBB1R1_PRIV17_Pos)           /*!< 0x00020000 */
#define FLASH_PRIVBB1R1_PRIV17                      FLASH_PRIVBB1R1_PRIV17_Msk                      /*!< Page 17 in bank 1 block-based privilege */
#define FLASH_PRIVBB1R1_PRIV18_Pos                  (18UL)
#define FLASH_PRIVBB1R1_PRIV18_Msk                  (0x1UL << FLASH_PRIVBB1R1_PRIV18_Pos)           /*!< 0x00040000 */
#define FLASH_PRIVBB1R1_PRIV18                      FLASH_PRIVBB1R1_PRIV18_Msk                      /*!< Page 18 in bank 1 block-based privilege */
#define FLASH_PRIVBB1R1_PRIV19_Pos                  (19UL)
#define FLASH_PRIVBB1R1_PRIV19_Msk                  (0x1UL << FLASH_PRIVBB1R1_PRIV19_Pos)           /*!< 0x00080000 */
#define FLASH_PRIVBB1R1_PRIV19                      FLASH_PRIVBB1R1_PRIV19_Msk                      /*!< Page 19 in bank 1 block-based privilege */
#define FLASH_PRIVBB1R1_PRIV20_Pos                  (20UL)
#define FLASH_PRIVBB1R1_PRIV20_Msk                  (0x1UL << FLASH_PRIVBB1R1_PRIV20_Pos)           /*!< 0x00100000 */
#define FLASH_PRIVBB1R1_PRIV20                      FLASH_PRIVBB1R1_PRIV20_Msk                      /*!< Page 20 in bank 1 block-based privilege */
#define FLASH_PRIVBB1R1_PRIV21_Pos                  (21UL)
#define FLASH_PRIVBB1R1_PRIV21_Msk                  (0x1UL << FLASH_PRIVBB1R1_PRIV21_Pos)           /*!< 0x00200000 */
#define FLASH_PRIVBB1R1_PRIV21                      FLASH_PRIVBB1R1_PRIV21_Msk                      /*!< Page 21 in bank 1 block-based privilege */
#define FLASH_PRIVBB1R1_PRIV22_Pos                  (22UL)
#define FLASH_PRIVBB1R1_PRIV22_Msk                  (0x1UL << FLASH_PRIVBB1R1_PRIV22_Pos)           /*!< 0x00400000 */
#define FLASH_PRIVBB1R1_PRIV22                      FLASH_PRIVBB1R1_PRIV22_Msk                      /*!< Page 22 in bank 1 block-based privilege */
#define FLASH_PRIVBB1R1_PRIV23_Pos                  (23UL)
#define FLASH_PRIVBB1R1_PRIV23_Msk                  (0x1UL << FLASH_PRIVBB1R1_PRIV23_Pos)           /*!< 0x00800000 */
#define FLASH_PRIVBB1R1_PRIV23                      FLASH_PRIVBB1R1_PRIV23_Msk                      /*!< Page 23 in bank 1 block-based privilege */
#define FLASH_PRIVBB1R1_PRIV24_Pos                  (24UL)
#define FLASH_PRIVBB1R1_PRIV24_Msk                  (0x1UL << FLASH_PRIVBB1R1_PRIV24_Pos)           /*!< 0x01000000 */
#define FLASH_PRIVBB1R1_PRIV24                      FLASH_PRIVBB1R1_PRIV24_Msk                      /*!< Page 24 in bank 1 block-based privilege */
#define FLASH_PRIVBB1R1_PRIV25_Pos                  (25UL)
#define FLASH_PRIVBB1R1_PRIV25_Msk                  (0x1UL << FLASH_PRIVBB1R1_PRIV25_Pos)           /*!< 0x02000000 */
#define FLASH_PRIVBB1R1_PRIV25                      FLASH_PRIVBB1R1_PRIV25_Msk                      /*!< Page 25 in bank 1 block-based privilege */
#define FLASH_PRIVBB1R1_PRIV26_Pos                  (26UL)
#define FLASH_PRIVBB1R1_PRIV26_Msk                  (0x1UL << FLASH_PRIVBB1R1_PRIV26_Pos)           /*!< 0x04000000 */
#define FLASH_PRIVBB1R1_PRIV26                      FLASH_PRIVBB1R1_PRIV26_Msk                      /*!< Page 26 in bank 1 block-based privilege */
#define FLASH_PRIVBB1R1_PRIV27_Pos                  (27UL)
#define FLASH_PRIVBB1R1_PRIV27_Msk                  (0x1UL << FLASH_PRIVBB1R1_PRIV27_Pos)           /*!< 0x08000000 */
#define FLASH_PRIVBB1R1_PRIV27                      FLASH_PRIVBB1R1_PRIV27_Msk                      /*!< Page 27 in bank 1 block-based privilege */
#define FLASH_PRIVBB1R1_PRIV28_Pos                  (28UL)
#define FLASH_PRIVBB1R1_PRIV28_Msk                  (0x1UL << FLASH_PRIVBB1R1_PRIV28_Pos)           /*!< 0x10000000 */
#define FLASH_PRIVBB1R1_PRIV28                      FLASH_PRIVBB1R1_PRIV28_Msk                      /*!< Page 28 in bank 1 block-based privilege */
#define FLASH_PRIVBB1R1_PRIV29_Pos                  (29UL)
#define FLASH_PRIVBB1R1_PRIV29_Msk                  (0x1UL << FLASH_PRIVBB1R1_PRIV29_Pos)           /*!< 0x20000000 */
#define FLASH_PRIVBB1R1_PRIV29                      FLASH_PRIVBB1R1_PRIV29_Msk                      /*!< Page 29 in bank 1 block-based privilege */
#define FLASH_PRIVBB1R1_PRIV30_Pos                  (30UL)
#define FLASH_PRIVBB1R1_PRIV30_Msk                  (0x1UL << FLASH_PRIVBB1R1_PRIV30_Pos)           /*!< 0x40000000 */
#define FLASH_PRIVBB1R1_PRIV30                      FLASH_PRIVBB1R1_PRIV30_Msk                      /*!< Page 30 in bank 1 block-based privilege */
#define FLASH_PRIVBB1R1_PRIV31_Pos                  (31UL)
#define FLASH_PRIVBB1R1_PRIV31_Msk                  (0x1UL << FLASH_PRIVBB1R1_PRIV31_Pos)           /*!< 0x80000000 */
#define FLASH_PRIVBB1R1_PRIV31                      FLASH_PRIVBB1R1_PRIV31_Msk                      /*!< Page 31 in bank 1 block-based privilege */

/*******************  Bit definition for FLASH_PRIVBB1R2 register  ******************/
#define FLASH_PRIVBB1R2_PRIV0_Pos                   (0UL)
#define FLASH_PRIVBB1R2_PRIV0_Msk                   (0x1UL << FLASH_PRIVBB1R2_PRIV0_Pos)            /*!< 0x00000001 */
#define FLASH_PRIVBB1R2_PRIV0                       FLASH_PRIVBB1R2_PRIV0_Msk                       /*!< Page 32 in bank 1 block-based privilege */
#define FLASH_PRIVBB1R2_PRIV1_Pos                   (1UL)
#define FLASH_PRIVBB1R2_PRIV1_Msk                   (0x1UL << FLASH_PRIVBB1R2_PRIV1_Pos)            /*!< 0x00000002 */
#define FLASH_PRIVBB1R2_PRIV1                       FLASH_PRIVBB1R2_PRIV1_Msk                       /*!< Page 33 in bank 1 block-based privilege */
#define FLASH_PRIVBB1R2_PRIV2_Pos                   (2UL)
#define FLASH_PRIVBB1R2_PRIV2_Msk                   (0x1UL << FLASH_PRIVBB1R2_PRIV2_Pos)            /*!< 0x00000004 */
#define FLASH_PRIVBB1R2_PRIV2                       FLASH_PRIVBB1R2_PRIV2_Msk                       /*!< Page 34 in bank 1 block-based privilege */
#define FLASH_PRIVBB1R2_PRIV3_Pos                   (3UL)
#define FLASH_PRIVBB1R2_PRIV3_Msk                   (0x1UL << FLASH_PRIVBB1R2_PRIV3_Pos)            /*!< 0x00000008 */
#define FLASH_PRIVBB1R2_PRIV3                       FLASH_PRIVBB1R2_PRIV3_Msk                       /*!< Page 35 in bank 1 block-based privilege */
#define FLASH_PRIVBB1R2_PRIV4_Pos                   (4UL)
#define FLASH_PRIVBB1R2_PRIV4_Msk                   (0x1UL << FLASH_PRIVBB1R2_PRIV4_Pos)            /*!< 0x00000010 */
#define FLASH_PRIVBB1R2_PRIV4                       FLASH_PRIVBB1R2_PRIV4_Msk                       /*!< Page 36 in bank 1 block-based privilege */
#define FLASH_PRIVBB1R2_PRIV5_Pos                   (5UL)
#define FLASH_PRIVBB1R2_PRIV5_Msk                   (0x1UL << FLASH_PRIVBB1R2_PRIV5_Pos)            /*!< 0x00000020 */
#define FLASH_PRIVBB1R2_PRIV5                       FLASH_PRIVBB1R2_PRIV5_Msk                       /*!< Page 37 in bank 1 block-based privilege */
#define FLASH_PRIVBB1R2_PRIV6_Pos                   (6UL)
#define FLASH_PRIVBB1R2_PRIV6_Msk                   (0x1UL << FLASH_PRIVBB1R2_PRIV6_Pos)            /*!< 0x00000040 */
#define FLASH_PRIVBB1R2_PRIV6                       FLASH_PRIVBB1R2_PRIV6_Msk                       /*!< Page 38 in bank 1 block-based privilege */
#define FLASH_PRIVBB1R2_PRIV7_Pos                   (7UL)
#define FLASH_PRIVBB1R2_PRIV7_Msk                   (0x1UL << FLASH_PRIVBB1R2_PRIV7_Pos)            /*!< 0x00000080 */
#define FLASH_PRIVBB1R2_PRIV7                       FLASH_PRIVBB1R2_PRIV7_Msk                       /*!< Page 39 in bank 1 block-based privilege */
#define FLASH_PRIVBB1R2_PRIV8_Pos                   (8UL)
#define FLASH_PRIVBB1R2_PRIV8_Msk                   (0x1UL << FLASH_PRIVBB1R2_PRIV8_Pos)            /*!< 0x00000100 */
#define FLASH_PRIVBB1R2_PRIV8                       FLASH_PRIVBB1R2_PRIV8_Msk                       /*!< Page 40 in bank 1 block-based privilege */
#define FLASH_PRIVBB1R2_PRIV9_Pos                   (9UL)
#define FLASH_PRIVBB1R2_PRIV9_Msk                   (0x1UL << FLASH_PRIVBB1R2_PRIV9_Pos)            /*!< 0x00000200 */
#define FLASH_PRIVBB1R2_PRIV9                       FLASH_PRIVBB1R2_PRIV9_Msk                       /*!< Page 41 in bank 1 block-based privilege */
#define FLASH_PRIVBB1R2_PRIV10_Pos                  (10UL)
#define FLASH_PRIVBB1R2_PRIV10_Msk                  (0x1UL << FLASH_PRIVBB1R2_PRIV10_Pos)           /*!< 0x00000400 */
#define FLASH_PRIVBB1R2_PRIV10                      FLASH_PRIVBB1R2_PRIV10_Msk                      /*!< Page 42 in bank 1 block-based privilege */
#define FLASH_PRIVBB1R2_PRIV11_Pos                  (11UL)
#define FLASH_PRIVBB1R2_PRIV11_Msk                  (0x1UL << FLASH_PRIVBB1R2_PRIV11_Pos)           /*!< 0x00000800 */
#define FLASH_PRIVBB1R2_PRIV11                      FLASH_PRIVBB1R2_PRIV11_Msk                      /*!< Page 43 in bank 1 block-based privilege */
#define FLASH_PRIVBB1R2_PRIV12_Pos                  (12UL)
#define FLASH_PRIVBB1R2_PRIV12_Msk                  (0x1UL << FLASH_PRIVBB1R2_PRIV12_Pos)           /*!< 0x00001000 */
#define FLASH_PRIVBB1R2_PRIV12                      FLASH_PRIVBB1R2_PRIV12_Msk                      /*!< Page 44 in bank 1 block-based privilege */
#define FLASH_PRIVBB1R2_PRIV13_Pos                  (13UL)
#define FLASH_PRIVBB1R2_PRIV13_Msk                  (0x1UL << FLASH_PRIVBB1R2_PRIV13_Pos)           /*!< 0x00002000 */
#define FLASH_PRIVBB1R2_PRIV13                      FLASH_PRIVBB1R2_PRIV13_Msk                      /*!< Page 45 in bank 1 block-based privilege */
#define FLASH_PRIVBB1R2_PRIV14_Pos                  (14UL)
#define FLASH_PRIVBB1R2_PRIV14_Msk                  (0x1UL << FLASH_PRIVBB1R2_PRIV14_Pos)           /*!< 0x00004000 */
#define FLASH_PRIVBB1R2_PRIV14                      FLASH_PRIVBB1R2_PRIV14_Msk                      /*!< Page 46 in bank 1 block-based privilege */
#define FLASH_PRIVBB1R2_PRIV15_Pos                  (15UL)
#define FLASH_PRIVBB1R2_PRIV15_Msk                  (0x1UL << FLASH_PRIVBB1R2_PRIV15_Pos)           /*!< 0x00008000 */
#define FLASH_PRIVBB1R2_PRIV15                      FLASH_PRIVBB1R2_PRIV15_Msk                      /*!< Page 47 in bank 1 block-based privilege */
#define FLASH_PRIVBB1R2_PRIV16_Pos                  (16UL)
#define FLASH_PRIVBB1R2_PRIV16_Msk                  (0x1UL << FLASH_PRIVBB1R2_PRIV16_Pos)           /*!< 0x00010000 */
#define FLASH_PRIVBB1R2_PRIV16                      FLASH_PRIVBB1R2_PRIV16_Msk                      /*!< Page 48 in bank 1 block-based privilege */
#define FLASH_PRIVBB1R2_PRIV17_Pos                  (17UL)
#define FLASH_PRIVBB1R2_PRIV17_Msk                  (0x1UL << FLASH_PRIVBB1R2_PRIV17_Pos)           /*!< 0x00020000 */
#define FLASH_PRIVBB1R2_PRIV17                      FLASH_PRIVBB1R2_PRIV17_Msk                      /*!< Page 49 in bank 1 block-based privilege */
#define FLASH_PRIVBB1R2_PRIV18_Pos                  (18UL)
#define FLASH_PRIVBB1R2_PRIV18_Msk                  (0x1UL << FLASH_PRIVBB1R2_PRIV18_Pos)           /*!< 0x00040000 */
#define FLASH_PRIVBB1R2_PRIV18                      FLASH_PRIVBB1R2_PRIV18_Msk                      /*!< Page 50 in bank 1 block-based privilege */
#define FLASH_PRIVBB1R2_PRIV19_Pos                  (19UL)
#define FLASH_PRIVBB1R2_PRIV19_Msk                  (0x1UL << FLASH_PRIVBB1R2_PRIV19_Pos)           /*!< 0x00080000 */
#define FLASH_PRIVBB1R2_PRIV19                      FLASH_PRIVBB1R2_PRIV19_Msk                      /*!< Page 51 in bank 1 block-based privilege */
#define FLASH_PRIVBB1R2_PRIV20_Pos                  (20UL)
#define FLASH_PRIVBB1R2_PRIV20_Msk                  (0x1UL << FLASH_PRIVBB1R2_PRIV20_Pos)           /*!< 0x00100000 */
#define FLASH_PRIVBB1R2_PRIV20                      FLASH_PRIVBB1R2_PRIV20_Msk                      /*!< Page 52 in bank 1 block-based privilege */
#define FLASH_PRIVBB1R2_PRIV21_Pos                  (21UL)
#define FLASH_PRIVBB1R2_PRIV21_Msk                  (0x1UL << FLASH_PRIVBB1R2_PRIV21_Pos)           /*!< 0x00200000 */
#define FLASH_PRIVBB1R2_PRIV21                      FLASH_PRIVBB1R2_PRIV21_Msk                      /*!< Page 53 in bank 1 block-based privilege */
#define FLASH_PRIVBB1R2_PRIV22_Pos                  (22UL)
#define FLASH_PRIVBB1R2_PRIV22_Msk                  (0x1UL << FLASH_PRIVBB1R2_PRIV22_Pos)           /*!< 0x00400000 */
#define FLASH_PRIVBB1R2_PRIV22                      FLASH_PRIVBB1R2_PRIV22_Msk                      /*!< Page 54 in bank 1 block-based privilege */
#define FLASH_PRIVBB1R2_PRIV23_Pos                  (23UL)
#define FLASH_PRIVBB1R2_PRIV23_Msk                  (0x1UL << FLASH_PRIVBB1R2_PRIV23_Pos)           /*!< 0x00800000 */
#define FLASH_PRIVBB1R2_PRIV23                      FLASH_PRIVBB1R2_PRIV23_Msk                      /*!< Page 55 in bank 1 block-based privilege */
#define FLASH_PRIVBB1R2_PRIV24_Pos                  (24UL)
#define FLASH_PRIVBB1R2_PRIV24_Msk                  (0x1UL << FLASH_PRIVBB1R2_PRIV24_Pos)           /*!< 0x01000000 */
#define FLASH_PRIVBB1R2_PRIV24                      FLASH_PRIVBB1R2_PRIV24_Msk                      /*!< Page 56 in bank 1 block-based privilege */
#define FLASH_PRIVBB1R2_PRIV25_Pos                  (25UL)
#define FLASH_PRIVBB1R2_PRIV25_Msk                  (0x1UL << FLASH_PRIVBB1R2_PRIV25_Pos)           /*!< 0x02000000 */
#define FLASH_PRIVBB1R2_PRIV25                      FLASH_PRIVBB1R2_PRIV25_Msk                      /*!< Page 57 in bank 1 block-based privilege */
#define FLASH_PRIVBB1R2_PRIV26_Pos                  (26UL)
#define FLASH_PRIVBB1R2_PRIV26_Msk                  (0x1UL << FLASH_PRIVBB1R2_PRIV26_Pos)           /*!< 0x04000000 */
#define FLASH_PRIVBB1R2_PRIV26                      FLASH_PRIVBB1R2_PRIV26_Msk                      /*!< Page 58 in bank 1 block-based privilege */
#define FLASH_PRIVBB1R2_PRIV27_Pos                  (27UL)
#define FLASH_PRIVBB1R2_PRIV27_Msk                  (0x1UL << FLASH_PRIVBB1R2_PRIV27_Pos)           /*!< 0x08000000 */
#define FLASH_PRIVBB1R2_PRIV27                      FLASH_PRIVBB1R2_PRIV27_Msk                      /*!< Page 59 in bank 1 block-based privilege */
#define FLASH_PRIVBB1R2_PRIV28_Pos                  (28UL)
#define FLASH_PRIVBB1R2_PRIV28_Msk                  (0x1UL << FLASH_PRIVBB1R2_PRIV28_Pos)           /*!< 0x10000000 */
#define FLASH_PRIVBB1R2_PRIV28                      FLASH_PRIVBB1R2_PRIV28_Msk                      /*!< Page 60 in bank 1 block-based privilege */
#define FLASH_PRIVBB1R2_PRIV29_Pos                  (29UL)
#define FLASH_PRIVBB1R2_PRIV29_Msk                  (0x1UL << FLASH_PRIVBB1R2_PRIV29_Pos)           /*!< 0x20000000 */
#define FLASH_PRIVBB1R2_PRIV29                      FLASH_PRIVBB1R2_PRIV29_Msk                      /*!< Page 61 in bank 1 block-based privilege */
#define FLASH_PRIVBB1R2_PRIV30_Pos                  (30UL)
#define FLASH_PRIVBB1R2_PRIV30_Msk                  (0x1UL << FLASH_PRIVBB1R2_PRIV30_Pos)           /*!< 0x40000000 */
#define FLASH_PRIVBB1R2_PRIV30                      FLASH_PRIVBB1R2_PRIV30_Msk                      /*!< Page 62 in bank 1 block-based privilege */
#define FLASH_PRIVBB1R2_PRIV31_Pos                  (31UL)
#define FLASH_PRIVBB1R2_PRIV31_Msk                  (0x1UL << FLASH_PRIVBB1R2_PRIV31_Pos)           /*!< 0x80000000 */
#define FLASH_PRIVBB1R2_PRIV31                      FLASH_PRIVBB1R2_PRIV31_Msk                      /*!< Page 63 in bank 1 block-based privilege */

/*******************  Bit definition for FLASH_PRIVBB1R3 register  ******************/
#define FLASH_PRIVBB1R3_PRIV0_Pos                   (0UL)
#define FLASH_PRIVBB1R3_PRIV0_Msk                   (0x1UL << FLASH_PRIVBB1R3_PRIV0_Pos)            /*!< 0x00000001 */
#define FLASH_PRIVBB1R3_PRIV0                       FLASH_PRIVBB1R3_PRIV0_Msk                       /*!< Page 64 in bank 1 block-based privilege */
#define FLASH_PRIVBB1R3_PRIV1_Pos                   (1UL)
#define FLASH_PRIVBB1R3_PRIV1_Msk                   (0x1UL << FLASH_PRIVBB1R3_PRIV1_Pos)            /*!< 0x00000002 */
#define FLASH_PRIVBB1R3_PRIV1                       FLASH_PRIVBB1R3_PRIV1_Msk                       /*!< Page 65 in bank 1 block-based privilege */
#define FLASH_PRIVBB1R3_PRIV2_Pos                   (2UL)
#define FLASH_PRIVBB1R3_PRIV2_Msk                   (0x1UL << FLASH_PRIVBB1R3_PRIV2_Pos)            /*!< 0x00000004 */
#define FLASH_PRIVBB1R3_PRIV2                       FLASH_PRIVBB1R3_PRIV2_Msk                       /*!< Page 66 in bank 1 block-based privilege */
#define FLASH_PRIVBB1R3_PRIV3_Pos                   (3UL)
#define FLASH_PRIVBB1R3_PRIV3_Msk                   (0x1UL << FLASH_PRIVBB1R3_PRIV3_Pos)            /*!< 0x00000008 */
#define FLASH_PRIVBB1R3_PRIV3                       FLASH_PRIVBB1R3_PRIV3_Msk                       /*!< Page 67 in bank 1 block-based privilege */
#define FLASH_PRIVBB1R3_PRIV4_Pos                   (4UL)
#define FLASH_PRIVBB1R3_PRIV4_Msk                   (0x1UL << FLASH_PRIVBB1R3_PRIV4_Pos)            /*!< 0x00000010 */
#define FLASH_PRIVBB1R3_PRIV4                       FLASH_PRIVBB1R3_PRIV4_Msk                       /*!< Page 68 in bank 1 block-based privilege */
#define FLASH_PRIVBB1R3_PRIV5_Pos                   (5UL)
#define FLASH_PRIVBB1R3_PRIV5_Msk                   (0x1UL << FLASH_PRIVBB1R3_PRIV5_Pos)            /*!< 0x00000020 */
#define FLASH_PRIVBB1R3_PRIV5                       FLASH_PRIVBB1R3_PRIV5_Msk                       /*!< Page 69 in bank 1 block-based privilege */
#define FLASH_PRIVBB1R3_PRIV6_Pos                   (6UL)
#define FLASH_PRIVBB1R3_PRIV6_Msk                   (0x1UL << FLASH_PRIVBB1R3_PRIV6_Pos)            /*!< 0x00000040 */
#define FLASH_PRIVBB1R3_PRIV6                       FLASH_PRIVBB1R3_PRIV6_Msk                       /*!< Page 70 in bank 1 block-based privilege */
#define FLASH_PRIVBB1R3_PRIV7_Pos                   (7UL)
#define FLASH_PRIVBB1R3_PRIV7_Msk                   (0x1UL << FLASH_PRIVBB1R3_PRIV7_Pos)            /*!< 0x00000080 */
#define FLASH_PRIVBB1R3_PRIV7                       FLASH_PRIVBB1R3_PRIV7_Msk                       /*!< Page 71 in bank 1 block-based privilege */
#define FLASH_PRIVBB1R3_PRIV8_Pos                   (8UL)
#define FLASH_PRIVBB1R3_PRIV8_Msk                   (0x1UL << FLASH_PRIVBB1R3_PRIV8_Pos)            /*!< 0x00000100 */
#define FLASH_PRIVBB1R3_PRIV8                       FLASH_PRIVBB1R3_PRIV8_Msk                       /*!< Page 72 in bank 1 block-based privilege */
#define FLASH_PRIVBB1R3_PRIV9_Pos                   (9UL)
#define FLASH_PRIVBB1R3_PRIV9_Msk                   (0x1UL << FLASH_PRIVBB1R3_PRIV9_Pos)            /*!< 0x00000200 */
#define FLASH_PRIVBB1R3_PRIV9                       FLASH_PRIVBB1R3_PRIV9_Msk                       /*!< Page 73 in bank 1 block-based privilege */
#define FLASH_PRIVBB1R3_PRIV10_Pos                  (10UL)
#define FLASH_PRIVBB1R3_PRIV10_Msk                  (0x1UL << FLASH_PRIVBB1R3_PRIV10_Pos)           /*!< 0x00000400 */
#define FLASH_PRIVBB1R3_PRIV10                      FLASH_PRIVBB1R3_PRIV10_Msk                      /*!< Page 74 in bank 1 block-based privilege */
#define FLASH_PRIVBB1R3_PRIV11_Pos                  (11UL)
#define FLASH_PRIVBB1R3_PRIV11_Msk                  (0x1UL << FLASH_PRIVBB1R3_PRIV11_Pos)           /*!< 0x00000800 */
#define FLASH_PRIVBB1R3_PRIV11                      FLASH_PRIVBB1R3_PRIV11_Msk                      /*!< Page 75 in bank 1 block-based privilege */
#define FLASH_PRIVBB1R3_PRIV12_Pos                  (12UL)
#define FLASH_PRIVBB1R3_PRIV12_Msk                  (0x1UL << FLASH_PRIVBB1R3_PRIV12_Pos)           /*!< 0x00001000 */
#define FLASH_PRIVBB1R3_PRIV12                      FLASH_PRIVBB1R3_PRIV12_Msk                      /*!< Page 76 in bank 1 block-based privilege */
#define FLASH_PRIVBB1R3_PRIV13_Pos                  (13UL)
#define FLASH_PRIVBB1R3_PRIV13_Msk                  (0x1UL << FLASH_PRIVBB1R3_PRIV13_Pos)           /*!< 0x00002000 */
#define FLASH_PRIVBB1R3_PRIV13                      FLASH_PRIVBB1R3_PRIV13_Msk                      /*!< Page 77 in bank 1 block-based privilege */
#define FLASH_PRIVBB1R3_PRIV14_Pos                  (14UL)
#define FLASH_PRIVBB1R3_PRIV14_Msk                  (0x1UL << FLASH_PRIVBB1R3_PRIV14_Pos)           /*!< 0x00004000 */
#define FLASH_PRIVBB1R3_PRIV14                      FLASH_PRIVBB1R3_PRIV14_Msk                      /*!< Page 78 in bank 1 block-based privilege */
#define FLASH_PRIVBB1R3_PRIV15_Pos                  (15UL)
#define FLASH_PRIVBB1R3_PRIV15_Msk                  (0x1UL << FLASH_PRIVBB1R3_PRIV15_Pos)           /*!< 0x00008000 */
#define FLASH_PRIVBB1R3_PRIV15                      FLASH_PRIVBB1R3_PRIV15_Msk                      /*!< Page 79 in bank 1 block-based privilege */
#define FLASH_PRIVBB1R3_PRIV16_Pos                  (16UL)
#define FLASH_PRIVBB1R3_PRIV16_Msk                  (0x1UL << FLASH_PRIVBB1R3_PRIV16_Pos)           /*!< 0x00010000 */
#define FLASH_PRIVBB1R3_PRIV16                      FLASH_PRIVBB1R3_PRIV16_Msk                      /*!< Page 80 in bank 1 block-based privilege */
#define FLASH_PRIVBB1R3_PRIV17_Pos                  (17UL)
#define FLASH_PRIVBB1R3_PRIV17_Msk                  (0x1UL << FLASH_PRIVBB1R3_PRIV17_Pos)           /*!< 0x00020000 */
#define FLASH_PRIVBB1R3_PRIV17                      FLASH_PRIVBB1R3_PRIV17_Msk                      /*!< Page 81 in bank 1 block-based privilege */
#define FLASH_PRIVBB1R3_PRIV18_Pos                  (18UL)
#define FLASH_PRIVBB1R3_PRIV18_Msk                  (0x1UL << FLASH_PRIVBB1R3_PRIV18_Pos)           /*!< 0x00040000 */
#define FLASH_PRIVBB1R3_PRIV18                      FLASH_PRIVBB1R3_PRIV18_Msk                      /*!< Page 82 in bank 1 block-based privilege */
#define FLASH_PRIVBB1R3_PRIV19_Pos                  (19UL)
#define FLASH_PRIVBB1R3_PRIV19_Msk                  (0x1UL << FLASH_PRIVBB1R3_PRIV19_Pos)           /*!< 0x00080000 */
#define FLASH_PRIVBB1R3_PRIV19                      FLASH_PRIVBB1R3_PRIV19_Msk                      /*!< Page 83 in bank 1 block-based privilege */
#define FLASH_PRIVBB1R3_PRIV20_Pos                  (20UL)
#define FLASH_PRIVBB1R3_PRIV20_Msk                  (0x1UL << FLASH_PRIVBB1R3_PRIV20_Pos)           /*!< 0x00100000 */
#define FLASH_PRIVBB1R3_PRIV20                      FLASH_PRIVBB1R3_PRIV20_Msk                      /*!< Page 84 in bank 1 block-based privilege */
#define FLASH_PRIVBB1R3_PRIV21_Pos                  (21UL)
#define FLASH_PRIVBB1R3_PRIV21_Msk                  (0x1UL << FLASH_PRIVBB1R3_PRIV21_Pos)           /*!< 0x00200000 */
#define FLASH_PRIVBB1R3_PRIV21                      FLASH_PRIVBB1R3_PRIV21_Msk                      /*!< Page 85 in bank 1 block-based privilege */
#define FLASH_PRIVBB1R3_PRIV22_Pos                  (22UL)
#define FLASH_PRIVBB1R3_PRIV22_Msk                  (0x1UL << FLASH_PRIVBB1R3_PRIV22_Pos)           /*!< 0x00400000 */
#define FLASH_PRIVBB1R3_PRIV22                      FLASH_PRIVBB1R3_PRIV22_Msk                      /*!< Page 86 in bank 1 block-based privilege */
#define FLASH_PRIVBB1R3_PRIV23_Pos                  (23UL)
#define FLASH_PRIVBB1R3_PRIV23_Msk                  (0x1UL << FLASH_PRIVBB1R3_PRIV23_Pos)           /*!< 0x00800000 */
#define FLASH_PRIVBB1R3_PRIV23                      FLASH_PRIVBB1R3_PRIV23_Msk                      /*!< Page 87 in bank 1 block-based privilege */
#define FLASH_PRIVBB1R3_PRIV24_Pos                  (24UL)
#define FLASH_PRIVBB1R3_PRIV24_Msk                  (0x1UL << FLASH_PRIVBB1R3_PRIV24_Pos)           /*!< 0x01000000 */
#define FLASH_PRIVBB1R3_PRIV24                      FLASH_PRIVBB1R3_PRIV24_Msk                      /*!< Page 88 in bank 1 block-based privilege */
#define FLASH_PRIVBB1R3_PRIV25_Pos                  (25UL)
#define FLASH_PRIVBB1R3_PRIV25_Msk                  (0x1UL << FLASH_PRIVBB1R3_PRIV25_Pos)           /*!< 0x02000000 */
#define FLASH_PRIVBB1R3_PRIV25                      FLASH_PRIVBB1R3_PRIV25_Msk                      /*!< Page 89 in bank 1 block-based privilege */
#define FLASH_PRIVBB1R3_PRIV26_Pos                  (26UL)
#define FLASH_PRIVBB1R3_PRIV26_Msk                  (0x1UL << FLASH_PRIVBB1R3_PRIV26_Pos)           /*!< 0x04000000 */
#define FLASH_PRIVBB1R3_PRIV26                      FLASH_PRIVBB1R3_PRIV26_Msk                      /*!< Page 90 in bank 1 block-based privilege */
#define FLASH_PRIVBB1R3_PRIV27_Pos                  (27UL)
#define FLASH_PRIVBB1R3_PRIV27_Msk                  (0x1UL << FLASH_PRIVBB1R3_PRIV27_Pos)           /*!< 0x08000000 */
#define FLASH_PRIVBB1R3_PRIV27                      FLASH_PRIVBB1R3_PRIV27_Msk                      /*!< Page 91 in bank 1 block-based privilege */
#define FLASH_PRIVBB1R3_PRIV28_Pos                  (28UL)
#define FLASH_PRIVBB1R3_PRIV28_Msk                  (0x1UL << FLASH_PRIVBB1R3_PRIV28_Pos)           /*!< 0x10000000 */
#define FLASH_PRIVBB1R3_PRIV28                      FLASH_PRIVBB1R3_PRIV28_Msk                      /*!< Page 92 in bank 1 block-based privilege */
#define FLASH_PRIVBB1R3_PRIV29_Pos                  (29UL)
#define FLASH_PRIVBB1R3_PRIV29_Msk                  (0x1UL << FLASH_PRIVBB1R3_PRIV29_Pos)           /*!< 0x20000000 */
#define FLASH_PRIVBB1R3_PRIV29                      FLASH_PRIVBB1R3_PRIV29_Msk                      /*!< Page 93 in bank 1 block-based privilege */
#define FLASH_PRIVBB1R3_PRIV30_Pos                  (30UL)
#define FLASH_PRIVBB1R3_PRIV30_Msk                  (0x1UL << FLASH_PRIVBB1R3_PRIV30_Pos)           /*!< 0x40000000 */
#define FLASH_PRIVBB1R3_PRIV30                      FLASH_PRIVBB1R3_PRIV30_Msk                      /*!< Page 94 in bank 1 block-based privilege */
#define FLASH_PRIVBB1R3_PRIV31_Pos                  (31UL)
#define FLASH_PRIVBB1R3_PRIV31_Msk                  (0x1UL << FLASH_PRIVBB1R3_PRIV31_Pos)           /*!< 0x80000000 */
#define FLASH_PRIVBB1R3_PRIV31                      FLASH_PRIVBB1R3_PRIV31_Msk                      /*!< Page 95 in bank 1 block-based privilege */

/*******************  Bit definition for FLASH_PRIVBB1R4 register  ******************/
#define FLASH_PRIVBB1R4_PRIV0_Pos                   (0UL)
#define FLASH_PRIVBB1R4_PRIV0_Msk                   (0x1UL << FLASH_PRIVBB1R4_PRIV0_Pos)            /*!< 0x00000001 */
#define FLASH_PRIVBB1R4_PRIV0                       FLASH_PRIVBB1R4_PRIV0_Msk                       /*!< Page 96 in bank 1 block-based privilege */
#define FLASH_PRIVBB1R4_PRIV1_Pos                   (1UL)
#define FLASH_PRIVBB1R4_PRIV1_Msk                   (0x1UL << FLASH_PRIVBB1R4_PRIV1_Pos)            /*!< 0x00000002 */
#define FLASH_PRIVBB1R4_PRIV1                       FLASH_PRIVBB1R4_PRIV1_Msk                       /*!< Page 97 in bank 1 block-based privilege */
#define FLASH_PRIVBB1R4_PRIV2_Pos                   (2UL)
#define FLASH_PRIVBB1R4_PRIV2_Msk                   (0x1UL << FLASH_PRIVBB1R4_PRIV2_Pos)            /*!< 0x00000004 */
#define FLASH_PRIVBB1R4_PRIV2                       FLASH_PRIVBB1R4_PRIV2_Msk                       /*!< Page 98 in bank 1 block-based privilege */
#define FLASH_PRIVBB1R4_PRIV3_Pos                   (3UL)
#define FLASH_PRIVBB1R4_PRIV3_Msk                   (0x1UL << FLASH_PRIVBB1R4_PRIV3_Pos)            /*!< 0x00000008 */
#define FLASH_PRIVBB1R4_PRIV3                       FLASH_PRIVBB1R4_PRIV3_Msk                       /*!< Page 99 in bank 1 block-based privilege */
#define FLASH_PRIVBB1R4_PRIV4_Pos                   (4UL)
#define FLASH_PRIVBB1R4_PRIV4_Msk                   (0x1UL << FLASH_PRIVBB1R4_PRIV4_Pos)            /*!< 0x00000010 */
#define FLASH_PRIVBB1R4_PRIV4                       FLASH_PRIVBB1R4_PRIV4_Msk                       /*!< Page 100 in bank 1 block-based privilege */
#define FLASH_PRIVBB1R4_PRIV5_Pos                   (5UL)
#define FLASH_PRIVBB1R4_PRIV5_Msk                   (0x1UL << FLASH_PRIVBB1R4_PRIV5_Pos)            /*!< 0x00000020 */
#define FLASH_PRIVBB1R4_PRIV5                       FLASH_PRIVBB1R4_PRIV5_Msk                       /*!< Page 101 in bank 1 block-based privilege */
#define FLASH_PRIVBB1R4_PRIV6_Pos                   (6UL)
#define FLASH_PRIVBB1R4_PRIV6_Msk                   (0x1UL << FLASH_PRIVBB1R4_PRIV6_Pos)            /*!< 0x00000040 */
#define FLASH_PRIVBB1R4_PRIV6                       FLASH_PRIVBB1R4_PRIV6_Msk                       /*!< Page 102 in bank 1 block-based privilege */
#define FLASH_PRIVBB1R4_PRIV7_Pos                   (7UL)
#define FLASH_PRIVBB1R4_PRIV7_Msk                   (0x1UL << FLASH_PRIVBB1R4_PRIV7_Pos)            /*!< 0x00000080 */
#define FLASH_PRIVBB1R4_PRIV7                       FLASH_PRIVBB1R4_PRIV7_Msk                       /*!< Page 103 in bank 1 block-based privilege */
#define FLASH_PRIVBB1R4_PRIV8_Pos                   (8UL)
#define FLASH_PRIVBB1R4_PRIV8_Msk                   (0x1UL << FLASH_PRIVBB1R4_PRIV8_Pos)            /*!< 0x00000100 */
#define FLASH_PRIVBB1R4_PRIV8                       FLASH_PRIVBB1R4_PRIV8_Msk                       /*!< Page 104 in bank 1 block-based privilege */
#define FLASH_PRIVBB1R4_PRIV9_Pos                   (9UL)
#define FLASH_PRIVBB1R4_PRIV9_Msk                   (0x1UL << FLASH_PRIVBB1R4_PRIV9_Pos)            /*!< 0x00000200 */
#define FLASH_PRIVBB1R4_PRIV9                       FLASH_PRIVBB1R4_PRIV9_Msk                       /*!< Page 105 in bank 1 block-based privilege */
#define FLASH_PRIVBB1R4_PRIV10_Pos                  (10UL)
#define FLASH_PRIVBB1R4_PRIV10_Msk                  (0x1UL << FLASH_PRIVBB1R4_PRIV10_Pos)           /*!< 0x00000400 */
#define FLASH_PRIVBB1R4_PRIV10                      FLASH_PRIVBB1R4_PRIV10_Msk                      /*!< Page 106 in bank 1 block-based privilege */
#define FLASH_PRIVBB1R4_PRIV11_Pos                  (11UL)
#define FLASH_PRIVBB1R4_PRIV11_Msk                  (0x1UL << FLASH_PRIVBB1R4_PRIV11_Pos)           /*!< 0x00000800 */
#define FLASH_PRIVBB1R4_PRIV11                      FLASH_PRIVBB1R4_PRIV11_Msk                      /*!< Page 107 in bank 1 block-based privilege */
#define FLASH_PRIVBB1R4_PRIV12_Pos                  (12UL)
#define FLASH_PRIVBB1R4_PRIV12_Msk                  (0x1UL << FLASH_PRIVBB1R4_PRIV12_Pos)           /*!< 0x00001000 */
#define FLASH_PRIVBB1R4_PRIV12                      FLASH_PRIVBB1R4_PRIV12_Msk                      /*!< Page 108 in bank 1 block-based privilege */
#define FLASH_PRIVBB1R4_PRIV13_Pos                  (13UL)
#define FLASH_PRIVBB1R4_PRIV13_Msk                  (0x1UL << FLASH_PRIVBB1R4_PRIV13_Pos)           /*!< 0x00002000 */
#define FLASH_PRIVBB1R4_PRIV13                      FLASH_PRIVBB1R4_PRIV13_Msk                      /*!< Page 109 in bank 1 block-based privilege */
#define FLASH_PRIVBB1R4_PRIV14_Pos                  (14UL)
#define FLASH_PRIVBB1R4_PRIV14_Msk                  (0x1UL << FLASH_PRIVBB1R4_PRIV14_Pos)           /*!< 0x00004000 */
#define FLASH_PRIVBB1R4_PRIV14                      FLASH_PRIVBB1R4_PRIV14_Msk                      /*!< Page 110 in bank 1 block-based privilege */
#define FLASH_PRIVBB1R4_PRIV15_Pos                  (15UL)
#define FLASH_PRIVBB1R4_PRIV15_Msk                  (0x1UL << FLASH_PRIVBB1R4_PRIV15_Pos)           /*!< 0x00008000 */
#define FLASH_PRIVBB1R4_PRIV15                      FLASH_PRIVBB1R4_PRIV15_Msk                      /*!< Page 111 in bank 1 block-based privilege */
#define FLASH_PRIVBB1R4_PRIV16_Pos                  (16UL)
#define FLASH_PRIVBB1R4_PRIV16_Msk                  (0x1UL << FLASH_PRIVBB1R4_PRIV16_Pos)           /*!< 0x00010000 */
#define FLASH_PRIVBB1R4_PRIV16                      FLASH_PRIVBB1R4_PRIV16_Msk                      /*!< Page 112 in bank 1 block-based privilege */
#define FLASH_PRIVBB1R4_PRIV17_Pos                  (17UL)
#define FLASH_PRIVBB1R4_PRIV17_Msk                  (0x1UL << FLASH_PRIVBB1R4_PRIV17_Pos)           /*!< 0x00020000 */
#define FLASH_PRIVBB1R4_PRIV17                      FLASH_PRIVBB1R4_PRIV17_Msk                      /*!< Page 113 in bank 1 block-based privilege */
#define FLASH_PRIVBB1R4_PRIV18_Pos                  (18UL)
#define FLASH_PRIVBB1R4_PRIV18_Msk                  (0x1UL << FLASH_PRIVBB1R4_PRIV18_Pos)           /*!< 0x00040000 */
#define FLASH_PRIVBB1R4_PRIV18                      FLASH_PRIVBB1R4_PRIV18_Msk                      /*!< Page 114 in bank 1 block-based privilege */
#define FLASH_PRIVBB1R4_PRIV19_Pos                  (19UL)
#define FLASH_PRIVBB1R4_PRIV19_Msk                  (0x1UL << FLASH_PRIVBB1R4_PRIV19_Pos)           /*!< 0x00080000 */
#define FLASH_PRIVBB1R4_PRIV19                      FLASH_PRIVBB1R4_PRIV19_Msk                      /*!< Page 115 in bank 1 block-based privilege */
#define FLASH_PRIVBB1R4_PRIV20_Pos                  (20UL)
#define FLASH_PRIVBB1R4_PRIV20_Msk                  (0x1UL << FLASH_PRIVBB1R4_PRIV20_Pos)           /*!< 0x00100000 */
#define FLASH_PRIVBB1R4_PRIV20                      FLASH_PRIVBB1R4_PRIV20_Msk                      /*!< Page 116 in bank 1 block-based privilege */
#define FLASH_PRIVBB1R4_PRIV21_Pos                  (21UL)
#define FLASH_PRIVBB1R4_PRIV21_Msk                  (0x1UL << FLASH_PRIVBB1R4_PRIV21_Pos)           /*!< 0x00200000 */
#define FLASH_PRIVBB1R4_PRIV21                      FLASH_PRIVBB1R4_PRIV21_Msk                      /*!< Page 117 in bank 1 block-based privilege */
#define FLASH_PRIVBB1R4_PRIV22_Pos                  (22UL)
#define FLASH_PRIVBB1R4_PRIV22_Msk                  (0x1UL << FLASH_PRIVBB1R4_PRIV22_Pos)           /*!< 0x00400000 */
#define FLASH_PRIVBB1R4_PRIV22                      FLASH_PRIVBB1R4_PRIV22_Msk                      /*!< Page 118 in bank 1 block-based privilege */
#define FLASH_PRIVBB1R4_PRIV23_Pos                  (23UL)
#define FLASH_PRIVBB1R4_PRIV23_Msk                  (0x1UL << FLASH_PRIVBB1R4_PRIV23_Pos)           /*!< 0x00800000 */
#define FLASH_PRIVBB1R4_PRIV23                      FLASH_PRIVBB1R4_PRIV23_Msk                      /*!< Page 119 in bank 1 block-based privilege */
#define FLASH_PRIVBB1R4_PRIV24_Pos                  (24UL)
#define FLASH_PRIVBB1R4_PRIV24_Msk                  (0x1UL << FLASH_PRIVBB1R4_PRIV24_Pos)           /*!< 0x01000000 */
#define FLASH_PRIVBB1R4_PRIV24                      FLASH_PRIVBB1R4_PRIV24_Msk                      /*!< Page 120 in bank 1 block-based privilege */
#define FLASH_PRIVBB1R4_PRIV25_Pos                  (25UL)
#define FLASH_PRIVBB1R4_PRIV25_Msk                  (0x1UL << FLASH_PRIVBB1R4_PRIV25_Pos)           /*!< 0x02000000 */
#define FLASH_PRIVBB1R4_PRIV25                      FLASH_PRIVBB1R4_PRIV25_Msk                      /*!< Page 121 in bank 1 block-based privilege */
#define FLASH_PRIVBB1R4_PRIV26_Pos                  (26UL)
#define FLASH_PRIVBB1R4_PRIV26_Msk                  (0x1UL << FLASH_PRIVBB1R4_PRIV26_Pos)           /*!< 0x04000000 */
#define FLASH_PRIVBB1R4_PRIV26                      FLASH_PRIVBB1R4_PRIV26_Msk                      /*!< Page 122 in bank 1 block-based privilege */
#define FLASH_PRIVBB1R4_PRIV27_Pos                  (27UL)
#define FLASH_PRIVBB1R4_PRIV27_Msk                  (0x1UL << FLASH_PRIVBB1R4_PRIV27_Pos)           /*!< 0x08000000 */
#define FLASH_PRIVBB1R4_PRIV27                      FLASH_PRIVBB1R4_PRIV27_Msk                      /*!< Page 123 in bank 1 block-based privilege */
#define FLASH_PRIVBB1R4_PRIV28_Pos                  (28UL)
#define FLASH_PRIVBB1R4_PRIV28_Msk                  (0x1UL << FLASH_PRIVBB1R4_PRIV28_Pos)           /*!< 0x10000000 */
#define FLASH_PRIVBB1R4_PRIV28                      FLASH_PRIVBB1R4_PRIV28_Msk                      /*!< Page 124 in bank 1 block-based privilege */
#define FLASH_PRIVBB1R4_PRIV29_Pos                  (29UL)
#define FLASH_PRIVBB1R4_PRIV29_Msk                  (0x1UL << FLASH_PRIVBB1R4_PRIV29_Pos)           /*!< 0x20000000 */
#define FLASH_PRIVBB1R4_PRIV29                      FLASH_PRIVBB1R4_PRIV29_Msk                      /*!< Page 125 in bank 1 block-based privilege */
#define FLASH_PRIVBB1R4_PRIV30_Pos                  (30UL)
#define FLASH_PRIVBB1R4_PRIV30_Msk                  (0x1UL << FLASH_PRIVBB1R4_PRIV30_Pos)           /*!< 0x40000000 */
#define FLASH_PRIVBB1R4_PRIV30                      FLASH_PRIVBB1R4_PRIV30_Msk                      /*!< Page 126 in bank 1 block-based privilege */
#define FLASH_PRIVBB1R4_PRIV31_Pos                  (31UL)
#define FLASH_PRIVBB1R4_PRIV31_Msk                  (0x1UL << FLASH_PRIVBB1R4_PRIV31_Pos)           /*!< 0x80000000 */
#define FLASH_PRIVBB1R4_PRIV31                      FLASH_PRIVBB1R4_PRIV31_Msk                      /*!< Page 127 in bank 1 block-based privilege */

/*******************  Bit definition for FLASH_PRIVBB2R1 register  ******************/
#define FLASH_PRIVBB2R1_PRIV0_Pos                   (0UL)
#define FLASH_PRIVBB2R1_PRIV0_Msk                   (0x1UL << FLASH_PRIVBB2R1_PRIV0_Pos)            /*!< 0x00000001 */
#define FLASH_PRIVBB2R1_PRIV0                       FLASH_PRIVBB2R1_PRIV0_Msk                       /*!< Page 0 in bank 2 block-based privilege */
#define FLASH_PRIVBB2R1_PRIV1_Pos                   (1UL)
#define FLASH_PRIVBB2R1_PRIV1_Msk                   (0x1UL << FLASH_PRIVBB2R1_PRIV1_Pos)            /*!< 0x00000002 */
#define FLASH_PRIVBB2R1_PRIV1                       FLASH_PRIVBB2R1_PRIV1_Msk                       /*!< Page 1 in bank 2 block-based privilege */
#define FLASH_PRIVBB2R1_PRIV2_Pos                   (2UL)
#define FLASH_PRIVBB2R1_PRIV2_Msk                   (0x1UL << FLASH_PRIVBB2R1_PRIV2_Pos)            /*!< 0x00000004 */
#define FLASH_PRIVBB2R1_PRIV2                       FLASH_PRIVBB2R1_PRIV2_Msk                       /*!< Page 2 in bank 2 block-based privilege */
#define FLASH_PRIVBB2R1_PRIV3_Pos                   (3UL)
#define FLASH_PRIVBB2R1_PRIV3_Msk                   (0x1UL << FLASH_PRIVBB2R1_PRIV3_Pos)            /*!< 0x00000008 */
#define FLASH_PRIVBB2R1_PRIV3                       FLASH_PRIVBB2R1_PRIV3_Msk                       /*!< Page 3 in bank 2 block-based privilege */
#define FLASH_PRIVBB2R1_PRIV4_Pos                   (4UL)
#define FLASH_PRIVBB2R1_PRIV4_Msk                   (0x1UL << FLASH_PRIVBB2R1_PRIV4_Pos)            /*!< 0x00000010 */
#define FLASH_PRIVBB2R1_PRIV4                       FLASH_PRIVBB2R1_PRIV4_Msk                       /*!< Page 4 in bank 2 block-based privilege */
#define FLASH_PRIVBB2R1_PRIV5_Pos                   (5UL)
#define FLASH_PRIVBB2R1_PRIV5_Msk                   (0x1UL << FLASH_PRIVBB2R1_PRIV5_Pos)            /*!< 0x00000020 */
#define FLASH_PRIVBB2R1_PRIV5                       FLASH_PRIVBB2R1_PRIV5_Msk                       /*!< Page 5 in bank 2 block-based privilege */
#define FLASH_PRIVBB2R1_PRIV6_Pos                   (6UL)
#define FLASH_PRIVBB2R1_PRIV6_Msk                   (0x1UL << FLASH_PRIVBB2R1_PRIV6_Pos)            /*!< 0x00000040 */
#define FLASH_PRIVBB2R1_PRIV6                       FLASH_PRIVBB2R1_PRIV6_Msk                       /*!< Page 6 in bank 2 block-based privilege */
#define FLASH_PRIVBB2R1_PRIV7_Pos                   (7UL)
#define FLASH_PRIVBB2R1_PRIV7_Msk                   (0x1UL << FLASH_PRIVBB2R1_PRIV7_Pos)            /*!< 0x00000080 */
#define FLASH_PRIVBB2R1_PRIV7                       FLASH_PRIVBB2R1_PRIV7_Msk                       /*!< Page 7 in bank 2 block-based privilege */
#define FLASH_PRIVBB2R1_PRIV8_Pos                   (8UL)
#define FLASH_PRIVBB2R1_PRIV8_Msk                   (0x1UL << FLASH_PRIVBB2R1_PRIV8_Pos)            /*!< 0x00000100 */
#define FLASH_PRIVBB2R1_PRIV8                       FLASH_PRIVBB2R1_PRIV8_Msk                       /*!< Page 8 in bank 2 block-based privilege */
#define FLASH_PRIVBB2R1_PRIV9_Pos                   (9UL)
#define FLASH_PRIVBB2R1_PRIV9_Msk                   (0x1UL << FLASH_PRIVBB2R1_PRIV9_Pos)            /*!< 0x00000200 */
#define FLASH_PRIVBB2R1_PRIV9                       FLASH_PRIVBB2R1_PRIV9_Msk                       /*!< Page 9 in bank 2 block-based privilege */
#define FLASH_PRIVBB2R1_PRIV10_Pos                  (10UL)
#define FLASH_PRIVBB2R1_PRIV10_Msk                  (0x1UL << FLASH_PRIVBB2R1_PRIV10_Pos)           /*!< 0x00000400 */
#define FLASH_PRIVBB2R1_PRIV10                      FLASH_PRIVBB2R1_PRIV10_Msk                      /*!< Page 10 in bank 2 block-based privilege */
#define FLASH_PRIVBB2R1_PRIV11_Pos                  (11UL)
#define FLASH_PRIVBB2R1_PRIV11_Msk                  (0x1UL << FLASH_PRIVBB2R1_PRIV11_Pos)           /*!< 0x00000800 */
#define FLASH_PRIVBB2R1_PRIV11                      FLASH_PRIVBB2R1_PRIV11_Msk                      /*!< Page 11 in bank 2 block-based privilege */
#define FLASH_PRIVBB2R1_PRIV12_Pos                  (12UL)
#define FLASH_PRIVBB2R1_PRIV12_Msk                  (0x1UL << FLASH_PRIVBB2R1_PRIV12_Pos)           /*!< 0x00001000 */
#define FLASH_PRIVBB2R1_PRIV12                      FLASH_PRIVBB2R1_PRIV12_Msk                      /*!< Page 12 in bank 2 block-based privilege */
#define FLASH_PRIVBB2R1_PRIV13_Pos                  (13UL)
#define FLASH_PRIVBB2R1_PRIV13_Msk                  (0x1UL << FLASH_PRIVBB2R1_PRIV13_Pos)           /*!< 0x00002000 */
#define FLASH_PRIVBB2R1_PRIV13                      FLASH_PRIVBB2R1_PRIV13_Msk                      /*!< Page 13 in bank 2 block-based privilege */
#define FLASH_PRIVBB2R1_PRIV14_Pos                  (14UL)
#define FLASH_PRIVBB2R1_PRIV14_Msk                  (0x1UL << FLASH_PRIVBB2R1_PRIV14_Pos)           /*!< 0x00004000 */
#define FLASH_PRIVBB2R1_PRIV14                      FLASH_PRIVBB2R1_PRIV14_Msk                      /*!< Page 14 in bank 2 block-based privilege */
#define FLASH_PRIVBB2R1_PRIV15_Pos                  (15UL)
#define FLASH_PRIVBB2R1_PRIV15_Msk                  (0x1UL << FLASH_PRIVBB2R1_PRIV15_Pos)           /*!< 0x00008000 */
#define FLASH_PRIVBB2R1_PRIV15                      FLASH_PRIVBB2R1_PRIV15_Msk                      /*!< Page 15 in bank 2 block-based privilege */
#define FLASH_PRIVBB2R1_PRIV16_Pos                  (16UL)
#define FLASH_PRIVBB2R1_PRIV16_Msk                  (0x1UL << FLASH_PRIVBB2R1_PRIV16_Pos)           /*!< 0x00010000 */
#define FLASH_PRIVBB2R1_PRIV16                      FLASH_PRIVBB2R1_PRIV16_Msk                      /*!< Page 16 in bank 2 block-based privilege */
#define FLASH_PRIVBB2R1_PRIV17_Pos                  (17UL)
#define FLASH_PRIVBB2R1_PRIV17_Msk                  (0x1UL << FLASH_PRIVBB2R1_PRIV17_Pos)           /*!< 0x00020000 */
#define FLASH_PRIVBB2R1_PRIV17                      FLASH_PRIVBB2R1_PRIV17_Msk                      /*!< Page 17 in bank 2 block-based privilege */
#define FLASH_PRIVBB2R1_PRIV18_Pos                  (18UL)
#define FLASH_PRIVBB2R1_PRIV18_Msk                  (0x1UL << FLASH_PRIVBB2R1_PRIV18_Pos)           /*!< 0x00040000 */
#define FLASH_PRIVBB2R1_PRIV18                      FLASH_PRIVBB2R1_PRIV18_Msk                      /*!< Page 18 in bank 2 block-based privilege */
#define FLASH_PRIVBB2R1_PRIV19_Pos                  (19UL)
#define FLASH_PRIVBB2R1_PRIV19_Msk                  (0x1UL << FLASH_PRIVBB2R1_PRIV19_Pos)           /*!< 0x00080000 */
#define FLASH_PRIVBB2R1_PRIV19                      FLASH_PRIVBB2R1_PRIV19_Msk                      /*!< Page 19 in bank 2 block-based privilege */
#define FLASH_PRIVBB2R1_PRIV20_Pos                  (20UL)
#define FLASH_PRIVBB2R1_PRIV20_Msk                  (0x1UL << FLASH_PRIVBB2R1_PRIV20_Pos)           /*!< 0x00100000 */
#define FLASH_PRIVBB2R1_PRIV20                      FLASH_PRIVBB2R1_PRIV20_Msk                      /*!< Page 20 in bank 2 block-based privilege */
#define FLASH_PRIVBB2R1_PRIV21_Pos                  (21UL)
#define FLASH_PRIVBB2R1_PRIV21_Msk                  (0x1UL << FLASH_PRIVBB2R1_PRIV21_Pos)           /*!< 0x00200000 */
#define FLASH_PRIVBB2R1_PRIV21                      FLASH_PRIVBB2R1_PRIV21_Msk                      /*!< Page 21 in bank 2 block-based privilege */
#define FLASH_PRIVBB2R1_PRIV22_Pos                  (22UL)
#define FLASH_PRIVBB2R1_PRIV22_Msk                  (0x1UL << FLASH_PRIVBB2R1_PRIV22_Pos)           /*!< 0x00400000 */
#define FLASH_PRIVBB2R1_PRIV22                      FLASH_PRIVBB2R1_PRIV22_Msk                      /*!< Page 22 in bank 2 block-based privilege */
#define FLASH_PRIVBB2R1_PRIV23_Pos                  (23UL)
#define FLASH_PRIVBB2R1_PRIV23_Msk                  (0x1UL << FLASH_PRIVBB2R1_PRIV23_Pos)           /*!< 0x00800000 */
#define FLASH_PRIVBB2R1_PRIV23                      FLASH_PRIVBB2R1_PRIV23_Msk                      /*!< Page 23 in bank 2 block-based privilege */
#define FLASH_PRIVBB2R1_PRIV24_Pos                  (24UL)
#define FLASH_PRIVBB2R1_PRIV24_Msk                  (0x1UL << FLASH_PRIVBB2R1_PRIV24_Pos)           /*!< 0x01000000 */
#define FLASH_PRIVBB2R1_PRIV24                      FLASH_PRIVBB2R1_PRIV24_Msk                      /*!< Page 24 in bank 2 block-based privilege */
#define FLASH_PRIVBB2R1_PRIV25_Pos                  (25UL)
#define FLASH_PRIVBB2R1_PRIV25_Msk                  (0x1UL << FLASH_PRIVBB2R1_PRIV25_Pos)           /*!< 0x02000000 */
#define FLASH_PRIVBB2R1_PRIV25                      FLASH_PRIVBB2R1_PRIV25_Msk                      /*!< Page 25 in bank 2 block-based privilege */
#define FLASH_PRIVBB2R1_PRIV26_Pos                  (26UL)
#define FLASH_PRIVBB2R1_PRIV26_Msk                  (0x1UL << FLASH_PRIVBB2R1_PRIV26_Pos)           /*!< 0x04000000 */
#define FLASH_PRIVBB2R1_PRIV26                      FLASH_PRIVBB2R1_PRIV26_Msk                      /*!< Page 26 in bank 2 block-based privilege */
#define FLASH_PRIVBB2R1_PRIV27_Pos                  (27UL)
#define FLASH_PRIVBB2R1_PRIV27_Msk                  (0x1UL << FLASH_PRIVBB2R1_PRIV27_Pos)           /*!< 0x08000000 */
#define FLASH_PRIVBB2R1_PRIV27                      FLASH_PRIVBB2R1_PRIV27_Msk                      /*!< Page 27 in bank 2 block-based privilege */
#define FLASH_PRIVBB2R1_PRIV28_Pos                  (28UL)
#define FLASH_PRIVBB2R1_PRIV28_Msk                  (0x1UL << FLASH_PRIVBB2R1_PRIV28_Pos)           /*!< 0x10000000 */
#define FLASH_PRIVBB2R1_PRIV28                      FLASH_PRIVBB2R1_PRIV28_Msk                      /*!< Page 28 in bank 2 block-based privilege */
#define FLASH_PRIVBB2R1_PRIV29_Pos                  (29UL)
#define FLASH_PRIVBB2R1_PRIV29_Msk                  (0x1UL << FLASH_PRIVBB2R1_PRIV29_Pos)           /*!< 0x20000000 */
#define FLASH_PRIVBB2R1_PRIV29                      FLASH_PRIVBB2R1_PRIV29_Msk                      /*!< Page 29 in bank 2 block-based privilege */
#define FLASH_PRIVBB2R1_PRIV30_Pos                  (30UL)
#define FLASH_PRIVBB2R1_PRIV30_Msk                  (0x1UL << FLASH_PRIVBB2R1_PRIV30_Pos)           /*!< 0x40000000 */
#define FLASH_PRIVBB2R1_PRIV30                      FLASH_PRIVBB2R1_PRIV30_Msk                      /*!< Page 30 in bank 2 block-based privilege */
#define FLASH_PRIVBB2R1_PRIV31_Pos                  (31UL)
#define FLASH_PRIVBB2R1_PRIV31_Msk                  (0x1UL << FLASH_PRIVBB2R1_PRIV31_Pos)           /*!< 0x80000000 */
#define FLASH_PRIVBB2R1_PRIV31                      FLASH_PRIVBB2R1_PRIV31_Msk                      /*!< Page 31 in bank 2 block-based privilege */

/*******************  Bit definition for FLASH_PRIVBB2R2 register  ******************/
#define FLASH_PRIVBB2R2_PRIV0_Pos                   (0UL)
#define FLASH_PRIVBB2R2_PRIV0_Msk                   (0x1UL << FLASH_PRIVBB2R2_PRIV0_Pos)            /*!< 0x00000001 */
#define FLASH_PRIVBB2R2_PRIV0                       FLASH_PRIVBB2R2_PRIV0_Msk                       /*!< Page 32 in bank 2 block-based privilege */
#define FLASH_PRIVBB2R2_PRIV1_Pos                   (1UL)
#define FLASH_PRIVBB2R2_PRIV1_Msk                   (0x1UL << FLASH_PRIVBB2R2_PRIV1_Pos)            /*!< 0x00000002 */
#define FLASH_PRIVBB2R2_PRIV1                       FLASH_PRIVBB2R2_PRIV1_Msk                       /*!< Page 33 in bank 2 block-based privilege */
#define FLASH_PRIVBB2R2_PRIV2_Pos                   (2UL)
#define FLASH_PRIVBB2R2_PRIV2_Msk                   (0x1UL << FLASH_PRIVBB2R2_PRIV2_Pos)            /*!< 0x00000004 */
#define FLASH_PRIVBB2R2_PRIV2                       FLASH_PRIVBB2R2_PRIV2_Msk                       /*!< Page 34 in bank 2 block-based privilege */
#define FLASH_PRIVBB2R2_PRIV3_Pos                   (3UL)
#define FLASH_PRIVBB2R2_PRIV3_Msk                   (0x1UL << FLASH_PRIVBB2R2_PRIV3_Pos)            /*!< 0x00000008 */
#define FLASH_PRIVBB2R2_PRIV3                       FLASH_PRIVBB2R2_PRIV3_Msk                       /*!< Page 35 in bank 2 block-based privilege */
#define FLASH_PRIVBB2R2_PRIV4_Pos                   (4UL)
#define FLASH_PRIVBB2R2_PRIV4_Msk                   (0x1UL << FLASH_PRIVBB2R2_PRIV4_Pos)            /*!< 0x00000010 */
#define FLASH_PRIVBB2R2_PRIV4                       FLASH_PRIVBB2R2_PRIV4_Msk                       /*!< Page 36 in bank 2 block-based privilege */
#define FLASH_PRIVBB2R2_PRIV5_Pos                   (5UL)
#define FLASH_PRIVBB2R2_PRIV5_Msk                   (0x1UL << FLASH_PRIVBB2R2_PRIV5_Pos)            /*!< 0x00000020 */
#define FLASH_PRIVBB2R2_PRIV5                       FLASH_PRIVBB2R2_PRIV5_Msk                       /*!< Page 37 in bank 2 block-based privilege */
#define FLASH_PRIVBB2R2_PRIV6_Pos                   (6UL)
#define FLASH_PRIVBB2R2_PRIV6_Msk                   (0x1UL << FLASH_PRIVBB2R2_PRIV6_Pos)            /*!< 0x00000040 */
#define FLASH_PRIVBB2R2_PRIV6                       FLASH_PRIVBB2R2_PRIV6_Msk                       /*!< Page 38 in bank 2 block-based privilege */
#define FLASH_PRIVBB2R2_PRIV7_Pos                   (7UL)
#define FLASH_PRIVBB2R2_PRIV7_Msk                   (0x1UL << FLASH_PRIVBB2R2_PRIV7_Pos)            /*!< 0x00000080 */
#define FLASH_PRIVBB2R2_PRIV7                       FLASH_PRIVBB2R2_PRIV7_Msk                       /*!< Page 39 in bank 2 block-based privilege */
#define FLASH_PRIVBB2R2_PRIV8_Pos                   (8UL)
#define FLASH_PRIVBB2R2_PRIV8_Msk                   (0x1UL << FLASH_PRIVBB2R2_PRIV8_Pos)            /*!< 0x00000100 */
#define FLASH_PRIVBB2R2_PRIV8                       FLASH_PRIVBB2R2_PRIV8_Msk                       /*!< Page 40 in bank 2 block-based privilege */
#define FLASH_PRIVBB2R2_PRIV9_Pos                   (9UL)
#define FLASH_PRIVBB2R2_PRIV9_Msk                   (0x1UL << FLASH_PRIVBB2R2_PRIV9_Pos)            /*!< 0x00000200 */
#define FLASH_PRIVBB2R2_PRIV9                       FLASH_PRIVBB2R2_PRIV9_Msk                       /*!< Page 41 in bank 2 block-based privilege */
#define FLASH_PRIVBB2R2_PRIV10_Pos                  (10UL)
#define FLASH_PRIVBB2R2_PRIV10_Msk                  (0x1UL << FLASH_PRIVBB2R2_PRIV10_Pos)           /*!< 0x00000400 */
#define FLASH_PRIVBB2R2_PRIV10                      FLASH_PRIVBB2R2_PRIV10_Msk                      /*!< Page 42 in bank 2 block-based privilege */
#define FLASH_PRIVBB2R2_PRIV11_Pos                  (11UL)
#define FLASH_PRIVBB2R2_PRIV11_Msk                  (0x1UL << FLASH_PRIVBB2R2_PRIV11_Pos)           /*!< 0x00000800 */
#define FLASH_PRIVBB2R2_PRIV11                      FLASH_PRIVBB2R2_PRIV11_Msk                      /*!< Page 43 in bank 2 block-based privilege */
#define FLASH_PRIVBB2R2_PRIV12_Pos                  (12UL)
#define FLASH_PRIVBB2R2_PRIV12_Msk                  (0x1UL << FLASH_PRIVBB2R2_PRIV12_Pos)           /*!< 0x00001000 */
#define FLASH_PRIVBB2R2_PRIV12                      FLASH_PRIVBB2R2_PRIV12_Msk                      /*!< Page 44 in bank 2 block-based privilege */
#define FLASH_PRIVBB2R2_PRIV13_Pos                  (13UL)
#define FLASH_PRIVBB2R2_PRIV13_Msk                  (0x1UL << FLASH_PRIVBB2R2_PRIV13_Pos)           /*!< 0x00002000 */
#define FLASH_PRIVBB2R2_PRIV13                      FLASH_PRIVBB2R2_PRIV13_Msk                      /*!< Page 45 in bank 2 block-based privilege */
#define FLASH_PRIVBB2R2_PRIV14_Pos                  (14UL)
#define FLASH_PRIVBB2R2_PRIV14_Msk                  (0x1UL << FLASH_PRIVBB2R2_PRIV14_Pos)           /*!< 0x00004000 */
#define FLASH_PRIVBB2R2_PRIV14                      FLASH_PRIVBB2R2_PRIV14_Msk                      /*!< Page 46 in bank 2 block-based privilege */
#define FLASH_PRIVBB2R2_PRIV15_Pos                  (15UL)
#define FLASH_PRIVBB2R2_PRIV15_Msk                  (0x1UL << FLASH_PRIVBB2R2_PRIV15_Pos)           /*!< 0x00008000 */
#define FLASH_PRIVBB2R2_PRIV15                      FLASH_PRIVBB2R2_PRIV15_Msk                      /*!< Page 47 in bank 2 block-based privilege */
#define FLASH_PRIVBB2R2_PRIV16_Pos                  (16UL)
#define FLASH_PRIVBB2R2_PRIV16_Msk                  (0x1UL << FLASH_PRIVBB2R2_PRIV16_Pos)           /*!< 0x00010000 */
#define FLASH_PRIVBB2R2_PRIV16                      FLASH_PRIVBB2R2_PRIV16_Msk                      /*!< Page 48 in bank 2 block-based privilege */
#define FLASH_PRIVBB2R2_PRIV17_Pos                  (17UL)
#define FLASH_PRIVBB2R2_PRIV17_Msk                  (0x1UL << FLASH_PRIVBB2R2_PRIV17_Pos)           /*!< 0x00020000 */
#define FLASH_PRIVBB2R2_PRIV17                      FLASH_PRIVBB2R2_PRIV17_Msk                      /*!< Page 49 in bank 2 block-based privilege */
#define FLASH_PRIVBB2R2_PRIV18_Pos                  (18UL)
#define FLASH_PRIVBB2R2_PRIV18_Msk                  (0x1UL << FLASH_PRIVBB2R2_PRIV18_Pos)           /*!< 0x00040000 */
#define FLASH_PRIVBB2R2_PRIV18                      FLASH_PRIVBB2R2_PRIV18_Msk                      /*!< Page 50 in bank 2 block-based privilege */
#define FLASH_PRIVBB2R2_PRIV19_Pos                  (19UL)
#define FLASH_PRIVBB2R2_PRIV19_Msk                  (0x1UL << FLASH_PRIVBB2R2_PRIV19_Pos)           /*!< 0x00080000 */
#define FLASH_PRIVBB2R2_PRIV19                      FLASH_PRIVBB2R2_PRIV19_Msk                      /*!< Page 51 in bank 2 block-based privilege */
#define FLASH_PRIVBB2R2_PRIV20_Pos                  (20UL)
#define FLASH_PRIVBB2R2_PRIV20_Msk                  (0x1UL << FLASH_PRIVBB2R2_PRIV20_Pos)           /*!< 0x00100000 */
#define FLASH_PRIVBB2R2_PRIV20                      FLASH_PRIVBB2R2_PRIV20_Msk                      /*!< Page 52 in bank 2 block-based privilege */
#define FLASH_PRIVBB2R2_PRIV21_Pos                  (21UL)
#define FLASH_PRIVBB2R2_PRIV21_Msk                  (0x1UL << FLASH_PRIVBB2R2_PRIV21_Pos)           /*!< 0x00200000 */
#define FLASH_PRIVBB2R2_PRIV21                      FLASH_PRIVBB2R2_PRIV21_Msk                      /*!< Page 53 in bank 2 block-based privilege */
#define FLASH_PRIVBB2R2_PRIV22_Pos                  (22UL)
#define FLASH_PRIVBB2R2_PRIV22_Msk                  (0x1UL << FLASH_PRIVBB2R2_PRIV22_Pos)           /*!< 0x00400000 */
#define FLASH_PRIVBB2R2_PRIV22                      FLASH_PRIVBB2R2_PRIV22_Msk                      /*!< Page 54 in bank 2 block-based privilege */
#define FLASH_PRIVBB2R2_PRIV23_Pos                  (23UL)
#define FLASH_PRIVBB2R2_PRIV23_Msk                  (0x1UL << FLASH_PRIVBB2R2_PRIV23_Pos)           /*!< 0x00800000 */
#define FLASH_PRIVBB2R2_PRIV23                      FLASH_PRIVBB2R2_PRIV23_Msk                      /*!< Page 55 in bank 2 block-based privilege */
#define FLASH_PRIVBB2R2_PRIV24_Pos                  (24UL)
#define FLASH_PRIVBB2R2_PRIV24_Msk                  (0x1UL << FLASH_PRIVBB2R2_PRIV24_Pos)           /*!< 0x01000000 */
#define FLASH_PRIVBB2R2_PRIV24                      FLASH_PRIVBB2R2_PRIV24_Msk                      /*!< Page 56 in bank 2 block-based privilege */
#define FLASH_PRIVBB2R2_PRIV25_Pos                  (25UL)
#define FLASH_PRIVBB2R2_PRIV25_Msk                  (0x1UL << FLASH_PRIVBB2R2_PRIV25_Pos)           /*!< 0x02000000 */
#define FLASH_PRIVBB2R2_PRIV25                      FLASH_PRIVBB2R2_PRIV25_Msk                      /*!< Page 57 in bank 2 block-based privilege */
#define FLASH_PRIVBB2R2_PRIV26_Pos                  (26UL)
#define FLASH_PRIVBB2R2_PRIV26_Msk                  (0x1UL << FLASH_PRIVBB2R2_PRIV26_Pos)           /*!< 0x04000000 */
#define FLASH_PRIVBB2R2_PRIV26                      FLASH_PRIVBB2R2_PRIV26_Msk                      /*!< Page 58 in bank 2 block-based privilege */
#define FLASH_PRIVBB2R2_PRIV27_Pos                  (27UL)
#define FLASH_PRIVBB2R2_PRIV27_Msk                  (0x1UL << FLASH_PRIVBB2R2_PRIV27_Pos)           /*!< 0x08000000 */
#define FLASH_PRIVBB2R2_PRIV27                      FLASH_PRIVBB2R2_PRIV27_Msk                      /*!< Page 59 in bank 2 block-based privilege */
#define FLASH_PRIVBB2R2_PRIV28_Pos                  (28UL)
#define FLASH_PRIVBB2R2_PRIV28_Msk                  (0x1UL << FLASH_PRIVBB2R2_PRIV28_Pos)           /*!< 0x10000000 */
#define FLASH_PRIVBB2R2_PRIV28                      FLASH_PRIVBB2R2_PRIV28_Msk                      /*!< Page 60 in bank 2 block-based privilege */
#define FLASH_PRIVBB2R2_PRIV29_Pos                  (29UL)
#define FLASH_PRIVBB2R2_PRIV29_Msk                  (0x1UL << FLASH_PRIVBB2R2_PRIV29_Pos)           /*!< 0x20000000 */
#define FLASH_PRIVBB2R2_PRIV29                      FLASH_PRIVBB2R2_PRIV29_Msk                      /*!< Page 61 in bank 2 block-based privilege */
#define FLASH_PRIVBB2R2_PRIV30_Pos                  (30UL)
#define FLASH_PRIVBB2R2_PRIV30_Msk                  (0x1UL << FLASH_PRIVBB2R2_PRIV30_Pos)           /*!< 0x40000000 */
#define FLASH_PRIVBB2R2_PRIV30                      FLASH_PRIVBB2R2_PRIV30_Msk                      /*!< Page 62 in bank 2 block-based privilege */
#define FLASH_PRIVBB2R2_PRIV31_Pos                  (31UL)
#define FLASH_PRIVBB2R2_PRIV31_Msk                  (0x1UL << FLASH_PRIVBB2R2_PRIV31_Pos)           /*!< 0x80000000 */
#define FLASH_PRIVBB2R2_PRIV31                      FLASH_PRIVBB2R2_PRIV31_Msk                      /*!< Page 63 in bank 2 block-based privilege */

/*******************  Bit definition for FLASH_PRIVBB2R3 register  ******************/
#define FLASH_PRIVBB2R3_PRIV0_Pos                   (0UL)
#define FLASH_PRIVBB2R3_PRIV0_Msk                   (0x1UL << FLASH_PRIVBB2R3_PRIV0_Pos)            /*!< 0x00000001 */
#define FLASH_PRIVBB2R3_PRIV0                       FLASH_PRIVBB2R3_PRIV0_Msk                       /*!< Page 64 in bank 2 block-based privilege */
#define FLASH_PRIVBB2R3_PRIV1_Pos                   (1UL)
#define FLASH_PRIVBB2R3_PRIV1_Msk                   (0x1UL << FLASH_PRIVBB2R3_PRIV1_Pos)            /*!< 0x00000002 */
#define FLASH_PRIVBB2R3_PRIV1                       FLASH_PRIVBB2R3_PRIV1_Msk                       /*!< Page 65 in bank 2 block-based privilege */
#define FLASH_PRIVBB2R3_PRIV2_Pos                   (2UL)
#define FLASH_PRIVBB2R3_PRIV2_Msk                   (0x1UL << FLASH_PRIVBB2R3_PRIV2_Pos)            /*!< 0x00000004 */
#define FLASH_PRIVBB2R3_PRIV2                       FLASH_PRIVBB2R3_PRIV2_Msk                       /*!< Page 66 in bank 2 block-based privilege */
#define FLASH_PRIVBB2R3_PRIV3_Pos                   (3UL)
#define FLASH_PRIVBB2R3_PRIV3_Msk                   (0x1UL << FLASH_PRIVBB2R3_PRIV3_Pos)            /*!< 0x00000008 */
#define FLASH_PRIVBB2R3_PRIV3                       FLASH_PRIVBB2R3_PRIV3_Msk                       /*!< Page 67 in bank 2 block-based privilege */
#define FLASH_PRIVBB2R3_PRIV4_Pos                   (4UL)
#define FLASH_PRIVBB2R3_PRIV4_Msk                   (0x1UL << FLASH_PRIVBB2R3_PRIV4_Pos)            /*!< 0x00000010 */
#define FLASH_PRIVBB2R3_PRIV4                       FLASH_PRIVBB2R3_PRIV4_Msk                       /*!< Page 68 in bank 2 block-based privilege */
#define FLASH_PRIVBB2R3_PRIV5_Pos                   (5UL)
#define FLASH_PRIVBB2R3_PRIV5_Msk                   (0x1UL << FLASH_PRIVBB2R3_PRIV5_Pos)            /*!< 0x00000020 */
#define FLASH_PRIVBB2R3_PRIV5                       FLASH_PRIVBB2R3_PRIV5_Msk                       /*!< Page 69 in bank 2 block-based privilege */
#define FLASH_PRIVBB2R3_PRIV6_Pos                   (6UL)
#define FLASH_PRIVBB2R3_PRIV6_Msk                   (0x1UL << FLASH_PRIVBB2R3_PRIV6_Pos)            /*!< 0x00000040 */
#define FLASH_PRIVBB2R3_PRIV6                       FLASH_PRIVBB2R3_PRIV6_Msk                       /*!< Page 70 in bank 2 block-based privilege */
#define FLASH_PRIVBB2R3_PRIV7_Pos                   (7UL)
#define FLASH_PRIVBB2R3_PRIV7_Msk                   (0x1UL << FLASH_PRIVBB2R3_PRIV7_Pos)            /*!< 0x00000080 */
#define FLASH_PRIVBB2R3_PRIV7                       FLASH_PRIVBB2R3_PRIV7_Msk                       /*!< Page 71 in bank 2 block-based privilege */
#define FLASH_PRIVBB2R3_PRIV8_Pos                   (8UL)
#define FLASH_PRIVBB2R3_PRIV8_Msk                   (0x1UL << FLASH_PRIVBB2R3_PRIV8_Pos)            /*!< 0x00000100 */
#define FLASH_PRIVBB2R3_PRIV8                       FLASH_PRIVBB2R3_PRIV8_Msk                       /*!< Page 72 in bank 2 block-based privilege */
#define FLASH_PRIVBB2R3_PRIV9_Pos                   (9UL)
#define FLASH_PRIVBB2R3_PRIV9_Msk                   (0x1UL << FLASH_PRIVBB2R3_PRIV9_Pos)            /*!< 0x00000200 */
#define FLASH_PRIVBB2R3_PRIV9                       FLASH_PRIVBB2R3_PRIV9_Msk                       /*!< Page 73 in bank 2 block-based privilege */
#define FLASH_PRIVBB2R3_PRIV10_Pos                  (10UL)
#define FLASH_PRIVBB2R3_PRIV10_Msk                  (0x1UL << FLASH_PRIVBB2R3_PRIV10_Pos)           /*!< 0x00000400 */
#define FLASH_PRIVBB2R3_PRIV10                      FLASH_PRIVBB2R3_PRIV10_Msk                      /*!< Page 74 in bank 2 block-based privilege */
#define FLASH_PRIVBB2R3_PRIV11_Pos                  (11UL)
#define FLASH_PRIVBB2R3_PRIV11_Msk                  (0x1UL << FLASH_PRIVBB2R3_PRIV11_Pos)           /*!< 0x00000800 */
#define FLASH_PRIVBB2R3_PRIV11                      FLASH_PRIVBB2R3_PRIV11_Msk                      /*!< Page 75 in bank 2 block-based privilege */
#define FLASH_PRIVBB2R3_PRIV12_Pos                  (12UL)
#define FLASH_PRIVBB2R3_PRIV12_Msk                  (0x1UL << FLASH_PRIVBB2R3_PRIV12_Pos)           /*!< 0x00001000 */
#define FLASH_PRIVBB2R3_PRIV12                      FLASH_PRIVBB2R3_PRIV12_Msk                      /*!< Page 76 in bank 2 block-based privilege */
#define FLASH_PRIVBB2R3_PRIV13_Pos                  (13UL)
#define FLASH_PRIVBB2R3_PRIV13_Msk                  (0x1UL << FLASH_PRIVBB2R3_PRIV13_Pos)           /*!< 0x00002000 */
#define FLASH_PRIVBB2R3_PRIV13                      FLASH_PRIVBB2R3_PRIV13_Msk                      /*!< Page 77 in bank 2 block-based privilege */
#define FLASH_PRIVBB2R3_PRIV14_Pos                  (14UL)
#define FLASH_PRIVBB2R3_PRIV14_Msk                  (0x1UL << FLASH_PRIVBB2R3_PRIV14_Pos)           /*!< 0x00004000 */
#define FLASH_PRIVBB2R3_PRIV14                      FLASH_PRIVBB2R3_PRIV14_Msk                      /*!< Page 78 in bank 2 block-based privilege */
#define FLASH_PRIVBB2R3_PRIV15_Pos                  (15UL)
#define FLASH_PRIVBB2R3_PRIV15_Msk                  (0x1UL << FLASH_PRIVBB2R3_PRIV15_Pos)           /*!< 0x00008000 */
#define FLASH_PRIVBB2R3_PRIV15                      FLASH_PRIVBB2R3_PRIV15_Msk                      /*!< Page 79 in bank 2 block-based privilege */
#define FLASH_PRIVBB2R3_PRIV16_Pos                  (16UL)
#define FLASH_PRIVBB2R3_PRIV16_Msk                  (0x1UL << FLASH_PRIVBB2R3_PRIV16_Pos)           /*!< 0x00010000 */
#define FLASH_PRIVBB2R3_PRIV16                      FLASH_PRIVBB2R3_PRIV16_Msk                      /*!< Page 80 in bank 2 block-based privilege */
#define FLASH_PRIVBB2R3_PRIV17_Pos                  (17UL)
#define FLASH_PRIVBB2R3_PRIV17_Msk                  (0x1UL << FLASH_PRIVBB2R3_PRIV17_Pos)           /*!< 0x00020000 */
#define FLASH_PRIVBB2R3_PRIV17                      FLASH_PRIVBB2R3_PRIV17_Msk                      /*!< Page 81 in bank 2 block-based privilege */
#define FLASH_PRIVBB2R3_PRIV18_Pos                  (18UL)
#define FLASH_PRIVBB2R3_PRIV18_Msk                  (0x1UL << FLASH_PRIVBB2R3_PRIV18_Pos)           /*!< 0x00040000 */
#define FLASH_PRIVBB2R3_PRIV18                      FLASH_PRIVBB2R3_PRIV18_Msk                      /*!< Page 82 in bank 2 block-based privilege */
#define FLASH_PRIVBB2R3_PRIV19_Pos                  (19UL)
#define FLASH_PRIVBB2R3_PRIV19_Msk                  (0x1UL << FLASH_PRIVBB2R3_PRIV19_Pos)           /*!< 0x00080000 */
#define FLASH_PRIVBB2R3_PRIV19                      FLASH_PRIVBB2R3_PRIV19_Msk                      /*!< Page 83 in bank 2 block-based privilege */
#define FLASH_PRIVBB2R3_PRIV20_Pos                  (20UL)
#define FLASH_PRIVBB2R3_PRIV20_Msk                  (0x1UL << FLASH_PRIVBB2R3_PRIV20_Pos)           /*!< 0x00100000 */
#define FLASH_PRIVBB2R3_PRIV20                      FLASH_PRIVBB2R3_PRIV20_Msk                      /*!< Page 84 in bank 2 block-based privilege */
#define FLASH_PRIVBB2R3_PRIV21_Pos                  (21UL)
#define FLASH_PRIVBB2R3_PRIV21_Msk                  (0x1UL << FLASH_PRIVBB2R3_PRIV21_Pos)           /*!< 0x00200000 */
#define FLASH_PRIVBB2R3_PRIV21                      FLASH_PRIVBB2R3_PRIV21_Msk                      /*!< Page 85 in bank 2 block-based privilege */
#define FLASH_PRIVBB2R3_PRIV22_Pos                  (22UL)
#define FLASH_PRIVBB2R3_PRIV22_Msk                  (0x1UL << FLASH_PRIVBB2R3_PRIV22_Pos)           /*!< 0x00400000 */
#define FLASH_PRIVBB2R3_PRIV22                      FLASH_PRIVBB2R3_PRIV22_Msk                      /*!< Page 86 in bank 2 block-based privilege */
#define FLASH_PRIVBB2R3_PRIV23_Pos                  (23UL)
#define FLASH_PRIVBB2R3_PRIV23_Msk                  (0x1UL << FLASH_PRIVBB2R3_PRIV23_Pos)           /*!< 0x00800000 */
#define FLASH_PRIVBB2R3_PRIV23                      FLASH_PRIVBB2R3_PRIV23_Msk                      /*!< Page 87 in bank 2 block-based privilege */
#define FLASH_PRIVBB2R3_PRIV24_Pos                  (24UL)
#define FLASH_PRIVBB2R3_PRIV24_Msk                  (0x1UL << FLASH_PRIVBB2R3_PRIV24_Pos)           /*!< 0x01000000 */
#define FLASH_PRIVBB2R3_PRIV24                      FLASH_PRIVBB2R3_PRIV24_Msk                      /*!< Page 88 in bank 2 block-based privilege */
#define FLASH_PRIVBB2R3_PRIV25_Pos                  (25UL)
#define FLASH_PRIVBB2R3_PRIV25_Msk                  (0x1UL << FLASH_PRIVBB2R3_PRIV25_Pos)           /*!< 0x02000000 */
#define FLASH_PRIVBB2R3_PRIV25                      FLASH_PRIVBB2R3_PRIV25_Msk                      /*!< Page 89 in bank 2 block-based privilege */
#define FLASH_PRIVBB2R3_PRIV26_Pos                  (26UL)
#define FLASH_PRIVBB2R3_PRIV26_Msk                  (0x1UL << FLASH_PRIVBB2R3_PRIV26_Pos)           /*!< 0x04000000 */
#define FLASH_PRIVBB2R3_PRIV26                      FLASH_PRIVBB2R3_PRIV26_Msk                      /*!< Page 90 in bank 2 block-based privilege */
#define FLASH_PRIVBB2R3_PRIV27_Pos                  (27UL)
#define FLASH_PRIVBB2R3_PRIV27_Msk                  (0x1UL << FLASH_PRIVBB2R3_PRIV27_Pos)           /*!< 0x08000000 */
#define FLASH_PRIVBB2R3_PRIV27                      FLASH_PRIVBB2R3_PRIV27_Msk                      /*!< Page 91 in bank 2 block-based privilege */
#define FLASH_PRIVBB2R3_PRIV28_Pos                  (28UL)
#define FLASH_PRIVBB2R3_PRIV28_Msk                  (0x1UL << FLASH_PRIVBB2R3_PRIV28_Pos)           /*!< 0x10000000 */
#define FLASH_PRIVBB2R3_PRIV28                      FLASH_PRIVBB2R3_PRIV28_Msk                      /*!< Page 92 in bank 2 block-based privilege */
#define FLASH_PRIVBB2R3_PRIV29_Pos                  (29UL)
#define FLASH_PRIVBB2R3_PRIV29_Msk                  (0x1UL << FLASH_PRIVBB2R3_PRIV29_Pos)           /*!< 0x20000000 */
#define FLASH_PRIVBB2R3_PRIV29                      FLASH_PRIVBB2R3_PRIV29_Msk                      /*!< Page 93 in bank 2 block-based privilege */
#define FLASH_PRIVBB2R3_PRIV30_Pos                  (30UL)
#define FLASH_PRIVBB2R3_PRIV30_Msk                  (0x1UL << FLASH_PRIVBB2R3_PRIV30_Pos)           /*!< 0x40000000 */
#define FLASH_PRIVBB2R3_PRIV30                      FLASH_PRIVBB2R3_PRIV30_Msk                      /*!< Page 94 in bank 2 block-based privilege */
#define FLASH_PRIVBB2R3_PRIV31_Pos                  (31UL)
#define FLASH_PRIVBB2R3_PRIV31_Msk                  (0x1UL << FLASH_PRIVBB2R3_PRIV31_Pos)           /*!< 0x80000000 */
#define FLASH_PRIVBB2R3_PRIV31                      FLASH_PRIVBB2R3_PRIV31_Msk                      /*!< Page 95 in bank 2 block-based privilege */

/*******************  Bit definition for FLASH_PRIVBB2R4 register  ******************/
#define FLASH_PRIVBB2R4_PRIV0_Pos                   (0UL)
#define FLASH_PRIVBB2R4_PRIV0_Msk                   (0x1UL << FLASH_PRIVBB2R4_PRIV0_Pos)            /*!< 0x00000001 */
#define FLASH_PRIVBB2R4_PRIV0                       FLASH_PRIVBB2R4_PRIV0_Msk                       /*!< Page 96 in bank 2 block-based privilege */
#define FLASH_PRIVBB2R4_PRIV1_Pos                   (1UL)
#define FLASH_PRIVBB2R4_PRIV1_Msk                   (0x1UL << FLASH_PRIVBB2R4_PRIV1_Pos)            /*!< 0x00000002 */
#define FLASH_PRIVBB2R4_PRIV1                       FLASH_PRIVBB2R4_PRIV1_Msk                       /*!< Page 97 in bank 2 block-based privilege */
#define FLASH_PRIVBB2R4_PRIV2_Pos                   (2UL)
#define FLASH_PRIVBB2R4_PRIV2_Msk                   (0x1UL << FLASH_PRIVBB2R4_PRIV2_Pos)            /*!< 0x00000004 */
#define FLASH_PRIVBB2R4_PRIV2                       FLASH_PRIVBB2R4_PRIV2_Msk                       /*!< Page 98 in bank 2 block-based privilege */
#define FLASH_PRIVBB2R4_PRIV3_Pos                   (3UL)
#define FLASH_PRIVBB2R4_PRIV3_Msk                   (0x1UL << FLASH_PRIVBB2R4_PRIV3_Pos)            /*!< 0x00000008 */
#define FLASH_PRIVBB2R4_PRIV3                       FLASH_PRIVBB2R4_PRIV3_Msk                       /*!< Page 99 in bank 2 block-based privilege */
#define FLASH_PRIVBB2R4_PRIV4_Pos                   (4UL)
#define FLASH_PRIVBB2R4_PRIV4_Msk                   (0x1UL << FLASH_PRIVBB2R4_PRIV4_Pos)            /*!< 0x00000010 */
#define FLASH_PRIVBB2R4_PRIV4                       FLASH_PRIVBB2R4_PRIV4_Msk                       /*!< Page 100 in bank 2 block-based privilege */
#define FLASH_PRIVBB2R4_PRIV5_Pos                   (5UL)
#define FLASH_PRIVBB2R4_PRIV5_Msk                   (0x1UL << FLASH_PRIVBB2R4_PRIV5_Pos)            /*!< 0x00000020 */
#define FLASH_PRIVBB2R4_PRIV5                       FLASH_PRIVBB2R4_PRIV5_Msk                       /*!< Page 101 in bank 2 block-based privilege */
#define FLASH_PRIVBB2R4_PRIV6_Pos                   (6UL)
#define FLASH_PRIVBB2R4_PRIV6_Msk                   (0x1UL << FLASH_PRIVBB2R4_PRIV6_Pos)            /*!< 0x00000040 */
#define FLASH_PRIVBB2R4_PRIV6                       FLASH_PRIVBB2R4_PRIV6_Msk                       /*!< Page 102 in bank 2 block-based privilege */
#define FLASH_PRIVBB2R4_PRIV7_Pos                   (7UL)
#define FLASH_PRIVBB2R4_PRIV7_Msk                   (0x1UL << FLASH_PRIVBB2R4_PRIV7_Pos)            /*!< 0x00000080 */
#define FLASH_PRIVBB2R4_PRIV7                       FLASH_PRIVBB2R4_PRIV7_Msk                       /*!< Page 103 in bank 2 block-based privilege */
#define FLASH_PRIVBB2R4_PRIV8_Pos                   (8UL)
#define FLASH_PRIVBB2R4_PRIV8_Msk                   (0x1UL << FLASH_PRIVBB2R4_PRIV8_Pos)            /*!< 0x00000100 */
#define FLASH_PRIVBB2R4_PRIV8                       FLASH_PRIVBB2R4_PRIV8_Msk                       /*!< Page 104 in bank 2 block-based privilege */
#define FLASH_PRIVBB2R4_PRIV9_Pos                   (9UL)
#define FLASH_PRIVBB2R4_PRIV9_Msk                   (0x1UL << FLASH_PRIVBB2R4_PRIV9_Pos)            /*!< 0x00000200 */
#define FLASH_PRIVBB2R4_PRIV9                       FLASH_PRIVBB2R4_PRIV9_Msk                       /*!< Page 105 in bank 2 block-based privilege */
#define FLASH_PRIVBB2R4_PRIV10_Pos                  (10UL)
#define FLASH_PRIVBB2R4_PRIV10_Msk                  (0x1UL << FLASH_PRIVBB2R4_PRIV10_Pos)           /*!< 0x00000400 */
#define FLASH_PRIVBB2R4_PRIV10                      FLASH_PRIVBB2R4_PRIV10_Msk                      /*!< Page 106 in bank 2 block-based privilege */
#define FLASH_PRIVBB2R4_PRIV11_Pos                  (11UL)
#define FLASH_PRIVBB2R4_PRIV11_Msk                  (0x1UL << FLASH_PRIVBB2R4_PRIV11_Pos)           /*!< 0x00000800 */
#define FLASH_PRIVBB2R4_PRIV11                      FLASH_PRIVBB2R4_PRIV11_Msk                      /*!< Page 107 in bank 2 block-based privilege */
#define FLASH_PRIVBB2R4_PRIV12_Pos                  (12UL)
#define FLASH_PRIVBB2R4_PRIV12_Msk                  (0x1UL << FLASH_PRIVBB2R4_PRIV12_Pos)           /*!< 0x00001000 */
#define FLASH_PRIVBB2R4_PRIV12                      FLASH_PRIVBB2R4_PRIV12_Msk                      /*!< Page 108 in bank 2 block-based privilege */
#define FLASH_PRIVBB2R4_PRIV13_Pos                  (13UL)
#define FLASH_PRIVBB2R4_PRIV13_Msk                  (0x1UL << FLASH_PRIVBB2R4_PRIV13_Pos)           /*!< 0x00002000 */
#define FLASH_PRIVBB2R4_PRIV13                      FLASH_PRIVBB2R4_PRIV13_Msk                      /*!< Page 109 in bank 2 block-based privilege */
#define FLASH_PRIVBB2R4_PRIV14_Pos                  (14UL)
#define FLASH_PRIVBB2R4_PRIV14_Msk                  (0x1UL << FLASH_PRIVBB2R4_PRIV14_Pos)           /*!< 0x00004000 */
#define FLASH_PRIVBB2R4_PRIV14                      FLASH_PRIVBB2R4_PRIV14_Msk                      /*!< Page 110 in bank 2 block-based privilege */
#define FLASH_PRIVBB2R4_PRIV15_Pos                  (15UL)
#define FLASH_PRIVBB2R4_PRIV15_Msk                  (0x1UL << FLASH_PRIVBB2R4_PRIV15_Pos)           /*!< 0x00008000 */
#define FLASH_PRIVBB2R4_PRIV15                      FLASH_PRIVBB2R4_PRIV15_Msk                      /*!< Page 111 in bank 2 block-based privilege */
#define FLASH_PRIVBB2R4_PRIV16_Pos                  (16UL)
#define FLASH_PRIVBB2R4_PRIV16_Msk                  (0x1UL << FLASH_PRIVBB2R4_PRIV16_Pos)           /*!< 0x00010000 */
#define FLASH_PRIVBB2R4_PRIV16                      FLASH_PRIVBB2R4_PRIV16_Msk                      /*!< Page 112 in bank 2 block-based privilege */
#define FLASH_PRIVBB2R4_PRIV17_Pos                  (17UL)
#define FLASH_PRIVBB2R4_PRIV17_Msk                  (0x1UL << FLASH_PRIVBB2R4_PRIV17_Pos)           /*!< 0x00020000 */
#define FLASH_PRIVBB2R4_PRIV17                      FLASH_PRIVBB2R4_PRIV17_Msk                      /*!< Page 113 in bank 2 block-based privilege */
#define FLASH_PRIVBB2R4_PRIV18_Pos                  (18UL)
#define FLASH_PRIVBB2R4_PRIV18_Msk                  (0x1UL << FLASH_PRIVBB2R4_PRIV18_Pos)           /*!< 0x00040000 */
#define FLASH_PRIVBB2R4_PRIV18                      FLASH_PRIVBB2R4_PRIV18_Msk                      /*!< Page 114 in bank 2 block-based privilege */
#define FLASH_PRIVBB2R4_PRIV19_Pos                  (19UL)
#define FLASH_PRIVBB2R4_PRIV19_Msk                  (0x1UL << FLASH_PRIVBB2R4_PRIV19_Pos)           /*!< 0x00080000 */
#define FLASH_PRIVBB2R4_PRIV19                      FLASH_PRIVBB2R4_PRIV19_Msk                      /*!< Page 115 in bank 2 block-based privilege */
#define FLASH_PRIVBB2R4_PRIV20_Pos                  (20UL)
#define FLASH_PRIVBB2R4_PRIV20_Msk                  (0x1UL << FLASH_PRIVBB2R4_PRIV20_Pos)           /*!< 0x00100000 */
#define FLASH_PRIVBB2R4_PRIV20                      FLASH_PRIVBB2R4_PRIV20_Msk                      /*!< Page 116 in bank 2 block-based privilege */
#define FLASH_PRIVBB2R4_PRIV21_Pos                  (21UL)
#define FLASH_PRIVBB2R4_PRIV21_Msk                  (0x1UL << FLASH_PRIVBB2R4_PRIV21_Pos)           /*!< 0x00200000 */
#define FLASH_PRIVBB2R4_PRIV21                      FLASH_PRIVBB2R4_PRIV21_Msk                      /*!< Page 117 in bank 2 block-based privilege */
#define FLASH_PRIVBB2R4_PRIV22_Pos                  (22UL)
#define FLASH_PRIVBB2R4_PRIV22_Msk                  (0x1UL << FLASH_PRIVBB2R4_PRIV22_Pos)           /*!< 0x00400000 */
#define FLASH_PRIVBB2R4_PRIV22                      FLASH_PRIVBB2R4_PRIV22_Msk                      /*!< Page 118 in bank 2 block-based privilege */
#define FLASH_PRIVBB2R4_PRIV23_Pos                  (23UL)
#define FLASH_PRIVBB2R4_PRIV23_Msk                  (0x1UL << FLASH_PRIVBB2R4_PRIV23_Pos)           /*!< 0x00800000 */
#define FLASH_PRIVBB2R4_PRIV23                      FLASH_PRIVBB2R4_PRIV23_Msk                      /*!< Page 119 in bank 2 block-based privilege */
#define FLASH_PRIVBB2R4_PRIV24_Pos                  (24UL)
#define FLASH_PRIVBB2R4_PRIV24_Msk                  (0x1UL << FLASH_PRIVBB2R4_PRIV24_Pos)           /*!< 0x01000000 */
#define FLASH_PRIVBB2R4_PRIV24                      FLASH_PRIVBB2R4_PRIV24_Msk                      /*!< Page 120 in bank 2 block-based privilege */
#define FLASH_PRIVBB2R4_PRIV25_Pos                  (25UL)
#define FLASH_PRIVBB2R4_PRIV25_Msk                  (0x1UL << FLASH_PRIVBB2R4_PRIV25_Pos)           /*!< 0x02000000 */
#define FLASH_PRIVBB2R4_PRIV25                      FLASH_PRIVBB2R4_PRIV25_Msk                      /*!< Page 121 in bank 2 block-based privilege */
#define FLASH_PRIVBB2R4_PRIV26_Pos                  (26UL)
#define FLASH_PRIVBB2R4_PRIV26_Msk                  (0x1UL << FLASH_PRIVBB2R4_PRIV26_Pos)           /*!< 0x04000000 */
#define FLASH_PRIVBB2R4_PRIV26                      FLASH_PRIVBB2R4_PRIV26_Msk                      /*!< Page 122 in bank 2 block-based privilege */
#define FLASH_PRIVBB2R4_PRIV27_Pos                  (27UL)
#define FLASH_PRIVBB2R4_PRIV27_Msk                  (0x1UL << FLASH_PRIVBB2R4_PRIV27_Pos)           /*!< 0x08000000 */
#define FLASH_PRIVBB2R4_PRIV27                      FLASH_PRIVBB2R4_PRIV27_Msk                      /*!< Page 123 in bank 2 block-based privilege */
#define FLASH_PRIVBB2R4_PRIV28_Pos                  (28UL)
#define FLASH_PRIVBB2R4_PRIV28_Msk                  (0x1UL << FLASH_PRIVBB2R4_PRIV28_Pos)           /*!< 0x10000000 */
#define FLASH_PRIVBB2R4_PRIV28                      FLASH_PRIVBB2R4_PRIV28_Msk                      /*!< Page 124 in bank 2 block-based privilege */
#define FLASH_PRIVBB2R4_PRIV29_Pos                  (29UL)
#define FLASH_PRIVBB2R4_PRIV29_Msk                  (0x1UL << FLASH_PRIVBB2R4_PRIV29_Pos)           /*!< 0x20000000 */
#define FLASH_PRIVBB2R4_PRIV29                      FLASH_PRIVBB2R4_PRIV29_Msk                      /*!< Page 125 in bank 2 block-based privilege */
#define FLASH_PRIVBB2R4_PRIV30_Pos                  (30UL)
#define FLASH_PRIVBB2R4_PRIV30_Msk                  (0x1UL << FLASH_PRIVBB2R4_PRIV30_Pos)           /*!< 0x40000000 */
#define FLASH_PRIVBB2R4_PRIV30                      FLASH_PRIVBB2R4_PRIV30_Msk                      /*!< Page 126 in bank 2 block-based privilege */
#define FLASH_PRIVBB2R4_PRIV31_Pos                  (31UL)
#define FLASH_PRIVBB2R4_PRIV31_Msk                  (0x1UL << FLASH_PRIVBB2R4_PRIV31_Pos)           /*!< 0x80000000 */
#define FLASH_PRIVBB2R4_PRIV31                      FLASH_PRIVBB2R4_PRIV31_Msk                      /*!< Page 127 in bank 2 block-based privilege */

/******************  Bits definition for FLASH_OEM1KEYR1 register  *****************/
#define FLASH_OEM1KEYR1_OEM1KEY_Pos         (0UL)
#define FLASH_OEM1KEYR1_OEM1KEY_Msk         (0xFFFFFFFFUL << FLASH_OEM1KEYR1_OEM1KEY_Pos) /*!< 0xFFFFFFFFF */
#define FLASH_OEM1KEYR1_OEM1KEY             FLASH_OEM1KEYR1_OEM1KEY_Msk                   /*!< OEM1 [31:0] bytes key */

/******************  Bits definition for FLASH_OEM1KEYR2 register  *****************/
#define FLASH_OEM1KEYR2_OEM1KEY_Pos         (0UL)
#define FLASH_OEM1KEYR2_OEM1KEY_Msk         (0xFFFFFFFFUL << FLASH_OEM1KEYR2_OEM1KEY_Pos) /*!< 0xFFFFFFFFF */
#define FLASH_OEM1KEYR2_OEM1KEY             FLASH_OEM1KEYR2_OEM1KEY_Msk                   /*!< OEM1 [63:32] bytes key */

/******************  Bits definition for FLASH_OEM1KEYR3 register  *****************/
#define FLASH_OEM1KEYR3_OEM1KEY_Pos         (0UL)
#define FLASH_OEM1KEYR3_OEM1KEY_Msk         (0xFFFFFFFFUL << FLASH_OEM1KEYR3_OEM1KEY_Pos) /*!< 0xFFFFFFFFF */
#define FLASH_OEM1KEYR3_OEM1KEY             FLASH_OEM1KEYR3_OEM1KEY_Msk                   /*!< OEM1 [95:64] bytes key */

/******************  Bits definition for FLASH_OEM1KEYR4 register  *****************/
#define FLASH_OEM1KEYR4_OEM1KEY_Pos         (0UL)
#define FLASH_OEM1KEYR4_OEM1KEY_Msk         (0xFFFFFFFFUL << FLASH_OEM1KEYR4_OEM1KEY_Pos) /*!< 0xFFFFFFFFF */
#define FLASH_OEM1KEYR4_OEM1KEY             FLASH_OEM1KEYR4_OEM1KEY_Msk                   /*!< OEM1 [127:96] bytes key */

/******************  Bits definition for FLASH_OEM2KEYR1 register  *****************/
#define FLASH_OEM2KEYR1_OEM2KEY_Pos         (0UL)
#define FLASH_OEM2KEYR1_OEM2KEY_Msk         (0xFFFFFFFFUL << FLASH_OEM2KEYR1_OEM2KEY_Pos) /*!< 0xFFFFFFFFF */
#define FLASH_OEM2KEYR1_OEM2KEY             FLASH_OEM2KEYR1_OEM2KEY_Msk                   /*!< OEM2 [31:0] bytes key */

/******************  Bits definition for FLASH_OEM2KEYR2 register  *****************/
#define FLASH_OEM2KEYR2_OEM2KEY_Pos         (0UL)
#define FLASH_OEM2KEYR2_OEM2KEY_Msk         (0xFFFFFFFFUL << FLASH_OEM2KEYR2_OEM2KEY_Pos) /*!< 0xFFFFFFFFF */
#define FLASH_OEM2KEYR2_OEM2KEY             FLASH_OEM2KEYR2_OEM2KEY_Msk                   /*!< OEM2 [63:32] bytes key */

/******************  Bits definition for FLASH_OEM2KEYR3 register  *****************/
#define FLASH_OEM2KEYR3_OEM2KEY_Pos         (0UL)
#define FLASH_OEM2KEYR3_OEM2KEY_Msk         (0xFFFFFFFFUL << FLASH_OEM2KEYR3_OEM2KEY_Pos) /*!< 0xFFFFFFFFF */
#define FLASH_OEM2KEYR3_OEM2KEY             FLASH_OEM2KEYR3_OEM2KEY_Msk                   /*!< OEM2 [95:64] bytes key */

/******************  Bits definition for FLASH_OEM2KEYR4 register  *****************/
#define FLASH_OEM2KEYR4_OEM2KEY_Pos         (0UL)
#define FLASH_OEM2KEYR4_OEM2KEY_Msk         (0xFFFFFFFFUL << FLASH_OEM2KEYR4_OEM2KEY_Pos) /*!< 0xFFFFFFFFF */
#define FLASH_OEM2KEYR4_OEM2KEY             FLASH_OEM2KEYR4_OEM2KEY_Msk                   /*!< OEM2 [127:96] bytes key */

/*******************  Bits definition for FLASH_OEMKEYSR register  *****************/
#define FLASH_OEMKEYSR_OEM1KEYCRC_Pos       (0UL)
#define FLASH_OEMKEYSR_OEM1KEYCRC_Msk       (0xFFUL << FLASH_OEMKEYSR_OEM1KEYCRC_Pos)  /*!< 0x000000FF */
#define FLASH_OEMKEYSR_OEM1KEYCRC           FLASH_OEMKEYSR_OEM1KEYCRC_Msk              /*!< 8-bits OEMKEY1 CRC */
#define FLASH_OEMKEYSR_OEM2KEYCRC_Pos       (16UL)
#define FLASH_OEMKEYSR_OEM2KEYCRC_Msk       (0xFFUL << FLASH_OEMKEYSR_OEM2KEYCRC_Pos)  /*!< 0x00FF0000 */
#define FLASH_OEMKEYSR_OEM2KEYCRC           FLASH_OEMKEYSR_OEM2KEYCRC_Msk              /*!< 8-bits OEMKEY2 CRC */

/******************************************************************************/
/*                                                                            */
/*                       General Purpose IOs (GPIO)                           */
/*                                                                            */
/******************************************************************************/
/******************  Bits definition for GPIO_MODER register  *****************/
#define GPIO_MODER_MODE0_Pos                (0UL)
#define GPIO_MODER_MODE0_Msk                (0x3UL << GPIO_MODER_MODE0_Pos)         /*!< 0x00000003 */
#define GPIO_MODER_MODE0                    GPIO_MODER_MODE0_Msk
#define GPIO_MODER_MODE0_0                  (0x1UL << GPIO_MODER_MODE0_Pos)         /*!< 0x00000001 */
#define GPIO_MODER_MODE0_1                  (0x2UL << GPIO_MODER_MODE0_Pos)         /*!< 0x00000002 */
#define GPIO_MODER_MODE1_Pos                (2UL)
#define GPIO_MODER_MODE1_Msk                (0x3UL << GPIO_MODER_MODE1_Pos)         /*!< 0x0000000C */
#define GPIO_MODER_MODE1                    GPIO_MODER_MODE1_Msk
#define GPIO_MODER_MODE1_0                  (0x1UL << GPIO_MODER_MODE1_Pos)         /*!< 0x00000004 */
#define GPIO_MODER_MODE1_1                  (0x2UL << GPIO_MODER_MODE1_Pos)         /*!< 0x00000008 */
#define GPIO_MODER_MODE2_Pos                (4UL)
#define GPIO_MODER_MODE2_Msk                (0x3UL << GPIO_MODER_MODE2_Pos)         /*!< 0x00000030 */
#define GPIO_MODER_MODE2                    GPIO_MODER_MODE2_Msk
#define GPIO_MODER_MODE2_0                  (0x1UL << GPIO_MODER_MODE2_Pos)         /*!< 0x00000010 */
#define GPIO_MODER_MODE2_1                  (0x2UL << GPIO_MODER_MODE2_Pos)         /*!< 0x00000020 */
#define GPIO_MODER_MODE3_Pos                (6UL)
#define GPIO_MODER_MODE3_Msk                (0x3UL << GPIO_MODER_MODE3_Pos)         /*!< 0x000000C0 */
#define GPIO_MODER_MODE3                    GPIO_MODER_MODE3_Msk
#define GPIO_MODER_MODE3_0                  (0x1UL << GPIO_MODER_MODE3_Pos)         /*!< 0x00000040 */
#define GPIO_MODER_MODE3_1                  (0x2UL << GPIO_MODER_MODE3_Pos)         /*!< 0x00000080 */
#define GPIO_MODER_MODE4_Pos                (8UL)
#define GPIO_MODER_MODE4_Msk                (0x3UL << GPIO_MODER_MODE4_Pos)         /*!< 0x00000300 */
#define GPIO_MODER_MODE4                    GPIO_MODER_MODE4_Msk
#define GPIO_MODER_MODE4_0                  (0x1UL << GPIO_MODER_MODE4_Pos)         /*!< 0x00000100 */
#define GPIO_MODER_MODE4_1                  (0x2UL << GPIO_MODER_MODE4_Pos)         /*!< 0x00000200 */
#define GPIO_MODER_MODE5_Pos                (10UL)
#define GPIO_MODER_MODE5_Msk                (0x3UL << GPIO_MODER_MODE5_Pos)         /*!< 0x00000C00 */
#define GPIO_MODER_MODE5                    GPIO_MODER_MODE5_Msk
#define GPIO_MODER_MODE5_0                  (0x1UL << GPIO_MODER_MODE5_Pos)         /*!< 0x00000400 */
#define GPIO_MODER_MODE5_1                  (0x2UL << GPIO_MODER_MODE5_Pos)         /*!< 0x00000800 */
#define GPIO_MODER_MODE6_Pos                (12UL)
#define GPIO_MODER_MODE6_Msk                (0x3UL << GPIO_MODER_MODE6_Pos)         /*!< 0x00003000 */
#define GPIO_MODER_MODE6                    GPIO_MODER_MODE6_Msk
#define GPIO_MODER_MODE6_0                  (0x1UL << GPIO_MODER_MODE6_Pos)         /*!< 0x00001000 */
#define GPIO_MODER_MODE6_1                  (0x2UL << GPIO_MODER_MODE6_Pos)         /*!< 0x00002000 */
#define GPIO_MODER_MODE7_Pos                (14UL)
#define GPIO_MODER_MODE7_Msk                (0x3UL << GPIO_MODER_MODE7_Pos)         /*!< 0x0000C000 */
#define GPIO_MODER_MODE7                    GPIO_MODER_MODE7_Msk
#define GPIO_MODER_MODE7_0                  (0x1UL << GPIO_MODER_MODE7_Pos)         /*!< 0x00004000 */
#define GPIO_MODER_MODE7_1                  (0x2UL << GPIO_MODER_MODE7_Pos)         /*!< 0x00008000 */
#define GPIO_MODER_MODE8_Pos                (16UL)
#define GPIO_MODER_MODE8_Msk                (0x3UL << GPIO_MODER_MODE8_Pos)         /*!< 0x00030000 */
#define GPIO_MODER_MODE8                    GPIO_MODER_MODE8_Msk
#define GPIO_MODER_MODE8_0                  (0x1UL << GPIO_MODER_MODE8_Pos)         /*!< 0x00010000 */
#define GPIO_MODER_MODE8_1                  (0x2UL << GPIO_MODER_MODE8_Pos)         /*!< 0x00020000 */
#define GPIO_MODER_MODE9_Pos                (18UL)
#define GPIO_MODER_MODE9_Msk                (0x3UL << GPIO_MODER_MODE9_Pos)         /*!< 0x000C0000 */
#define GPIO_MODER_MODE9                    GPIO_MODER_MODE9_Msk
#define GPIO_MODER_MODE9_0                  (0x1UL << GPIO_MODER_MODE9_Pos)         /*!< 0x00040000 */
#define GPIO_MODER_MODE9_1                  (0x2UL << GPIO_MODER_MODE9_Pos)         /*!< 0x00080000 */
#define GPIO_MODER_MODE10_Pos               (20UL)
#define GPIO_MODER_MODE10_Msk               (0x3UL << GPIO_MODER_MODE10_Pos)        /*!< 0x00300000 */
#define GPIO_MODER_MODE10                   GPIO_MODER_MODE10_Msk
#define GPIO_MODER_MODE10_0                 (0x1UL << GPIO_MODER_MODE10_Pos)        /*!< 0x00100000 */
#define GPIO_MODER_MODE10_1                 (0x2UL << GPIO_MODER_MODE10_Pos)        /*!< 0x00200000 */
#define GPIO_MODER_MODE11_Pos               (22UL)
#define GPIO_MODER_MODE11_Msk               (0x3UL << GPIO_MODER_MODE11_Pos)        /*!< 0x00C00000 */
#define GPIO_MODER_MODE11                   GPIO_MODER_MODE11_Msk
#define GPIO_MODER_MODE11_0                 (0x1UL << GPIO_MODER_MODE11_Pos)        /*!< 0x00400000 */
#define GPIO_MODER_MODE11_1                 (0x2UL << GPIO_MODER_MODE11_Pos)        /*!< 0x00800000 */
#define GPIO_MODER_MODE12_Pos               (24UL)
#define GPIO_MODER_MODE12_Msk               (0x3UL << GPIO_MODER_MODE12_Pos)        /*!< 0x03000000 */
#define GPIO_MODER_MODE12                   GPIO_MODER_MODE12_Msk
#define GPIO_MODER_MODE12_0                 (0x1UL << GPIO_MODER_MODE12_Pos)        /*!< 0x01000000 */
#define GPIO_MODER_MODE12_1                 (0x2UL << GPIO_MODER_MODE12_Pos)        /*!< 0x02000000 */
#define GPIO_MODER_MODE13_Pos               (26UL)
#define GPIO_MODER_MODE13_Msk               (0x3UL << GPIO_MODER_MODE13_Pos)        /*!< 0x0C000000 */
#define GPIO_MODER_MODE13                   GPIO_MODER_MODE13_Msk
#define GPIO_MODER_MODE13_0                 (0x1UL << GPIO_MODER_MODE13_Pos)        /*!< 0x04000000 */
#define GPIO_MODER_MODE13_1                 (0x2UL << GPIO_MODER_MODE13_Pos)        /*!< 0x08000000 */
#define GPIO_MODER_MODE14_Pos               (28UL)
#define GPIO_MODER_MODE14_Msk               (0x3UL << GPIO_MODER_MODE14_Pos)        /*!< 0x30000000 */
#define GPIO_MODER_MODE14                   GPIO_MODER_MODE14_Msk
#define GPIO_MODER_MODE14_0                 (0x1UL << GPIO_MODER_MODE14_Pos)        /*!< 0x10000000 */
#define GPIO_MODER_MODE14_1                 (0x2UL << GPIO_MODER_MODE14_Pos)        /*!< 0x20000000 */
#define GPIO_MODER_MODE15_Pos               (30UL)
#define GPIO_MODER_MODE15_Msk               (0x3UL << GPIO_MODER_MODE15_Pos)        /*!< 0xC0000000 */
#define GPIO_MODER_MODE15                   GPIO_MODER_MODE15_Msk
#define GPIO_MODER_MODE15_0                 (0x1UL << GPIO_MODER_MODE15_Pos)        /*!< 0x40000000 */
#define GPIO_MODER_MODE15_1                 (0x2UL << GPIO_MODER_MODE15_Pos)        /*!< 0x80000000 */

/******************  Bits definition for GPIO_OTYPER register  ****************/
#define GPIO_OTYPER_OT0_Pos                 (0UL)
#define GPIO_OTYPER_OT0_Msk                 (0x1UL << GPIO_OTYPER_OT0_Pos)          /*!< 0x00000001 */
#define GPIO_OTYPER_OT0                     GPIO_OTYPER_OT0_Msk
#define GPIO_OTYPER_OT1_Pos                 (1UL)
#define GPIO_OTYPER_OT1_Msk                 (0x1UL << GPIO_OTYPER_OT1_Pos)          /*!< 0x00000002 */
#define GPIO_OTYPER_OT1                     GPIO_OTYPER_OT1_Msk
#define GPIO_OTYPER_OT2_Pos                 (2UL)
#define GPIO_OTYPER_OT2_Msk                 (0x1UL << GPIO_OTYPER_OT2_Pos)          /*!< 0x00000004 */
#define GPIO_OTYPER_OT2                     GPIO_OTYPER_OT2_Msk
#define GPIO_OTYPER_OT3_Pos                 (3UL)
#define GPIO_OTYPER_OT3_Msk                 (0x1UL << GPIO_OTYPER_OT3_Pos)          /*!< 0x00000008 */
#define GPIO_OTYPER_OT3                     GPIO_OTYPER_OT3_Msk
#define GPIO_OTYPER_OT4_Pos                 (4UL)
#define GPIO_OTYPER_OT4_Msk                 (0x1UL << GPIO_OTYPER_OT4_Pos)          /*!< 0x00000010 */
#define GPIO_OTYPER_OT4                     GPIO_OTYPER_OT4_Msk
#define GPIO_OTYPER_OT5_Pos                 (5UL)
#define GPIO_OTYPER_OT5_Msk                 (0x1UL << GPIO_OTYPER_OT5_Pos)          /*!< 0x00000020 */
#define GPIO_OTYPER_OT5                     GPIO_OTYPER_OT5_Msk
#define GPIO_OTYPER_OT6_Pos                 (6UL)
#define GPIO_OTYPER_OT6_Msk                 (0x1UL << GPIO_OTYPER_OT6_Pos)          /*!< 0x00000040 */
#define GPIO_OTYPER_OT6                     GPIO_OTYPER_OT6_Msk
#define GPIO_OTYPER_OT7_Pos                 (7UL)
#define GPIO_OTYPER_OT7_Msk                 (0x1UL << GPIO_OTYPER_OT7_Pos)          /*!< 0x00000080 */
#define GPIO_OTYPER_OT7                     GPIO_OTYPER_OT7_Msk
#define GPIO_OTYPER_OT8_Pos                 (8UL)
#define GPIO_OTYPER_OT8_Msk                 (0x1UL << GPIO_OTYPER_OT8_Pos)          /*!< 0x00000100 */
#define GPIO_OTYPER_OT8                     GPIO_OTYPER_OT8_Msk
#define GPIO_OTYPER_OT9_Pos                 (9UL)
#define GPIO_OTYPER_OT9_Msk                 (0x1UL << GPIO_OTYPER_OT9_Pos)          /*!< 0x00000200 */
#define GPIO_OTYPER_OT9                     GPIO_OTYPER_OT9_Msk
#define GPIO_OTYPER_OT10_Pos                (10UL)
#define GPIO_OTYPER_OT10_Msk                (0x1UL << GPIO_OTYPER_OT10_Pos)         /*!< 0x00000400 */
#define GPIO_OTYPER_OT10                    GPIO_OTYPER_OT10_Msk
#define GPIO_OTYPER_OT11_Pos                (11UL)
#define GPIO_OTYPER_OT11_Msk                (0x1UL << GPIO_OTYPER_OT11_Pos)         /*!< 0x00000800 */
#define GPIO_OTYPER_OT11                    GPIO_OTYPER_OT11_Msk
#define GPIO_OTYPER_OT12_Pos                (12UL)
#define GPIO_OTYPER_OT12_Msk                (0x1UL << GPIO_OTYPER_OT12_Pos)         /*!< 0x00001000 */
#define GPIO_OTYPER_OT12                    GPIO_OTYPER_OT12_Msk
#define GPIO_OTYPER_OT13_Pos                (13UL)
#define GPIO_OTYPER_OT13_Msk                (0x1UL << GPIO_OTYPER_OT13_Pos)         /*!< 0x00002000 */
#define GPIO_OTYPER_OT13                    GPIO_OTYPER_OT13_Msk
#define GPIO_OTYPER_OT14_Pos                (14UL)
#define GPIO_OTYPER_OT14_Msk                (0x1UL << GPIO_OTYPER_OT14_Pos)         /*!< 0x00004000 */
#define GPIO_OTYPER_OT14                    GPIO_OTYPER_OT14_Msk
#define GPIO_OTYPER_OT15_Pos                (15UL)
#define GPIO_OTYPER_OT15_Msk                (0x1UL << GPIO_OTYPER_OT15_Pos)         /*!< 0x00008000 */
#define GPIO_OTYPER_OT15                    GPIO_OTYPER_OT15_Msk

/******************  Bits definition for GPIO_OSPEEDR register  ***************/
#define GPIO_OSPEEDR_OSPEED0_Pos            (0UL)
#define GPIO_OSPEEDR_OSPEED0_Msk            (0x3UL << GPIO_OSPEEDR_OSPEED0_Pos)     /*!< 0x00000003 */
#define GPIO_OSPEEDR_OSPEED0                GPIO_OSPEEDR_OSPEED0_Msk
#define GPIO_OSPEEDR_OSPEED0_0              (0x1UL << GPIO_OSPEEDR_OSPEED0_Pos)     /*!< 0x00000001 */
#define GPIO_OSPEEDR_OSPEED0_1              (0x2UL << GPIO_OSPEEDR_OSPEED0_Pos)     /*!< 0x00000002 */
#define GPIO_OSPEEDR_OSPEED1_Pos            (2UL)
#define GPIO_OSPEEDR_OSPEED1_Msk            (0x3UL << GPIO_OSPEEDR_OSPEED1_Pos)     /*!< 0x0000000C */
#define GPIO_OSPEEDR_OSPEED1                GPIO_OSPEEDR_OSPEED1_Msk
#define GPIO_OSPEEDR_OSPEED1_0              (0x1UL << GPIO_OSPEEDR_OSPEED1_Pos)     /*!< 0x00000004 */
#define GPIO_OSPEEDR_OSPEED1_1              (0x2UL << GPIO_OSPEEDR_OSPEED1_Pos)     /*!< 0x00000008 */
#define GPIO_OSPEEDR_OSPEED2_Pos            (4UL)
#define GPIO_OSPEEDR_OSPEED2_Msk            (0x3UL << GPIO_OSPEEDR_OSPEED2_Pos)     /*!< 0x00000030 */
#define GPIO_OSPEEDR_OSPEED2                GPIO_OSPEEDR_OSPEED2_Msk
#define GPIO_OSPEEDR_OSPEED2_0              (0x1UL << GPIO_OSPEEDR_OSPEED2_Pos)     /*!< 0x00000010 */
#define GPIO_OSPEEDR_OSPEED2_1              (0x2UL << GPIO_OSPEEDR_OSPEED2_Pos)     /*!< 0x00000020 */
#define GPIO_OSPEEDR_OSPEED3_Pos            (6UL)
#define GPIO_OSPEEDR_OSPEED3_Msk            (0x3UL << GPIO_OSPEEDR_OSPEED3_Pos)     /*!< 0x000000C0 */
#define GPIO_OSPEEDR_OSPEED3                GPIO_OSPEEDR_OSPEED3_Msk
#define GPIO_OSPEEDR_OSPEED3_0              (0x1UL << GPIO_OSPEEDR_OSPEED3_Pos)     /*!< 0x00000040 */
#define GPIO_OSPEEDR_OSPEED3_1              (0x2UL << GPIO_OSPEEDR_OSPEED3_Pos)     /*!< 0x00000080 */
#define GPIO_OSPEEDR_OSPEED4_Pos            (8UL)
#define GPIO_OSPEEDR_OSPEED4_Msk            (0x3UL << GPIO_OSPEEDR_OSPEED4_Pos)     /*!< 0x00000300 */
#define GPIO_OSPEEDR_OSPEED4                GPIO_OSPEEDR_OSPEED4_Msk
#define GPIO_OSPEEDR_OSPEED4_0              (0x1UL << GPIO_OSPEEDR_OSPEED4_Pos)     /*!< 0x00000100 */
#define GPIO_OSPEEDR_OSPEED4_1              (0x2UL << GPIO_OSPEEDR_OSPEED4_Pos)     /*!< 0x00000200 */
#define GPIO_OSPEEDR_OSPEED5_Pos            (10UL)
#define GPIO_OSPEEDR_OSPEED5_Msk            (0x3UL << GPIO_OSPEEDR_OSPEED5_Pos)     /*!< 0x00000C00 */
#define GPIO_OSPEEDR_OSPEED5                GPIO_OSPEEDR_OSPEED5_Msk
#define GPIO_OSPEEDR_OSPEED5_0              (0x1UL << GPIO_OSPEEDR_OSPEED5_Pos)     /*!< 0x00000400 */
#define GPIO_OSPEEDR_OSPEED5_1              (0x2UL << GPIO_OSPEEDR_OSPEED5_Pos)     /*!< 0x00000800 */
#define GPIO_OSPEEDR_OSPEED6_Pos            (12UL)
#define GPIO_OSPEEDR_OSPEED6_Msk            (0x3UL << GPIO_OSPEEDR_OSPEED6_Pos)     /*!< 0x00003000 */
#define GPIO_OSPEEDR_OSPEED6                GPIO_OSPEEDR_OSPEED6_Msk
#define GPIO_OSPEEDR_OSPEED6_0              (0x1UL << GPIO_OSPEEDR_OSPEED6_Pos)     /*!< 0x00001000 */
#define GPIO_OSPEEDR_OSPEED6_1              (0x2UL << GPIO_OSPEEDR_OSPEED6_Pos)     /*!< 0x00002000 */
#define GPIO_OSPEEDR_OSPEED7_Pos            (14UL)
#define GPIO_OSPEEDR_OSPEED7_Msk            (0x3UL << GPIO_OSPEEDR_OSPEED7_Pos)     /*!< 0x0000C000 */
#define GPIO_OSPEEDR_OSPEED7                GPIO_OSPEEDR_OSPEED7_Msk
#define GPIO_OSPEEDR_OSPEED7_0              (0x1UL << GPIO_OSPEEDR_OSPEED7_Pos)     /*!< 0x00004000 */
#define GPIO_OSPEEDR_OSPEED7_1              (0x2UL << GPIO_OSPEEDR_OSPEED7_Pos)     /*!< 0x00008000 */
#define GPIO_OSPEEDR_OSPEED8_Pos            (16UL)
#define GPIO_OSPEEDR_OSPEED8_Msk            (0x3UL << GPIO_OSPEEDR_OSPEED8_Pos)     /*!< 0x00030000 */
#define GPIO_OSPEEDR_OSPEED8                GPIO_OSPEEDR_OSPEED8_Msk
#define GPIO_OSPEEDR_OSPEED8_0              (0x1UL << GPIO_OSPEEDR_OSPEED8_Pos)     /*!< 0x00010000 */
#define GPIO_OSPEEDR_OSPEED8_1              (0x2UL << GPIO_OSPEEDR_OSPEED8_Pos)     /*!< 0x00020000 */
#define GPIO_OSPEEDR_OSPEED9_Pos            (18UL)
#define GPIO_OSPEEDR_OSPEED9_Msk            (0x3UL << GPIO_OSPEEDR_OSPEED9_Pos)     /*!< 0x000C0000 */
#define GPIO_OSPEEDR_OSPEED9                GPIO_OSPEEDR_OSPEED9_Msk
#define GPIO_OSPEEDR_OSPEED9_0              (0x1UL << GPIO_OSPEEDR_OSPEED9_Pos)     /*!< 0x00040000 */
#define GPIO_OSPEEDR_OSPEED9_1              (0x2UL << GPIO_OSPEEDR_OSPEED9_Pos)     /*!< 0x00080000 */
#define GPIO_OSPEEDR_OSPEED10_Pos           (20UL)
#define GPIO_OSPEEDR_OSPEED10_Msk           (0x3UL << GPIO_OSPEEDR_OSPEED10_Pos)    /*!< 0x00300000 */
#define GPIO_OSPEEDR_OSPEED10               GPIO_OSPEEDR_OSPEED10_Msk
#define GPIO_OSPEEDR_OSPEED10_0             (0x1UL << GPIO_OSPEEDR_OSPEED10_Pos)    /*!< 0x00100000 */
#define GPIO_OSPEEDR_OSPEED10_1             (0x2UL << GPIO_OSPEEDR_OSPEED10_Pos)    /*!< 0x00200000 */
#define GPIO_OSPEEDR_OSPEED11_Pos           (22UL)
#define GPIO_OSPEEDR_OSPEED11_Msk           (0x3UL << GPIO_OSPEEDR_OSPEED11_Pos)    /*!< 0x00C00000 */
#define GPIO_OSPEEDR_OSPEED11               GPIO_OSPEEDR_OSPEED11_Msk
#define GPIO_OSPEEDR_OSPEED11_0             (0x1UL << GPIO_OSPEEDR_OSPEED11_Pos)    /*!< 0x00400000 */
#define GPIO_OSPEEDR_OSPEED11_1             (0x2UL << GPIO_OSPEEDR_OSPEED11_Pos)    /*!< 0x00800000 */
#define GPIO_OSPEEDR_OSPEED12_Pos           (24UL)
#define GPIO_OSPEEDR_OSPEED12_Msk           (0x3UL << GPIO_OSPEEDR_OSPEED12_Pos)    /*!< 0x03000000 */
#define GPIO_OSPEEDR_OSPEED12               GPIO_OSPEEDR_OSPEED12_Msk
#define GPIO_OSPEEDR_OSPEED12_0             (0x1UL << GPIO_OSPEEDR_OSPEED12_Pos)    /*!< 0x01000000 */
#define GPIO_OSPEEDR_OSPEED12_1             (0x2UL << GPIO_OSPEEDR_OSPEED12_Pos)    /*!< 0x02000000 */
#define GPIO_OSPEEDR_OSPEED13_Pos           (26UL)
#define GPIO_OSPEEDR_OSPEED13_Msk           (0x3UL << GPIO_OSPEEDR_OSPEED13_Pos)    /*!< 0x0C000000 */
#define GPIO_OSPEEDR_OSPEED13               GPIO_OSPEEDR_OSPEED13_Msk
#define GPIO_OSPEEDR_OSPEED13_0             (0x1UL << GPIO_OSPEEDR_OSPEED13_Pos)    /*!< 0x04000000 */
#define GPIO_OSPEEDR_OSPEED13_1             (0x2UL << GPIO_OSPEEDR_OSPEED13_Pos)    /*!< 0x08000000 */
#define GPIO_OSPEEDR_OSPEED14_Pos           (28UL)
#define GPIO_OSPEEDR_OSPEED14_Msk           (0x3UL << GPIO_OSPEEDR_OSPEED14_Pos)    /*!< 0x30000000 */
#define GPIO_OSPEEDR_OSPEED14               GPIO_OSPEEDR_OSPEED14_Msk
#define GPIO_OSPEEDR_OSPEED14_0             (0x1UL << GPIO_OSPEEDR_OSPEED14_Pos)    /*!< 0x10000000 */
#define GPIO_OSPEEDR_OSPEED14_1             (0x2UL << GPIO_OSPEEDR_OSPEED14_Pos)    /*!< 0x20000000 */
#define GPIO_OSPEEDR_OSPEED15_Pos           (30UL)
#define GPIO_OSPEEDR_OSPEED15_Msk           (0x3UL << GPIO_OSPEEDR_OSPEED15_Pos)    /*!< 0xC0000000 */
#define GPIO_OSPEEDR_OSPEED15               GPIO_OSPEEDR_OSPEED15_Msk
#define GPIO_OSPEEDR_OSPEED15_0             (0x1UL << GPIO_OSPEEDR_OSPEED15_Pos)    /*!< 0x40000000 */
#define GPIO_OSPEEDR_OSPEED15_1             (0x2UL << GPIO_OSPEEDR_OSPEED15_Pos)    /*!< 0x80000000 */

/******************  Bits definition for GPIO_PUPDR register  *****************/
#define GPIO_PUPDR_PUPD0_Pos                (0UL)
#define GPIO_PUPDR_PUPD0_Msk                (0x3UL << GPIO_PUPDR_PUPD0_Pos)         /*!< 0x00000003 */
#define GPIO_PUPDR_PUPD0                    GPIO_PUPDR_PUPD0_Msk
#define GPIO_PUPDR_PUPD0_0                  (0x1UL << GPIO_PUPDR_PUPD0_Pos)         /*!< 0x00000001 */
#define GPIO_PUPDR_PUPD0_1                  (0x2UL << GPIO_PUPDR_PUPD0_Pos)         /*!< 0x00000002 */
#define GPIO_PUPDR_PUPD1_Pos                (2UL)
#define GPIO_PUPDR_PUPD1_Msk                (0x3UL << GPIO_PUPDR_PUPD1_Pos)         /*!< 0x0000000C */
#define GPIO_PUPDR_PUPD1                    GPIO_PUPDR_PUPD1_Msk
#define GPIO_PUPDR_PUPD1_0                  (0x1UL << GPIO_PUPDR_PUPD1_Pos)         /*!< 0x00000004 */
#define GPIO_PUPDR_PUPD1_1                  (0x2UL << GPIO_PUPDR_PUPD1_Pos)         /*!< 0x00000008 */
#define GPIO_PUPDR_PUPD2_Pos                (4UL)
#define GPIO_PUPDR_PUPD2_Msk                (0x3UL << GPIO_PUPDR_PUPD2_Pos)         /*!< 0x00000030 */
#define GPIO_PUPDR_PUPD2                    GPIO_PUPDR_PUPD2_Msk
#define GPIO_PUPDR_PUPD2_0                  (0x1UL << GPIO_PUPDR_PUPD2_Pos)         /*!< 0x00000010 */
#define GPIO_PUPDR_PUPD2_1                  (0x2UL << GPIO_PUPDR_PUPD2_Pos)         /*!< 0x00000020 */
#define GPIO_PUPDR_PUPD3_Pos                (6UL)
#define GPIO_PUPDR_PUPD3_Msk                (0x3UL << GPIO_PUPDR_PUPD3_Pos)         /*!< 0x000000C0 */
#define GPIO_PUPDR_PUPD3                    GPIO_PUPDR_PUPD3_Msk
#define GPIO_PUPDR_PUPD3_0                  (0x1UL << GPIO_PUPDR_PUPD3_Pos)         /*!< 0x00000040 */
#define GPIO_PUPDR_PUPD3_1                  (0x2UL << GPIO_PUPDR_PUPD3_Pos)         /*!< 0x00000080 */
#define GPIO_PUPDR_PUPD4_Pos                (8UL)
#define GPIO_PUPDR_PUPD4_Msk                (0x3UL << GPIO_PUPDR_PUPD4_Pos)         /*!< 0x00000300 */
#define GPIO_PUPDR_PUPD4                    GPIO_PUPDR_PUPD4_Msk
#define GPIO_PUPDR_PUPD4_0                  (0x1UL << GPIO_PUPDR_PUPD4_Pos)         /*!< 0x00000100 */
#define GPIO_PUPDR_PUPD4_1                  (0x2UL << GPIO_PUPDR_PUPD4_Pos)         /*!< 0x00000200 */
#define GPIO_PUPDR_PUPD5_Pos                (10UL)
#define GPIO_PUPDR_PUPD5_Msk                (0x3UL << GPIO_PUPDR_PUPD5_Pos)         /*!< 0x00000C00 */
#define GPIO_PUPDR_PUPD5                    GPIO_PUPDR_PUPD5_Msk
#define GPIO_PUPDR_PUPD5_0                  (0x1UL << GPIO_PUPDR_PUPD5_Pos)         /*!< 0x00000400 */
#define GPIO_PUPDR_PUPD5_1                  (0x2UL << GPIO_PUPDR_PUPD5_Pos)         /*!< 0x00000800 */
#define GPIO_PUPDR_PUPD6_Pos                (12UL)
#define GPIO_PUPDR_PUPD6_Msk                (0x3UL << GPIO_PUPDR_PUPD6_Pos)         /*!< 0x00003000 */
#define GPIO_PUPDR_PUPD6                    GPIO_PUPDR_PUPD6_Msk
#define GPIO_PUPDR_PUPD6_0                  (0x1UL << GPIO_PUPDR_PUPD6_Pos)         /*!< 0x00001000 */
#define GPIO_PUPDR_PUPD6_1                  (0x2UL << GPIO_PUPDR_PUPD6_Pos)         /*!< 0x00002000 */
#define GPIO_PUPDR_PUPD7_Pos                (14UL)
#define GPIO_PUPDR_PUPD7_Msk                (0x3UL << GPIO_PUPDR_PUPD7_Pos)         /*!< 0x0000C000 */
#define GPIO_PUPDR_PUPD7                    GPIO_PUPDR_PUPD7_Msk
#define GPIO_PUPDR_PUPD7_0                  (0x1UL << GPIO_PUPDR_PUPD7_Pos)         /*!< 0x00004000 */
#define GPIO_PUPDR_PUPD7_1                  (0x2UL << GPIO_PUPDR_PUPD7_Pos)         /*!< 0x00008000 */
#define GPIO_PUPDR_PUPD8_Pos                (16UL)
#define GPIO_PUPDR_PUPD8_Msk                (0x3UL << GPIO_PUPDR_PUPD8_Pos)         /*!< 0x00030000 */
#define GPIO_PUPDR_PUPD8                    GPIO_PUPDR_PUPD8_Msk
#define GPIO_PUPDR_PUPD8_0                  (0x1UL << GPIO_PUPDR_PUPD8_Pos)         /*!< 0x00010000 */
#define GPIO_PUPDR_PUPD8_1                  (0x2UL << GPIO_PUPDR_PUPD8_Pos)         /*!< 0x00020000 */
#define GPIO_PUPDR_PUPD9_Pos                (18UL)
#define GPIO_PUPDR_PUPD9_Msk                (0x3UL << GPIO_PUPDR_PUPD9_Pos)         /*!< 0x000C0000 */
#define GPIO_PUPDR_PUPD9                    GPIO_PUPDR_PUPD9_Msk
#define GPIO_PUPDR_PUPD9_0                  (0x1UL << GPIO_PUPDR_PUPD9_Pos)         /*!< 0x00040000 */
#define GPIO_PUPDR_PUPD9_1                  (0x2UL << GPIO_PUPDR_PUPD9_Pos)         /*!< 0x00080000 */
#define GPIO_PUPDR_PUPD10_Pos               (20UL)
#define GPIO_PUPDR_PUPD10_Msk               (0x3UL << GPIO_PUPDR_PUPD10_Pos)        /*!< 0x00300000 */
#define GPIO_PUPDR_PUPD10                   GPIO_PUPDR_PUPD10_Msk
#define GPIO_PUPDR_PUPD10_0                 (0x1UL << GPIO_PUPDR_PUPD10_Pos)        /*!< 0x00100000 */
#define GPIO_PUPDR_PUPD10_1                 (0x2UL << GPIO_PUPDR_PUPD10_Pos)        /*!< 0x00200000 */
#define GPIO_PUPDR_PUPD11_Pos               (22UL)
#define GPIO_PUPDR_PUPD11_Msk               (0x3UL << GPIO_PUPDR_PUPD11_Pos)        /*!< 0x00C00000 */
#define GPIO_PUPDR_PUPD11                   GPIO_PUPDR_PUPD11_Msk
#define GPIO_PUPDR_PUPD11_0                 (0x1UL << GPIO_PUPDR_PUPD11_Pos)        /*!< 0x00400000 */
#define GPIO_PUPDR_PUPD11_1                 (0x2UL << GPIO_PUPDR_PUPD11_Pos)        /*!< 0x00800000 */
#define GPIO_PUPDR_PUPD12_Pos               (24UL)
#define GPIO_PUPDR_PUPD12_Msk               (0x3UL << GPIO_PUPDR_PUPD12_Pos)        /*!< 0x03000000 */
#define GPIO_PUPDR_PUPD12                   GPIO_PUPDR_PUPD12_Msk
#define GPIO_PUPDR_PUPD12_0                 (0x1UL << GPIO_PUPDR_PUPD12_Pos)        /*!< 0x01000000 */
#define GPIO_PUPDR_PUPD12_1                 (0x2UL << GPIO_PUPDR_PUPD12_Pos)        /*!< 0x02000000 */
#define GPIO_PUPDR_PUPD13_Pos               (26UL)
#define GPIO_PUPDR_PUPD13_Msk               (0x3UL << GPIO_PUPDR_PUPD13_Pos)        /*!< 0x0C000000 */
#define GPIO_PUPDR_PUPD13                   GPIO_PUPDR_PUPD13_Msk
#define GPIO_PUPDR_PUPD13_0                 (0x1UL << GPIO_PUPDR_PUPD13_Pos)        /*!< 0x04000000 */
#define GPIO_PUPDR_PUPD13_1                 (0x2UL << GPIO_PUPDR_PUPD13_Pos)        /*!< 0x08000000 */
#define GPIO_PUPDR_PUPD14_Pos               (28UL)
#define GPIO_PUPDR_PUPD14_Msk               (0x3UL << GPIO_PUPDR_PUPD14_Pos)        /*!< 0x30000000 */
#define GPIO_PUPDR_PUPD14                   GPIO_PUPDR_PUPD14_Msk
#define GPIO_PUPDR_PUPD14_0                 (0x1UL << GPIO_PUPDR_PUPD14_Pos)        /*!< 0x10000000 */
#define GPIO_PUPDR_PUPD14_1                 (0x2UL << GPIO_PUPDR_PUPD14_Pos)        /*!< 0x20000000 */
#define GPIO_PUPDR_PUPD15_Pos               (30UL)
#define GPIO_PUPDR_PUPD15_Msk               (0x3UL << GPIO_PUPDR_PUPD15_Pos)        /*!< 0xC0000000 */
#define GPIO_PUPDR_PUPD15                   GPIO_PUPDR_PUPD15_Msk
#define GPIO_PUPDR_PUPD15_0                 (0x1UL << GPIO_PUPDR_PUPD15_Pos)        /*!< 0x40000000 */
#define GPIO_PUPDR_PUPD15_1                 (0x2UL << GPIO_PUPDR_PUPD15_Pos)        /*!< 0x80000000 */

/******************  Bits definition for GPIO_IDR register  *******************/
#define GPIO_IDR_ID0_Pos                    (0UL)
#define GPIO_IDR_ID0_Msk                    (0x1UL << GPIO_IDR_ID0_Pos)             /*!< 0x00000001 */
#define GPIO_IDR_ID0                        GPIO_IDR_ID0_Msk
#define GPIO_IDR_ID1_Pos                    (1UL)
#define GPIO_IDR_ID1_Msk                    (0x1UL << GPIO_IDR_ID1_Pos)             /*!< 0x00000002 */
#define GPIO_IDR_ID1                        GPIO_IDR_ID1_Msk
#define GPIO_IDR_ID2_Pos                    (2UL)
#define GPIO_IDR_ID2_Msk                    (0x1UL << GPIO_IDR_ID2_Pos)             /*!< 0x00000004 */
#define GPIO_IDR_ID2                        GPIO_IDR_ID2_Msk
#define GPIO_IDR_ID3_Pos                    (3UL)
#define GPIO_IDR_ID3_Msk                    (0x1UL << GPIO_IDR_ID3_Pos)             /*!< 0x00000008 */
#define GPIO_IDR_ID3                        GPIO_IDR_ID3_Msk
#define GPIO_IDR_ID4_Pos                    (4UL)
#define GPIO_IDR_ID4_Msk                    (0x1UL << GPIO_IDR_ID4_Pos)             /*!< 0x00000010 */
#define GPIO_IDR_ID4                        GPIO_IDR_ID4_Msk
#define GPIO_IDR_ID5_Pos                    (5UL)
#define GPIO_IDR_ID5_Msk                    (0x1UL << GPIO_IDR_ID5_Pos)             /*!< 0x00000020 */
#define GPIO_IDR_ID5                        GPIO_IDR_ID5_Msk
#define GPIO_IDR_ID6_Pos                    (6UL)
#define GPIO_IDR_ID6_Msk                    (0x1UL << GPIO_IDR_ID6_Pos)             /*!< 0x00000040 */
#define GPIO_IDR_ID6                        GPIO_IDR_ID6_Msk
#define GPIO_IDR_ID7_Pos                    (7UL)
#define GPIO_IDR_ID7_Msk                    (0x1UL << GPIO_IDR_ID7_Pos)             /*!< 0x00000080 */
#define GPIO_IDR_ID7                        GPIO_IDR_ID7_Msk
#define GPIO_IDR_ID8_Pos                    (8UL)
#define GPIO_IDR_ID8_Msk                    (0x1UL << GPIO_IDR_ID8_Pos)             /*!< 0x00000100 */
#define GPIO_IDR_ID8                        GPIO_IDR_ID8_Msk
#define GPIO_IDR_ID9_Pos                    (9UL)
#define GPIO_IDR_ID9_Msk                    (0x1UL << GPIO_IDR_ID9_Pos)             /*!< 0x00000200 */
#define GPIO_IDR_ID9                        GPIO_IDR_ID9_Msk
#define GPIO_IDR_ID10_Pos                   (10UL)
#define GPIO_IDR_ID10_Msk                   (0x1UL << GPIO_IDR_ID10_Pos)            /*!< 0x00000400 */
#define GPIO_IDR_ID10                       GPIO_IDR_ID10_Msk
#define GPIO_IDR_ID11_Pos                   (11UL)
#define GPIO_IDR_ID11_Msk                   (0x1UL << GPIO_IDR_ID11_Pos)            /*!< 0x00000800 */
#define GPIO_IDR_ID11                       GPIO_IDR_ID11_Msk
#define GPIO_IDR_ID12_Pos                   (12UL)
#define GPIO_IDR_ID12_Msk                   (0x1UL << GPIO_IDR_ID12_Pos)            /*!< 0x00001000 */
#define GPIO_IDR_ID12                       GPIO_IDR_ID12_Msk
#define GPIO_IDR_ID13_Pos                   (13UL)
#define GPIO_IDR_ID13_Msk                   (0x1UL << GPIO_IDR_ID13_Pos)            /*!< 0x00002000 */
#define GPIO_IDR_ID13                       GPIO_IDR_ID13_Msk
#define GPIO_IDR_ID14_Pos                   (14UL)
#define GPIO_IDR_ID14_Msk                   (0x1UL << GPIO_IDR_ID14_Pos)            /*!< 0x00004000 */
#define GPIO_IDR_ID14                       GPIO_IDR_ID14_Msk
#define GPIO_IDR_ID15_Pos                   (15UL)
#define GPIO_IDR_ID15_Msk                   (0x1UL << GPIO_IDR_ID15_Pos)            /*!< 0x00008000 */
#define GPIO_IDR_ID15                       GPIO_IDR_ID15_Msk

/******************  Bits definition for GPIO_ODR register  *******************/
#define GPIO_ODR_OD0_Pos                    (0UL)
#define GPIO_ODR_OD0_Msk                    (0x1UL << GPIO_ODR_OD0_Pos)             /*!< 0x00000001 */
#define GPIO_ODR_OD0                        GPIO_ODR_OD0_Msk
#define GPIO_ODR_OD1_Pos                    (1UL)
#define GPIO_ODR_OD1_Msk                    (0x1UL << GPIO_ODR_OD1_Pos)             /*!< 0x00000002 */
#define GPIO_ODR_OD1                        GPIO_ODR_OD1_Msk
#define GPIO_ODR_OD2_Pos                    (2UL)
#define GPIO_ODR_OD2_Msk                    (0x1UL << GPIO_ODR_OD2_Pos)             /*!< 0x00000004 */
#define GPIO_ODR_OD2                        GPIO_ODR_OD2_Msk
#define GPIO_ODR_OD3_Pos                    (3UL)
#define GPIO_ODR_OD3_Msk                    (0x1UL << GPIO_ODR_OD3_Pos)             /*!< 0x00000008 */
#define GPIO_ODR_OD3                        GPIO_ODR_OD3_Msk
#define GPIO_ODR_OD4_Pos                    (4UL)
#define GPIO_ODR_OD4_Msk                    (0x1UL << GPIO_ODR_OD4_Pos)             /*!< 0x00000010 */
#define GPIO_ODR_OD4                        GPIO_ODR_OD4_Msk
#define GPIO_ODR_OD5_Pos                    (5UL)
#define GPIO_ODR_OD5_Msk                    (0x1UL << GPIO_ODR_OD5_Pos)             /*!< 0x00000020 */
#define GPIO_ODR_OD5                        GPIO_ODR_OD5_Msk
#define GPIO_ODR_OD6_Pos                    (6UL)
#define GPIO_ODR_OD6_Msk                    (0x1UL << GPIO_ODR_OD6_Pos)             /*!< 0x00000040 */
#define GPIO_ODR_OD6                        GPIO_ODR_OD6_Msk
#define GPIO_ODR_OD7_Pos                    (7UL)
#define GPIO_ODR_OD7_Msk                    (0x1UL << GPIO_ODR_OD7_Pos)             /*!< 0x00000080 */
#define GPIO_ODR_OD7                        GPIO_ODR_OD7_Msk
#define GPIO_ODR_OD8_Pos                    (8UL)
#define GPIO_ODR_OD8_Msk                    (0x1UL << GPIO_ODR_OD8_Pos)             /*!< 0x00000100 */
#define GPIO_ODR_OD8                        GPIO_ODR_OD8_Msk
#define GPIO_ODR_OD9_Pos                    (9UL)
#define GPIO_ODR_OD9_Msk                    (0x1UL << GPIO_ODR_OD9_Pos)             /*!< 0x00000200 */
#define GPIO_ODR_OD9                        GPIO_ODR_OD9_Msk
#define GPIO_ODR_OD10_Pos                   (10UL)
#define GPIO_ODR_OD10_Msk                   (0x1UL << GPIO_ODR_OD10_Pos)            /*!< 0x00000400 */
#define GPIO_ODR_OD10                       GPIO_ODR_OD10_Msk
#define GPIO_ODR_OD11_Pos                   (11UL)
#define GPIO_ODR_OD11_Msk                   (0x1UL << GPIO_ODR_OD11_Pos)            /*!< 0x00000800 */
#define GPIO_ODR_OD11                       GPIO_ODR_OD11_Msk
#define GPIO_ODR_OD12_Pos                   (12UL)
#define GPIO_ODR_OD12_Msk                   (0x1UL << GPIO_ODR_OD12_Pos)            /*!< 0x00001000 */
#define GPIO_ODR_OD12                       GPIO_ODR_OD12_Msk
#define GPIO_ODR_OD13_Pos                   (13UL)
#define GPIO_ODR_OD13_Msk                   (0x1UL << GPIO_ODR_OD13_Pos)            /*!< 0x00002000 */
#define GPIO_ODR_OD13                       GPIO_ODR_OD13_Msk
#define GPIO_ODR_OD14_Pos                   (14UL)
#define GPIO_ODR_OD14_Msk                   (0x1UL << GPIO_ODR_OD14_Pos)            /*!< 0x00004000 */
#define GPIO_ODR_OD14                       GPIO_ODR_OD14_Msk
#define GPIO_ODR_OD15_Pos                   (15UL)
#define GPIO_ODR_OD15_Msk                   (0x1UL << GPIO_ODR_OD15_Pos)            /*!< 0x00008000 */
#define GPIO_ODR_OD15                       GPIO_ODR_OD15_Msk

/******************  Bits definition for GPIO_BSRR register  ******************/
#define GPIO_BSRR_BS0_Pos                   (0UL)
#define GPIO_BSRR_BS0_Msk                   (0x1UL << GPIO_BSRR_BS0_Pos)            /*!< 0x00000001 */
#define GPIO_BSRR_BS0                       GPIO_BSRR_BS0_Msk
#define GPIO_BSRR_BS1_Pos                   (1UL)
#define GPIO_BSRR_BS1_Msk                   (0x1UL << GPIO_BSRR_BS1_Pos)            /*!< 0x00000002 */
#define GPIO_BSRR_BS1                       GPIO_BSRR_BS1_Msk
#define GPIO_BSRR_BS2_Pos                   (2UL)
#define GPIO_BSRR_BS2_Msk                   (0x1UL << GPIO_BSRR_BS2_Pos)            /*!< 0x00000004 */
#define GPIO_BSRR_BS2                       GPIO_BSRR_BS2_Msk
#define GPIO_BSRR_BS3_Pos                   (3UL)
#define GPIO_BSRR_BS3_Msk                   (0x1UL << GPIO_BSRR_BS3_Pos)            /*!< 0x00000008 */
#define GPIO_BSRR_BS3                       GPIO_BSRR_BS3_Msk
#define GPIO_BSRR_BS4_Pos                   (4UL)
#define GPIO_BSRR_BS4_Msk                   (0x1UL << GPIO_BSRR_BS4_Pos)            /*!< 0x00000010 */
#define GPIO_BSRR_BS4                       GPIO_BSRR_BS4_Msk
#define GPIO_BSRR_BS5_Pos                   (5UL)
#define GPIO_BSRR_BS5_Msk                   (0x1UL << GPIO_BSRR_BS5_Pos)            /*!< 0x00000020 */
#define GPIO_BSRR_BS5                       GPIO_BSRR_BS5_Msk
#define GPIO_BSRR_BS6_Pos                   (6UL)
#define GPIO_BSRR_BS6_Msk                   (0x1UL << GPIO_BSRR_BS6_Pos)            /*!< 0x00000040 */
#define GPIO_BSRR_BS6                       GPIO_BSRR_BS6_Msk
#define GPIO_BSRR_BS7_Pos                   (7UL)
#define GPIO_BSRR_BS7_Msk                   (0x1UL << GPIO_BSRR_BS7_Pos)            /*!< 0x00000080 */
#define GPIO_BSRR_BS7                       GPIO_BSRR_BS7_Msk
#define GPIO_BSRR_BS8_Pos                   (8UL)
#define GPIO_BSRR_BS8_Msk                   (0x1UL << GPIO_BSRR_BS8_Pos)            /*!< 0x00000100 */
#define GPIO_BSRR_BS8                       GPIO_BSRR_BS8_Msk
#define GPIO_BSRR_BS9_Pos                   (9UL)
#define GPIO_BSRR_BS9_Msk                   (0x1UL << GPIO_BSRR_BS9_Pos)            /*!< 0x00000200 */
#define GPIO_BSRR_BS9                       GPIO_BSRR_BS9_Msk
#define GPIO_BSRR_BS10_Pos                  (10UL)
#define GPIO_BSRR_BS10_Msk                  (0x1UL << GPIO_BSRR_BS10_Pos)           /*!< 0x00000400 */
#define GPIO_BSRR_BS10                      GPIO_BSRR_BS10_Msk
#define GPIO_BSRR_BS11_Pos                  (11UL)
#define GPIO_BSRR_BS11_Msk                  (0x1UL << GPIO_BSRR_BS11_Pos)           /*!< 0x00000800 */
#define GPIO_BSRR_BS11                      GPIO_BSRR_BS11_Msk
#define GPIO_BSRR_BS12_Pos                  (12UL)
#define GPIO_BSRR_BS12_Msk                  (0x1UL << GPIO_BSRR_BS12_Pos)           /*!< 0x00001000 */
#define GPIO_BSRR_BS12                      GPIO_BSRR_BS12_Msk
#define GPIO_BSRR_BS13_Pos                  (13UL)
#define GPIO_BSRR_BS13_Msk                  (0x1UL << GPIO_BSRR_BS13_Pos)           /*!< 0x00002000 */
#define GPIO_BSRR_BS13                      GPIO_BSRR_BS13_Msk
#define GPIO_BSRR_BS14_Pos                  (14UL)
#define GPIO_BSRR_BS14_Msk                  (0x1UL << GPIO_BSRR_BS14_Pos)           /*!< 0x00004000 */
#define GPIO_BSRR_BS14                      GPIO_BSRR_BS14_Msk
#define GPIO_BSRR_BS15_Pos                  (15UL)
#define GPIO_BSRR_BS15_Msk                  (0x1UL << GPIO_BSRR_BS15_Pos)           /*!< 0x00008000 */
#define GPIO_BSRR_BS15                      GPIO_BSRR_BS15_Msk
#define GPIO_BSRR_BR0_Pos                   (16UL)
#define GPIO_BSRR_BR0_Msk                   (0x1UL << GPIO_BSRR_BR0_Pos)            /*!< 0x00010000 */
#define GPIO_BSRR_BR0                       GPIO_BSRR_BR0_Msk
#define GPIO_BSRR_BR1_Pos                   (17UL)
#define GPIO_BSRR_BR1_Msk                   (0x1UL << GPIO_BSRR_BR1_Pos)            /*!< 0x00020000 */
#define GPIO_BSRR_BR1                       GPIO_BSRR_BR1_Msk
#define GPIO_BSRR_BR2_Pos                   (18UL)
#define GPIO_BSRR_BR2_Msk                   (0x1UL << GPIO_BSRR_BR2_Pos)            /*!< 0x00040000 */
#define GPIO_BSRR_BR2                       GPIO_BSRR_BR2_Msk
#define GPIO_BSRR_BR3_Pos                   (19UL)
#define GPIO_BSRR_BR3_Msk                   (0x1UL << GPIO_BSRR_BR3_Pos)            /*!< 0x00080000 */
#define GPIO_BSRR_BR3                       GPIO_BSRR_BR3_Msk
#define GPIO_BSRR_BR4_Pos                   (20UL)
#define GPIO_BSRR_BR4_Msk                   (0x1UL << GPIO_BSRR_BR4_Pos)            /*!< 0x00100000 */
#define GPIO_BSRR_BR4                       GPIO_BSRR_BR4_Msk
#define GPIO_BSRR_BR5_Pos                   (21UL)
#define GPIO_BSRR_BR5_Msk                   (0x1UL << GPIO_BSRR_BR5_Pos)            /*!< 0x00200000 */
#define GPIO_BSRR_BR5                       GPIO_BSRR_BR5_Msk
#define GPIO_BSRR_BR6_Pos                   (22UL)
#define GPIO_BSRR_BR6_Msk                   (0x1UL << GPIO_BSRR_BR6_Pos)            /*!< 0x00400000 */
#define GPIO_BSRR_BR6                       GPIO_BSRR_BR6_Msk
#define GPIO_BSRR_BR7_Pos                   (23UL)
#define GPIO_BSRR_BR7_Msk                   (0x1UL << GPIO_BSRR_BR7_Pos)            /*!< 0x00800000 */
#define GPIO_BSRR_BR7                       GPIO_BSRR_BR7_Msk
#define GPIO_BSRR_BR8_Pos                   (24UL)
#define GPIO_BSRR_BR8_Msk                   (0x1UL << GPIO_BSRR_BR8_Pos)            /*!< 0x01000000 */
#define GPIO_BSRR_BR8                       GPIO_BSRR_BR8_Msk
#define GPIO_BSRR_BR9_Pos                   (25UL)
#define GPIO_BSRR_BR9_Msk                   (0x1UL << GPIO_BSRR_BR9_Pos)            /*!< 0x02000000 */
#define GPIO_BSRR_BR9                       GPIO_BSRR_BR9_Msk
#define GPIO_BSRR_BR10_Pos                  (26UL)
#define GPIO_BSRR_BR10_Msk                  (0x1UL << GPIO_BSRR_BR10_Pos)           /*!< 0x04000000 */
#define GPIO_BSRR_BR10                      GPIO_BSRR_BR10_Msk
#define GPIO_BSRR_BR11_Pos                  (27UL)
#define GPIO_BSRR_BR11_Msk                  (0x1UL << GPIO_BSRR_BR11_Pos)           /*!< 0x08000000 */
#define GPIO_BSRR_BR11                      GPIO_BSRR_BR11_Msk
#define GPIO_BSRR_BR12_Pos                  (28UL)
#define GPIO_BSRR_BR12_Msk                  (0x1UL << GPIO_BSRR_BR12_Pos)           /*!< 0x10000000 */
#define GPIO_BSRR_BR12                      GPIO_BSRR_BR12_Msk
#define GPIO_BSRR_BR13_Pos                  (29UL)
#define GPIO_BSRR_BR13_Msk                  (0x1UL << GPIO_BSRR_BR13_Pos)           /*!< 0x20000000 */
#define GPIO_BSRR_BR13                      GPIO_BSRR_BR13_Msk
#define GPIO_BSRR_BR14_Pos                  (30UL)
#define GPIO_BSRR_BR14_Msk                  (0x1UL << GPIO_BSRR_BR14_Pos)           /*!< 0x40000000 */
#define GPIO_BSRR_BR14                      GPIO_BSRR_BR14_Msk
#define GPIO_BSRR_BR15_Pos                  (31UL)
#define GPIO_BSRR_BR15_Msk                  (0x1UL << GPIO_BSRR_BR15_Pos)           /*!< 0x80000000 */
#define GPIO_BSRR_BR15                      GPIO_BSRR_BR15_Msk

/****************** Bit definition for GPIO_LCKR register *********************/
#define GPIO_LCKR_LCK0_Pos                  (0UL)
#define GPIO_LCKR_LCK0_Msk                  (0x1UL << GPIO_LCKR_LCK0_Pos)           /*!< 0x00000001 */
#define GPIO_LCKR_LCK0                      GPIO_LCKR_LCK0_Msk
#define GPIO_LCKR_LCK1_Pos                  (1UL)
#define GPIO_LCKR_LCK1_Msk                  (0x1UL << GPIO_LCKR_LCK1_Pos)           /*!< 0x00000002 */
#define GPIO_LCKR_LCK1                      GPIO_LCKR_LCK1_Msk
#define GPIO_LCKR_LCK2_Pos                  (2UL)
#define GPIO_LCKR_LCK2_Msk                  (0x1UL << GPIO_LCKR_LCK2_Pos)           /*!< 0x00000004 */
#define GPIO_LCKR_LCK2                      GPIO_LCKR_LCK2_Msk
#define GPIO_LCKR_LCK3_Pos                  (3UL)
#define GPIO_LCKR_LCK3_Msk                  (0x1UL << GPIO_LCKR_LCK3_Pos)           /*!< 0x00000008 */
#define GPIO_LCKR_LCK3                      GPIO_LCKR_LCK3_Msk
#define GPIO_LCKR_LCK4_Pos                  (4UL)
#define GPIO_LCKR_LCK4_Msk                  (0x1UL << GPIO_LCKR_LCK4_Pos)           /*!< 0x00000010 */
#define GPIO_LCKR_LCK4                      GPIO_LCKR_LCK4_Msk
#define GPIO_LCKR_LCK5_Pos                  (5UL)
#define GPIO_LCKR_LCK5_Msk                  (0x1UL << GPIO_LCKR_LCK5_Pos)           /*!< 0x00000020 */
#define GPIO_LCKR_LCK5                      GPIO_LCKR_LCK5_Msk
#define GPIO_LCKR_LCK6_Pos                  (6UL)
#define GPIO_LCKR_LCK6_Msk                  (0x1UL << GPIO_LCKR_LCK6_Pos)           /*!< 0x00000040 */
#define GPIO_LCKR_LCK6                      GPIO_LCKR_LCK6_Msk
#define GPIO_LCKR_LCK7_Pos                  (7UL)
#define GPIO_LCKR_LCK7_Msk                  (0x1UL << GPIO_LCKR_LCK7_Pos)           /*!< 0x00000080 */
#define GPIO_LCKR_LCK7                      GPIO_LCKR_LCK7_Msk
#define GPIO_LCKR_LCK8_Pos                  (8UL)
#define GPIO_LCKR_LCK8_Msk                  (0x1UL << GPIO_LCKR_LCK8_Pos)           /*!< 0x00000100 */
#define GPIO_LCKR_LCK8                      GPIO_LCKR_LCK8_Msk
#define GPIO_LCKR_LCK9_Pos                  (9UL)
#define GPIO_LCKR_LCK9_Msk                  (0x1UL << GPIO_LCKR_LCK9_Pos)           /*!< 0x00000200 */
#define GPIO_LCKR_LCK9                      GPIO_LCKR_LCK9_Msk
#define GPIO_LCKR_LCK10_Pos                 (10UL)
#define GPIO_LCKR_LCK10_Msk                 (0x1UL << GPIO_LCKR_LCK10_Pos)          /*!< 0x00000400 */
#define GPIO_LCKR_LCK10                     GPIO_LCKR_LCK10_Msk
#define GPIO_LCKR_LCK11_Pos                 (11UL)
#define GPIO_LCKR_LCK11_Msk                 (0x1UL << GPIO_LCKR_LCK11_Pos)          /*!< 0x00000800 */
#define GPIO_LCKR_LCK11                     GPIO_LCKR_LCK11_Msk
#define GPIO_LCKR_LCK12_Pos                 (12UL)
#define GPIO_LCKR_LCK12_Msk                 (0x1UL << GPIO_LCKR_LCK12_Pos)          /*!< 0x00001000 */
#define GPIO_LCKR_LCK12                     GPIO_LCKR_LCK12_Msk
#define GPIO_LCKR_LCK13_Pos                 (13UL)
#define GPIO_LCKR_LCK13_Msk                 (0x1UL << GPIO_LCKR_LCK13_Pos)          /*!< 0x00002000 */
#define GPIO_LCKR_LCK13                     GPIO_LCKR_LCK13_Msk
#define GPIO_LCKR_LCK14_Pos                 (14UL)
#define GPIO_LCKR_LCK14_Msk                 (0x1UL << GPIO_LCKR_LCK14_Pos)          /*!< 0x00004000 */
#define GPIO_LCKR_LCK14                     GPIO_LCKR_LCK14_Msk
#define GPIO_LCKR_LCK15_Pos                 (15UL)
#define GPIO_LCKR_LCK15_Msk                 (0x1UL << GPIO_LCKR_LCK15_Pos)          /*!< 0x00008000 */
#define GPIO_LCKR_LCK15                     GPIO_LCKR_LCK15_Msk
#define GPIO_LCKR_LCKK_Pos                  (16UL)
#define GPIO_LCKR_LCKK_Msk                  (0x1UL << GPIO_LCKR_LCKK_Pos)           /*!< 0x00010000 */
#define GPIO_LCKR_LCKK                      GPIO_LCKR_LCKK_Msk

/****************** Bit definition for GPIO_AFRL register *********************/
#define GPIO_AFRL_AFSEL0_Pos                (0UL)
#define GPIO_AFRL_AFSEL0_Msk                (0xFUL << GPIO_AFRL_AFSEL0_Pos)         /*!< 0x0000000F */
#define GPIO_AFRL_AFSEL0                    GPIO_AFRL_AFSEL0_Msk
#define GPIO_AFRL_AFSEL0_0                  (0x1UL << GPIO_AFRL_AFSEL0_Pos)         /*!< 0x00000001 */
#define GPIO_AFRL_AFSEL0_1                  (0x2UL << GPIO_AFRL_AFSEL0_Pos)         /*!< 0x00000002 */
#define GPIO_AFRL_AFSEL0_2                  (0x4UL << GPIO_AFRL_AFSEL0_Pos)         /*!< 0x00000004 */
#define GPIO_AFRL_AFSEL0_3                  (0x8UL << GPIO_AFRL_AFSEL0_Pos)         /*!< 0x00000008 */
#define GPIO_AFRL_AFSEL1_Pos                (4UL)
#define GPIO_AFRL_AFSEL1_Msk                (0xFUL << GPIO_AFRL_AFSEL1_Pos)         /*!< 0x000000F0 */
#define GPIO_AFRL_AFSEL1                    GPIO_AFRL_AFSEL1_Msk
#define GPIO_AFRL_AFSEL1_0                  (0x1UL << GPIO_AFRL_AFSEL1_Pos)         /*!< 0x00000010 */
#define GPIO_AFRL_AFSEL1_1                  (0x2UL << GPIO_AFRL_AFSEL1_Pos)         /*!< 0x00000020 */
#define GPIO_AFRL_AFSEL1_2                  (0x4UL << GPIO_AFRL_AFSEL1_Pos)         /*!< 0x00000040 */
#define GPIO_AFRL_AFSEL1_3                  (0x8UL << GPIO_AFRL_AFSEL1_Pos)         /*!< 0x00000080 */
#define GPIO_AFRL_AFSEL2_Pos                (8UL)
#define GPIO_AFRL_AFSEL2_Msk                (0xFUL << GPIO_AFRL_AFSEL2_Pos)         /*!< 0x00000F00 */
#define GPIO_AFRL_AFSEL2                    GPIO_AFRL_AFSEL2_Msk
#define GPIO_AFRL_AFSEL2_0                  (0x1UL << GPIO_AFRL_AFSEL2_Pos)         /*!< 0x00000100 */
#define GPIO_AFRL_AFSEL2_1                  (0x2UL << GPIO_AFRL_AFSEL2_Pos)         /*!< 0x00000200 */
#define GPIO_AFRL_AFSEL2_2                  (0x4UL << GPIO_AFRL_AFSEL2_Pos)         /*!< 0x00000400 */
#define GPIO_AFRL_AFSEL2_3                  (0x8UL << GPIO_AFRL_AFSEL2_Pos)         /*!< 0x00000800 */
#define GPIO_AFRL_AFSEL3_Pos                (12UL)
#define GPIO_AFRL_AFSEL3_Msk                (0xFUL << GPIO_AFRL_AFSEL3_Pos)         /*!< 0x0000F000 */
#define GPIO_AFRL_AFSEL3                    GPIO_AFRL_AFSEL3_Msk
#define GPIO_AFRL_AFSEL3_0                  (0x1UL << GPIO_AFRL_AFSEL3_Pos)         /*!< 0x00001000 */
#define GPIO_AFRL_AFSEL3_1                  (0x2UL << GPIO_AFRL_AFSEL3_Pos)         /*!< 0x00002000 */
#define GPIO_AFRL_AFSEL3_2                  (0x4UL << GPIO_AFRL_AFSEL3_Pos)         /*!< 0x00004000 */
#define GPIO_AFRL_AFSEL3_3                  (0x8UL << GPIO_AFRL_AFSEL3_Pos)         /*!< 0x00008000 */
#define GPIO_AFRL_AFSEL4_Pos                (16UL)
#define GPIO_AFRL_AFSEL4_Msk                (0xFUL << GPIO_AFRL_AFSEL4_Pos)         /*!< 0x000F0000 */
#define GPIO_AFRL_AFSEL4                    GPIO_AFRL_AFSEL4_Msk
#define GPIO_AFRL_AFSEL4_0                  (0x1UL << GPIO_AFRL_AFSEL4_Pos)         /*!< 0x00010000 */
#define GPIO_AFRL_AFSEL4_1                  (0x2UL << GPIO_AFRL_AFSEL4_Pos)         /*!< 0x00020000 */
#define GPIO_AFRL_AFSEL4_2                  (0x4UL << GPIO_AFRL_AFSEL4_Pos)         /*!< 0x00040000 */
#define GPIO_AFRL_AFSEL4_3                  (0x8UL << GPIO_AFRL_AFSEL4_Pos)         /*!< 0x00080000 */
#define GPIO_AFRL_AFSEL5_Pos                (20UL)
#define GPIO_AFRL_AFSEL5_Msk                (0xFUL << GPIO_AFRL_AFSEL5_Pos)         /*!< 0x00F00000 */
#define GPIO_AFRL_AFSEL5                    GPIO_AFRL_AFSEL5_Msk
#define GPIO_AFRL_AFSEL5_0                  (0x1UL << GPIO_AFRL_AFSEL5_Pos)         /*!< 0x00100000 */
#define GPIO_AFRL_AFSEL5_1                  (0x2UL << GPIO_AFRL_AFSEL5_Pos)         /*!< 0x00200000 */
#define GPIO_AFRL_AFSEL5_2                  (0x4UL << GPIO_AFRL_AFSEL5_Pos)         /*!< 0x00400000 */
#define GPIO_AFRL_AFSEL5_3                  (0x8UL << GPIO_AFRL_AFSEL5_Pos)         /*!< 0x00800000 */
#define GPIO_AFRL_AFSEL6_Pos                (24UL)
#define GPIO_AFRL_AFSEL6_Msk                (0xFUL << GPIO_AFRL_AFSEL6_Pos)         /*!< 0x0F000000 */
#define GPIO_AFRL_AFSEL6                    GPIO_AFRL_AFSEL6_Msk
#define GPIO_AFRL_AFSEL6_0                  (0x1UL << GPIO_AFRL_AFSEL6_Pos)         /*!< 0x01000000 */
#define GPIO_AFRL_AFSEL6_1                  (0x2UL << GPIO_AFRL_AFSEL6_Pos)         /*!< 0x02000000 */
#define GPIO_AFRL_AFSEL6_2                  (0x4UL << GPIO_AFRL_AFSEL6_Pos)         /*!< 0x04000000 */
#define GPIO_AFRL_AFSEL6_3                  (0x8UL << GPIO_AFRL_AFSEL6_Pos)         /*!< 0x08000000 */
#define GPIO_AFRL_AFSEL7_Pos                (28UL)
#define GPIO_AFRL_AFSEL7_Msk                (0xFUL << GPIO_AFRL_AFSEL7_Pos)         /*!< 0xF0000000 */
#define GPIO_AFRL_AFSEL7                    GPIO_AFRL_AFSEL7_Msk
#define GPIO_AFRL_AFSEL7_0                  (0x1UL << GPIO_AFRL_AFSEL7_Pos)         /*!< 0x10000000 */
#define GPIO_AFRL_AFSEL7_1                  (0x2UL << GPIO_AFRL_AFSEL7_Pos)         /*!< 0x20000000 */
#define GPIO_AFRL_AFSEL7_2                  (0x4UL << GPIO_AFRL_AFSEL7_Pos)         /*!< 0x40000000 */
#define GPIO_AFRL_AFSEL7_3                  (0x8UL << GPIO_AFRL_AFSEL7_Pos)         /*!< 0x80000000 */

/****************** Bit definition for GPIO_AFRH register *********************/
#define GPIO_AFRH_AFSEL8_Pos                (0UL)
#define GPIO_AFRH_AFSEL8_Msk                (0xFUL << GPIO_AFRH_AFSEL8_Pos)         /*!< 0x0000000F */
#define GPIO_AFRH_AFSEL8                    GPIO_AFRH_AFSEL8_Msk
#define GPIO_AFRH_AFSEL8_0                  (0x1UL << GPIO_AFRH_AFSEL8_Pos)         /*!< 0x00000001 */
#define GPIO_AFRH_AFSEL8_1                  (0x2UL << GPIO_AFRH_AFSEL8_Pos)         /*!< 0x00000002 */
#define GPIO_AFRH_AFSEL8_2                  (0x4UL << GPIO_AFRH_AFSEL8_Pos)         /*!< 0x00000004 */
#define GPIO_AFRH_AFSEL8_3                  (0x8UL << GPIO_AFRH_AFSEL8_Pos)         /*!< 0x00000008 */
#define GPIO_AFRH_AFSEL9_Pos                (4UL)
#define GPIO_AFRH_AFSEL9_Msk                (0xFUL << GPIO_AFRH_AFSEL9_Pos)         /*!< 0x000000F0 */
#define GPIO_AFRH_AFSEL9                    GPIO_AFRH_AFSEL9_Msk
#define GPIO_AFRH_AFSEL9_0                  (0x1UL << GPIO_AFRH_AFSEL9_Pos)         /*!< 0x00000010 */
#define GPIO_AFRH_AFSEL9_1                  (0x2UL << GPIO_AFRH_AFSEL9_Pos)         /*!< 0x00000020 */
#define GPIO_AFRH_AFSEL9_2                  (0x4UL << GPIO_AFRH_AFSEL9_Pos)         /*!< 0x00000040 */
#define GPIO_AFRH_AFSEL9_3                  (0x8UL << GPIO_AFRH_AFSEL9_Pos)         /*!< 0x00000080 */
#define GPIO_AFRH_AFSEL10_Pos               (8UL)
#define GPIO_AFRH_AFSEL10_Msk               (0xFUL << GPIO_AFRH_AFSEL10_Pos)        /*!< 0x00000F00 */
#define GPIO_AFRH_AFSEL10                   GPIO_AFRH_AFSEL10_Msk
#define GPIO_AFRH_AFSEL10_0                 (0x1UL << GPIO_AFRH_AFSEL10_Pos)        /*!< 0x00000100 */
#define GPIO_AFRH_AFSEL10_1                 (0x2UL << GPIO_AFRH_AFSEL10_Pos)        /*!< 0x00000200 */
#define GPIO_AFRH_AFSEL10_2                 (0x4UL << GPIO_AFRH_AFSEL10_Pos)        /*!< 0x00000400 */
#define GPIO_AFRH_AFSEL10_3                 (0x8UL << GPIO_AFRH_AFSEL10_Pos)        /*!< 0x00000800 */
#define GPIO_AFRH_AFSEL11_Pos               (12UL)
#define GPIO_AFRH_AFSEL11_Msk               (0xFUL << GPIO_AFRH_AFSEL11_Pos)        /*!< 0x0000F000 */
#define GPIO_AFRH_AFSEL11                   GPIO_AFRH_AFSEL11_Msk
#define GPIO_AFRH_AFSEL11_0                 (0x1UL << GPIO_AFRH_AFSEL11_Pos)        /*!< 0x00001000 */
#define GPIO_AFRH_AFSEL11_1                 (0x2UL << GPIO_AFRH_AFSEL11_Pos)        /*!< 0x00002000 */
#define GPIO_AFRH_AFSEL11_2                 (0x4UL << GPIO_AFRH_AFSEL11_Pos)        /*!< 0x00004000 */
#define GPIO_AFRH_AFSEL11_3                 (0x8UL << GPIO_AFRH_AFSEL11_Pos)        /*!< 0x00008000 */
#define GPIO_AFRH_AFSEL12_Pos               (16UL)
#define GPIO_AFRH_AFSEL12_Msk               (0xFUL << GPIO_AFRH_AFSEL12_Pos)        /*!< 0x000F0000 */
#define GPIO_AFRH_AFSEL12                   GPIO_AFRH_AFSEL12_Msk
#define GPIO_AFRH_AFSEL12_0                 (0x1UL << GPIO_AFRH_AFSEL12_Pos)        /*!< 0x00010000 */
#define GPIO_AFRH_AFSEL12_1                 (0x2UL << GPIO_AFRH_AFSEL12_Pos)        /*!< 0x00020000 */
#define GPIO_AFRH_AFSEL12_2                 (0x4UL << GPIO_AFRH_AFSEL12_Pos)        /*!< 0x00040000 */
#define GPIO_AFRH_AFSEL12_3                 (0x8UL << GPIO_AFRH_AFSEL12_Pos)        /*!< 0x00080000 */
#define GPIO_AFRH_AFSEL13_Pos               (20UL)
#define GPIO_AFRH_AFSEL13_Msk               (0xFUL << GPIO_AFRH_AFSEL13_Pos)        /*!< 0x00F00000 */
#define GPIO_AFRH_AFSEL13                   GPIO_AFRH_AFSEL13_Msk
#define GPIO_AFRH_AFSEL13_0                 (0x1UL << GPIO_AFRH_AFSEL13_Pos)        /*!< 0x00100000 */
#define GPIO_AFRH_AFSEL13_1                 (0x2UL << GPIO_AFRH_AFSEL13_Pos)        /*!< 0x00200000 */
#define GPIO_AFRH_AFSEL13_2                 (0x4UL << GPIO_AFRH_AFSEL13_Pos)        /*!< 0x00400000 */
#define GPIO_AFRH_AFSEL13_3                 (0x8UL << GPIO_AFRH_AFSEL13_Pos)        /*!< 0x00800000 */
#define GPIO_AFRH_AFSEL14_Pos               (24UL)
#define GPIO_AFRH_AFSEL14_Msk               (0xFUL << GPIO_AFRH_AFSEL14_Pos)        /*!< 0x0F000000 */
#define GPIO_AFRH_AFSEL14                   GPIO_AFRH_AFSEL14_Msk
#define GPIO_AFRH_AFSEL14_0                 (0x1UL << GPIO_AFRH_AFSEL14_Pos)        /*!< 0x01000000 */
#define GPIO_AFRH_AFSEL14_1                 (0x2UL << GPIO_AFRH_AFSEL14_Pos)        /*!< 0x02000000 */
#define GPIO_AFRH_AFSEL14_2                 (0x4UL << GPIO_AFRH_AFSEL14_Pos)        /*!< 0x04000000 */
#define GPIO_AFRH_AFSEL14_3                 (0x8UL << GPIO_AFRH_AFSEL14_Pos)        /*!< 0x08000000 */
#define GPIO_AFRH_AFSEL15_Pos               (28UL)
#define GPIO_AFRH_AFSEL15_Msk               (0xFUL << GPIO_AFRH_AFSEL15_Pos)        /*!< 0xF0000000 */
#define GPIO_AFRH_AFSEL15                   GPIO_AFRH_AFSEL15_Msk
#define GPIO_AFRH_AFSEL15_0                 (0x1UL << GPIO_AFRH_AFSEL15_Pos)        /*!< 0x10000000 */
#define GPIO_AFRH_AFSEL15_1                 (0x2UL << GPIO_AFRH_AFSEL15_Pos)        /*!< 0x20000000 */
#define GPIO_AFRH_AFSEL15_2                 (0x4UL << GPIO_AFRH_AFSEL15_Pos)        /*!< 0x40000000 */
#define GPIO_AFRH_AFSEL15_3                 (0x8UL << GPIO_AFRH_AFSEL15_Pos)        /*!< 0x80000000 */

/******************  Bits definition for GPIO_BRR register  ******************/
#define GPIO_BRR_BR0_Pos                    (0UL)
#define GPIO_BRR_BR0_Msk                    (0x1UL << GPIO_BRR_BR0_Pos)             /*!< 0x00000001 */
#define GPIO_BRR_BR0                        GPIO_BRR_BR0_Msk
#define GPIO_BRR_BR1_Pos                    (1UL)
#define GPIO_BRR_BR1_Msk                    (0x1UL << GPIO_BRR_BR1_Pos)             /*!< 0x00000002 */
#define GPIO_BRR_BR1                        GPIO_BRR_BR1_Msk
#define GPIO_BRR_BR2_Pos                    (2UL)
#define GPIO_BRR_BR2_Msk                    (0x1UL << GPIO_BRR_BR2_Pos)             /*!< 0x00000004 */
#define GPIO_BRR_BR2                        GPIO_BRR_BR2_Msk
#define GPIO_BRR_BR3_Pos                    (3UL)
#define GPIO_BRR_BR3_Msk                    (0x1UL << GPIO_BRR_BR3_Pos)             /*!< 0x00000008 */
#define GPIO_BRR_BR3                        GPIO_BRR_BR3_Msk
#define GPIO_BRR_BR4_Pos                    (4UL)
#define GPIO_BRR_BR4_Msk                    (0x1UL << GPIO_BRR_BR4_Pos)             /*!< 0x00000010 */
#define GPIO_BRR_BR4                        GPIO_BRR_BR4_Msk
#define GPIO_BRR_BR5_Pos                    (5UL)
#define GPIO_BRR_BR5_Msk                    (0x1UL << GPIO_BRR_BR5_Pos)             /*!< 0x00000020 */
#define GPIO_BRR_BR5                        GPIO_BRR_BR5_Msk
#define GPIO_BRR_BR6_Pos                    (6UL)
#define GPIO_BRR_BR6_Msk                    (0x1UL << GPIO_BRR_BR6_Pos)             /*!< 0x00000040 */
#define GPIO_BRR_BR6                        GPIO_BRR_BR6_Msk
#define GPIO_BRR_BR7_Pos                    (7UL)
#define GPIO_BRR_BR7_Msk                    (0x1UL << GPIO_BRR_BR7_Pos)             /*!< 0x00000080 */
#define GPIO_BRR_BR7                        GPIO_BRR_BR7_Msk
#define GPIO_BRR_BR8_Pos                    (8UL)
#define GPIO_BRR_BR8_Msk                    (0x1UL << GPIO_BRR_BR8_Pos)             /*!< 0x00000100 */
#define GPIO_BRR_BR8                        GPIO_BRR_BR8_Msk
#define GPIO_BRR_BR9_Pos                    (9UL)
#define GPIO_BRR_BR9_Msk                    (0x1UL << GPIO_BRR_BR9_Pos)             /*!< 0x00000200 */
#define GPIO_BRR_BR9                        GPIO_BRR_BR9_Msk
#define GPIO_BRR_BR10_Pos                   (10UL)
#define GPIO_BRR_BR10_Msk                   (0x1UL << GPIO_BRR_BR10_Pos)            /*!< 0x00000400 */
#define GPIO_BRR_BR10                       GPIO_BRR_BR10_Msk
#define GPIO_BRR_BR11_Pos                   (11UL)
#define GPIO_BRR_BR11_Msk                   (0x1UL << GPIO_BRR_BR11_Pos)            /*!< 0x00000800 */
#define GPIO_BRR_BR11                       GPIO_BRR_BR11_Msk
#define GPIO_BRR_BR12_Pos                   (12UL)
#define GPIO_BRR_BR12_Msk                   (0x1UL << GPIO_BRR_BR12_Pos)            /*!< 0x00001000 */
#define GPIO_BRR_BR12                       GPIO_BRR_BR12_Msk
#define GPIO_BRR_BR13_Pos                   (13UL)
#define GPIO_BRR_BR13_Msk                   (0x1UL << GPIO_BRR_BR13_Pos)            /*!< 0x00002000 */
#define GPIO_BRR_BR13                       GPIO_BRR_BR13_Msk
#define GPIO_BRR_BR14_Pos                   (14UL)
#define GPIO_BRR_BR14_Msk                   (0x1UL << GPIO_BRR_BR14_Pos)            /*!< 0x00004000 */
#define GPIO_BRR_BR14                       GPIO_BRR_BR14_Msk
#define GPIO_BRR_BR15_Pos                   (15UL)
#define GPIO_BRR_BR15_Msk                   (0x1UL << GPIO_BRR_BR15_Pos)            /*!< 0x00008000 */
#define GPIO_BRR_BR15                       GPIO_BRR_BR15_Msk

/******************  Bits definition for GPIO_HSLVR register  ******************/
#define GPIO_HSLVR_HSLV0_Pos                (0UL)
#define GPIO_HSLVR_HSLV0_Msk                (0x1UL << GPIO_HSLVR_HSLV0_Pos)         /*!< 0x00000001 */
#define GPIO_HSLVR_HSLV0                    GPIO_HSLVR_HSLV0_Msk
#define GPIO_HSLVR_HSLV1_Pos                (1UL)
#define GPIO_HSLVR_HSLV1_Msk                (0x1UL << GPIO_HSLVR_HSLV1_Pos)         /*!< 0x00000002 */
#define GPIO_HSLVR_HSLV1                    GPIO_HSLVR_HSLV1_Msk
#define GPIO_HSLVR_HSLV2_Pos                (2UL)
#define GPIO_HSLVR_HSLV2_Msk                (0x1UL << GPIO_HSLVR_HSLV2_Pos)         /*!< 0x00000004 */
#define GPIO_HSLVR_HSLV2                    GPIO_HSLVR_HSLV2_Msk
#define GPIO_HSLVR_HSLV3_Pos                (3UL)
#define GPIO_HSLVR_HSLV3_Msk                (0x1UL << GPIO_HSLVR_HSLV3_Pos)         /*!< 0x00000008 */
#define GPIO_HSLVR_HSLV3                    GPIO_HSLVR_HSLV3_Msk
#define GPIO_HSLVR_HSLV4_Pos                (4UL)
#define GPIO_HSLVR_HSLV4_Msk                (0x1UL << GPIO_HSLVR_HSLV4_Pos)         /*!< 0x00000010 */
#define GPIO_HSLVR_HSLV4                    GPIO_HSLVR_HSLV4_Msk
#define GPIO_HSLVR_HSLV5_Pos                (5UL)
#define GPIO_HSLVR_HSLV5_Msk                (0x1UL << GPIO_HSLVR_HSLV5_Pos)         /*!< 0x00000020 */
#define GPIO_HSLVR_HSLV5                    GPIO_HSLVR_HSLV5_Msk
#define GPIO_HSLVR_HSLV6_Pos                (6UL)
#define GPIO_HSLVR_HSLV6_Msk                (0x1UL << GPIO_HSLVR_HSLV6_Pos)         /*!< 0x00000040 */
#define GPIO_HSLVR_HSLV6                    GPIO_HSLVR_HSLV6_Msk
#define GPIO_HSLVR_HSLV7_Pos                (7UL)
#define GPIO_HSLVR_HSLV7_Msk                (0x1UL << GPIO_HSLVR_HSLV7_Pos)         /*!< 0x00000080 */
#define GPIO_HSLVR_HSLV7                    GPIO_HSLVR_HSLV7_Msk
#define GPIO_HSLVR_HSLV8_Pos                (8UL)
#define GPIO_HSLVR_HSLV8_Msk                (0x1UL << GPIO_HSLVR_HSLV8_Pos)         /*!< 0x00000100 */
#define GPIO_HSLVR_HSLV8                    GPIO_HSLVR_HSLV8_Msk
#define GPIO_HSLVR_HSLV9_Pos                (9UL)
#define GPIO_HSLVR_HSLV9_Msk                (0x1UL << GPIO_HSLVR_HSLV9_Pos)         /*!< 0x00000200 */
#define GPIO_HSLVR_HSLV9                    GPIO_HSLVR_HSLV9_Msk
#define GPIO_HSLVR_HSLV10_Pos               (10UL)
#define GPIO_HSLVR_HSLV10_Msk               (0x1UL << GPIO_HSLVR_HSLV10_Pos)        /*!< 0x00000400 */
#define GPIO_HSLVR_HSLV10                   GPIO_HSLVR_HSLV10_Msk
#define GPIO_HSLVR_HSLV11_Pos               (11UL)
#define GPIO_HSLVR_HSLV11_Msk               (x1UL << GPIO_HSLVR_HSLV11_Pos)         /*!< 0x00000800 */
#define GPIO_HSLVR_HSLV11                   GPIO_HSLVR_HSLV11_Msk
#define GPIO_HSLVR_HSLV12_Pos               (12UL)
#define GPIO_HSLVR_HSLV12_Msk               (0x1UL << GPIO_HSLVR_HSLV12_Pos)        /*!< 0x00001000 */
#define GPIO_HSLVR_HSLV12                   GPIO_HSLVR_HSLV12_Msk
#define GPIO_HSLVR_HSLV13_Pos               (13UL)
#define GPIO_HSLVR_HSLV13_Msk               (0x1UL << GPIO_HSLVR_HSLV13_Pos)        /*!< 0x00002000 */
#define GPIO_HSLVR_HSLV13                   GPIO_HSLVR_HSLV13_Msk
#define GPIO_HSLVR_HSLV14_Pos               (14UL)
#define GPIO_HSLVR_HSLV14_Msk               (0x1UL << GPIO_HSLVR_HSLV14_Pos)        /*!< 0x00004000 */
#define GPIO_HSLVR_HSLV14                   GPIO_HSLVR_HSLV14_Msk
#define GPIO_HSLVR_HSLV15_Pos               (15UL)
#define GPIO_HSLVR_HSLV15_Msk               (0x1UL << GPIO_HSLVR_HSLV15_Pos)        /*!< 0x00008000 */
#define GPIO_HSLVR_HSLV15                   GPIO_HSLVR_HSLV15_Msk

/******************  Bits definition for GPIO_SECCFGR register  ******************/
#define GPIO_SECCFGR_SEC0_Pos               (0UL)
#define GPIO_SECCFGR_SEC0_Msk               (0x1UL << GPIO_SECCFGR_SEC0_Pos)        /*!< 0x00000001 */
#define GPIO_SECCFGR_SEC0                   GPIO_SECCFGR_SEC0_Msk
#define GPIO_SECCFGR_SEC1_Pos               (1UL)
#define GPIO_SECCFGR_SEC1_Msk               (0x1UL << GPIO_SECCFGR_SEC1_Pos)        /*!< 0x00000002 */
#define GPIO_SECCFGR_SEC1                   GPIO_SECCFGR_SEC1_Msk
#define GPIO_SECCFGR_SEC2_Pos               (2UL)
#define GPIO_SECCFGR_SEC2_Msk               (0x1UL << GPIO_SECCFGR_SEC2_Pos)        /*!< 0x00000004 */
#define GPIO_SECCFGR_SEC2                   GPIO_SECCFGR_SEC2_Msk
#define GPIO_SECCFGR_SEC3_Pos               (3UL)
#define GPIO_SECCFGR_SEC3_Msk               (0x1UL << GPIO_SECCFGR_SEC3_Pos)        /*!< 0x00000008 */
#define GPIO_SECCFGR_SEC3                   GPIO_SECCFGR_SEC3_Msk
#define GPIO_SECCFGR_SEC4_Pos               (4UL)
#define GPIO_SECCFGR_SEC4_Msk               (0x1UL << GPIO_SECCFGR_SEC4_Pos)        /*!< 0x00000010 */
#define GPIO_SECCFGR_SEC4                   GPIO_SECCFGR_SEC4_Msk
#define GPIO_SECCFGR_SEC5_Pos               (5UL)
#define GPIO_SECCFGR_SEC5_Msk               (0x1UL << GPIO_SECCFGR_SEC5_Pos)        /*!< 0x00000020 */
#define GPIO_SECCFGR_SEC5                   GPIO_SECCFGR_SEC5_Msk
#define GPIO_SECCFGR_SEC6_Pos               (6UL)
#define GPIO_SECCFGR_SEC6_Msk               (0x1UL << GPIO_SECCFGR_SEC6_Pos)        /*!< 0x00000040 */
#define GPIO_SECCFGR_SEC6                   GPIO_SECCFGR_SEC6_Msk
#define GPIO_SECCFGR_SEC7_Pos               (7UL)
#define GPIO_SECCFGR_SEC7_Msk               (0x1UL << GPIO_SECCFGR_SEC7_Pos)        /*!< 0x00000080 */
#define GPIO_SECCFGR_SEC7                   GPIO_SECCFGR_SEC7_Msk
#define GPIO_SECCFGR_SEC8_Pos               (8UL)
#define GPIO_SECCFGR_SEC8_Msk               (0x1UL << GPIO_SECCFGR_SEC8_Pos)        /*!< 0x00000100 */
#define GPIO_SECCFGR_SEC8                   GPIO_SECCFGR_SEC8_Msk
#define GPIO_SECCFGR_SEC9_Pos               (9UL)
#define GPIO_SECCFGR_SEC9_Msk               (0x1UL << GPIO_SECCFGR_SEC9_Pos)        /*!< 0x00000200 */
#define GPIO_SECCFGR_SEC9                   GPIO_SECCFGR_SEC9_Msk
#define GPIO_SECCFGR_SEC10_Pos              (10UL)
#define GPIO_SECCFGR_SEC10_Msk              (0x1UL << GPIO_SECCFGR_SEC10_Pos)       /*!< 0x00000400 */
#define GPIO_SECCFGR_SEC10                  GPIO_SECCFGR_SEC10_Msk
#define GPIO_SECCFGR_SEC11_Pos              (11UL)
#define GPIO_SECCFGR_SEC11_Msk              (x1UL << GPIO_SECCFGR_SEC11_Pos)        /*!< 0x00000800 */
#define GPIO_SECCFGR_SEC11                  GPIO_SECCFGR_SEC11_Msk
#define GPIO_SECCFGR_SEC12_Pos              (12UL)
#define GPIO_SECCFGR_SEC12_Msk              (0x1UL << GPIO_SECCFGR_SEC12_Pos)       /*!< 0x00001000 */
#define GPIO_SECCFGR_SEC12                  GPIO_SECCFGR_SEC12_Msk
#define GPIO_SECCFGR_SEC13_Pos              (13UL)
#define GPIO_SECCFGR_SEC13_Msk              (0x1UL << GPIO_SECCFGR_SEC13_Pos)       /*!< 0x00002000 */
#define GPIO_SECCFGR_SEC13                  GPIO_SECCFGR_SEC13_Msk
#define GPIO_SECCFGR_SEC14_Pos              (14UL)
#define GPIO_SECCFGR_SEC14_Msk              (0x1UL << GPIO_SECCFGR_SEC14_Pos)       /*!< 0x00004000 */
#define GPIO_SECCFGR_SEC14                  GPIO_SECCFGR_SEC14_Msk
#define GPIO_SECCFGR_SEC15_Pos              (15UL)
#define GPIO_SECCFGR_SEC15_Msk              (0x1UL << GPIO_SECCFGR_SEC15_Pos)       /*!< 0x00008000 */
#define GPIO_SECCFGR_SEC15                  GPIO_SECCFGR_SEC15_Msk

/*****************************************************************************/
/*                                                                           */
/*                        Global TrustZone Control                           */
/*                                                                           */
/*****************************************************************************/
/*******************  Bits definition for GTZC_TZSC_CR register  ******************/
#define GTZC_TZSC_CR_LCK_Pos                (0UL)
#define GTZC_TZSC_CR_LCK_Msk                (0x01UL << GTZC_TZSC_CR_LCK_Pos)        /*!< 0x00000001 */

/*******  Bits definition for TZSC _SECCFGRx/_PRIVCFGRx registers  *****/
/*******  Bits definition for TZIC _IERx/_SRx/_IFCRx registers  ********/

/***************  Bits definition for register x=1 (TZSC1) *************/
#define GTZC_CFGR1_TIM2_Pos                 (0UL)
#define GTZC_CFGR1_TIM2_Msk                 (0x01UL << GTZC_CFGR1_TIM2_Pos)         /*!< 0x00000001 */
#define GTZC_CFGR1_TIM3_Pos                 (1UL)
#define GTZC_CFGR1_TIM3_Msk                 (0x01UL << GTZC_CFGR1_TIM3_Pos)         /*!< 0x00000002 */
#define GTZC_CFGR1_TIM4_Pos                 (2UL)
#define GTZC_CFGR1_TIM4_Msk                 (0x01UL << GTZC_CFGR1_TIM4_Pos)         /*!< 0x00000004 */
#define GTZC_CFGR1_TIM6_Pos                 (4UL)
#define GTZC_CFGR1_TIM6_Msk                 (0x01UL << GTZC_CFGR1_TIM6_Pos)         /*!< 0x00000010 */
#define GTZC_CFGR1_TIM7_Pos                 (5UL)
#define GTZC_CFGR1_TIM7_Msk                 (0x01UL << GTZC_CFGR1_TIM7_Pos)         /*!< 0x00000020 */
#define GTZC_CFGR1_WWDG_Pos                 (6UL)
#define GTZC_CFGR1_WWDG_Msk                 (0x01UL << GTZC_CFGR1_WWDG_Pos)         /*!< 0x00000040 */
#define GTZC_CFGR1_IWDG_Pos                 (7UL)
#define GTZC_CFGR1_IWDG_Msk                 (0x01UL << GTZC_CFGR1_IWDG_Pos)         /*!< 0x00000080 */
#define GTZC_CFGR1_SPI2_Pos                 (8UL)
#define GTZC_CFGR1_SPI2_Msk                 (0x01UL << GTZC_CFGR1_SPI2_Pos)         /*!< 0x00000100 */
#define GTZC_CFGR1_USART3_Pos               (10UL)
#define GTZC_CFGR1_USART3_Msk               (0x01UL << GTZC_CFGR1_USART3_Pos)       /*!< 0x00000400 */
#define GTZC_CFGR1_UART4_Pos                (11UL)
#define GTZC_CFGR1_UART4_Msk                (0x01UL << GTZC_CFGR1_UART4_Pos)        /*!< 0x00000800 */
#define GTZC_CFGR1_UART5_Pos                (12UL)
#define GTZC_CFGR1_UART5_Msk                (0x01UL << GTZC_CFGR1_UART5_Pos)        /*!< 0x00001000 */
#define GTZC_CFGR1_I2C1_Pos                 (13UL)
#define GTZC_CFGR1_I2C1_Msk                 (0x01UL << GTZC_CFGR1_I2C1_Pos)         /*!< 0x00002000 */
#define GTZC_CFGR1_I2C2_Pos                 (14UL)
#define GTZC_CFGR1_I2C2_Msk                 (0x01UL << GTZC_CFGR1_I2C2_Pos)         /*!< 0x00004000 */
#define GTZC_CFGR1_CRS_Pos                  (15UL)
#define GTZC_CFGR1_CRS_Msk                  (0x01UL << GTZC_CFGR1_CRS_Pos)          /*!< 0x00008000 */
#define GTZC_CFGR1_LPTIM2_Pos               (17UL)
#define GTZC_CFGR1_LPTIM2_Msk               (0x01UL << GTZC_CFGR1_LPTIM2_Pos)       /*!< 0x00020000 */
#define GTZC_CFGR1_FDCAN1_Pos               (18UL)
#define GTZC_CFGR1_FDCAN1_Msk               (0x01UL << GTZC_CFGR1_FDCAN1_Pos)       /*!< 0x00040000 */
#define GTZC_CFGR1_SPI3_Pos                 (21UL)
#define GTZC_CFGR1_SPI3_Msk                 (0x01UL << GTZC_CFGR1_SPI3_Pos)         /*!< 0x00200000 */
#define GTZC_CFGR1_I3C1_Pos                 (22UL)
#define GTZC_CFGR1_I3C1_Msk                 (0x01UL << GTZC_CFGR1_I3C1_Pos)         /*!< 0x00400000 */
#define GTZC_CFGR1_OPAMP_Pos                (23UL)
#define GTZC_CFGR1_OPAMP_Msk                (0x01UL << GTZC_CFGR1_OPAMP_Pos)        /*!< 0x00800000 */
#define GTZC_CFGR1_VREFBUF_Pos              (24UL)
#define GTZC_CFGR1_VREFBUF_Msk              (0x01UL << GTZC_CFGR1_VREFBUF_Pos)      /*!< 0x01000000 */

/***************  Bits definition for register x=2 (TZSC1) *************/
#define GTZC_CFGR2_TIM1_Pos                 (0UL)
#define GTZC_CFGR2_TIM1_Msk                 (0x01UL << GTZC_CFGR2_TIM1_Pos)         /*!< 0x00000001 */
#define GTZC_CFGR2_SPI1_Pos                 (1UL)
#define GTZC_CFGR2_SPI1_Msk                 (0x01UL << GTZC_CFGR2_SPI1_Pos)         /*!< 0x00000002 */
#define GTZC_CFGR2_USART1_Pos               (3UL)
#define GTZC_CFGR2_USART1_Msk               (0x01UL << GTZC_CFGR2_USART1_Pos)       /*!< 0x00000008 */
#define GTZC_CFGR2_TIM15_Pos                (4UL)
#define GTZC_CFGR2_TIM15_Msk                (0x01UL << GTZC_CFGR2_TIM15_Pos)        /*!< 0x00000010 */
#define GTZC_CFGR2_TIM16_Pos                (5UL)
#define GTZC_CFGR2_TIM16_Msk                (0x01UL << GTZC_CFGR2_TIM16_Pos)        /*!< 0x00000020 */
#define GTZC_CFGR2_TIM17_Pos                (6UL)
#define GTZC_CFGR2_TIM17_Msk                (0x01UL << GTZC_CFGR2_TIM17_Pos)        /*!< 0x00000040 */
#define GTZC_CFGR2_SAI1_Pos                 (7UL)
#define GTZC_CFGR2_SAI1_Msk                 (0x01UL << GTZC_CFGR2_SAI1_Pos)         /*!< 0x00000080 */
#define GTZC_CFGR2_USB_Pos                  (9UL)
#define GTZC_CFGR2_USB_Msk                  (0x01UL << GTZC_CFGR2_USB_Pos)          /*!< 0x00000200 */
#define GTZC_CFGR2_I3C2_Pos                 (10UL)
#define GTZC_CFGR2_I3C2_Msk                 (0x01UL << GTZC_CFGR2_I3C2_Pos)         /*!< 0x00000400 */
#define GTZC_CFGR2_LPUART1_Pos              (11UL)
#define GTZC_CFGR2_LPUART1_Msk              (0x01UL << GTZC_CFGR2_LPUART1_Pos)      /*!< 0x00000800 */
#define GTZC_CFGR2_I2C3_Pos                 (12UL)
#define GTZC_CFGR2_I2C3_Msk                 (0x01UL << GTZC_CFGR2_I2C3_Pos)         /*!< 0x00001000 */
#define GTZC_CFGR2_LPTIM1_Pos               (13UL)
#define GTZC_CFGR2_LPTIM1_Msk               (0x01UL << GTZC_CFGR2_LPTIM1_Pos)       /*!< 0x00002000 */
#define GTZC_CFGR2_LPTIM3_Pos               (14UL)
#define GTZC_CFGR2_LPTIM3_Msk               (0x01UL << GTZC_CFGR2_LPTIM3_Pos)       /*!< 0x00004000 */
#define GTZC_CFGR2_LPTIM4_Pos               (15UL)
#define GTZC_CFGR2_LPTIM4_Msk               (0x01UL << GTZC_CFGR2_LPTIM4_Pos)       /*!< 0x00008000 */
#define GTZC_CFGR2_COMP_Pos                 (16UL)
#define GTZC_CFGR2_COMP_Msk                 (0x01UL << GTZC_CFGR2_COMP_Pos)         /*!< 0x00010000 */

/***************  Bits definition for register x=3 (TZSC1) *************/
#define GTZC_CFGR3_CRC_Pos                  (3UL)
#define GTZC_CFGR3_CRC_Msk                  (0x01UL << GTZC_CFGR3_CRC_Pos)          /*!< 0x00000004 */
#define GTZC_CFGR3_TSC_Pos                  (4UL)
#define GTZC_CFGR3_TSC_Msk                  (0x01UL << GTZC_CFGR3_TSC_Pos)          /*!< 0x00000008 */
#define GTZC_CFGR3_ICACHE_REG_Pos           (6UL)
#define GTZC_CFGR3_ICACHE_REG_Msk           (0x01UL << GTZC_CFGR3_ICACHE_REG_Pos)   /*!< 0x00000020 */
#define GTZC_CFGR3_ADC12_Pos                (8UL)
#define GTZC_CFGR3_ADC12_Msk                (0x01UL << GTZC_CFGR3_ADC12_Pos)        /*!< 0x00000100 */
#define GTZC_CFGR3_AES_Pos                  (11UL)
#define GTZC_CFGR3_AES_Msk                  (0x01UL << GTZC_CFGR3_AES_Pos)          /*!< 0x00000800 */
#define GTZC_CFGR3_HASH_Pos                 (12UL)
#define GTZC_CFGR3_HASH_Msk                 (0x01UL << GTZC_CFGR3_HASH_Pos)         /*!< 0x00001000 */
#define GTZC_CFGR3_RNG_Pos                  (13UL)
#define GTZC_CFGR3_RNG_Msk                  (0x01UL << GTZC_CFGR3_RNG_Pos)          /*!< 0x00002000 */
#define GTZC_CFGR3_PKA_Pos                  (14UL)
#define GTZC_CFGR3_PKA_Msk                  (0x01UL << GTZC_CFGR3_PKA_Pos)          /*!< 0x00004000 */
#define GTZC_CFGR3_SAES_Pos                 (15UL)
#define GTZC_CFGR3_SAES_Msk                 (0x01UL << GTZC_CFGR3_SAES_Pos)         /*!< 0x00008000 */
#define GTZC_CFGR3_CCB_Pos                  (16UL)
#define GTZC_CFGR3_CCB_Msk                  (0x01UL << GTZC_CFGR3_CCB_Pos)          /*!< 0x00010000 */
#define GTZC_CFGR3_SDMMC1_Pos               (17UL)
#define GTZC_CFGR3_SDMMC1_Msk               (0x01UL << GTZC_CFGR3_SDMMC1_Pos)       /*!< 0x00020000 */
#define GTZC_CFGR3_OCTOSPI1_REG_Pos         (20UL)
#define GTZC_CFGR3_OCTOSPI1_REG_Msk         (0x01UL << GTZC_CFGR3_OCTOSPI1_REG_Pos) /*!< 0x00080000 */
#define GTZC_CFGR3_RAMCFG_Pos               (22UL)
#define GTZC_CFGR3_RAMCFG_Msk               (0x01UL << GTZC_CFGR3_RAMCFG_Pos)       /*!< 0x00400000 */
#define GTZC_CFGR3_DAC1_Pos                 (23UL)
#define GTZC_CFGR3_DAC1_Msk                 (0x01UL << GTZC_CFGR3_DAC1_Pos)         /*!< 0x00800000 */
#define GTZC_CFGR3_ADF1_Pos                 (24UL)
#define GTZC_CFGR3_ADF1_Msk                 (0x01UL << GTZC_CFGR3_ADF1_Pos)         /*!< 0x01000000 */

/***************  Bits definition for register x=4 (TZSC1) *************/
#define GTZC_CFGR4_GPDMA1_Pos               (0UL)
#define GTZC_CFGR4_GPDMA1_Msk               (0x01UL << GTZC_CFGR4_GPDMA1_Pos)       /*!< 0x00000001 */
#define GTZC_CFGR4_FLASH_Pos                (1UL)
#define GTZC_CFGR4_FLASH_Msk                (0x01UL << GTZC_CFGR4_FLASH_Pos)        /*!< 0x00000002 */
#define GTZC_CFGR4_FLASH_REG_Pos            (2UL)
#define GTZC_CFGR4_FLASH_REG_Msk            (0x01UL << GTZC_CFGR4_FLASH_REG_Pos)    /*!< 0x00000004 */
#define GTZC_CFGR4_PWR_Pos                  (3UL)
#define GTZC_CFGR4_PWR_Msk                  (0x01UL << GTZC_CFGR4_PWR_Pos)          /*!< 0x00000008 */
#define GTZC_CFGR4_RCC_Pos                  (4UL)
#define GTZC_CFGR4_RCC_Msk                  (0x01UL << GTZC_CFGR4_RCC_Pos)          /*!< 0x00000010 */
#define GTZC_CFGR4_SYSCFG_Pos               (5UL)
#define GTZC_CFGR4_SYSCFG_Msk               (0x01UL << GTZC_CFGR4_SYSCFG_Pos)       /*!< 0x00000020 */
#define GTZC_CFGR4_EXTI_Pos                 (6UL)
#define GTZC_CFGR4_EXTI_Msk                 (0x01UL << GTZC_CFGR4_EXTI_Pos)         /*!< 0x00000040 */
#define GTZC_CFGR4_RTC_Pos                  (7UL)
#define GTZC_CFGR4_RTC_Msk                  (0x01UL << GTZC_CFGR4_RTC_Pos)          /*!< 0x00000080 */
#define GTZC_CFGR4_TAMP_Pos                 (8UL)
#define GTZC_CFGR4_TAMP_Msk                 (0x01UL << GTZC_CFGR4_TAMP_Pos)         /*!< 0x00000100 */
#define GTZC_CFGR4_TZSC_Pos                 (14UL)
#define GTZC_CFGR4_TZSC_Msk                 (0x01UL << GTZC_CFGR4_TZSC_Pos)         /*!< 0x00004000 */
#define GTZC_CFGR4_TZIC_Pos                 (15UL)
#define GTZC_CFGR4_TZIC_Msk                 (0x01UL << GTZC_CFGR4_TZIC_Pos)         /*!< 0x00008000 */
#define GTZC_CFGR4_SRAM1_Pos                (24UL)
#define GTZC_CFGR4_SRAM1_Msk                (0x01UL << GTZC_CFGR4_SRAM1_Pos)        /*!< 0x01000000 */
#define GTZC_CFGR4_MPCBB1_REG_Pos           (25UL)
#define GTZC_CFGR4_MPCBB1_REG_Msk           (0x01UL << GTZC_CFGR4_MPCBB1_REG_Pos)   /*!< 0x02000000 */
#define GTZC_CFGR4_SRAM2_Pos                (26UL)
#define GTZC_CFGR4_SRAM2_Msk                (0x01UL << GTZC_CFGR4_SRAM2_Pos)        /*!< 0x04000000 */
#define GTZC_CFGR4_MPCBB2_REG_Pos           (27UL)
#define GTZC_CFGR4_MPCBB2_REG_Msk           (0x01UL << GTZC_CFGR4_MPCBB2_REG_Pos)   /*!< 0x08000000 */

/*******************  Bits definition for GTZC_TZSC1_SECCFGR1 register  ***************/
#define GTZC_TZSC1_SECCFGR1_TIM2_Pos            GTZC_CFGR1_TIM2_Pos
#define GTZC_TZSC1_SECCFGR1_TIM2_Msk            GTZC_CFGR1_TIM2_Msk
#define GTZC_TZSC1_SECCFGR1_TIM3_Pos            GTZC_CFGR1_TIM3_Pos
#define GTZC_TZSC1_SECCFGR1_TIM3_Msk            GTZC_CFGR1_TIM3_Msk
#define GTZC_TZSC1_SECCFGR1_TIM4_Pos            GTZC_CFGR1_TIM4_Pos
#define GTZC_TZSC1_SECCFGR1_TIM4_Msk            GTZC_CFGR1_TIM4_Msk
#define GTZC_TZSC1_SECCFGR1_TIM5_Pos            GTZC_CFGR1_TIM5_Pos
#define GTZC_TZSC1_SECCFGR1_TIM5_Msk            GTZC_CFGR1_TIM5_Msk
#define GTZC_TZSC1_SECCFGR1_TIM6_Pos            GTZC_CFGR1_TIM6_Pos
#define GTZC_TZSC1_SECCFGR1_TIM6_Msk            GTZC_CFGR1_TIM6_Msk
#define GTZC_TZSC1_SECCFGR1_TIM7_Pos            GTZC_CFGR1_TIM7_Pos
#define GTZC_TZSC1_SECCFGR1_TIM7_Msk            GTZC_CFGR1_TIM7_Msk
#define GTZC_TZSC1_SECCFGR1_WWDG_Pos            GTZC_CFGR1_WWDG_Pos
#define GTZC_TZSC1_SECCFGR1_WWDG_Msk            GTZC_CFGR1_WWDG_Msk
#define GTZC_TZSC1_SECCFGR1_IWDG_Pos            GTZC_CFGR1_IWDG_Pos
#define GTZC_TZSC1_SECCFGR1_IWDG_Msk            GTZC_CFGR1_IWDG_Msk
#define GTZC_TZSC1_SECCFGR1_SPI2_Pos            GTZC_CFGR1_SPI2_Pos
#define GTZC_TZSC1_SECCFGR1_SPI2_Msk            GTZC_CFGR1_SPI2_Msk
#define GTZC_TZSC1_SECCFGR1_USART3_Pos          GTZC_CFGR1_USART3_Pos
#define GTZC_TZSC1_SECCFGR1_USART3_Msk          GTZC_CFGR1_USART3_Msk
#define GTZC_TZSC1_SECCFGR1_UART4_Pos           GTZC_CFGR1_UART4_Pos
#define GTZC_TZSC1_SECCFGR1_UART4_Msk           GTZC_CFGR1_UART4_Msk
#define GTZC_TZSC1_SECCFGR1_UART5_Pos           GTZC_CFGR1_UART5_Pos
#define GTZC_TZSC1_SECCFGR1_UART5_Msk           GTZC_CFGR1_UART5_Msk
#define GTZC_TZSC1_SECCFGR1_I2C1_Pos            GTZC_CFGR1_I2C1_Pos
#define GTZC_TZSC1_SECCFGR1_I2C1_Msk            GTZC_CFGR1_I2C1_Msk
#define GTZC_TZSC1_SECCFGR1_I2C2_Pos            GTZC_CFGR1_I2C2_Pos
#define GTZC_TZSC1_SECCFGR1_I2C2_Msk            GTZC_CFGR1_I2C2_Msk
#define GTZC_TZSC1_SECCFGR1_CRS_Pos             GTZC_CFGR1_CRS_Pos
#define GTZC_TZSC1_SECCFGR1_CRS_Msk             GTZC_CFGR1_CRS_Msk
#define GTZC_TZSC1_SECCFGR1_LPTIM2_Pos          GTZC_CFGR1_LPTIM2_Pos
#define GTZC_TZSC1_SECCFGR1_LPTIM2_Msk          GTZC_CFGR1_LPTIM2_Msk
#define GTZC_TZSC1_SECCFGR1_FDCAN1_Pos          GTZC_CFGR1_FDCAN1_Pos
#define GTZC_TZSC1_SECCFGR1_FDCAN1_Msk          GTZC_CFGR1_FDCAN1_Msk
#define GTZC_TZSC1_SECCFGR1_SPI3_Pos            GTZC_CFGR1_SPI3_Pos
#define GTZC_TZSC1_SECCFGR1_SPI3_Msk            GTZC_CFGR1_SPI3_Msk
#define GTZC_TZSC1_SECCFGR1_I3C1_Pos            GTZC_CFGR1_I3C1_Pos
#define GTZC_TZSC1_SECCFGR1_I3C1_Msk            GTZC_CFGR1_I3C1_Msk
#define GTZC_TZSC1_SECCFGR1_OPAMP_Pos           GTZC_CFGR1_OPAMP_Pos
#define GTZC_TZSC1_SECCFGR1_OPAMP_Msk           GTZC_CFGR1_OPAMP_Msk
#define GTZC_TZSC1_SECCFGR1_VREFBUF_Pos         GTZC_CFGR1_VREFBUF_Pos
#define GTZC_TZSC1_SECCFGR1_VREFBUF_Msk         GTZC_CFGR1_VREFBUF_Msk

/*******************  Bits definition for GTZC_TZSC1_SECCFGR2 register  ***************/
#define GTZC_TZSC1_SECCFGR2_TIM1_Pos            GTZC_CFGR2_TIM1_Pos
#define GTZC_TZSC1_SECCFGR2_TIM1_Msk            GTZC_CFGR2_TIM1_Msk
#define GTZC_TZSC1_SECCFGR2_SPI1_Pos            GTZC_CFGR2_SPI1_Pos
#define GTZC_TZSC1_SECCFGR2_SPI1_Msk            GTZC_CFGR2_SPI1_Msk
#define GTZC_TZSC1_SECCFGR2_USART1_Pos          GTZC_CFGR2_USART1_Pos
#define GTZC_TZSC1_SECCFGR2_USART1_Msk          GTZC_CFGR2_USART1_Msk
#define GTZC_TZSC1_SECCFGR2_TIM15_Pos           GTZC_CFGR2_TIM15_Pos
#define GTZC_TZSC1_SECCFGR2_TIM15_Msk           GTZC_CFGR2_TIM15_Msk
#define GTZC_TZSC1_SECCFGR2_TIM16_Pos           GTZC_CFGR2_TIM16_Pos
#define GTZC_TZSC1_SECCFGR2_TIM16_Msk           GTZC_CFGR2_TIM16_Msk
#define GTZC_TZSC1_SECCFGR2_TIM17_Pos           GTZC_CFGR2_TIM17_Pos
#define GTZC_TZSC1_SECCFGR2_TIM17_Msk           GTZC_CFGR2_TIM17_Msk
#define GTZC_TZSC1_SECCFGR2_SAI1_Pos            GTZC_CFGR2_SAI1_Pos
#define GTZC_TZSC1_SECCFGR2_SAI1_Msk            GTZC_CFGR2_SAI1_Msk
#define GTZC_TZSC1_SECCFGR2_USB_Pos             GTZC_CFGR2_USB_Pos
#define GTZC_TZSC1_SECCFGR2_USB_Msk             GTZC_CFGR2_USB_Msk
#define GTZC_TZSC1_SECCFGR2_I3C2_Pos            GTZC_CFGR2_I3C2_Pos
#define GTZC_TZSC1_SECCFGR2_I3C2_Msk            GTZC_CFGR2_I3C2_Msk
#define GTZC_TZSC1_SECCFGR2_LPUART1_Pos         GTZC_CFGR2_LPUART1_Pos
#define GTZC_TZSC1_SECCFGR2_LPUART1_Msk         GTZC_CFGR2_LPUART1_Msk
#define GTZC_TZSC1_SECCFGR2_I2C3_Pos            GTZC_CFGR2_I2C3_Pos
#define GTZC_TZSC1_SECCFGR2_I2C3_Msk            GTZC_CFGR2_I2C3_Msk
#define GTZC_TZSC1_SECCFGR2_LPTIM1_Pos          GTZC_CFGR2_LPTIM1_Pos
#define GTZC_TZSC1_SECCFGR2_LPTIM1_Msk          GTZC_CFGR2_LPTIM1_Msk
#define GTZC_TZSC1_SECCFGR2_LPTIM3_Pos          GTZC_CFGR2_LPTIM3_Pos
#define GTZC_TZSC1_SECCFGR2_LPTIM3_Msk          GTZC_CFGR2_LPTIM3_Msk
#define GTZC_TZSC1_SECCFGR2_LPTIM4_Pos          GTZC_CFGR2_LPTIM4_Pos
#define GTZC_TZSC1_SECCFGR2_LPTIM4_Msk          GTZC_CFGR2_LPTIM4_Msk
#define GTZC_TZSC1_SECCFGR2_COMP_Pos            GTZC_CFGR2_COMP_Pos
#define GTZC_TZSC1_SECCFGR2_COMP_Msk            GTZC_CFGR2_COMP_Msk

/*******************  Bits definition for GTZC_TZSC1_SECCFGR3 register  ***************/
#define GTZC_TZSC1_SECCFGR3_CRC_Pos             GTZC_CFGR3_CRC_Pos
#define GTZC_TZSC1_SECCFGR3_CRC_Msk             GTZC_CFGR3_CRC_Msk
#define GTZC_TZSC1_SECCFGR3_TSC_Pos             GTZC_CFGR3_TSC_Pos
#define GTZC_TZSC1_SECCFGR3_TSC_Msk             GTZC_CFGR3_TSC_Msk
#define GTZC_TZSC1_SECCFGR3_ICACHE_REG_Pos      GTZC_CFGR3_ICACHE_REG_Pos
#define GTZC_TZSC1_SECCFGR3_ICACHE_REG_Msk      GTZC_CFGR3_ICACHE_REG_Msk
#define GTZC_TZSC1_SECCFGR3_ADC12_Pos           GTZC_CFGR3_ADC12_Pos
#define GTZC_TZSC1_SECCFGR3_ADC12_Msk           GTZC_CFGR3_ADC12_Msk
#define GTZC_TZSC1_SECCFGR3_AES_Pos             GTZC_CFGR3_AES_Pos
#define GTZC_TZSC1_SECCFGR3_AES_Msk             GTZC_CFGR3_AES_Msk
#define GTZC_TZSC1_SECCFGR3_HASH_Pos            GTZC_CFGR3_HASH_Pos
#define GTZC_TZSC1_SECCFGR3_HASH_Msk            GTZC_CFGR3_HASH_Msk
#define GTZC_TZSC1_SECCFGR3_RNG_Pos             GTZC_CFGR3_RNG_Pos
#define GTZC_TZSC1_SECCFGR3_RNG_Msk             GTZC_CFGR3_RNG_Msk
#define GTZC_TZSC1_SECCFGR3_PKA_Pos             GTZC_CFGR3_PKA_Pos
#define GTZC_TZSC1_SECCFGR3_PKA_Msk             GTZC_CFGR3_PKA_Msk
#define GTZC_TZSC1_SECCFGR3_SAES_Pos            GTZC_CFGR3_SAES_Pos
#define GTZC_TZSC1_SECCFGR3_SAES_Msk            GTZC_CFGR3_SAES_Msk
#define GTZC_TZSC1_SECCFGR3_CCB_Pos             GTZC_CFGR3_CCB_Pos
#define GTZC_TZSC1_SECCFGR3_CCB_Msk             GTZC_CFGR3_CCB_Msk
#define GTZC_TZSC1_SECCFGR3_SDMMC1_Pos          GTZC_CFGR3_SDMMC1_Pos
#define GTZC_TZSC1_SECCFGR3_SDMMC1_Msk          GTZC_CFGR3_SDMMC1_Msk
#define GTZC_TZSC1_SECCFGR3_OCTOSPI1_REG_Pos    GTZC_CFGR3_OCTOSPI1_REG_Pos
#define GTZC_TZSC1_SECCFGR3_OCTOSPI1_REG_Msk    GTZC_CFGR3_OCTOSPI1_REG_Msk
#define GTZC_TZSC1_SECCFGR3_RAMCFG_Pos          GTZC_CFGR3_RAMCFG_Pos
#define GTZC_TZSC1_SECCFGR3_RAMCFG_Msk          GTZC_CFGR3_RAMCFG_Msk
#define GTZC_TZSC1_SECCFGR3_DAC1_Pos            GTZC_CFGR3_DAC1_Pos
#define GTZC_TZSC1_SECCFGR3_DAC1_Msk            GTZC_CFGR3_DAC1_Msk
#define GTZC_TZSC1_SECCFGR3_ADF1_Pos            GTZC_CFGR3_ADF1_Pos
#define GTZC_TZSC1_SECCFGR3_ADF1_Msk            GTZC_CFGR3_ADF1_Msk

/*******************  Bits definition for GTZC_TZSC1_PRIVCFGR1 register  ***************/
#define GTZC_TZSC1_PRIVCFGR1_TIM2_Pos           GTZC_CFGR1_TIM2_Pos
#define GTZC_TZSC1_PRIVCFGR1_TIM2_Msk           GTZC_CFGR1_TIM2_Msk
#define GTZC_TZSC1_PRIVCFGR1_TIM3_Pos           GTZC_CFGR1_TIM3_Pos
#define GTZC_TZSC1_PRIVCFGR1_TIM3_Msk           GTZC_CFGR1_TIM3_Msk
#define GTZC_TZSC1_PRIVCFGR1_TIM4_Pos           GTZC_CFGR1_TIM4_Pos
#define GTZC_TZSC1_PRIVCFGR1_TIM4_Msk           GTZC_CFGR1_TIM4_Msk
#define GTZC_TZSC1_PRIVCFGR1_TIM5_Pos           GTZC_CFGR1_TIM5_Pos
#define GTZC_TZSC1_PRIVCFGR1_TIM5_Msk           GTZC_CFGR1_TIM5_Msk
#define GTZC_TZSC1_PRIVCFGR1_TIM6_Pos           GTZC_CFGR1_TIM6_Pos
#define GTZC_TZSC1_PRIVCFGR1_TIM6_Msk           GTZC_CFGR1_TIM6_Msk
#define GTZC_TZSC1_PRIVCFGR1_TIM7_Pos           GTZC_CFGR1_TIM7_Pos
#define GTZC_TZSC1_PRIVCFGR1_TIM7_Msk           GTZC_CFGR1_TIM7_Msk
#define GTZC_TZSC1_PRIVCFGR1_WWDG_Pos           GTZC_CFGR1_WWDG_Pos
#define GTZC_TZSC1_PRIVCFGR1_WWDG_Msk           GTZC_CFGR1_WWDG_Msk
#define GTZC_TZSC1_PRIVCFGR1_IWDG_Pos           GTZC_CFGR1_IWDG_Pos
#define GTZC_TZSC1_PRIVCFGR1_IWDG_Msk           GTZC_CFGR1_IWDG_Msk
#define GTZC_TZSC1_PRIVCFGR1_SPI2_Pos           GTZC_CFGR1_SPI2_Pos
#define GTZC_TZSC1_PRIVCFGR1_SPI2_Msk           GTZC_CFGR1_SPI2_Msk
#define GTZC_TZSC1_PRIVCFGR1_USART3_Pos         GTZC_CFGR1_USART3_Pos
#define GTZC_TZSC1_PRIVCFGR1_USART3_Msk         GTZC_CFGR1_USART3_Msk
#define GTZC_TZSC1_PRIVCFGR1_UART4_Pos          GTZC_CFGR1_UART4_Pos
#define GTZC_TZSC1_PRIVCFGR1_UART4_Msk          GTZC_CFGR1_UART4_Msk
#define GTZC_TZSC1_PRIVCFGR1_UART5_Pos          GTZC_CFGR1_UART5_Pos
#define GTZC_TZSC1_PRIVCFGR1_UART5_Msk          GTZC_CFGR1_UART5_Msk
#define GTZC_TZSC1_PRIVCFGR1_I2C1_Pos           GTZC_CFGR1_I2C1_Pos
#define GTZC_TZSC1_PRIVCFGR1_I2C1_Msk           GTZC_CFGR1_I2C1_Msk
#define GTZC_TZSC1_PRIVCFGR1_I2C2_Pos           GTZC_CFGR1_I2C2_Pos
#define GTZC_TZSC1_PRIVCFGR1_I2C2_Msk           GTZC_CFGR1_I2C2_Msk
#define GTZC_TZSC1_PRIVCFGR1_CRS_Pos            GTZC_CFGR1_CRS_Pos
#define GTZC_TZSC1_PRIVCFGR1_CRS_Msk            GTZC_CFGR1_CRS_Msk
#define GTZC_TZSC1_PRIVCFGR1_LPTIM2_Pos         GTZC_CFGR1_LPTIM2_Pos
#define GTZC_TZSC1_PRIVCFGR1_LPTIM2_Msk         GTZC_CFGR1_LPTIM2_Msk
#define GTZC_TZSC1_PRIVCFGR1_FDCAN1_Pos         GTZC_CFGR1_FDCAN1_Pos
#define GTZC_TZSC1_PRIVCFGR1_FDCAN1_Msk         GTZC_CFGR1_FDCAN1_Msk
#define GTZC_TZSC1_PRIVCFGR1_SPI3_Pos           GTZC_CFGR1_SPI3_Pos
#define GTZC_TZSC1_PRIVCFGR1_SPI3_Msk           GTZC_CFGR1_SPI3_Msk
#define GTZC_TZSC1_PRIVCFGR1_I3C1_Pos           GTZC_CFGR1_I3C1_Pos
#define GTZC_TZSC1_PRIVCFGR1_I3C1_Msk           GTZC_CFGR1_I3C1_Msk
#define GTZC_TZSC1_PRIVCFGR1_OPAMP_Pos          GTZC_CFGR1_OPAMP_Pos
#define GTZC_TZSC1_PRIVCFGR1_OPAMP_Msk          GTZC_CFGR1_OPAMP_Msk
#define GTZC_TZSC1_PRIVCFGR1_VREFBUF_Pos        GTZC_CFGR1_VREFBUF_Pos
#define GTZC_TZSC1_PRIVCFGR1_VREFBUF_Msk        GTZC_CFGR1_VREFBUF_Msk

/*******************  Bits definition for GTZC_TZSC1_PRIVCFGR2 register  ***************/
#define GTZC_TZSC1_PRIVCFGR2_TIM1_Pos           GTZC_CFGR2_TIM1_Pos
#define GTZC_TZSC1_PRIVCFGR2_TIM1_Msk           GTZC_CFGR2_TIM1_Msk
#define GTZC_TZSC1_PRIVCFGR2_SPI1_Pos           GTZC_CFGR2_SPI1_Pos
#define GTZC_TZSC1_PRIVCFGR2_SPI1_Msk           GTZC_CFGR2_SPI1_Msk
#define GTZC_TZSC1_PRIVCFGR2_USART1_Pos         GTZC_CFGR2_USART1_Pos
#define GTZC_TZSC1_PRIVCFGR2_USART1_Msk         GTZC_CFGR2_USART1_Msk
#define GTZC_TZSC1_PRIVCFGR2_TIM15_Pos          GTZC_CFGR2_TIM15_Pos
#define GTZC_TZSC1_PRIVCFGR2_TIM15_Msk          GTZC_CFGR2_TIM15_Msk
#define GTZC_TZSC1_PRIVCFGR2_TIM16_Pos          GTZC_CFGR2_TIM16_Pos
#define GTZC_TZSC1_PRIVCFGR2_TIM16_Msk          GTZC_CFGR2_TIM16_Msk
#define GTZC_TZSC1_PRIVCFGR2_TIM17_Pos          GTZC_CFGR2_TIM17_Pos
#define GTZC_TZSC1_PRIVCFGR2_TIM17_Msk          GTZC_CFGR2_TIM17_Msk
#define GTZC_TZSC1_PRIVCFGR2_SAI1_Pos           GTZC_CFGR2_SAI1_Pos
#define GTZC_TZSC1_PRIVCFGR2_SAI1_Msk           GTZC_CFGR2_SAI1_Msk
#define GTZC_TZSC1_PRIVCFGR2_USB_Pos            GTZC_CFGR2_USB_Pos
#define GTZC_TZSC1_PRIVCFGR2_USB_Msk            GTZC_CFGR2_USB_Msk
#define GTZC_TZSC1_PRIVCFGR2_I3C2_Pos           GTZC_CFGR2_I3C2_Pos
#define GTZC_TZSC1_PRIVCFGR2_I3C2_Msk           GTZC_CFGR2_I3C2_Msk
#define GTZC_TZSC1_PRIVCFGR2_LPUART1_Pos        GTZC_CFGR2_LPUART1_Pos
#define GTZC_TZSC1_PRIVCFGR2_LPUART1_Msk        GTZC_CFGR2_LPUART1_Msk
#define GTZC_TZSC1_PRIVCFGR2_I2C3_Pos           GTZC_CFGR2_I2C3_Pos
#define GTZC_TZSC1_PRIVCFGR2_I2C3_Msk           GTZC_CFGR2_I2C3_Msk
#define GTZC_TZSC1_PRIVCFGR2_LPTIM1_Pos         GTZC_CFGR2_LPTIM1_Pos
#define GTZC_TZSC1_PRIVCFGR2_LPTIM1_Msk         GTZC_CFGR2_LPTIM1_Msk
#define GTZC_TZSC1_PRIVCFGR2_LPTIM3_Pos         GTZC_CFGR2_LPTIM3_Pos
#define GTZC_TZSC1_PRIVCFGR2_LPTIM3_Msk         GTZC_CFGR2_LPTIM3_Msk
#define GTZC_TZSC1_PRIVCFGR2_LPTIM4_Pos         GTZC_CFGR2_LPTIM4_Pos
#define GTZC_TZSC1_PRIVCFGR2_LPTIM4_Msk         GTZC_CFGR2_LPTIM4_Msk
#define GTZC_TZSC1_PRIVCFGR2_COMP_Pos           GTZC_CFGR2_COMP_Pos
#define GTZC_TZSC1_PRIVCFGR2_COMP_Msk           GTZC_CFGR2_COMP_Msk

/*******************  Bits definition for GTZC_TZSC1_PRIVCFGR3 register  ***************/
#define GTZC_TZSC1_PRIVCFGR3_CRC_Pos            GTZC_CFGR3_CRC_Pos
#define GTZC_TZSC1_PRIVCFGR3_CRC_Msk            GTZC_CFGR3_CRC_Msk
#define GTZC_TZSC1_PRIVCFGR3_TSC_Pos            GTZC_CFGR3_TSC_Pos
#define GTZC_TZSC1_PRIVCFGR3_TSC_Msk            GTZC_CFGR3_TSC_Msk
#define GTZC_TZSC1_PRIVCFGR3_ICACHE_REG_Pos     GTZC_CFGR3_ICACHE_REG_Pos
#define GTZC_TZSC1_PRIVCFGR3_ICACHE_REG_Msk     GTZC_CFGR3_ICACHE_REG_Msk
#define GTZC_TZSC1_PRIVCFGR3_ADC12_Pos          GTZC_CFGR3_ADC12_Pos
#define GTZC_TZSC1_PRIVCFGR3_ADC12_Msk          GTZC_CFGR3_ADC12_Msk
#define GTZC_TZSC1_PRIVCFGR3_AES_Pos            GTZC_CFGR3_AES_Pos
#define GTZC_TZSC1_PRIVCFGR3_AES_Msk            GTZC_CFGR3_AES_Msk
#define GTZC_TZSC1_PRIVCFGR3_HASH_Pos           GTZC_CFGR3_HASH_Pos
#define GTZC_TZSC1_PRIVCFGR3_HASH_Msk           GTZC_CFGR3_HASH_Msk
#define GTZC_TZSC1_PRIVCFGR3_RNG_Pos            GTZC_CFGR3_RNG_Pos
#define GTZC_TZSC1_PRIVCFGR3_RNG_Msk            GTZC_CFGR3_RNG_Msk
#define GTZC_TZSC1_PRIVCFGR3_PKA_Pos            GTZC_CFGR3_PKA_Pos
#define GTZC_TZSC1_PRIVCFGR3_PKA_Msk            GTZC_CFGR3_PKA_Msk
#define GTZC_TZSC1_PRIVCFGR3_SAES_Pos           GTZC_CFGR3_SAES_Pos
#define GTZC_TZSC1_PRIVCFGR3_SAES_Msk           GTZC_CFGR3_SAES_Msk
#define GTZC_TZSC1_PRIVCFGR3_CCB_Pos            GTZC_CFGR3_CCB_Pos
#define GTZC_TZSC1_PRIVCFGR3_CCB_Msk            GTZC_CFGR3_CCB_Msk
#define GTZC_TZSC1_PRIVCFGR3_SDMMC1_Pos         GTZC_CFGR3_SDMMC1_Pos
#define GTZC_TZSC1_PRIVCFGR3_SDMMC1_Msk         GTZC_CFGR3_SDMMC1_Msk
#define GTZC_TZSC1_PRIVCFGR3_OCTOSPI1_REG_Pos   GTZC_CFGR3_OCTOSPI1_REG_Pos
#define GTZC_TZSC1_PRIVCFGR3_OCTOSPI1_REG_Msk   GTZC_CFGR3_OCTOSPI1_REG_Msk
#define GTZC_TZSC1_PRIVCFGR3_RAMCFG_Pos         GTZC_CFGR3_RAMCFG_Pos
#define GTZC_TZSC1_PRIVCFGR3_RAMCFG_Msk         GTZC_CFGR3_RAMCFG_Msk
#define GTZC_TZSC1_PRIVCFGR3_DAC1_Pos           GTZC_CFGR3_DAC1_Pos
#define GTZC_TZSC1_PRIVCFGR3_DAC1_Msk           GTZC_CFGR3_DAC1_Msk
#define GTZC_TZSC1_PRIVCFGR3_ADF1_Pos           GTZC_CFGR3_ADF1_Pos
#define GTZC_TZSC1_PRIVCFGR3_ADF1_Msk           GTZC_CFGR3_ADF1_Msk

/*******************  Bits definition for GTZC_TZIC1_IER1 register  ***************/
#define GTZC_TZIC1_IER1_TIM2_Pos                GTZC_CFGR1_TIM2_Pos
#define GTZC_TZIC1_IER1_TIM2_Msk                GTZC_CFGR1_TIM2_Msk
#define GTZC_TZIC1_IER1_TIM3_Pos                GTZC_CFGR1_TIM3_Pos
#define GTZC_TZIC1_IER1_TIM3_Msk                GTZC_CFGR1_TIM3_Msk
#define GTZC_TZIC1_IER1_TIM4_Pos                GTZC_CFGR1_TIM4_Pos
#define GTZC_TZIC1_IER1_TIM4_Msk                GTZC_CFGR1_TIM4_Msk
#define GTZC_TZIC1_IER1_TIM5_Pos                GTZC_CFGR1_TIM5_Pos
#define GTZC_TZIC1_IER1_TIM5_Msk                GTZC_CFGR1_TIM5_Msk
#define GTZC_TZIC1_IER1_TIM6_Pos                GTZC_CFGR1_TIM6_Pos
#define GTZC_TZIC1_IER1_TIM6_Msk                GTZC_CFGR1_TIM6_Msk
#define GTZC_TZIC1_IER1_TIM7_Pos                GTZC_CFGR1_TIM7_Pos
#define GTZC_TZIC1_IER1_TIM7_Msk                GTZC_CFGR1_TIM7_Msk
#define GTZC_TZIC1_IER1_WWDG_Pos                GTZC_CFGR1_WWDG_Pos
#define GTZC_TZIC1_IER1_WWDG_Msk                GTZC_CFGR1_WWDG_Msk
#define GTZC_TZIC1_IER1_IWDG_Pos                GTZC_CFGR1_IWDG_Pos
#define GTZC_TZIC1_IER1_IWDG_Msk                GTZC_CFGR1_IWDG_Msk
#define GTZC_TZIC1_IER1_SPI2_Pos                GTZC_CFGR1_SPI2_Pos
#define GTZC_TZIC1_IER1_SPI2_Msk                GTZC_CFGR1_SPI2_Msk
#define GTZC_TZIC1_IER1_USART3_Pos              GTZC_CFGR1_USART3_Pos
#define GTZC_TZIC1_IER1_USART3_Msk              GTZC_CFGR1_USART3_Msk
#define GTZC_TZIC1_IER1_UART4_Pos               GTZC_CFGR1_UART4_Pos
#define GTZC_TZIC1_IER1_UART4_Msk               GTZC_CFGR1_UART4_Msk
#define GTZC_TZIC1_IER1_UART5_Pos               GTZC_CFGR1_UART5_Pos
#define GTZC_TZIC1_IER1_UART5_Msk               GTZC_CFGR1_UART5_Msk
#define GTZC_TZIC1_IER1_I2C1_Pos                GTZC_CFGR1_I2C1_Pos
#define GTZC_TZIC1_IER1_I2C1_Msk                GTZC_CFGR1_I2C1_Msk
#define GTZC_TZIC1_IER1_I2C2_Pos                GTZC_CFGR1_I2C2_Pos
#define GTZC_TZIC1_IER1_I2C2_Msk                GTZC_CFGR1_I2C2_Msk
#define GTZC_TZIC1_IER1_CRS_Pos                 GTZC_CFGR1_CRS_Pos
#define GTZC_TZIC1_IER1_CRS_Msk                 GTZC_CFGR1_CRS_Msk
#define GTZC_TZIC1_IER1_LPTIM2_Pos              GTZC_CFGR1_LPTIM2_Pos
#define GTZC_TZIC1_IER1_LPTIM2_Msk              GTZC_CFGR1_LPTIM2_Msk
#define GTZC_TZIC1_IER1_FDCAN1_Pos              GTZC_CFGR1_FDCAN1_Pos
#define GTZC_TZIC1_IER1_FDCAN1_Msk              GTZC_CFGR1_FDCAN1_Msk
#define GTZC_TZIC1_IER1_SPI3_Pos                GTZC_CFGR1_SPI3_Pos
#define GTZC_TZIC1_IER1_SPI3_Msk                GTZC_CFGR1_SPI3_Msk
#define GTZC_TZIC1_IER1_I3C1_Pos                GTZC_CFGR1_I3C1_Pos
#define GTZC_TZIC1_IER1_I3C1_Msk                GTZC_CFGR1_I3C1_Msk
#define GTZC_TZIC1_IER1_OPAMP_Pos               GTZC_CFGR1_OPAMP_Pos
#define GTZC_TZIC1_IER1_OPAMP_Msk               GTZC_CFGR1_OPAMP_Msk
#define GTZC_TZIC1_IER1_VREFBUF_Pos             GTZC_CFGR1_VREFBUF_Pos
#define GTZC_TZIC1_IER1_VREFBUF_Msk             GTZC_CFGR1_VREFBUF_Msk

/*******************  Bits definition for GTZC_TZIC1_IER2 register  ***************/
#define GTZC_TZIC1_IER2_TIM1_Pos                GTZC_CFGR2_TIM1_Pos
#define GTZC_TZIC1_IER2_TIM1_Msk                GTZC_CFGR2_TIM1_Msk
#define GTZC_TZIC1_IER2_SPI1_Pos                GTZC_CFGR2_SPI1_Pos
#define GTZC_TZIC1_IER2_SPI1_Msk                GTZC_CFGR2_SPI1_Msk
#define GTZC_TZIC1_IER2_USART1_Pos              GTZC_CFGR2_USART1_Pos
#define GTZC_TZIC1_IER2_USART1_Msk              GTZC_CFGR2_USART1_Msk
#define GTZC_TZIC1_IER2_TIM15_Pos               GTZC_CFGR2_TIM15_Pos
#define GTZC_TZIC1_IER2_TIM15_Msk               GTZC_CFGR2_TIM15_Msk
#define GTZC_TZIC1_IER2_TIM16_Pos               GTZC_CFGR2_TIM16_Pos
#define GTZC_TZIC1_IER2_TIM16_Msk               GTZC_CFGR2_TIM16_Msk
#define GTZC_TZIC1_IER2_TIM17_Pos               GTZC_CFGR2_TIM17_Pos
#define GTZC_TZIC1_IER2_TIM17_Msk               GTZC_CFGR2_TIM17_Msk
#define GTZC_TZIC1_IER2_SAI1_Pos                GTZC_CFGR2_SAI1_Pos
#define GTZC_TZIC1_IER2_SAI1_Msk                GTZC_CFGR2_SAI1_Msk
#define GTZC_TZIC1_IER2_USB_Pos                 GTZC_CFGR2_USB_Pos
#define GTZC_TZIC1_IER2_USB_Msk                 GTZC_CFGR2_USB_Msk
#define GTZC_TZIC1_IER2_I3C2_Pos                GTZC_CFGR2_I3C2_Pos
#define GTZC_TZIC1_IER2_I3C2_Msk                GTZC_CFGR2_I3C2_Msk
#define GTZC_TZIC1_IER2_LPUART1_Pos             GTZC_CFGR2_LPUART1_Pos
#define GTZC_TZIC1_IER2_LPUART1_Msk             GTZC_CFGR2_LPUART1_Msk
#define GTZC_TZIC1_IER2_I2C3_Pos                GTZC_CFGR2_I2C3_Pos
#define GTZC_TZIC1_IER2_I2C3_Msk                GTZC_CFGR2_I2C3_Msk
#define GTZC_TZIC1_IER2_LPTIM1_Pos              GTZC_CFGR2_LPTIM1_Pos
#define GTZC_TZIC1_IER2_LPTIM1_Msk              GTZC_CFGR2_LPTIM1_Msk
#define GTZC_TZIC1_IER2_LPTIM3_Pos              GTZC_CFGR2_LPTIM3_Pos
#define GTZC_TZIC1_IER2_LPTIM3_Msk              GTZC_CFGR2_LPTIM3_Msk
#define GTZC_TZIC1_IER2_LPTIM4_Pos              GTZC_CFGR2_LPTIM4_Pos
#define GTZC_TZIC1_IER2_LPTIM4_Msk              GTZC_CFGR2_LPTIM4_Msk
#define GTZC_TZIC1_IER2_COMP_Pos                GTZC_CFGR2_COMP_Pos
#define GTZC_TZIC1_IER2_COMP_Msk                GTZC_CFGR2_COMP_Msk

/*******************  Bits definition for GTZC_TZIC1_IER3 register  ***************/
#define GTZC_TZIC1_IER3_CRC_Pos                 GTZC_CFGR3_CRC_Pos
#define GTZC_TZIC1_IER3_CRC_Msk                 GTZC_CFGR3_CRC_Msk
#define GTZC_TZIC1_IER3_TSC_Pos                 GTZC_CFGR3_TSC_Pos
#define GTZC_TZIC1_IER3_TSC_Msk                 GTZC_CFGR3_TSC_Msk
#define GTZC_TZIC1_IER3_ICACHE_REG_Pos          GTZC_CFGR3_ICACHE_REG_Pos
#define GTZC_TZIC1_IER3_ICACHE_REG_Msk          GTZC_CFGR3_ICACHE_REG_Msk
#define GTZC_TZIC1_IER3_ADC12_Pos               GTZC_CFGR3_ADC12_Pos
#define GTZC_TZIC1_IER3_ADC12_Msk               GTZC_CFGR3_ADC12_Msk
#define GTZC_TZIC1_IER3_AES_Pos                 GTZC_CFGR3_AES_Pos
#define GTZC_TZIC1_IER3_AES_Msk                 GTZC_CFGR3_AES_Msk
#define GTZC_TZIC1_IER3_HASH_Pos                GTZC_CFGR3_HASH_Pos
#define GTZC_TZIC1_IER3_HASH_Msk                GTZC_CFGR3_HASH_Msk
#define GTZC_TZIC1_IER3_RNG_Pos                 GTZC_CFGR3_RNG_Pos
#define GTZC_TZIC1_IER3_RNG_Msk                 GTZC_CFGR3_RNG_Msk
#define GTZC_TZIC1_IER3_PKA_Pos                 GTZC_CFGR3_PKA_Pos
#define GTZC_TZIC1_IER3_PKA_Msk                 GTZC_CFGR3_PKA_Msk
#define GTZC_TZIC1_IER3_SAES_Pos                GTZC_CFGR3_SAES_Pos
#define GTZC_TZIC1_IER3_SAES_Msk                GTZC_CFGR3_SAES_Msk
#define GTZC_TZIC1_IER3_CCB_Pos                 GTZC_CFGR3_CCB_Pos
#define GTZC_TZIC1_IER3_CCB_Msk                 GTZC_CFGR3_CCB_Msk
#define GTZC_TZIC1_IER3_SDMMC1_Pos              GTZC_CFGR3_SDMMC1_Pos
#define GTZC_TZIC1_IER3_SDMMC1_Msk              GTZC_CFGR3_SDMMC1_Msk
#define GTZC_TZIC1_IER3_OCTOSPI1_REG_Pos        GTZC_CFGR3_OCTOSPI1_REG_Pos
#define GTZC_TZIC1_IER3_OCTOSPI1_REG_Msk        GTZC_CFGR3_OCTOSPI1_REG_Msk
#define GTZC_TZIC1_IER3_RAMCFG_Pos              GTZC_CFGR3_RAMCFG_Pos
#define GTZC_TZIC1_IER3_RAMCFG_Msk              GTZC_CFGR3_RAMCFG_Msk
#define GTZC_TZIC1_IER3_DAC1_Pos                GTZC_CFGR3_DAC1_Pos
#define GTZC_TZIC1_IER3_DAC1_Msk                GTZC_CFGR3_DAC1_Msk
#define GTZC_TZIC1_IER3_ADF1_Pos                GTZC_CFGR3_ADF1_Pos
#define GTZC_TZIC1_IER3_ADF1_Msk                GTZC_CFGR3_ADF1_Msk

/*******************  Bits definition for GTZC_TZIC1_IER4 register  ***************/
#define GTZC_TZIC1_IER4_GPDMA1_Pos              GTZC_CFGR4_GPDMA1_Pos
#define GTZC_TZIC1_IER4_GPDMA1_Msk              GTZC_CFGR4_GPDMA1_Msk
#define GTZC_TZIC1_IER4_FLASH_REG_Pos           GTZC_CFGR4_FLASH_REG_Pos
#define GTZC_TZIC1_IER4_FLASH_REG_Msk           GTZC_CFGR4_FLASH_REG_Msk
#define GTZC_TZIC1_IER4_FLASH_Pos               GTZC_CFGR4_FLASH_Pos
#define GTZC_TZIC1_IER4_FLASH_Msk               GTZC_CFGR4_FLASH_Msk
#define GTZC_TZIC1_IER4_PWR_Pos                 GTZC_CFGR4_PWR_Pos
#define GTZC_TZIC1_IER4_PWR_Msk                 GTZC_CFGR4_PWR_Msk
#define GTZC_TZIC1_IER4_RCC_Pos                 GTZC_CFGR4_RCC_Pos
#define GTZC_TZIC1_IER4_RCC_Msk                 GTZC_CFGR4_RCC_Msk
#define GTZC_TZIC1_IER4_SYSCFG_Pos              GTZC_CFGR4_SYSCFG_Pos
#define GTZC_TZIC1_IER4_SYSCFG_Msk              GTZC_CFGR4_SYSCFG_Msk
#define GTZC_TZIC1_IER4_EXTI_Pos                GTZC_CFGR4_EXTI_Pos
#define GTZC_TZIC1_IER4_EXTI_Msk                GTZC_CFGR4_EXTI_Msk
#define GTZC_TZIC1_IER4_RTC_Pos                 GTZC_CFGR4_RTC_Pos
#define GTZC_TZIC1_IER4_RTC_Msk                 GTZC_CFGR4_RTC_Msk
#define GTZC_TZIC1_IER4_TAMP_Pos                GTZC_CFGR4_TAMP_Pos
#define GTZC_TZIC1_IER4_TAMP_Msk                GTZC_CFGR4_TAMP_Msk
#define GTZC_TZIC1_IER4_TZSC_Pos                GTZC_CFGR4_TZSC_Pos
#define GTZC_TZIC1_IER4_TZSC_Msk                GTZC_CFGR4_TZSC_Msk
#define GTZC_TZIC1_IER4_TZIC_Pos                GTZC_CFGR4_TZIC_Pos
#define GTZC_TZIC1_IER4_TZIC_Msk                GTZC_CFGR4_TZIC_Msk
#define GTZC_TZIC1_IER4_SRAM1_Pos               GTZC_CFGR4_SRAM1_Pos
#define GTZC_TZIC1_IER4_SRAM1_Msk               GTZC_CFGR4_SRAM1_Msk
#define GTZC_TZIC1_IER4_MPCBB1_REG_Pos          GTZC_CFGR4_MPCBB1_REG_Pos
#define GTZC_TZIC1_IER4_MPCBB1_REG_Msk          GTZC_CFGR4_MPCBB1_REG_Msk
#define GTZC_TZIC1_IER4_SRAM2_Pos               GTZC_CFGR4_SRAM2_Pos
#define GTZC_TZIC1_IER4_SRAM2_Msk               GTZC_CFGR4_SRAM2_Msk
#define GTZC_TZIC1_IER4_MPCBB2_REG_Pos          GTZC_CFGR4_MPCBB2_REG_Pos
#define GTZC_TZIC1_IER4_MPCBB2_REG_Msk          GTZC_CFGR4_MPCBB2_REG_Msk

/*******************  Bits definition for GTZC_TZIC1_SR1 register  ***************/
#define GTZC_TZIC1_SR1_TIM2_Pos                 GTZC_CFGR1_TIM2_Pos
#define GTZC_TZIC1_SR1_TIM2_Msk                 GTZC_CFGR1_TIM2_Msk
#define GTZC_TZIC1_SR1_TIM3_Pos                 GTZC_CFGR1_TIM3_Pos
#define GTZC_TZIC1_SR1_TIM3_Msk                 GTZC_CFGR1_TIM3_Msk
#define GTZC_TZIC1_SR1_TIM4_Pos                 GTZC_CFGR1_TIM4_Pos
#define GTZC_TZIC1_SR1_TIM4_Msk                 GTZC_CFGR1_TIM4_Msk
#define GTZC_TZIC1_SR1_TIM5_Pos                 GTZC_CFGR1_TIM5_Pos
#define GTZC_TZIC1_SR1_TIM5_Msk                 GTZC_CFGR1_TIM5_Msk
#define GTZC_TZIC1_SR1_TIM6_Pos                 GTZC_CFGR1_TIM6_Pos
#define GTZC_TZIC1_SR1_TIM6_Msk                 GTZC_CFGR1_TIM6_Msk
#define GTZC_TZIC1_SR1_TIM7_Pos                 GTZC_CFGR1_TIM7_Pos
#define GTZC_TZIC1_SR1_TIM7_Msk                 GTZC_CFGR1_TIM7_Msk
#define GTZC_TZIC1_SR1_WWDG_Pos                 GTZC_CFGR1_WWDG_Pos
#define GTZC_TZIC1_SR1_WWDG_Msk                 GTZC_CFGR1_WWDG_Msk
#define GTZC_TZIC1_SR1_IWDG_Pos                 GTZC_CFGR1_IWDG_Pos
#define GTZC_TZIC1_SR1_IWDG_Msk                 GTZC_CFGR1_IWDG_Msk
#define GTZC_TZIC1_SR1_SPI2_Pos                 GTZC_CFGR1_SPI2_Pos
#define GTZC_TZIC1_SR1_SPI2_Msk                 GTZC_CFGR1_SPI2_Msk
#define GTZC_TZIC1_SR1_USART3_Pos               GTZC_CFGR1_USART3_Pos
#define GTZC_TZIC1_SR1_USART3_Msk               GTZC_CFGR1_USART3_Msk
#define GTZC_TZIC1_SR1_UART4_Pos                GTZC_CFGR1_UART4_Pos
#define GTZC_TZIC1_SR1_UART4_Msk                GTZC_CFGR1_UART4_Msk
#define GTZC_TZIC1_SR1_UART5_Pos                GTZC_CFGR1_UART5_Pos
#define GTZC_TZIC1_SR1_UART5_Msk                GTZC_CFGR1_UART5_Msk
#define GTZC_TZIC1_SR1_I2C1_Pos                 GTZC_CFGR1_I2C1_Pos
#define GTZC_TZIC1_SR1_I2C1_Msk                 GTZC_CFGR1_I2C1_Msk
#define GTZC_TZIC1_SR1_I2C2_Pos                 GTZC_CFGR1_I2C2_Pos
#define GTZC_TZIC1_SR1_I2C2_Msk                 GTZC_CFGR1_I2C2_Msk
#define GTZC_TZIC1_SR1_CRS_Pos                  GTZC_CFGR1_CRS_Pos
#define GTZC_TZIC1_SR1_CRS_Msk                  GTZC_CFGR1_CRS_Msk
#define GTZC_TZIC1_SR1_LPTIM2_Pos               GTZC_CFGR1_LPTIM2_Pos
#define GTZC_TZIC1_SR1_LPTIM2_Msk               GTZC_CFGR1_LPTIM2_Msk
#define GTZC_TZIC1_SR1_FDCAN1_Pos               GTZC_CFGR1_FDCAN1_Pos
#define GTZC_TZIC1_SR1_FDCAN1_Msk               GTZC_CFGR1_FDCAN1_Msk
#define GTZC_TZIC1_SR1_SPI3_Pos                 GTZC_CFGR1_SPI3_Pos
#define GTZC_TZIC1_SR1_SPI3_Msk                 GTZC_CFGR1_SPI3_Msk
#define GTZC_TZIC1_SR1_I3C1_Pos                 GTZC_CFGR1_I3C1_Pos
#define GTZC_TZIC1_SR1_I3C1_Msk                 GTZC_CFGR1_I3C1_Msk
#define GTZC_TZIC1_SR1_OPAMP_Pos                GTZC_CFGR1_OPAMP_Pos
#define GTZC_TZIC1_SR1_OPAMP_Msk                GTZC_CFGR1_OPAMP_Msk
#define GTZC_TZIC1_SR1_VREFBUF_Pos              GTZC_CFGR1_VREFBUF_Pos
#define GTZC_TZIC1_SR1_VREFBUF_Msk              GTZC_CFGR1_VREFBUF_Msk

/*******************  Bits definition for GTZC_TZIC1_SR2 register  ***************/
#define GTZC_TZIC1_SR2_TIM1_Pos                 GTZC_CFGR2_TIM1_Pos
#define GTZC_TZIC1_SR2_TIM1_Msk                 GTZC_CFGR2_TIM1_Msk
#define GTZC_TZIC1_SR2_SPI1_Pos                 GTZC_CFGR2_SPI1_Pos
#define GTZC_TZIC1_SR2_SPI1_Msk
#define GTZC_TZIC1_SR2_USART1_Pos               GTZC_CFGR2_USART1_Pos
#define GTZC_TZIC1_SR2_USART1_Msk               GTZC_CFGR2_USART1_Msk
#define GTZC_TZIC1_SR2_TIM15_Pos                GTZC_CFGR2_TIM15_Pos
#define GTZC_TZIC1_SR2_TIM15_Msk                GTZC_CFGR2_TIM15_Msk
#define GTZC_TZIC1_SR2_TIM16_Pos                GTZC_CFGR2_TIM16_Pos
#define GTZC_TZIC1_SR2_TIM16_Msk                GTZC_CFGR2_TIM16_Msk
#define GTZC_TZIC1_SR2_TIM17_Pos                GTZC_CFGR2_TIM17_Pos
#define GTZC_TZIC1_SR2_TIM17_Msk                GTZC_CFGR2_TIM17_Msk
#define GTZC_TZIC1_SR2_SAI1_Pos                 GTZC_CFGR2_SAI1_Pos
#define GTZC_TZIC1_SR2_SAI1_Msk                 GTZC_CFGR2_SAI1_Msk
#define GTZC_TZIC1_SR2_USB_Pos                  GTZC_CFGR2_USB_Pos
#define GTZC_TZIC1_SR2_USB_Msk                  GTZC_CFGR2_USB_Msk
#define GTZC_TZIC1_SR2_I3C2_Pos                 GTZC_CFGR2_I3C2_Pos
#define GTZC_TZIC1_SR2_I3C2_Msk                 GTZC_CFGR2_I3C2_Msk
#define GTZC_TZIC1_SR2_LPUART1_Pos              GTZC_CFGR2_LPUART1_Pos
#define GTZC_TZIC1_SR2_LPUART1_Msk              GTZC_CFGR2_LPUART1_Msk
#define GTZC_TZIC1_SR2_I2C3_Pos                 GTZC_CFGR2_I2C3_Pos
#define GTZC_TZIC1_SR2_I2C3_Msk                 GTZC_CFGR2_I2C3_Msk
#define GTZC_TZIC1_SR2_LPTIM1_Pos               GTZC_CFGR2_LPTIM1_Pos
#define GTZC_TZIC1_SR2_LPTIM1_Msk               GTZC_CFGR2_LPTIM1_Msk
#define GTZC_TZIC1_SR2_LPTIM3_Pos               GTZC_CFGR2_LPTIM3_Pos
#define GTZC_TZIC1_SR2_LPTIM3_Msk               GTZC_CFGR2_LPTIM3_Msk
#define GTZC_TZIC1_SR2_LPTIM4_Pos               GTZC_CFGR2_LPTIM4_Pos
#define GTZC_TZIC1_SR2_LPTIM4_Msk               GTZC_CFGR2_LPTIM4_Msk
#define GTZC_TZIC1_SR2_COMP_Pos                 GTZC_CFGR2_COMP_Pos
#define GTZC_TZIC1_SR2_COMP_Msk                 GTZC_CFGR2_COMP_Msk

/*******************  Bits definition for GTZC_TZIC1_SR3 register  ***************/
#define GTZC_TZIC1_SR3_CRC_Pos                  GTZC_CFGR3_CRC_Pos
#define GTZC_TZIC1_SR3_CRC_Msk                  GTZC_CFGR3_CRC_Msk
#define GTZC_TZIC1_SR3_TSC_Pos                  GTZC_CFGR3_TSC_Pos
#define GTZC_TZIC1_SR3_TSC_Msk                  GTZC_CFGR3_TSC_Msk
#define GTZC_TZIC1_SR3_ICACHE_REG_Pos           GTZC_CFGR3_ICACHE_REG_Pos
#define GTZC_TZIC1_SR3_ICACHE_REG_Msk           GTZC_CFGR3_ICACHE_REG_Msk
#define GTZC_TZIC1_SR3_ADC12_Pos                GTZC_CFGR3_ADC12_Pos
#define GTZC_TZIC1_SR3_ADC12_Msk                GTZC_CFGR3_ADC12_Msk
#define GTZC_TZIC1_SR3_AES_Pos                  GTZC_CFGR3_AES_Pos
#define GTZC_TZIC1_SR3_AES_Msk                  GTZC_CFGR3_AES_Msk
#define GTZC_TZIC1_SR3_HASH_Pos                 GTZC_CFGR3_HASH_Pos
#define GTZC_TZIC1_SR3_HASH_Msk                 GTZC_CFGR3_HASH_Msk
#define GTZC_TZIC1_SR3_RNG_Pos                  GTZC_CFGR3_RNG_Pos
#define GTZC_TZIC1_SR3_RNG_Msk                  GTZC_CFGR3_RNG_Msk
#define GTZC_TZIC1_SR3_PKA_Pos                  GTZC_CFGR3_PKA_Pos
#define GTZC_TZIC1_SR3_PKA_Msk                  GTZC_CFGR3_PKA_Msk
#define GTZC_TZIC1_SR3_SAES_Pos                 GTZC_CFGR3_SAES_Pos
#define GTZC_TZIC1_SR3_SAES_Msk                 GTZC_CFGR3_SAES_Msk
#define GTZC_TZIC1_SR3_CCB_Pos                  GTZC_CFGR3_CCB_Pos
#define GTZC_TZIC1_SR3_CCB_Msk                  GTZC_CFGR3_CCB_Msk
#define GTZC_TZIC1_SR3_SDMMC1_Pos               GTZC_CFGR3_SDMMC1_Pos
#define GTZC_TZIC1_SR3_SDMMC1_Msk               GTZC_CFGR3_SDMMC1_Msk
#define GTZC_TZIC1_SR3_OCTOSPI1_REG_Pos         GTZC_CFGR3_OCTOSPI1_REG_Pos
#define GTZC_TZIC1_SR3_OCTOSPI1_REG_Msk         GTZC_CFGR3_OCTOSPI1_REG_Msk
#define GTZC_TZIC1_SR3_RAMCFG_Pos               GTZC_CFGR3_RAMCFG_Pos
#define GTZC_TZIC1_SR3_RAMCFG_Msk               GTZC_CFGR3_RAMCFG_Msk
#define GTZC_TZIC1_SR3_DAC1_Pos                 GTZC_CFGR3_DAC1_Pos
#define GTZC_TZIC1_SR3_DAC1_Msk                 GTZC_CFGR3_DAC1_Msk
#define GTZC_TZIC1_SR3_ADF1_Pos                 GTZC_CFGR3_ADF1_Pos
#define GTZC_TZIC1_SR3_ADF1_Msk                 GTZC_CFGR3_ADF1_Msk

/*******************  Bits definition for GTZC_TZIC1_SR4 register  ***************/
#define GTZC_TZIC1_SR4_GPDMA1_Pos               GTZC_CFGR4_GPDMA1_Pos
#define GTZC_TZIC1_SR4_GPDMA1_Msk               GTZC_CFGR4_GPDMA1_Msk
#define GTZC_TZIC1_SR4_FLASH_REG_Pos            GTZC_CFGR4_FLASH_REG_Pos
#define GTZC_TZIC1_SR4_FLASH_REG_Msk            GTZC_CFGR4_FLASH_REG_Msk
#define GTZC_TZIC1_SR4_FLASH_Pos                GTZC_CFGR4_FLASH_Pos
#define GTZC_TZIC1_SR4_FLASH_Msk                GTZC_CFGR4_FLASH_Msk
#define GTZC_TZIC1_SR4_PWR_Pos                  GTZC_CFGR4_PWR_Pos
#define GTZC_TZIC1_SR4_PWR_Msk                  GTZC_CFGR4_PWR_Msk
#define GTZC_TZIC1_SR4_RCC_Pos                  GTZC_CFGR4_RCC_Pos
#define GTZC_TZIC1_SR4_RCC_Msk                  GTZC_CFGR4_RCC_Msk
#define GTZC_TZIC1_SR4_SYSCFG_Pos               GTZC_CFGR4_SYSCFG_Pos
#define GTZC_TZIC1_SR4_SYSCFG_Msk               GTZC_CFGR4_SYSCFG_Msk
#define GTZC_TZIC1_SR4_EXTI_Pos                 GTZC_CFGR4_EXTI_Pos
#define GTZC_TZIC1_SR4_EXTI_Msk                 GTZC_CFGR4_EXTI_Msk
#define GTZC_TZIC1_SR4_RTC_Pos                  GTZC_CFGR4_RTC_Pos
#define GTZC_TZIC1_SR4_RTC_Msk                  GTZC_CFGR4_RTC_Msk
#define GTZC_TZIC1_SR4_TAMP_Pos                 GTZC_CFGR4_TAMP_Pos
#define GTZC_TZIC1_SR4_TAMP_Msk                 GTZC_CFGR4_TAMP_Msk
#define GTZC_TZIC1_SR4_TZSC_Pos                 GTZC_CFGR4_TZSC_Pos
#define GTZC_TZIC1_SR4_TZSC_Msk                 GTZC_CFGR4_TZSC_Msk
#define GTZC_TZIC1_SR4_TZIC_Pos                 GTZC_CFGR4_TZIC_Pos
#define GTZC_TZIC1_SR4_TZIC_Msk                 GTZC_CFGR4_TZIC_Msk
#define GTZC_TZIC1_SR4_SRAM1_Pos                GTZC_CFGR4_SRAM1_Pos
#define GTZC_TZIC1_SR4_SRAM1_Msk                GTZC_CFGR4_SRAM1_Msk
#define GTZC_TZIC1_SR4_MPCBB1_REG_Pos           GTZC_CFGR4_MPCBB1_REG_Pos
#define GTZC_TZIC1_SR4_MPCBB1_REG_Msk           GTZC_CFGR4_MPCBB1_REG_Msk
#define GTZC_TZIC1_SR4_SRAM2_Pos                GTZC_CFGR4_SRAM2_Pos
#define GTZC_TZIC1_SR4_SRAM2_Msk                GTZC_CFGR4_SRAM2_Msk
#define GTZC_TZIC1_SR4_MPCBB2_REG_Pos           GTZC_CFGR4_MPCBB2_REG_Pos
#define GTZC_TZIC1_SR4_MPCBB2_REG_Msk           GTZC_CFGR4_MPCBB2_REG_Msk

/******************  Bits definition for GTZC_TZIC1_FCR1 register  ***************/
#define GTZC_TZIC1_FCR1_TIM2_Pos                GTZC_CFGR1_TIM2_Pos
#define GTZC_TZIC1_FCR1_TIM2_Msk                GTZC_CFGR1_TIM2_Msk
#define GTZC_TZIC1_FCR1_TIM3_Pos                GTZC_CFGR1_TIM3_Pos
#define GTZC_TZIC1_FCR1_TIM3_Msk                GTZC_CFGR1_TIM3_Msk
#define GTZC_TZIC1_FCR1_TIM4_Pos                GTZC_CFGR1_TIM4_Pos
#define GTZC_TZIC1_FCR1_TIM4_Msk                GTZC_CFGR1_TIM4_Msk
#define GTZC_TZIC1_FCR1_TIM5_Pos                GTZC_CFGR1_TIM5_Pos
#define GTZC_TZIC1_FCR1_TIM5_Msk                GTZC_CFGR1_TIM5_Msk
#define GTZC_TZIC1_FCR1_TIM6_Pos                GTZC_CFGR1_TIM6_Pos
#define GTZC_TZIC1_FCR1_TIM6_Msk                GTZC_CFGR1_TIM6_Msk
#define GTZC_TZIC1_FCR1_TIM7_Pos                GTZC_CFGR1_TIM7_Pos
#define GTZC_TZIC1_FCR1_TIM7_Msk                GTZC_CFGR1_TIM7_Msk
#define GTZC_TZIC1_FCR1_WWDG_Pos                GTZC_CFGR1_WWDG_Pos
#define GTZC_TZIC1_FCR1_WWDG_Msk                GTZC_CFGR1_WWDG_Msk
#define GTZC_TZIC1_FCR1_IWDG_Pos                GTZC_CFGR1_IWDG_Pos
#define GTZC_TZIC1_FCR1_IWDG_Msk                GTZC_CFGR1_IWDG_Msk
#define GTZC_TZIC1_FCR1_SPI2_Pos                GTZC_CFGR1_SPI2_Pos
#define GTZC_TZIC1_FCR1_SPI2_Msk                GTZC_CFGR1_SPI2_Msk
#define GTZC_TZIC1_FCR1_USART3_Pos              GTZC_CFGR1_USART3_Pos
#define GTZC_TZIC1_FCR1_USART3_Msk              GTZC_CFGR1_USART3_Msk
#define GTZC_TZIC1_FCR1_UART4_Pos               GTZC_CFGR1_UART4_Pos
#define GTZC_TZIC1_FCR1_UART4_Msk               GTZC_CFGR1_UART4_Msk
#define GTZC_TZIC1_FCR1_UART5_Pos               GTZC_CFGR1_UART5_Pos
#define GTZC_TZIC1_FCR1_UART5_Msk               GTZC_CFGR1_UART5_Msk
#define GTZC_TZIC1_FCR1_I2C1_Pos                GTZC_CFGR1_I2C1_Pos
#define GTZC_TZIC1_FCR1_I2C1_Msk                GTZC_CFGR1_I2C1_Msk
#define GTZC_TZIC1_FCR1_I2C2_Pos                GTZC_CFGR1_I2C2_Pos
#define GTZC_TZIC1_FCR1_I2C2_Msk                GTZC_CFGR1_I2C2_Msk
#define GTZC_TZIC1_FCR1_CRS_Pos                 GTZC_CFGR1_CRS_Pos
#define GTZC_TZIC1_FCR1_CRS_Msk                 GTZC_CFGR1_CRS_Msk
#define GTZC_TZIC1_FCR1_LPTIM2_Pos              GTZC_CFGR1_LPTIM2_Pos
#define GTZC_TZIC1_FCR1_LPTIM2_Msk              GTZC_CFGR1_LPTIM2_Msk
#define GTZC_TZIC1_FCR1_FDCAN1_Pos              GTZC_CFGR1_FDCAN1_Pos
#define GTZC_TZIC1_FCR1_FDCAN1_Msk              GTZC_CFGR1_FDCAN1_Msk
#define GTZC_TZIC1_FCR1_SPI3_Pos                GTZC_CFGR1_SPI3_Pos
#define GTZC_TZIC1_FCR1_SPI3_Msk                GTZC_CFGR1_SPI3_Msk
#define GTZC_TZIC1_FCR1_I3C1_Pos                GTZC_CFGR1_I3C1_Pos
#define GTZC_TZIC1_FCR1_I3C1_Msk                GTZC_CFGR1_I3C1_Msk
#define GTZC_TZIC1_FCR1_OPAMP_Pos               GTZC_CFGR1_OPAMP_Pos
#define GTZC_TZIC1_FCR1_OPAMP_Msk               GTZC_CFGR1_OPAMP_Msk
#define GTZC_TZIC1_FCR1_VREFBUF_Pos             GTZC_CFGR1_VREFBUF_Pos
#define GTZC_TZIC1_FCR1_VREFBUF_Msk             GTZC_CFGR1_VREFBUF_Msk

/******************  Bits definition for GTZC_TZIC1_FCR2 register  ***************/
#define GTZC_TZIC1_FCR2_TIM1_Pos                GTZC_CFGR2_TIM1_Pos
#define GTZC_TZIC1_FCR2_TIM1_Msk                GTZC_CFGR2_TIM1_Msk
#define GTZC_TZIC1_FCR2_SPI1_Pos                GTZC_CFGR2_SPI1_Pos
#define GTZC_TZIC1_FCR2_SPI1_Msk                GTZC_CFGR2_SPI1_Msk
#define GTZC_TZIC1_FCR2_USART1_Pos              GTZC_CFGR2_USART1_Pos
#define GTZC_TZIC1_FCR2_USART1_Msk              GTZC_CFGR2_USART1_Msk
#define GTZC_TZIC1_FCR2_TIM15_Pos               GTZC_CFGR2_TIM15_Pos
#define GTZC_TZIC1_FCR2_TIM15_Msk               GTZC_CFGR2_TIM15_Msk
#define GTZC_TZIC1_FCR2_TIM16_Pos               GTZC_CFGR2_TIM16_Pos
#define GTZC_TZIC1_FCR2_TIM16_Msk               GTZC_CFGR2_TIM16_Msk
#define GTZC_TZIC1_FCR2_TIM17_Pos               GTZC_CFGR2_TIM17_Pos
#define GTZC_TZIC1_FCR2_TIM17_Msk               GTZC_CFGR2_TIM17_Msk
#define GTZC_TZIC1_FCR2_SAI1_Pos                GTZC_CFGR2_SAI1_Pos
#define GTZC_TZIC1_FCR2_SAI1_Msk                GTZC_CFGR2_SAI1_Msk
#define GTZC_TZIC1_FCR2_USB_Pos                 GTZC_CFGR2_USB_Pos
#define GTZC_TZIC1_FCR2_USB_Msk                 GTZC_CFGR2_USB_Msk
#define GTZC_TZIC1_FCR2_I3C2_Pos                GTZC_CFGR2_I3C2_Pos
#define GTZC_TZIC1_FCR2_I3C2_Msk                GTZC_CFGR2_I3C2_Msk
#define GTZC_TZIC1_FCR2_LPUART1_Pos             GTZC_CFGR2_LPUART1_Pos
#define GTZC_TZIC1_FCR2_LPUART1_Msk             GTZC_CFGR2_LPUART1_Msk
#define GTZC_TZIC1_FCR2_I2C3_Pos                GTZC_CFGR2_I2C3_Pos
#define GTZC_TZIC1_FCR2_I2C3_Msk                GTZC_CFGR2_I2C3_Msk
#define GTZC_TZIC1_FCR2_LPTIM1_Pos              GTZC_CFGR2_LPTIM1_Pos
#define GTZC_TZIC1_FCR2_LPTIM1_Msk              GTZC_CFGR2_LPTIM1_Msk
#define GTZC_TZIC1_FCR2_LPTIM3_Pos              GTZC_CFGR2_LPTIM3_Pos
#define GTZC_TZIC1_FCR2_LPTIM3_Msk              GTZC_CFGR2_LPTIM3_Msk
#define GTZC_TZIC1_FCR2_LPTIM4_Pos              GTZC_CFGR2_LPTIM4_Pos
#define GTZC_TZIC1_FCR2_LPTIM4_Msk              GTZC_CFGR2_LPTIM4_Msk
#define GTZC_TZIC1_FCR2_COMP_Pos                GTZC_CFGR2_COMP_Pos
#define GTZC_TZIC1_FCR2_COMP_Msk                GTZC_CFGR2_COMP_Msk

/******************  Bits definition for GTZC_TZIC1_FCR3 register  ***************/
#define GTZC_TZIC1_FCR3_CRC_Pos                 GTZC_CFGR3_CRC_Pos
#define GTZC_TZIC1_FCR3_CRC_Msk                 GTZC_CFGR3_CRC_Msk
#define GTZC_TZIC1_FCR3_TSC_Pos                 GTZC_CFGR3_TSC_Pos
#define GTZC_TZIC1_FCR3_TSC_Msk                 GTZC_CFGR3_TSC_Msk
#define GTZC_TZIC1_FCR3_ICACHE_REG_Pos          GTZC_CFGR3_ICACHE_REG_Pos
#define GTZC_TZIC1_FCR3_ICACHE_REG_Msk          GTZC_CFGR3_ICACHE_REG_Msk
#define GTZC_TZIC1_FCR3_ADC12_Pos               GTZC_CFGR3_ADC12_Pos
#define GTZC_TZIC1_FCR3_ADC12_Msk               GTZC_CFGR3_ADC12_Msk
#define GTZC_TZIC1_FCR3_AES_Pos                 GTZC_CFGR3_AES_Pos
#define GTZC_TZIC1_FCR3_AES_Msk                 GTZC_CFGR3_AES_Msk
#define GTZC_TZIC1_FCR3_HASH_Pos                GTZC_CFGR3_HASH_Pos
#define GTZC_TZIC1_FCR3_HASH_Msk                GTZC_CFGR3_HASH_Msk
#define GTZC_TZIC1_FCR3_RNG_Pos                 GTZC_CFGR3_RNG_Pos
#define GTZC_TZIC1_FCR3_RNG_Msk                 GTZC_CFGR3_RNG_Msk
#define GTZC_TZIC1_FCR3_PKA_Pos                 GTZC_CFGR3_PKA_Pos
#define GTZC_TZIC1_FCR3_PKA_Msk                 GTZC_CFGR3_PKA_Msk
#define GTZC_TZIC1_FCR3_SAES_Pos                GTZC_CFGR3_SAES_Pos
#define GTZC_TZIC1_FCR3_SAES_Msk                GTZC_CFGR3_SAES_Msk
#define GTZC_TZIC1_FCR3_CCB_Pos                 GTZC_CFGR3_CCB_Pos
#define GTZC_TZIC1_FCR3_CCB_Msk                 GTZC_CFGR3_CCB_Msk
#define GTZC_TZIC1_FCR3_SDMMC1_Pos              GTZC_CFGR3_SDMMC1_Pos
#define GTZC_TZIC1_FCR3_SDMMC1_Msk              GTZC_CFGR3_SDMMC1_Msk
#define GTZC_TZIC1_FCR3_OCTOSPI1_REG_Pos        GTZC_CFGR3_OCTOSPI1_REG_Pos
#define GTZC_TZIC1_FCR3_OCTOSPI1_REG_Msk        GTZC_CFGR3_OCTOSPI1_REG_Msk
#define GTZC_TZIC1_FCR3_RAMCFG_Pos              GTZC_CFGR3_RAMCFG_Pos
#define GTZC_TZIC1_FCR3_RAMCFG_Msk              GTZC_CFGR3_RAMCFG_Msk
#define GTZC_TZIC1_FCR3_DAC1_Pos                GTZC_CFGR3_DAC1_Pos
#define GTZC_TZIC1_FCR3_DAC1_Msk                GTZC_CFGR3_DAC1_Msk
#define GTZC_TZIC1_FCR3_ADF1_Pos                GTZC_CFGR3_ADF1_Pos
#define GTZC_TZIC1_FCR3_ADF1_Msk                GTZC_CFGR3_ADF1_Msk

/******************  Bits definition for GTZC_TZIC1_FCR4 register  ***************/
#define GTZC_TZIC1_FCR4_GPDMA1_Pos              GTZC_CFGR4_GPDMA1_Pos
#define GTZC_TZIC1_FCR4_GPDMA1_Msk              GTZC_CFGR4_GPDMA1_Msk
#define GTZC_TZIC1_FCR4_FLASH_REG_Pos           GTZC_CFGR4_FLASH_REG_Pos
#define GTZC_TZIC1_FCR4_FLASH_REG_Msk           GTZC_CFGR4_FLASH_REG_Msk
#define GTZC_TZIC1_FCR4_FLASH_Pos               GTZC_CFGR4_FLASH_Pos
#define GTZC_TZIC1_FCR4_FLASH_Msk               GTZC_CFGR4_FLASH_Msk
#define GTZC_TZIC1_FCR4_PWR_Pos                 GTZC_CFGR4_PWR_Pos
#define GTZC_TZIC1_FCR4_PWR_Msk                 GTZC_CFGR4_PWR_Msk
#define GTZC_TZIC1_FCR4_RCC_Pos                 GTZC_CFGR4_RCC_Pos
#define GTZC_TZIC1_FCR4_RCC_Msk                 GTZC_CFGR4_RCC_Msk
#define GTZC_TZIC1_FCR4_SYSCFG_Pos              GTZC_CFGR4_SYSCFG_Pos
#define GTZC_TZIC1_FCR4_SYSCFG_Msk              GTZC_CFGR4_SYSCFG_Msk
#define GTZC_TZIC1_FCR4_EXTI_Pos                GTZC_CFGR4_EXTI_Pos
#define GTZC_TZIC1_FCR4_EXTI_Msk                GTZC_CFGR4_EXTI_Msk
#define GTZC_TZIC1_FCR4_RTC_Pos                 GTZC_CFGR4_RTC_Pos
#define GTZC_TZIC1_FCR4_RTC_Msk                 GTZC_CFGR4_RTC_Msk
#define GTZC_TZIC1_FCR4_TAMP_Pos                GTZC_CFGR4_TAMP_Pos
#define GTZC_TZIC1_FCR4_TAMP_Msk                GTZC_CFGR4_TAMP_Msk
#define GTZC_TZIC1_FCR4_TZSC_Pos                GTZC_CFGR4_TZSC_Pos
#define GTZC_TZIC1_FCR4_TZSC_Msk                GTZC_CFGR4_TZSC_Msk
#define GTZC_TZIC1_FCR4_TZIC_Pos                GTZC_CFGR4_TZIC_Pos
#define GTZC_TZIC1_FCR4_TZIC_Msk                GTZC_CFGR4_TZIC_Msk
#define GTZC_TZIC1_FCR4_SRAM1_Pos               GTZC_CFGR4_SRAM1_Pos
#define GTZC_TZIC1_FCR4_SRAM1_Msk               GTZC_CFGR4_SRAM1_Msk
#define GTZC_TZIC1_FCR4_MPCBB1_REG_Pos          GTZC_CFGR4_MPCBB1_REG_Pos
#define GTZC_TZIC1_FCR4_MPCBB1_REG_Msk          GTZC_CFGR4_MPCBB1_REG_Msk
#define GTZC_TZIC1_FCR4_SRAM2_Pos               GTZC_CFGR4_SRAM2_Pos
#define GTZC_TZIC1_FCR4_SRAM2_Msk               GTZC_CFGR4_SRAM2_Msk
#define GTZC_TZIC1_FCR4_MPCBB2_REG_Pos          GTZC_CFGR4_MPCBB2_REG_Pos
#define GTZC_TZIC1_FCR4_MPCBB2_REG_Msk          GTZC_CFGR4_MPCBB2_REG_Msk

/*******************  Bits definition for GTZC_MPCBB_CR register  *****************/
#define GTZC_MPCBB_CR_GLOCK_Pos             (0UL)
#define GTZC_MPCBB_CR_GLOCK_Msk             (0x01UL << GTZC_MPCBB_CR_GLOCK_Pos)       /*!< 0x00000001 */
#define GTZC_MPCBB_CR_INVSECSTATE_Pos       (30UL)
#define GTZC_MPCBB_CR_INVSECSTATE_Msk       (0x01UL << GTZC_MPCBB_CR_INVSECSTATE_Pos) /*!< 0x40000000 */
#define GTZC_MPCBB_CR_SRWILADIS_Pos         (31UL)
#define GTZC_MPCBB_CR_SRWILADIS_Msk         (0x01UL << GTZC_MPCBB_CR_SRWILADIS_Pos)   /*!< 0x80000000 */

/*******************  Bits definition for GTZC_MPCBB_CFGLOCKR1 register  ************/
#define GTZC_MPCBB_CFGLOCKR1_SPLCK0_Pos      (0UL)
#define GTZC_MPCBB_CFGLOCKR1_SPLCK0_Msk      (0x01UL << GTZC_MPCBB_CFGLOCKR1_SPLCK0_Pos) /*!< 0x00000001 */
#define GTZC_MPCBB_CFGLOCKR1_SPLCK1_Pos      (1UL)
#define GTZC_MPCBB_CFGLOCKR1_SPLCK1_Msk      (0x01UL << GTZC_MPCBB_CFGLOCKR1_SPLCK1_Pos) /*!< 0x00000002 */
#define GTZC_MPCBB_CFGLOCKR1_SPLCK2_Pos      (2UL)
#define GTZC_MPCBB_CFGLOCKR1_SPLCK2_Msk      (0x01UL << GTZC_MPCBB_CFGLOCKR1_SPLCK2_Pos) /*!< 0x00000004 */
#define GTZC_MPCBB_CFGLOCKR1_SPLCK3_Pos      (3UL)
#define GTZC_MPCBB_CFGLOCKR1_SPLCK3_Msk      (0x01UL << GTZC_MPCBB_CFGLOCKR1_SPLCK3_Pos) /*!< 0x00000008 */
#define GTZC_MPCBB_CFGLOCKR1_SPLCK4_Pos      (4UL)
#define GTZC_MPCBB_CFGLOCKR1_SPLCK4_Msk      (0x01UL << GTZC_MPCBB_CFGLOCKR1_SPLCK4_Pos) /*!< 0x00000010 */
#define GTZC_MPCBB_CFGLOCKR1_SPLCK5_Pos      (5UL)
#define GTZC_MPCBB_CFGLOCKR1_SPLCK5_Msk      (0x01UL << GTZC_MPCBB_CFGLOCKR1_SPLCK5_Pos) /*!< 0x00000020 */
#define GTZC_MPCBB_CFGLOCKR1_SPLCK6_Pos      (6UL)
#define GTZC_MPCBB_CFGLOCKR1_SPLCK6_Msk      (0x01UL << GTZC_MPCBB_CFGLOCKR1_SPLCK6_Pos) /*!< 0x00000040 */
#define GTZC_MPCBB_CFGLOCKR1_SPLCK7_Pos      (7UL)
#define GTZC_MPCBB_CFGLOCKR1_SPLCK7_Msk      (0x01UL << GTZC_MPCBB_CFGLOCKR1_SPLCK7_Pos) /*!< 0x00000080 */
#define GTZC_MPCBB_CFGLOCKR1_SPLCK8_Pos      (8UL)
#define GTZC_MPCBB_CFGLOCKR1_SPLCK8_Msk      (0x01UL << GTZC_MPCBB_CFGLOCKR1_SPLCK8_Pos) /*!< 0x00000100 */
#define GTZC_MPCBB_CFGLOCKR1_SPLCK9_Pos      (9UL)
#define GTZC_MPCBB_CFGLOCKR1_SPLCK9_Msk      (0x01UL << GTZC_MPCBB_CFGLOCKR1_SPLCK9_Pos) /*!< 0x00000200 */
#define GTZC_MPCBB_CFGLOCKR1_SPLCK10_Pos     (10UL)
#define GTZC_MPCBB_CFGLOCKR1_SPLCK10_Msk     (0x01UL << GTZC_MPCBB_CFGLOCKR1_SPLCK10_Pos) /*!< 0x00000400 */
#define GTZC_MPCBB_CFGLOCKR1_SPLCK11_Pos     (11UL)
#define GTZC_MPCBB_CFGLOCKR1_SPLCK11_Msk     (0x01UL << GTZC_MPCBB_CFGLOCKR1_SPLCK11_Pos) /*!< 0x00000800 */
#define GTZC_MPCBB_CFGLOCKR1_SPLCK12_Pos     (12UL)
#define GTZC_MPCBB_CFGLOCKR1_SPLCK12_Msk     (0x01UL << GTZC_MPCBB_CFGLOCKR1_SPLCK12_Pos) /*!< 0x00001000 */
#define GTZC_MPCBB_CFGLOCKR1_SPLCK13_Pos     (13UL)
#define GTZC_MPCBB_CFGLOCKR1_SPLCK13_Msk     (0x01UL << GTZC_MPCBB_CFGLOCKR1_SPLCK13_Pos) /*!< 0x00002000 */
#define GTZC_MPCBB_CFGLOCKR1_SPLCK14_Pos     (14UL)
#define GTZC_MPCBB_CFGLOCKR1_SPLCK14_Msk     (0x01UL << GTZC_MPCBB_CFGLOCKR1_SPLCK14_Pos) /*!< 0x00004000 */
#define GTZC_MPCBB_CFGLOCKR1_SPLCK15_Pos     (15UL)
#define GTZC_MPCBB_CFGLOCKR1_SPLCK15_Msk     (0x01UL << GTZC_MPCBB_CFGLOCKR1_SPLCK15_Pos) /*!< 0x00008000 */
#define GTZC_MPCBB_CFGLOCKR1_SPLCK16_Pos     (16UL)
#define GTZC_MPCBB_CFGLOCKR1_SPLCK16_Msk     (0x01UL << GTZC_MPCBB_CFGLOCKR1_SPLCK16_Pos) /*!< 0x00010000 */
#define GTZC_MPCBB_CFGLOCKR1_SPLCK17_Pos     (17UL)
#define GTZC_MPCBB_CFGLOCKR1_SPLCK17_Msk     (0x01UL << GTZC_MPCBB_CFGLOCKR1_SPLCK17_Pos) /*!< 0x00020000 */
#define GTZC_MPCBB_CFGLOCKR1_SPLCK18_Pos     (18UL)
#define GTZC_MPCBB_CFGLOCKR1_SPLCK18_Msk     (0x01UL << GTZC_MPCBB_CFGLOCKR1_SPLCK18_Pos) /*!< 0x00040000 */
#define GTZC_MPCBB_CFGLOCKR1_SPLCK19_Pos     (19UL)
#define GTZC_MPCBB_CFGLOCKR1_SPLCK19_Msk     (0x01UL << GTZC_MPCBB_CFGLOCKR1_SPLCK19_Pos) /*!< 0x00080000 */
#define GTZC_MPCBB_CFGLOCKR1_SPLCK20_Pos     (20UL)
#define GTZC_MPCBB_CFGLOCKR1_SPLCK20_Msk     (0x01UL << GTZC_MPCBB_CFGLOCKR1_SPLCK20_Pos) /*!< 0x00100000 */
#define GTZC_MPCBB_CFGLOCKR1_SPLCK21_Pos     (21UL)
#define GTZC_MPCBB_CFGLOCKR1_SPLCK21_Msk     (0x01UL << GTZC_MPCBB_CFGLOCKR1_SPLCK21_Pos) /*!< 0x00200000 */
#define GTZC_MPCBB_CFGLOCKR1_SPLCK22_Pos     (22UL)
#define GTZC_MPCBB_CFGLOCKR1_SPLCK22_Msk     (0x01UL << GTZC_MPCBB_CFGLOCKR1_SPLCK22_Pos) /*!< 0x00400000 */
#define GTZC_MPCBB_CFGLOCKR1_SPLCK23_Pos     (23UL)
#define GTZC_MPCBB_CFGLOCKR1_SPLCK23_Msk     (0x01UL << GTZC_MPCBB_CFGLOCKR1_SPLCK23_Pos) /*!< 0x00800000 */
#define GTZC_MPCBB_CFGLOCKR1_SPLCK24_Pos     (24UL)
#define GTZC_MPCBB_CFGLOCKR1_SPLCK24_Msk     (0x01UL << GTZC_MPCBB_CFGLOCKR1_SPLCK24_Pos) /*!< 0x01000000 */
#define GTZC_MPCBB_CFGLOCKR1_SPLCK25_Pos     (25UL)
#define GTZC_MPCBB_CFGLOCKR1_SPLCK25_Msk     (0x01UL << GTZC_MPCBB_CFGLOCKR1_SPLCK25_Pos) /*!< 0x02000000 */
#define GTZC_MPCBB_CFGLOCKR1_SPLCK26_Pos     (26UL)
#define GTZC_MPCBB_CFGLOCKR1_SPLCK26_Msk     (0x01UL << GTZC_MPCBB_CFGLOCKR1_SPLCK26_Pos) /*!< 0x04000000 */
#define GTZC_MPCBB_CFGLOCKR1_SPLCK27_Pos     (27UL)
#define GTZC_MPCBB_CFGLOCKR1_SPLCK27_Msk     (0x01UL << GTZC_MPCBB_CFGLOCKR1_SPLCK27_Pos) /*!< 0x08000000 */
#define GTZC_MPCBB_CFGLOCKR1_SPLCK28_Pos     (28UL)
#define GTZC_MPCBB_CFGLOCKR1_SPLCK28_Msk     (0x01UL << GTZC_MPCBB_CFGLOCKR1_SPLCK28_Pos) /*!< 0x10000000 */
#define GTZC_MPCBB_CFGLOCKR1_SPLCK29_Pos     (29UL)
#define GTZC_MPCBB_CFGLOCKR1_SPLCK29_Msk     (0x01UL << GTZC_MPCBB_CFGLOCKR1_SPLCK29_Pos) /*!< 0x20000000 */
#define GTZC_MPCBB_CFGLOCKR1_SPLCK30_Pos     (30UL)
#define GTZC_MPCBB_CFGLOCKR1_SPLCK30_Msk     (0x01UL << GTZC_MPCBB_CFGLOCKR1_SPLCK30_Pos) /*!< 0x40000000 */
#define GTZC_MPCBB_CFGLOCKR1_SPLCK31_Pos     (31UL)
#define GTZC_MPCBB_CFGLOCKR1_SPLCK31_Msk     (0x01UL << GTZC_MPCBB_CFGLOCKR1_SPLCK31_Pos) /*!< 0x80000000 */

/*******************  Bits definition for GTZC_MPCBB_SECCFGR register  ************/
#define GTZC_MPCBB_SECCFGR_SEC0_Pos      (0UL)
#define GTZC_MPCBB_SECCFGR_SEC0_Msk      (0x01UL << GTZC_MPCBB_SECCFGR_SEC0_Pos)          /*!< 0x00000001 */
#define GTZC_MPCBB_SECCFGR_SEC1_Pos      (1UL)
#define GTZC_MPCBB_SECCFGR_SEC1_Msk      (0x01UL << GTZC_MPCBB_SECCFGR_SEC1_Pos)          /*!< 0x00000002 */
#define GTZC_MPCBB_SECCFGR_SEC2_Pos      (2UL)
#define GTZC_MPCBB_SECCFGR_SEC2_Msk      (0x01UL << GTZC_MPCBB_SECCFGR_SEC2_Pos)          /*!< 0x00000004 */
#define GTZC_MPCBB_SECCFGR_SEC3_Pos      (3UL)
#define GTZC_MPCBB_SECCFGR_SEC3_Msk      (0x01UL << GTZC_MPCBB_SECCFGR_SEC3_Pos)         /*!< 0x00000008 */
#define GTZC_MPCBB_SECCFGR_SEC4_Pos      (4UL)
#define GTZC_MPCBB_SECCFGR_SEC4_Msk      (0x01UL << GTZC_MPCBB_SECCFGR_SEC4_Pos)         /*!< 0x00000010 */
#define GTZC_MPCBB_SECCFGR_SEC5_Pos      (5UL)
#define GTZC_MPCBB_SECCFGR_SEC5_Msk      (0x01UL << GTZC_MPCBB_SECCFGR_SEC5_Pos)         /*!< 0x00000020 */
#define GTZC_MPCBB_SECCFGR_SEC6_Pos      (6UL)
#define GTZC_MPCBB_SECCFGR_SEC6_Msk      (0x01UL << GTZC_MPCBB_SECCFGR_SEC6_Pos)         /*!< 0x00000040 */
#define GTZC_MPCBB_SECCFGR_SEC7_Pos      (7UL)
#define GTZC_MPCBB_SECCFGR_SEC7_Msk      (0x01UL << GTZC_MPCBB_SECCFGR_SEC7_Pos)         /*!< 0x00000080 */
#define GTZC_MPCBB_SECCFGR_SEC8_Pos      (8UL)
#define GTZC_MPCBB_SECCFGR_SEC8_Msk      (0x01UL << GTZC_MPCBB_SECCFGR_SEC8_Pos)         /*!< 0x00000100 */
#define GTZC_MPCBB_SECCFGR_SEC9_Pos      (9UL)
#define GTZC_MPCBB_SECCFGR_SEC9_Msk      (0x01UL << GTZC_MPCBB_SECCFGR_SEC9_Pos)         /*!< 0x00000200 */
#define GTZC_MPCBB_SECCFGR_SEC10_Pos     (10UL)
#define GTZC_MPCBB_SECCFGR_SEC10_Msk     (0x01UL << GTZC_MPCBB_SECCFGR_SEC10_Pos)        /*!< 0x00000400 */
#define GTZC_MPCBB_SECCFGR_SEC11_Pos     (11UL)
#define GTZC_MPCBB_SECCFGR_SEC11_Msk     (0x01UL << GTZC_MPCBB_SECCFGR_SEC11_Pos)        /*!< 0x00000800 */
#define GTZC_MPCBB_SECCFGR_SEC12_Pos     (12UL)
#define GTZC_MPCBB_SECCFGR_SEC12_Msk     (0x01UL << GTZC_MPCBB_SECCFGR_SEC12_Pos)        /*!< 0x00001000 */
#define GTZC_MPCBB_SECCFGR_SEC13_Pos     (13UL)
#define GTZC_MPCBB_SECCFGR_SEC13_Msk     (0x01UL << GTZC_MPCBB_SECCFGR_SEC13_Pos)        /*!< 0x00002000 */
#define GTZC_MPCBB_SECCFGR_SEC14_Pos     (14UL)
#define GTZC_MPCBB_SECCFGR_SEC14_Msk     (0x01UL << GTZC_MPCBB_SECCFGR_SEC14_Pos)        /*!< 0x00004000 */
#define GTZC_MPCBB_SECCFGR_SEC15_Pos     (15UL)
#define GTZC_MPCBB_SECCFGR_SEC15_Msk     (0x01UL << GTZC_MPCBB_SECCFGR_SEC15_Pos)        /*!< 0x00008000 */
#define GTZC_MPCBB_SECCFGR_SEC16_Pos     (16UL)
#define GTZC_MPCBB_SECCFGR_SEC16_Msk     (0x01UL << GTZC_MPCBB_SECCFGR_SEC16_Pos)        /*!< 0x00010000 */
#define GTZC_MPCBB_SECCFGR_SEC17_Pos     (17UL)
#define GTZC_MPCBB_SECCFGR_SEC17_Msk     (0x01UL << GTZC_MPCBB_SECCFGR_SEC17_Pos)        /*!< 0x00020000 */
#define GTZC_MPCBB_SECCFGR_SEC18_Pos     (18UL)
#define GTZC_MPCBB_SECCFGR_SEC18_Msk     (0x01UL << GTZC_MPCBB_SECCFGR_SEC18_Pos)        /*!< 0x00040000 */
#define GTZC_MPCBB_SECCFGR_SEC19_Pos     (19UL)
#define GTZC_MPCBB_SECCFGR_SEC19_Msk     (0x01UL << GTZC_MPCBB_SECCFGR_SEC19_Pos)        /*!< 0x00080000 */
#define GTZC_MPCBB_SECCFGR_SEC20_Pos     (20UL)
#define GTZC_MPCBB_SECCFGR_SEC20_Msk     (0x01UL << GTZC_MPCBB_SECCFGR_SEC20_Pos)        /*!< 0x00100000 */
#define GTZC_MPCBB_SECCFGR_SEC21_Pos     (21UL)
#define GTZC_MPCBB_SECCFGR_SEC21_Msk     (0x01UL << GTZC_MPCBB_SECCFGR_SEC21_Pos)        /*!< 0x00200000 */
#define GTZC_MPCBB_SECCFGR_SEC22_Pos     (22UL)
#define GTZC_MPCBB_SECCFGR_SEC22_Msk     (0x01UL << GTZC_MPCBB_SECCFGR_SEC22_Pos)        /*!< 0x00400000 */
#define GTZC_MPCBB_SECCFGR_SEC23_Pos     (23UL)
#define GTZC_MPCBB_SECCFGR_SEC23_Msk     (0x01UL << GTZC_MPCBB_SECCFGR_SEC23_Pos)        /*!< 0x00800000 */
#define GTZC_MPCBB_SECCFGR_SEC24_Pos     (24UL)
#define GTZC_MPCBB_SECCFGR_SEC24_Msk     (0x01UL << GTZC_MPCBB_SECCFGR_SEC24_Pos)        /*!< 0x01000000 */
#define GTZC_MPCBB_SECCFGR_SEC25_Pos     (25UL)
#define GTZC_MPCBB_SECCFGR_SEC25_Msk     (0x01UL << GTZC_MPCBB_SECCFGR_SEC25_Pos)        /*!< 0x02000000 */
#define GTZC_MPCBB_SECCFGR_SEC26_Pos     (26UL)
#define GTZC_MPCBB_SECCFGR_SEC26_Msk     (0x01UL << GTZC_MPCBB_SECCFGR_SEC26_Pos)        /*!< 0x04000000 */
#define GTZC_MPCBB_SECCFGR_SEC27_Pos     (27UL)
#define GTZC_MPCBB_SECCFGR_SEC27_Msk     (0x01UL << GTZC_MPCBB_SECCFGR_SEC27_Pos)        /*!< 0x08000000 */
#define GTZC_MPCBB_SECCFGR_SEC28_Pos     (28UL)
#define GTZC_MPCBB_SECCFGR_SEC28_Msk     (0x01UL << GTZC_MPCBB_SECCFGR_SEC28_Pos)        /*!< 0x10000000 */
#define GTZC_MPCBB_SECCFGR_SEC29_Pos     (29UL)
#define GTZC_MPCBB_SECCFGR_SEC29_Msk     (0x01UL << GTZC_MPCBB_SECCFGR_SEC29_Pos)        /*!< 0x20000000 */
#define GTZC_MPCBB_SECCFGR_SEC30_Pos     (30UL)
#define GTZC_MPCBB_SECCFGR_SEC30_Msk     (0x01UL << GTZC_MPCBB_SECCFGR_SEC30_Pos)        /*!< 0x40000000 */
#define GTZC_MPCBB_SECCFGR_SEC31_Pos     (31UL)
#define GTZC_MPCBB_SECCFGR_SEC31_Msk     (0x01UL << GTZC_MPCBB_SECCFGR_SEC31_Pos)        /*!< 0x80000000 */

/*******************  Bits definition for GTZC_MPCBB_PRIVCFGR register  ************/
#define GTZC_MPCBB_PRIVCFGR_PRIV0_Pos      (0UL)
#define GTZC_MPCBB_PRIVCFGR_PRIV0_Msk      (0x01UL << GTZC_MPCBB_PRIVCFGR_PRIV0_Pos)     /*!< 0x00000001 */
#define GTZC_MPCBB_PRIVCFGR_PRIV1_Pos      (1UL)
#define GTZC_MPCBB_PRIVCFGR_PRIV1_Msk      (0x01UL << GTZC_MPCBB_PRIVCFGR_PRIV1_Pos)     /*!< 0x00000002 */
#define GTZC_MPCBB_PRIVCFGR_PRIV2_Pos      (2UL)
#define GTZC_MPCBB_PRIVCFGR_PRIV2_Msk      (0x01UL << GTZC_MPCBB_PRIVCFGR_PRIV2_Pos)     /*!< 0x00000004 */
#define GTZC_MPCBB_PRIVCFGR_PRIV3_Pos      (3UL)
#define GTZC_MPCBB_PRIVCFGR_PRIV3_Msk      (0x01UL << GTZC_MPCBB_PRIVCFGR_PRIV3_Pos)     /*!< 0x00000008 */
#define GTZC_MPCBB_PRIVCFGR_PRIV4_Pos      (4UL)
#define GTZC_MPCBB_PRIVCFGR_PRIV4_Msk      (0x01UL << GTZC_MPCBB_PRIVCFGR_PRIV4_Pos)     /*!< 0x00000010 */
#define GTZC_MPCBB_PRIVCFGR_PRIV5_Pos      (5UL)
#define GTZC_MPCBB_PRIVCFGR_PRIV5_Msk      (0x01UL << GTZC_MPCBB_PRIVCFGR_PRIV5_Pos)     /*!< 0x00000020 */
#define GTZC_MPCBB_PRIVCFGR_PRIV6_Pos      (6UL)
#define GTZC_MPCBB_PRIVCFGR_PRIV6_Msk      (0x01UL << GTZC_MPCBB_PRIVCFGR_PRIV6_Pos)     /*!< 0x00000040 */
#define GTZC_MPCBB_PRIVCFGR_PRIV7_Pos      (7UL)
#define GTZC_MPCBB_PRIVCFGR_PRIV7_Msk      (0x01UL << GTZC_MPCBB_PRIVCFGR_PRIV7_Pos)     /*!< 0x00000080 */
#define GTZC_MPCBB_PRIVCFGR_PRIV8_Pos      (8UL)
#define GTZC_MPCBB_PRIVCFGR_PRIV8_Msk      (0x01UL << GTZC_MPCBB_PRIVCFGR_PRIV8_Pos)     /*!< 0x00000100 */
#define GTZC_MPCBB_PRIVCFGR_PRIV9_Pos      (9UL)
#define GTZC_MPCBB_PRIVCFGR_PRIV9_Msk      (0x01UL << GTZC_MPCBB_PRIVCFGR_PRIV9_Pos)     /*!< 0x00000200 */
#define GTZC_MPCBB_PRIVCFGR_PRIV10_Pos     (10UL)
#define GTZC_MPCBB_PRIVCFGR_PRIV10_Msk     (0x01UL << GTZC_MPCBB_PRIVCFGR_PRIV10_Pos)    /*!< 0x00000400 */
#define GTZC_MPCBB_PRIVCFGR_PRIV11_Pos     (11UL)
#define GTZC_MPCBB_PRIVCFGR_PRIV11_Msk     (0x01UL << GTZC_MPCBB_PRIVCFGR_PRIV11_Pos)    /*!< 0x00000800 */
#define GTZC_MPCBB_PRIVCFGR_PRIV12_Pos     (12UL)
#define GTZC_MPCBB_PRIVCFGR_PRIV12_Msk     (0x01UL << GTZC_MPCBB_PRIVCFGR_PRIV12_Pos)    /*!< 0x00001000 */
#define GTZC_MPCBB_PRIVCFGR_PRIV13_Pos     (13UL)
#define GTZC_MPCBB_PRIVCFGR_PRIV13_Msk     (0x01UL << GTZC_MPCBB_PRIVCFGR_PRIV13_Pos)    /*!< 0x00002000 */
#define GTZC_MPCBB_PRIVCFGR_PRIV14_Pos     (14UL)
#define GTZC_MPCBB_PRIVCFGR_PRIV14_Msk     (0x01UL << GTZC_MPCBB_PRIVCFGR_PRIV14_Pos)    /*!< 0x00004000 */
#define GTZC_MPCBB_PRIVCFGR_PRIV15_Pos     (15UL)
#define GTZC_MPCBB_PRIVCFGR_PRIV15_Msk     (0x01UL << GTZC_MPCBB_PRIVCFGR_PRIV15_Pos)    /*!< 0x00008000 */
#define GTZC_MPCBB_PRIVCFGR_PRIV16_Pos     (16UL)
#define GTZC_MPCBB_PRIVCFGR_PRIV16_Msk     (0x01UL << GTZC_MPCBB_PRIVCFGR_PRIV16_Pos)    /*!< 0x00010000 */
#define GTZC_MPCBB_PRIVCFGR_PRIV17_Pos     (17UL)
#define GTZC_MPCBB_PRIVCFGR_PRIV17_Msk     (0x01UL << GTZC_MPCBB_PRIVCFGR_PRIV17_Pos)    /*!< 0x00020000 */
#define GTZC_MPCBB_PRIVCFGR_PRIV18_Pos     (18UL)
#define GTZC_MPCBB_PRIVCFGR_PRIV18_Msk     (0x01UL << GTZC_MPCBB_PRIVCFGR_PRIV18_Pos)    /*!< 0x00040000 */
#define GTZC_MPCBB_PRIVCFGR_PRIV19_Pos     (19UL)
#define GTZC_MPCBB_PRIVCFGR_PRIV19_Msk     (0x01UL << GTZC_MPCBB_PRIVCFGR_PRIV19_Pos)    /*!< 0x00080000 */
#define GTZC_MPCBB_PRIVCFGR_PRIV20_Pos     (20UL)
#define GTZC_MPCBB_PRIVCFGR_PRIV20_Msk     (0x01UL << GTZC_MPCBB_PRIVCFGR_PRIV20_Pos)    /*!< 0x00100000 */
#define GTZC_MPCBB_PRIVCFGR_PRIV21_Pos     (21UL)
#define GTZC_MPCBB_PRIVCFGR_PRIV21_Msk     (0x01UL << GTZC_MPCBB_PRIVCFGR_PRIV21_Pos)    /*!< 0x00200000 */
#define GTZC_MPCBB_PRIVCFGR_PRIV22_Pos     (22UL)
#define GTZC_MPCBB_PRIVCFGR_PRIV22_Msk     (0x01UL << GTZC_MPCBB_PRIVCFGR_PRIV22_Pos)    /*!< 0x00400000 */
#define GTZC_MPCBB_PRIVCFGR_PRIV23_Pos     (23UL)
#define GTZC_MPCBB_PRIVCFGR_PRIV23_Msk     (0x01UL << GTZC_MPCBB_PRIVCFGR_PRIV23_Pos)    /*!< 0x00800000 */
#define GTZC_MPCBB_PRIVCFGR_PRIV24_Pos     (24UL)
#define GTZC_MPCBB_PRIVCFGR_PRIV24_Msk     (0x01UL << GTZC_MPCBB_PRIVCFGR_PRIV24_Pos)    /*!< 0x01000000 */
#define GTZC_MPCBB_PRIVCFGR_PRIV25_Pos     (25UL)
#define GTZC_MPCBB_PRIVCFGR_PRIV25_Msk     (0x01UL << GTZC_MPCBB_PRIVCFGR_PRIV25_Pos)    /*!< 0x02000000 */
#define GTZC_MPCBB_PRIVCFGR_PRIV26_Pos     (26UL)
#define GTZC_MPCBB_PRIVCFGR_PRIV26_Msk     (0x01UL << GTZC_MPCBB_PRIVCFGR_PRIV26_Pos)    /*!< 0x04000000 */
#define GTZC_MPCBB_PRIVCFGR_PRIV27_Pos     (27UL)
#define GTZC_MPCBB_PRIVCFGR_PRIV27_Msk     (0x01UL << GTZC_MPCBB_PRIVCFGR_PRIV27_Pos)    /*!< 0x08000000 */
#define GTZC_MPCBB_PRIVCFGR_PRIV28_Pos     (28UL)
#define GTZC_MPCBB_PRIVCFGR_PRIV28_Msk     (0x01UL << GTZC_MPCBB_PRIVCFGR_PRIV28_Pos)    /*!< 0x10000000 */
#define GTZC_MPCBB_PRIVCFGR_PRIV29_Pos     (29UL)
#define GTZC_MPCBB_PRIVCFGR_PRIV29_Msk     (0x01UL << GTZC_MPCBB_PRIVCFGR_PRIV29_Pos)    /*!< 0x20000000 */
#define GTZC_MPCBB_PRIVCFGR_PRIV30_Pos     (30UL)
#define GTZC_MPCBB_PRIVCFGR_PRIV30_Msk     (0x01UL << GTZC_MPCBB_PRIVCFGR_PRIV30_Pos)    /*!< 0x40000000 */
#define GTZC_MPCBB_PRIVCFGR_PRIV31_Pos     (31UL)
#define GTZC_MPCBB_PRIVCFGR_PRIV31_Msk     (0x01UL << GTZC_MPCBB_PRIVCFGR_PRIV31_Pos)    /*!< 0x80000000 */

/******************************************************************************/
/*                                                                            */
/*                                    HASH                                    */
/*                                                                            */
/******************************************************************************/
/******************  Bits definition for HASH_CR register  ********************/
#define HASH_CR_INIT_Pos                    (2UL)
#define HASH_CR_INIT_Msk                    (0x1UL << HASH_CR_INIT_Pos)             /*!< 0x00000004 */
#define HASH_CR_INIT                        HASH_CR_INIT_Msk
#define HASH_CR_DMAE_Pos                    (3UL)
#define HASH_CR_DMAE_Msk                    (0x1UL << HASH_CR_DMAE_Pos)             /*!< 0x00000008 */
#define HASH_CR_DMAE                        HASH_CR_DMAE_Msk
#define HASH_CR_DATATYPE_Pos                (4UL)
#define HASH_CR_DATATYPE_Msk                (0x3UL << HASH_CR_DATATYPE_Pos)         /*!< 0x00000030 */
#define HASH_CR_DATATYPE                    HASH_CR_DATATYPE_Msk
#define HASH_CR_DATATYPE_0                  (0x1UL << HASH_CR_DATATYPE_Pos)         /*!< 0x00000010 */
#define HASH_CR_DATATYPE_1                  (0x2UL << HASH_CR_DATATYPE_Pos)         /*!< 0x00000020 */
#define HASH_CR_MODE_Pos                    (6UL)
#define HASH_CR_MODE_Msk                    (0x1UL << HASH_CR_MODE_Pos)             /*!< 0x00000040 */
#define HASH_CR_MODE                        HASH_CR_MODE_Msk
#define HASH_CR_NBW_Pos                     (8UL)
#define HASH_CR_NBW_Msk                     (0xFUL << HASH_CR_NBW_Pos)              /*!< 0x00000F00 */
#define HASH_CR_NBW                         HASH_CR_NBW_Msk
#define HASH_CR_NBW_0                       (0x1UL << HASH_CR_NBW_Pos)              /*!< 0x00000100 */
#define HASH_CR_NBW_1                       (0x2UL << HASH_CR_NBW_Pos)              /*!< 0x00000200 */
#define HASH_CR_NBW_2                       (0x4UL << HASH_CR_NBW_Pos)              /*!< 0x00000400 */
#define HASH_CR_NBW_3                       (0x8UL << HASH_CR_NBW_Pos)              /*!< 0x00000800 */
#define HASH_CR_DINNE_Pos                   (12UL)
#define HASH_CR_DINNE_Msk                   (0x1UL << HASH_CR_DINNE_Pos)            /*!< 0x00001000 */
#define HASH_CR_DINNE                       HASH_CR_DINNE_Msk
#define HASH_CR_MDMAT_Pos                   (13UL)
#define HASH_CR_MDMAT_Msk                   (0x1UL << HASH_CR_MDMAT_Pos)            /*!< 0x00002000 */
#define HASH_CR_MDMAT                       HASH_CR_MDMAT_Msk
#define HASH_CR_LKEY_Pos                    (16UL)
#define HASH_CR_LKEY_Msk                    (0x1UL << HASH_CR_LKEY_Pos)             /*!< 0x00010000 */
#define HASH_CR_LKEY                        HASH_CR_LKEY_Msk
#define HASH_CR_ALGO_Pos                    (17UL)
#define HASH_CR_ALGO_Msk                    (0xFUL << HASH_CR_ALGO_Pos)             /*!< 0x001E0000 */
#define HASH_CR_ALGO                        HASH_CR_ALGO_Msk
#define HASH_CR_ALGO_0                      (0x1UL << HASH_CR_ALGO_Pos)             /*!< 0x00020000 */
#define HASH_CR_ALGO_1                      (0x2UL << HASH_CR_ALGO_Pos)             /*!< 0x00040000 */
#define HASH_CR_ALGO_2                      (0x4UL << HASH_CR_ALGO_Pos)             /*!< 0x00080000 */
#define HASH_CR_ALGO_3                      (0x8UL << HASH_CR_ALGO_Pos)             /*!< 0x00100000 */

/******************  Bits definition for HASH_STR register  *******************/
#define HASH_STR_NBLW_Pos                   (0UL)
#define HASH_STR_NBLW_Msk                   (0x1FUL << HASH_STR_NBLW_Pos)           /*!< 0x0000001F */
#define HASH_STR_NBLW                       HASH_STR_NBLW_Msk
#define HASH_STR_NBLW_0                     (0x01UL << HASH_STR_NBLW_Pos)           /*!< 0x00000001 */
#define HASH_STR_NBLW_1                     (0x02UL << HASH_STR_NBLW_Pos)           /*!< 0x00000002 */
#define HASH_STR_NBLW_2                     (0x04UL << HASH_STR_NBLW_Pos)           /*!< 0x00000004 */
#define HASH_STR_NBLW_3                     (0x08UL << HASH_STR_NBLW_Pos)           /*!< 0x00000008 */
#define HASH_STR_NBLW_4                     (0x10UL << HASH_STR_NBLW_Pos)           /*!< 0x00000010 */
#define HASH_STR_DCAL_Pos                   (8UL)
#define HASH_STR_DCAL_Msk                   (0x1UL << HASH_STR_DCAL_Pos)            /*!< 0x00000100 */
#define HASH_STR_DCAL                       HASH_STR_DCAL_Msk

/******************  Bits definition for HASH_SHA3CFGR register  ********************/
#define HASH_SHA3CFGR_PADBYTE_Pos           (0UL)
#define HASH_SHA3CFGR_PADBYTE_Msk           (0xFFUL << HASH_SHA3CFGR_PADBYTE_Pos)            /*!< 0x000000FF */
#define HASH_SHA3CFGR_PADBYTE               HASH_SHA3CFGR_PADBYTE_Msk
#define HASH_SHA3CFGR_PADCONFIG_Pos         (8UL)
#define HASH_SHA3CFGR_PADCONFIG_Msk         (0x1UL << HASH_SHA3CFGR_PADCONFIG_Pos)             /*!< 0x00000100 */
#define HASH_SHA3CFGR_PADCONFIG             HASH_SHA3CFGR_PADCONFIG_Msk
#define HASH_SHA3CFGR_START_RND_Pos         (9UL)
#define HASH_SHA3CFGR_START_RND_Msk         (0x1FUL << HASH_SHA3CFGR_START_RND_Pos)             /*!< 0x00003E00 */
#define HASH_SHA3CFGR_START_RND             HASH_SHA3CFGR_START_RND_Msk
#define HASH_SHA3CFGR_END_RND_Pos           (14UL)
#define HASH_SHA3CFGR_END_RND_Msk           (0x1FUL << HASH_SHA3CFGR_END_RND_Pos)             /*!< 0x0007C000 */
#define HASH_SHA3CFGR_END_RND               HASH_SHA3CFGR_END_RND_Msk
#define HASH_SHA3CFGR_IN_RATE_Pos           (19UL)
#define HASH_SHA3CFGR_IN_RATE_Msk           (0x1FUL << HASH_SHA3CFGR_IN_RATE_Pos)             /*!< 0x0F80000 */
#define HASH_SHA3CFGR_IN_RATE               HASH_SHA3CFGR_IN_RATE_Msk

/******************  Bits definition for HASH_IMR register  *******************/
#define HASH_IMR_DINIE_Pos                  (0UL)
#define HASH_IMR_DINIE_Msk                  (0x1UL << HASH_IMR_DINIE_Pos)           /*!< 0x00000001 */
#define HASH_IMR_DINIE                      HASH_IMR_DINIE_Msk
#define HASH_IMR_DCIE_Pos                   (1UL)
#define HASH_IMR_DCIE_Msk                   (0x1UL << HASH_IMR_DCIE_Pos)            /*!< 0x00000002 */
#define HASH_IMR_DCIE                       HASH_IMR_DCIE_Msk

/******************  Bits definition for HASH_SR register  ********************/
#define HASH_SR_DINIS_Pos                   (0UL)
#define HASH_SR_DINIS_Msk                   (0x1UL << HASH_SR_DINIS_Pos)            /*!< 0x00000001 */
#define HASH_SR_DINIS                       HASH_SR_DINIS_Msk
#define HASH_SR_DCIS_Pos                    (1UL)
#define HASH_SR_DCIS_Msk                    (0x1UL << HASH_SR_DCIS_Pos)             /*!< 0x00000002 */
#define HASH_SR_DCIS                        HASH_SR_DCIS_Msk
#define HASH_SR_DMAS_Pos                    (2UL)
#define HASH_SR_DMAS_Msk                    (0x1UL << HASH_SR_DMAS_Pos)             /*!< 0x00000004 */
#define HASH_SR_DMAS                        HASH_SR_DMAS_Msk
#define HASH_SR_BUSY_Pos                    (3UL)
#define HASH_SR_BUSY_Msk                    (0x1UL << HASH_SR_BUSY_Pos)             /*!< 0x00000008 */
#define HASH_SR_BUSY                        HASH_SR_BUSY_Msk
#define HASH_SR_NBWP_Pos                    (9UL)
#define HASH_SR_NBWP_Msk                    (0x3FUL << HASH_SR_NBWP_Pos)             /*!< 0x00007E00 */
#define HASH_SR_NBWP                        HASH_SR_NBWP_Msk
#define HASH_SR_DINNE_Pos                   (15UL)
#define HASH_SR_DINNE_Msk                   (0x1UL << HASH_SR_DINNE_Pos)            /*!< 0x00008000 */
#define HASH_SR_DINNE                       HASH_SR_DINNE_Msk
#define HASH_SR_NBWE_Pos                    (16UL)
#define HASH_SR_NBWE_Msk                    (0x3FUL << HASH_SR_NBWE_Pos)             /*!< 0x000F0000 */
#define HASH_SR_NBWE                        HASH_SR_NBWE_Msk

/******************************************************************************/
/*                                                                            */
/*                      Inter-integrated Circuit Interface (I2C)              */
/*                                                                            */
/******************************************************************************/
/*******************  Bit definition for I2C_CR1 register  *******************/
#define I2C_CR1_PE_Pos                      (0UL)
#define I2C_CR1_PE_Msk                      (0x1UL << I2C_CR1_PE_Pos)               /*!< 0x00000001 */
#define I2C_CR1_PE                          I2C_CR1_PE_Msk                          /*!< Peripheral enable */
#define I2C_CR1_TXIE_Pos                    (1UL)
#define I2C_CR1_TXIE_Msk                    (0x1UL << I2C_CR1_TXIE_Pos)             /*!< 0x00000002 */
#define I2C_CR1_TXIE                        I2C_CR1_TXIE_Msk                        /*!< TX interrupt enable */
#define I2C_CR1_RXIE_Pos                    (2UL)
#define I2C_CR1_RXIE_Msk                    (0x1UL << I2C_CR1_RXIE_Pos)             /*!< 0x00000004 */
#define I2C_CR1_RXIE                        I2C_CR1_RXIE_Msk                        /*!< RX interrupt enable */
#define I2C_CR1_ADDRIE_Pos                  (3UL)
#define I2C_CR1_ADDRIE_Msk                  (0x1UL << I2C_CR1_ADDRIE_Pos)           /*!< 0x00000008 */
#define I2C_CR1_ADDRIE                      I2C_CR1_ADDRIE_Msk                      /*!< Address match interrupt enable */
#define I2C_CR1_NACKIE_Pos                  (4UL)
#define I2C_CR1_NACKIE_Msk                  (0x1UL << I2C_CR1_NACKIE_Pos)           /*!< 0x00000010 */
#define I2C_CR1_NACKIE                      I2C_CR1_NACKIE_Msk                      /*!< NACK received interrupt enable */
#define I2C_CR1_STOPIE_Pos                  (5UL)
#define I2C_CR1_STOPIE_Msk                  (0x1UL << I2C_CR1_STOPIE_Pos)           /*!< 0x00000020 */
#define I2C_CR1_STOPIE                      I2C_CR1_STOPIE_Msk                      /*!< STOP detection interrupt enable */
#define I2C_CR1_TCIE_Pos                    (6UL)
#define I2C_CR1_TCIE_Msk                    (0x1UL << I2C_CR1_TCIE_Pos)             /*!< 0x00000040 */
#define I2C_CR1_TCIE                        I2C_CR1_TCIE_Msk                        /*!< Transfer complete interrupt enable */
#define I2C_CR1_ERRIE_Pos                   (7UL)
#define I2C_CR1_ERRIE_Msk                   (0x1UL << I2C_CR1_ERRIE_Pos)            /*!< 0x00000080 */
#define I2C_CR1_ERRIE                       I2C_CR1_ERRIE_Msk                       /*!< Errors interrupt enable */
#define I2C_CR1_DNF_Pos                     (8UL)
#define I2C_CR1_DNF_Msk                     (0xFUL << I2C_CR1_DNF_Pos)              /*!< 0x00000F00 */
#define I2C_CR1_DNF                         I2C_CR1_DNF_Msk                         /*!< Digital noise filter */
#define I2C_CR1_ANFOFF_Pos                  (12UL)
#define I2C_CR1_ANFOFF_Msk                  (0x1UL << I2C_CR1_ANFOFF_Pos)           /*!< 0x00001000 */
#define I2C_CR1_ANFOFF                      I2C_CR1_ANFOFF_Msk                      /*!< Analog noise filter OFF */
#define I2C_CR1_SWRST_Pos                   (13UL)
#define I2C_CR1_SWRST_Msk                   (0x1UL << I2C_CR1_SWRST_Pos)            /*!< 0x00002000 */
#define I2C_CR1_SWRST                       I2C_CR1_SWRST_Msk                       /*!< Software reset */
#define I2C_CR1_TXDMAEN_Pos                 (14UL)
#define I2C_CR1_TXDMAEN_Msk                 (0x1UL << I2C_CR1_TXDMAEN_Pos)          /*!< 0x00004000 */
#define I2C_CR1_TXDMAEN                     I2C_CR1_TXDMAEN_Msk                     /*!< DMA transmission requests enable */
#define I2C_CR1_RXDMAEN_Pos                 (15UL)
#define I2C_CR1_RXDMAEN_Msk                 (0x1UL << I2C_CR1_RXDMAEN_Pos)          /*!< 0x00008000 */
#define I2C_CR1_RXDMAEN                     I2C_CR1_RXDMAEN_Msk                     /*!< DMA reception requests enable */
#define I2C_CR1_SBC_Pos                     (16UL)
#define I2C_CR1_SBC_Msk                     (0x1UL << I2C_CR1_SBC_Pos)              /*!< 0x00010000 */
#define I2C_CR1_SBC                         I2C_CR1_SBC_Msk                         /*!< Slave byte control */
#define I2C_CR1_NOSTRETCH_Pos               (17UL)
#define I2C_CR1_NOSTRETCH_Msk               (0x1UL << I2C_CR1_NOSTRETCH_Pos)        /*!< 0x00020000 */
#define I2C_CR1_NOSTRETCH                   I2C_CR1_NOSTRETCH_Msk                   /*!< Clock stretching disable */
#define I2C_CR1_WUPEN_Pos                   (18UL)
#define I2C_CR1_WUPEN_Msk                   (0x1UL << I2C_CR1_WUPEN_Pos)            /*!< 0x00040000 */
#define I2C_CR1_WUPEN                       I2C_CR1_WUPEN_Msk                       /*!< Wakeup from STOP enable */
#define I2C_CR1_GCEN_Pos                    (19UL)
#define I2C_CR1_GCEN_Msk                    (0x1UL << I2C_CR1_GCEN_Pos)             /*!< 0x00080000 */
#define I2C_CR1_GCEN                        I2C_CR1_GCEN_Msk                        /*!< General call enable */
#define I2C_CR1_SMBHEN_Pos                  (20UL)
#define I2C_CR1_SMBHEN_Msk                  (0x1UL << I2C_CR1_SMBHEN_Pos)           /*!< 0x00100000 */
#define I2C_CR1_SMBHEN                      I2C_CR1_SMBHEN_Msk                      /*!< SMBus host address enable */
#define I2C_CR1_SMBDEN_Pos                  (21UL)
#define I2C_CR1_SMBDEN_Msk                  (0x1UL << I2C_CR1_SMBDEN_Pos)           /*!< 0x00200000 */
#define I2C_CR1_SMBDEN                      I2C_CR1_SMBDEN_Msk                      /*!< SMBus device default address enable */
#define I2C_CR1_ALERTEN_Pos                 (22UL)
#define I2C_CR1_ALERTEN_Msk                 (0x1UL << I2C_CR1_ALERTEN_Pos)          /*!< 0x00400000 */
#define I2C_CR1_ALERTEN                     I2C_CR1_ALERTEN_Msk                     /*!< SMBus alert enable */
#define I2C_CR1_PECEN_Pos                   (23UL)
#define I2C_CR1_PECEN_Msk                   (0x1UL << I2C_CR1_PECEN_Pos)            /*!< 0x00800000 */
#define I2C_CR1_PECEN                       I2C_CR1_PECEN_Msk                       /*!< PEC enable */
#define I2C_CR1_FMP_Pos                     (24UL)
#define I2C_CR1_FMP_Msk                     (0x1UL << I2C_CR1_FMP_Pos)              /*!< 0x01000000 */
#define I2C_CR1_FMP                         I2C_CR1_FMP_Msk                         /*!< FMP enable */
#define I2C_CR1_ADDRACLR_Pos                (30UL)
#define I2C_CR1_ADDRACLR_Msk                (0x1UL << I2C_CR1_ADDRACLR_Pos)         /*!< 0x40000000 */
#define I2C_CR1_ADDRACLR                    I2C_CR1_ADDRACLR_Msk                    /*!< ADDRACLR enable */
#define I2C_CR1_STOPFACLR_Pos               (31UL)
#define I2C_CR1_STOPFACLR_Msk               (0x1UL << I2C_CR1_STOPFACLR_Pos)        /*!< 0x80000000 */
#define I2C_CR1_STOPFACLR                   I2C_CR1_STOPFACLR_Msk                   /*!< STOPFACLR enable */

/******************  Bit definition for I2C_CR2 register  ********************/
#define I2C_CR2_SADD_Pos                    (0UL)
#define I2C_CR2_SADD_Msk                    (0x3FFUL << I2C_CR2_SADD_Pos)           /*!< 0x000003FF */
#define I2C_CR2_SADD                        I2C_CR2_SADD_Msk                        /*!< Slave address (master mode) */
#define I2C_CR2_RD_WRN_Pos                  (10UL)
#define I2C_CR2_RD_WRN_Msk                  (0x1UL << I2C_CR2_RD_WRN_Pos)           /*!< 0x00000400 */
#define I2C_CR2_RD_WRN                      I2C_CR2_RD_WRN_Msk                      /*!< Transfer direction (master mode) */
#define I2C_CR2_ADD10_Pos                   (11UL)
#define I2C_CR2_ADD10_Msk                   (0x1UL << I2C_CR2_ADD10_Pos)            /*!< 0x00000800 */
#define I2C_CR2_ADD10                       I2C_CR2_ADD10_Msk                       /*!< 10-bit addressing mode (master mode) */
#define I2C_CR2_HEAD10R_Pos                 (12UL)
#define I2C_CR2_HEAD10R_Msk                 (0x1UL << I2C_CR2_HEAD10R_Pos)          /*!< 0x00001000 */
#define I2C_CR2_HEAD10R                     I2C_CR2_HEAD10R_Msk                     /*!< 10-bit address header only read direction (master mode) */
#define I2C_CR2_START_Pos                   (13UL)
#define I2C_CR2_START_Msk                   (0x1UL << I2C_CR2_START_Pos)            /*!< 0x00002000 */
#define I2C_CR2_START                       I2C_CR2_START_Msk                       /*!< START generation */
#define I2C_CR2_STOP_Pos                    (14UL)
#define I2C_CR2_STOP_Msk                    (0x1UL << I2C_CR2_STOP_Pos)             /*!< 0x00004000 */
#define I2C_CR2_STOP                        I2C_CR2_STOP_Msk                        /*!< STOP generation (master mode) */
#define I2C_CR2_NACK_Pos                    (15UL)
#define I2C_CR2_NACK_Msk                    (0x1UL << I2C_CR2_NACK_Pos)             /*!< 0x00008000 */
#define I2C_CR2_NACK                        I2C_CR2_NACK_Msk                        /*!< NACK generation (slave mode) */
#define I2C_CR2_NBYTES_Pos                  (16UL)
#define I2C_CR2_NBYTES_Msk                  (0xFFUL << I2C_CR2_NBYTES_Pos)          /*!< 0x00FF0000 */
#define I2C_CR2_NBYTES                      I2C_CR2_NBYTES_Msk                      /*!< Number of bytes */
#define I2C_CR2_RELOAD_Pos                  (24UL)
#define I2C_CR2_RELOAD_Msk                  (0x1UL << I2C_CR2_RELOAD_Pos)           /*!< 0x01000000 */
#define I2C_CR2_RELOAD                      I2C_CR2_RELOAD_Msk                      /*!< NBYTES reload mode */
#define I2C_CR2_AUTOEND_Pos                 (25UL)
#define I2C_CR2_AUTOEND_Msk                 (0x1UL << I2C_CR2_AUTOEND_Pos)          /*!< 0x02000000 */
#define I2C_CR2_AUTOEND                     I2C_CR2_AUTOEND_Msk                     /*!< Automatic end mode (master mode) */
#define I2C_CR2_PECBYTE_Pos                 (26UL)
#define I2C_CR2_PECBYTE_Msk                 (0x1UL << I2C_CR2_PECBYTE_Pos)          /*!< 0x04000000 */
#define I2C_CR2_PECBYTE                     I2C_CR2_PECBYTE_Msk                     /*!< Packet error checking byte */

/*******************  Bit definition for I2C_OAR1 register  ******************/
#define I2C_OAR1_OA1_Pos                    (0UL)
#define I2C_OAR1_OA1_Msk                    (0x3FFUL << I2C_OAR1_OA1_Pos)           /*!< 0x000003FF */
#define I2C_OAR1_OA1                        I2C_OAR1_OA1_Msk                        /*!< Interface own address 1 */
#define I2C_OAR1_OA1MODE_Pos                (10UL)
#define I2C_OAR1_OA1MODE_Msk                (0x1UL << I2C_OAR1_OA1MODE_Pos)         /*!< 0x00000400 */
#define I2C_OAR1_OA1MODE                    I2C_OAR1_OA1MODE_Msk                    /*!< Own address 1 10-bit mode */
#define I2C_OAR1_OA1EN_Pos                  (15UL)
#define I2C_OAR1_OA1EN_Msk                  (0x1UL << I2C_OAR1_OA1EN_Pos)           /*!< 0x00008000 */
#define I2C_OAR1_OA1EN                      I2C_OAR1_OA1EN_Msk                      /*!< Own address 1 enable */

/*******************  Bit definition for I2C_OAR2 register  ******************/
#define I2C_OAR2_OA2_Pos                    (1UL)
#define I2C_OAR2_OA2_Msk                    (0x7FUL << I2C_OAR2_OA2_Pos)            /*!< 0x000000FE */
#define I2C_OAR2_OA2                        I2C_OAR2_OA2_Msk                        /*!< Interface own address 2 */
#define I2C_OAR2_OA2MSK_Pos                 (8UL)
#define I2C_OAR2_OA2MSK_Msk                 (0x7UL << I2C_OAR2_OA2MSK_Pos)          /*!< 0x00000700 */
#define I2C_OAR2_OA2MSK                     I2C_OAR2_OA2MSK_Msk                     /*!< Own address 2 masks */
#define I2C_OAR2_OA2NOMASK                  (0x00000000UL)                          /*!< No mask                                        */
#define I2C_OAR2_OA2MASK01_Pos              (8UL)
#define I2C_OAR2_OA2MASK01_Msk              (0x1UL << I2C_OAR2_OA2MASK01_Pos)       /*!< 0x00000100 */
#define I2C_OAR2_OA2MASK01                  I2C_OAR2_OA2MASK01_Msk                  /*!< OA2[1] is masked, Only OA2[7:2] are compared   */
#define I2C_OAR2_OA2MASK02_Pos              (9UL)
#define I2C_OAR2_OA2MASK02_Msk              (0x1UL << I2C_OAR2_OA2MASK02_Pos)       /*!< 0x00000200 */
#define I2C_OAR2_OA2MASK02                  I2C_OAR2_OA2MASK02_Msk                  /*!< OA2[2:1] is masked, Only OA2[7:3] are compared */
#define I2C_OAR2_OA2MASK03_Pos              (8UL)
#define I2C_OAR2_OA2MASK03_Msk              (0x3UL << I2C_OAR2_OA2MASK03_Pos)       /*!< 0x00000300 */
#define I2C_OAR2_OA2MASK03                  I2C_OAR2_OA2MASK03_Msk                  /*!< OA2[3:1] is masked, Only OA2[7:4] are compared */
#define I2C_OAR2_OA2MASK04_Pos              (10UL)
#define I2C_OAR2_OA2MASK04_Msk              (0x1UL << I2C_OAR2_OA2MASK04_Pos)       /*!< 0x00000400 */
#define I2C_OAR2_OA2MASK04                  I2C_OAR2_OA2MASK04_Msk                  /*!< OA2[4:1] is masked, Only OA2[7:5] are compared */
#define I2C_OAR2_OA2MASK05_Pos              (8UL)
#define I2C_OAR2_OA2MASK05_Msk              (0x5UL << I2C_OAR2_OA2MASK05_Pos)       /*!< 0x00000500 */
#define I2C_OAR2_OA2MASK05                  I2C_OAR2_OA2MASK05_Msk                  /*!< OA2[5:1] is masked, Only OA2[7:6] are compared */
#define I2C_OAR2_OA2MASK06_Pos              (9UL)
#define I2C_OAR2_OA2MASK06_Msk              (0x3UL << I2C_OAR2_OA2MASK06_Pos)       /*!< 0x00000600 */
#define I2C_OAR2_OA2MASK06                  I2C_OAR2_OA2MASK06_Msk                  /*!< OA2[6:1] is masked, Only OA2[7] are compared   */
#define I2C_OAR2_OA2MASK07_Pos              (8UL)
#define I2C_OAR2_OA2MASK07_Msk              (0x7UL << I2C_OAR2_OA2MASK07_Pos)       /*!< 0x00000700 */
#define I2C_OAR2_OA2MASK07                  I2C_OAR2_OA2MASK07_Msk                  /*!< OA2[7:1] is masked, No comparison is done      */
#define I2C_OAR2_OA2EN_Pos                  (15UL)
#define I2C_OAR2_OA2EN_Msk                  (0x1UL << I2C_OAR2_OA2EN_Pos)           /*!< 0x00008000 */
#define I2C_OAR2_OA2EN                      I2C_OAR2_OA2EN_Msk                      /*!< Own address 2 enable */

/*******************  Bit definition for I2C_TIMINGR register *******************/
#define I2C_TIMINGR_SCLL_Pos                (0UL)
#define I2C_TIMINGR_SCLL_Msk                (0xFFUL << I2C_TIMINGR_SCLL_Pos)        /*!< 0x000000FF */
#define I2C_TIMINGR_SCLL                    I2C_TIMINGR_SCLL_Msk                    /*!< SCL low period (master mode) */
#define I2C_TIMINGR_SCLH_Pos                (8UL)
#define I2C_TIMINGR_SCLH_Msk                (0xFFUL << I2C_TIMINGR_SCLH_Pos)        /*!< 0x0000FF00 */
#define I2C_TIMINGR_SCLH                    I2C_TIMINGR_SCLH_Msk                    /*!< SCL high period (master mode) */
#define I2C_TIMINGR_SDADEL_Pos              (16UL)
#define I2C_TIMINGR_SDADEL_Msk              (0xFUL << I2C_TIMINGR_SDADEL_Pos)       /*!< 0x000F0000 */
#define I2C_TIMINGR_SDADEL                  I2C_TIMINGR_SDADEL_Msk                  /*!< Data hold time */
#define I2C_TIMINGR_SCLDEL_Pos              (20UL)
#define I2C_TIMINGR_SCLDEL_Msk              (0xFUL << I2C_TIMINGR_SCLDEL_Pos)       /*!< 0x00F00000 */
#define I2C_TIMINGR_SCLDEL                  I2C_TIMINGR_SCLDEL_Msk                  /*!< Data setup time */
#define I2C_TIMINGR_PRESC_Pos               (28UL)
#define I2C_TIMINGR_PRESC_Msk               (0xFUL << I2C_TIMINGR_PRESC_Pos)        /*!< 0xF0000000 */
#define I2C_TIMINGR_PRESC                   I2C_TIMINGR_PRESC_Msk                   /*!< Timings prescaler */

/******************* Bit definition for I2C_TIMEOUTR register *******************/
#define I2C_TIMEOUTR_TIMEOUTA_Pos           (0UL)
#define I2C_TIMEOUTR_TIMEOUTA_Msk           (0xFFFUL << I2C_TIMEOUTR_TIMEOUTA_Pos)  /*!< 0x00000FFF */
#define I2C_TIMEOUTR_TIMEOUTA               I2C_TIMEOUTR_TIMEOUTA_Msk               /*!< Bus timeout A */
#define I2C_TIMEOUTR_TIDLE_Pos              (12UL)
#define I2C_TIMEOUTR_TIDLE_Msk              (0x1UL << I2C_TIMEOUTR_TIDLE_Pos)       /*!< 0x00001000 */
#define I2C_TIMEOUTR_TIDLE                  I2C_TIMEOUTR_TIDLE_Msk                  /*!< Idle clock timeout detection */
#define I2C_TIMEOUTR_TIMOUTEN_Pos           (15UL)
#define I2C_TIMEOUTR_TIMOUTEN_Msk           (0x1UL << I2C_TIMEOUTR_TIMOUTEN_Pos)    /*!< 0x00008000 */
#define I2C_TIMEOUTR_TIMOUTEN               I2C_TIMEOUTR_TIMOUTEN_Msk               /*!< Clock timeout enable */
#define I2C_TIMEOUTR_TIMEOUTB_Pos           (16UL)
#define I2C_TIMEOUTR_TIMEOUTB_Msk           (0xFFFUL << I2C_TIMEOUTR_TIMEOUTB_Pos)  /*!< 0x0FFF0000 */
#define I2C_TIMEOUTR_TIMEOUTB               I2C_TIMEOUTR_TIMEOUTB_Msk               /*!< Bus timeout B*/
#define I2C_TIMEOUTR_TEXTEN_Pos             (31UL)
#define I2C_TIMEOUTR_TEXTEN_Msk             (0x1UL << I2C_TIMEOUTR_TEXTEN_Pos)      /*!< 0x80000000 */
#define I2C_TIMEOUTR_TEXTEN                 I2C_TIMEOUTR_TEXTEN_Msk                 /*!< Extended clock timeout enable */

/******************  Bit definition for I2C_ISR register  *********************/
#define I2C_ISR_TXE_Pos                     (0UL)
#define I2C_ISR_TXE_Msk                     (0x1UL << I2C_ISR_TXE_Pos)              /*!< 0x00000001 */
#define I2C_ISR_TXE                         I2C_ISR_TXE_Msk                         /*!< Transmit data register empty */
#define I2C_ISR_TXIS_Pos                    (1UL)
#define I2C_ISR_TXIS_Msk                    (0x1UL << I2C_ISR_TXIS_Pos)             /*!< 0x00000002 */
#define I2C_ISR_TXIS                        I2C_ISR_TXIS_Msk                        /*!< Transmit interrupt status */
#define I2C_ISR_RXNE_Pos                    (2UL)
#define I2C_ISR_RXNE_Msk                    (0x1UL << I2C_ISR_RXNE_Pos)             /*!< 0x00000004 */
#define I2C_ISR_RXNE                        I2C_ISR_RXNE_Msk                        /*!< Receive data register not empty */
#define I2C_ISR_ADDR_Pos                    (3UL)
#define I2C_ISR_ADDR_Msk                    (0x1UL << I2C_ISR_ADDR_Pos)             /*!< 0x00000008 */
#define I2C_ISR_ADDR                        I2C_ISR_ADDR_Msk                        /*!< Address matched (slave mode)*/
#define I2C_ISR_NACKF_Pos                   (4UL)
#define I2C_ISR_NACKF_Msk                   (0x1UL << I2C_ISR_NACKF_Pos)            /*!< 0x00000010 */
#define I2C_ISR_NACKF                       I2C_ISR_NACKF_Msk                       /*!< NACK received flag */
#define I2C_ISR_STOPF_Pos                   (5UL)
#define I2C_ISR_STOPF_Msk                   (0x1UL << I2C_ISR_STOPF_Pos)            /*!< 0x00000020 */
#define I2C_ISR_STOPF                       I2C_ISR_STOPF_Msk                       /*!< STOP detection flag */
#define I2C_ISR_TC_Pos                      (6UL)
#define I2C_ISR_TC_Msk                      (0x1UL << I2C_ISR_TC_Pos)               /*!< 0x00000040 */
#define I2C_ISR_TC                          I2C_ISR_TC_Msk                          /*!< Transfer complete (master mode) */
#define I2C_ISR_TCR_Pos                     (7UL)
#define I2C_ISR_TCR_Msk                     (0x1UL << I2C_ISR_TCR_Pos)              /*!< 0x00000080 */
#define I2C_ISR_TCR                         I2C_ISR_TCR_Msk                         /*!< Transfer complete reload */
#define I2C_ISR_BERR_Pos                    (8UL)
#define I2C_ISR_BERR_Msk                    (0x1UL << I2C_ISR_BERR_Pos)             /*!< 0x00000100 */
#define I2C_ISR_BERR                        I2C_ISR_BERR_Msk                        /*!< Bus error */
#define I2C_ISR_ARLO_Pos                    (9UL)
#define I2C_ISR_ARLO_Msk                    (0x1UL << I2C_ISR_ARLO_Pos)             /*!< 0x00000200 */
#define I2C_ISR_ARLO                        I2C_ISR_ARLO_Msk                        /*!< Arbitration lost */
#define I2C_ISR_OVR_Pos                     (10UL)
#define I2C_ISR_OVR_Msk                     (0x1UL << I2C_ISR_OVR_Pos)              /*!< 0x00000400 */
#define I2C_ISR_OVR                         I2C_ISR_OVR_Msk                         /*!< Overrun/Underrun */
#define I2C_ISR_PECERR_Pos                  (11UL)
#define I2C_ISR_PECERR_Msk                  (0x1UL << I2C_ISR_PECERR_Pos)           /*!< 0x00000800 */
#define I2C_ISR_PECERR                      I2C_ISR_PECERR_Msk                      /*!< PEC error in reception */
#define I2C_ISR_TIMEOUT_Pos                 (12UL)
#define I2C_ISR_TIMEOUT_Msk                 (0x1UL << I2C_ISR_TIMEOUT_Pos)          /*!< 0x00001000 */
#define I2C_ISR_TIMEOUT                     I2C_ISR_TIMEOUT_Msk                     /*!< Timeout or Tlow detection flag */
#define I2C_ISR_ALERT_Pos                   (13UL)
#define I2C_ISR_ALERT_Msk                   (0x1UL << I2C_ISR_ALERT_Pos)            /*!< 0x00002000 */
#define I2C_ISR_ALERT                       I2C_ISR_ALERT_Msk                       /*!< SMBus alert */
#define I2C_ISR_BUSY_Pos                    (15UL)
#define I2C_ISR_BUSY_Msk                    (0x1UL << I2C_ISR_BUSY_Pos)             /*!< 0x00008000 */
#define I2C_ISR_BUSY                        I2C_ISR_BUSY_Msk                        /*!< Bus busy */
#define I2C_ISR_DIR_Pos                     (16UL)
#define I2C_ISR_DIR_Msk                     (0x1UL << I2C_ISR_DIR_Pos)              /*!< 0x00010000 */
#define I2C_ISR_DIR                         I2C_ISR_DIR_Msk                         /*!< Transfer direction (slave mode) */
#define I2C_ISR_ADDCODE_Pos                 (17UL)
#define I2C_ISR_ADDCODE_Msk                 (0x7FUL << I2C_ISR_ADDCODE_Pos)         /*!< 0x00FE0000 */
#define I2C_ISR_ADDCODE                     I2C_ISR_ADDCODE_Msk                     /*!< Address match code (slave mode) */

/******************  Bit definition for I2C_ICR register  *********************/
#define I2C_ICR_ADDRCF_Pos                  (3UL)
#define I2C_ICR_ADDRCF_Msk                  (0x1UL << I2C_ICR_ADDRCF_Pos)           /*!< 0x00000008 */
#define I2C_ICR_ADDRCF                      I2C_ICR_ADDRCF_Msk                      /*!< Address matched clear flag */
#define I2C_ICR_NACKCF_Pos                  (4UL)
#define I2C_ICR_NACKCF_Msk                  (0x1UL << I2C_ICR_NACKCF_Pos)           /*!< 0x00000010 */
#define I2C_ICR_NACKCF                      I2C_ICR_NACKCF_Msk                      /*!< NACK clear flag */
#define I2C_ICR_STOPCF_Pos                  (5UL)
#define I2C_ICR_STOPCF_Msk                  (0x1UL << I2C_ICR_STOPCF_Pos)           /*!< 0x00000020 */
#define I2C_ICR_STOPCF                      I2C_ICR_STOPCF_Msk                      /*!< STOP detection clear flag */
#define I2C_ICR_BERRCF_Pos                  (8UL)
#define I2C_ICR_BERRCF_Msk                  (0x1UL << I2C_ICR_BERRCF_Pos)           /*!< 0x00000100 */
#define I2C_ICR_BERRCF                      I2C_ICR_BERRCF_Msk                      /*!< Bus error clear flag */
#define I2C_ICR_ARLOCF_Pos                  (9UL)
#define I2C_ICR_ARLOCF_Msk                  (0x1UL << I2C_ICR_ARLOCF_Pos)           /*!< 0x00000200 */
#define I2C_ICR_ARLOCF                      I2C_ICR_ARLOCF_Msk                      /*!< Arbitration lost clear flag */
#define I2C_ICR_OVRCF_Pos                   (10UL)
#define I2C_ICR_OVRCF_Msk                   (0x1UL << I2C_ICR_OVRCF_Pos)            /*!< 0x00000400 */
#define I2C_ICR_OVRCF                       I2C_ICR_OVRCF_Msk                       /*!< Overrun/Underrun clear flag */
#define I2C_ICR_PECCF_Pos                   (11UL)
#define I2C_ICR_PECCF_Msk                   (0x1UL << I2C_ICR_PECCF_Pos)            /*!< 0x00000800 */
#define I2C_ICR_PECCF                       I2C_ICR_PECCF_Msk                       /*!< PAC error clear flag */
#define I2C_ICR_TIMOUTCF_Pos                (12UL)
#define I2C_ICR_TIMOUTCF_Msk                (0x1UL << I2C_ICR_TIMOUTCF_Pos)         /*!< 0x00001000 */
#define I2C_ICR_TIMOUTCF                    I2C_ICR_TIMOUTCF_Msk                    /*!< Timeout clear flag */
#define I2C_ICR_ALERTCF_Pos                 (13UL)
#define I2C_ICR_ALERTCF_Msk                 (0x1UL << I2C_ICR_ALERTCF_Pos)          /*!< 0x00002000 */
#define I2C_ICR_ALERTCF                     I2C_ICR_ALERTCF_Msk                     /*!< Alert clear flag */

/******************  Bit definition for I2C_PECR register  *********************/
#define I2C_PECR_PEC_Pos                    (0UL)
#define I2C_PECR_PEC_Msk                    (0xFFUL << I2C_PECR_PEC_Pos)            /*!< 0x000000FF */
#define I2C_PECR_PEC                        I2C_PECR_PEC_Msk                        /*!< PEC register */

/******************  Bit definition for I2C_RXDR register  *********************/
#define I2C_RXDR_RXDATA_Pos                 (0UL)
#define I2C_RXDR_RXDATA_Msk                 (0xFFUL << I2C_RXDR_RXDATA_Pos)         /*!< 0x000000FF */
#define I2C_RXDR_RXDATA                     I2C_RXDR_RXDATA_Msk                     /*!< 8-bit receive data */

/******************  Bit definition for I2C_TXDR register  *********************/
#define I2C_TXDR_TXDATA_Pos                 (0UL)
#define I2C_TXDR_TXDATA_Msk                 (0xFFUL << I2C_TXDR_TXDATA_Pos)         /*!< 0x000000FF */
#define I2C_TXDR_TXDATA                     I2C_TXDR_TXDATA_Msk                     /*!< 8-bit transmit data */

/******************  Bit definition for I2C_AUTOCR register  ********************/
#define I2C_AUTOCR_TCDMAEN_Pos              (6UL)
#define I2C_AUTOCR_TCDMAEN_Msk              (0x1UL << I2C_AUTOCR_TCDMAEN_Pos)       /*!< 0x00000040 */
#define I2C_AUTOCR_TCDMAEN                  I2C_AUTOCR_TCDMAEN_Msk                  /*!< DMA request enable on Transfer Complete event */
#define I2C_AUTOCR_TCRDMAEN_Pos             (7UL)
#define I2C_AUTOCR_TCRDMAEN_Msk             (0x1UL << I2C_AUTOCR_TCRDMAEN_Pos)      /*!< 0x00000080 */
#define I2C_AUTOCR_TCRDMAEN                 I2C_AUTOCR_TCRDMAEN_Msk                 /*!< DMA request enable on Transfer Complete Reload event */
#define I2C_AUTOCR_TRIGSEL_Pos              (16UL)
#define I2C_AUTOCR_TRIGSEL_Msk              (0xFUL << I2C_AUTOCR_TRIGSEL_Pos)       /*!< 0x000F0000 */
#define I2C_AUTOCR_TRIGSEL                  I2C_AUTOCR_TRIGSEL_Msk                  /*!< Trigger selection */
#define I2C_AUTOCR_TRIGPOL_Pos              (20UL)
#define I2C_AUTOCR_TRIGPOL_Msk              (0x1UL << I2C_AUTOCR_TRIGPOL_Pos)       /*!< 0x000100000 */
#define I2C_AUTOCR_TRIGPOL                  I2C_AUTOCR_TRIGPOL_Msk                  /*!< Trigger polarity */
#define I2C_AUTOCR_TRIGEN_Pos               (21UL)
#define I2C_AUTOCR_TRIGEN_Msk               (0x1UL << I2C_AUTOCR_TRIGEN_Pos)        /*!< 0x000200000 */
#define I2C_AUTOCR_TRIGEN                   I2C_AUTOCR_TRIGEN_Msk                   /*!< Trigger enable */

/******************************************************************************/
/*                                                                            */
/*             Improved Inter-integrated Circuit Interface (I3C)              */
/*                                                                            */
/******************************************************************************/
/*******************  Bit definition for I3C_CR register  *********************/
#define I3C_CR_DCNT_Pos                     (0UL)
#define I3C_CR_DCNT_Msk                     (0xFFFFUL << I3C_CR_DCNT_Pos)           /*!< 0x0000FFFF */
#define I3C_CR_DCNT                         I3C_CR_DCNT_Msk                         /*!< Data Byte Count */
#define I3C_CR_RNW_Pos                      (16UL)
#define I3C_CR_RNW_Msk                      (0x1UL << I3C_CR_RNW_Pos)               /*!< 0x00010000 */
#define I3C_CR_RNW                          I3C_CR_RNW_Msk                          /*!< Read Not Write */
#define I3C_CR_CCC_Pos                      (16UL)
#define I3C_CR_CCC_Msk                      (0xFFUL << I3C_CR_CCC_Pos)              /*!< 0x00FF0000 */
#define I3C_CR_CCC                          I3C_CR_CCC_Msk                          /*!< 8-Bit CCC code */
#define I3C_CR_ADD_Pos                      (17UL)
#define I3C_CR_ADD_Msk                      (0x7FUL << I3C_CR_ADD_Pos)              /*!< 0x00FE0000 */
#define I3C_CR_ADD                          I3C_CR_ADD_Msk                          /*!< Target Address */
#define I3C_CR_MTYPE_Pos                    (27UL)
#define I3C_CR_MTYPE_Msk                    (0xFUL << I3C_CR_MTYPE_Pos)             /*!< 0xF8000000 */
#define I3C_CR_MTYPE                        I3C_CR_MTYPE_Msk                        /*!< Message Type */
#define I3C_CR_MTYPE_0                      (0x1UL << I3C_CR_MTYPE_Pos)             /*!< 0x08000000 */
#define I3C_CR_MTYPE_1                      (0x2UL << I3C_CR_MTYPE_Pos)             /*!< 0x10000000 */
#define I3C_CR_MTYPE_2                      (0x4UL << I3C_CR_MTYPE_Pos)             /*!< 0x20000000 */
#define I3C_CR_MTYPE_3                      (0x8UL << I3C_CR_MTYPE_Pos)             /*!< 0x40000000 */
#define I3C_CR_MEND_Pos                     (31UL)
#define I3C_CR_MEND_Msk                     (0x1UL << I3C_CR_MEND_Pos)              /*!< 0x80000000 */
#define I3C_CR_MEND                         I3C_CR_MEND_Msk                         /*!< Message End */

/*******************  Bit definition for I3C_CFGR register  *******************/
#define I3C_CFGR_EN_Pos                     (0UL)
#define I3C_CFGR_EN_Msk                     (0x1UL << I3C_CFGR_EN_Pos)              /*!< 0x00000001 */
#define I3C_CFGR_EN                         I3C_CFGR_EN_Msk                         /*!< Peripheral Enable */
#define I3C_CFGR_CRINIT_Pos                 (1UL)
#define I3C_CFGR_CRINIT_Msk                 (0x1UL << I3C_CFGR_CRINIT_Pos)          /*!< 0x00000002 */
#define I3C_CFGR_CRINIT                     I3C_CFGR_CRINIT_Msk                     /*!< Peripheral Init mode (Target/Controller) */
#define I3C_CFGR_NOARBH_Pos                 (2UL)
#define I3C_CFGR_NOARBH_Msk                 (0x1UL << I3C_CFGR_NOARBH_Pos)          /*!< 0x00000004 */
#define I3C_CFGR_NOARBH                     I3C_CFGR_NOARBH_Msk                     /*!< No Arbitration Header (7'h7E)*/
#define I3C_CFGR_RSTPTRN_Pos                (3UL)
#define I3C_CFGR_RSTPTRN_Msk                (0x1UL << I3C_CFGR_RSTPTRN_Pos)         /*!< 0x00000008 */
#define I3C_CFGR_RSTPTRN                    I3C_CFGR_RSTPTRN_Msk                    /*!< Reset Pattern enable */
#define I3C_CFGR_EXITPTRN_Pos               (4UL)
#define I3C_CFGR_EXITPTRN_Msk               (0x1UL << I3C_CFGR_EXITPTRN_Pos)        /*!< 0x00000010 */
#define I3C_CFGR_EXITPTRN                   I3C_CFGR_EXITPTRN_Msk                   /*!< Exit Pattern enable */
#define I3C_CFGR_HKSDAEN_Pos                (5UL)
#define I3C_CFGR_HKSDAEN_Msk                (0x1UL << I3C_CFGR_HKSDAEN_Pos)         /*!< 0x00000020 */
#define I3C_CFGR_HKSDAEN                    I3C_CFGR_HKSDAEN_Msk                    /*!< High-Keeper on SDA Enable */
#define I3C_CFGR_HJACK_Pos                  (7UL)
#define I3C_CFGR_HJACK_Msk                  (0x1UL << I3C_CFGR_HJACK_Pos)           /*!< 0x00000080 */
#define I3C_CFGR_HJACK                      I3C_CFGR_HJACK_Msk                      /*!< Hot Join Acknowledgment */
#define I3C_CFGR_RXDMAEN_Pos                (8UL)
#define I3C_CFGR_RXDMAEN_Msk                (0x1UL << I3C_CFGR_RXDMAEN_Pos)         /*!< 0x00000100 */
#define I3C_CFGR_RXDMAEN                    I3C_CFGR_RXDMAEN_Msk                    /*!< RX FIFO DMA mode Enable */
#define I3C_CFGR_RXFLUSH_Pos                (9UL)
#define I3C_CFGR_RXFLUSH_Msk                (0x1UL << I3C_CFGR_RXFLUSH_Pos)         /*!< 0x00000200 */
#define I3C_CFGR_RXFLUSH                    I3C_CFGR_RXFLUSH_Msk                    /*!< RX FIFO Flush */
#define I3C_CFGR_RXTHRES_Pos                (10UL)
#define I3C_CFGR_RXTHRES_Msk                (0x1UL << I3C_CFGR_RXTHRES_Pos)         /*!< 0x00000400 */
#define I3C_CFGR_RXTHRES                    I3C_CFGR_RXTHRES_Msk                    /*!< RX FIFO Threshold */
#define I3C_CFGR_TXDMAEN_Pos                (12UL)
#define I3C_CFGR_TXDMAEN_Msk                (0x1UL << I3C_CFGR_TXDMAEN_Pos)         /*!< 0x00001000 */
#define I3C_CFGR_TXDMAEN                    I3C_CFGR_TXDMAEN_Msk                    /*!< TX FIFO DMA mode Enable */
#define I3C_CFGR_TXFLUSH_Pos                (13UL)
#define I3C_CFGR_TXFLUSH_Msk                (0x1UL << I3C_CFGR_TXFLUSH_Pos)         /*!< 0x00002000 */
#define I3C_CFGR_TXFLUSH                    I3C_CFGR_TXFLUSH_Msk                    /*!< TX FIFO Flush */
#define I3C_CFGR_TXTHRES_Pos                (14UL)
#define I3C_CFGR_TXTHRES_Msk                (0x1UL << I3C_CFGR_TXTHRES_Pos)         /*!< 0x00004000 */
#define I3C_CFGR_TXTHRES                    I3C_CFGR_TXTHRES_Msk                    /*!< TX FIFO Threshold */
#define I3C_CFGR_SDMAEN_Pos                 (16UL)
#define I3C_CFGR_SDMAEN_Msk                 (0x1UL << I3C_CFGR_SDMAEN_Pos)          /*!< 0x00010000 */
#define I3C_CFGR_SDMAEN                     I3C_CFGR_SDMAEN_Msk                     /*!< Status FIFO DMA mode Enable */
#define I3C_CFGR_SFLUSH_Pos                 (17UL)
#define I3C_CFGR_SFLUSH_Msk                 (0x1UL << I3C_CFGR_SFLUSH_Pos)          /*!< 0x00020000 */
#define I3C_CFGR_SFLUSH                     I3C_CFGR_SFLUSH_Msk                     /*!< Status FIFO Flush */
#define I3C_CFGR_SMODE_Pos                  (18UL)
#define I3C_CFGR_SMODE_Msk                  (0x1UL << I3C_CFGR_SMODE_Pos)           /*!< 0x00040000 */
#define I3C_CFGR_SMODE                      I3C_CFGR_SMODE_Msk                      /*!< Status FIFO mode Enable */
#define I3C_CFGR_TMODE_Pos                  (19UL)
#define I3C_CFGR_TMODE_Msk                  (0x1UL << I3C_CFGR_TMODE_Pos)           /*!< 0x00080000 */
#define I3C_CFGR_TMODE                      I3C_CFGR_TMODE_Msk                      /*!< Control FIFO mode Enable */
#define I3C_CFGR_CDMAEN_Pos                 (20UL)
#define I3C_CFGR_CDMAEN_Msk                 (0x1UL << I3C_CFGR_CDMAEN_Pos)          /*!< 0x00100000 */
#define I3C_CFGR_CDMAEN                     I3C_CFGR_CDMAEN_Msk                     /*!< Control FIFO DMA mode Enable */
#define I3C_CFGR_CFLUSH_Pos                 (21UL)
#define I3C_CFGR_CFLUSH_Msk                 (0x1UL << I3C_CFGR_CFLUSH_Pos)          /*!< 0x00200000 */
#define I3C_CFGR_CFLUSH                     I3C_CFGR_CFLUSH_Msk                     /*!< Control FIFO Flush */
#define I3C_CFGR_FCFDIS_Pos                 (23UL)
#define I3C_CFGR_FCFDIS_Msk                 (0x1UL << I3C_CFGR_FCFDIS_Pos)          /*!< 0x00800000 */
#define I3C_CFGR_FCFDIS                     I3C_CFGR_FCFDIS_Msk                     /*!< FCF generation disable */
#define I3C_CFGR_TRIGSEL_Pos                (24UL)
#define I3C_CFGR_TRIGSEL_Msk                (0xFUL << I3C_CFGR_TRIGSEL_Pos)         /*!< 0x0F000000 */
#define I3C_CFGR_TRIGSEL                    I3C_CFGR_TRIGSEL_Msk                    /*!< Trigger selection */
#define I3C_CFGR_TRIGPOL_Pos                (28UL)
#define I3C_CFGR_TRIGPOL_Msk                (0x1UL << I3C_CFGR_TRIGPOL_Pos)         /*!< 0x10000000 */
#define I3C_CFGR_TRIGPOL                    I3C_CFGR_TRIGPOL_Msk                    /*!< Trigger polarity */
#define I3C_CFGR_TRIGHWEN_Pos               (29UL)
#define I3C_CFGR_TRIGHWEN_Msk               (0x1UL << I3C_CFGR_TRIGHWEN_Pos)        /*!< 0x20000000 */
#define I3C_CFGR_TRIGHWEN                   I3C_CFGR_TRIGHWEN_Msk                   /*!< Trigger enable */
#define I3C_CFGR_TSFSET_Pos                 (30UL)
#define I3C_CFGR_TSFSET_Msk                 (0x1UL << I3C_CFGR_TSFSET_Pos)          /*!< 0x40000000 */
#define I3C_CFGR_TSFSET                     I3C_CFGR_TSFSET_Msk                     /*!< Transfer Set */

/*******************  Bit definition for I3C_RDR register  ********************/
#define I3C_RDR_RDB0_Pos                    (0UL)
#define I3C_RDR_RDB0_Msk                    (0xFFUL << I3C_RDR_RDB0_Pos)            /*!< 0x000000FF */
#define I3C_RDR_RDB0                        I3C_RDR_RDB0_Msk                        /*!< Receive Data Byte */

/******************  Bit definition for I3C_RDWR register  ********************/
#define I3C_RDWR_RDBx_Pos                   (0UL)
#define I3C_RDWR_RDBx_Msk                   (0xFFFFFFFFUL << I3C_RDWR_RDBx_Pos)     /*!< 0xFFFFFFFF */
#define I3C_RDWR_RDBx                       I3C_RDWR_RDBx_Msk                       /*!< Receive Data Byte, full double word */
#define I3C_RDWR_RDB0_Pos                   (0UL)
#define I3C_RDWR_RDB0_Msk                   (0xFFUL << I3C_RDWR_RDB0_Pos)           /*!< 0x000000FF */
#define I3C_RDWR_RDB0                       I3C_RDWR_RDB0_Msk                       /*!< Receive Data Byte 0 */
#define I3C_RDWR_RDB1_Pos                   (8UL)
#define I3C_RDWR_RDB1_Msk                   (0xFFUL << I3C_RDWR_RDB1_Pos)           /*!< 0x0000FF00 */
#define I3C_RDWR_RDB1                       I3C_RDWR_RDB1_Msk                       /*!< Receive Data Byte 1 */
#define I3C_RDWR_RDB2_Pos                   (16UL)
#define I3C_RDWR_RDB2_Msk                   (0xFFUL << I3C_RDWR_RDB2_Pos)           /*!< 0x00FF0000 */
#define I3C_RDWR_RDB2                       I3C_RDWR_RDB2_Msk                       /*!< Receive Data Byte 2 */
#define I3C_RDWR_RDB3_Pos                   (24UL)
#define I3C_RDWR_RDB3_Msk                   (0xFFUL << I3C_RDWR_RDB3_Pos)           /*!< 0xFF000000 */
#define I3C_RDWR_RDB3                       I3C_RDWR_RDB3_Msk                       /*!< Receive Data Byte 3 */

/*******************  Bit definition for I3C_TDR register  ********************/
#define I3C_TDR_TDB0_Pos                    (0UL)
#define I3C_TDR_TDB0_Msk                    (0xFFUL << I3C_TDR_TDB0_Pos)            /*!< 0x000000FF */
#define I3C_TDR_TDB0                        I3C_TDR_TDB0_Msk                        /*!< Transmit Data Byte */

/******************  Bit definition for I3C_TDWR register  ********************/
#define I3C_TDWR_TDBx_Pos                   (0UL)
#define I3C_TDWR_TDBx_Msk                   (0xFFFFFFFFUL << I3C_TDWR_TDBx_Pos)     /*!< 0xFFFFFFFF */
#define I3C_TDWR_TDBx                       I3C_TDWR_TDBx_Msk                       /*!< Transmit Data Byte, full double word */
#define I3C_TDWR_TDB0_Pos                   (0UL)
#define I3C_TDWR_TDB0_Msk                   (0xFFUL << I3C_TDWR_TDB0_Pos)           /*!< 0x000000FF */
#define I3C_TDWR_TDB0                       I3C_TDWR_TDB0_Msk                       /*!< Transmit Data Byte 0 */
#define I3C_TDWR_TDB1_Pos                   (8UL)
#define I3C_TDWR_TDB1_Msk                   (0xFFUL << I3C_TDWR_TDB1_Pos)           /*!< 0x0000FF00 */
#define I3C_TDWR_TDB1                       I3C_TDWR_TDB1_Msk                       /*!< Transmit Data Byte 1 */
#define I3C_TDWR_TDB2_Pos                   (16UL)
#define I3C_TDWR_TDB2_Msk                   (0xFFUL << I3C_TDWR_TDB2_Pos)           /*!< 0x00FF0000 */
#define I3C_TDWR_TDB2                       I3C_TDWR_TDB2_Msk                       /*!< Transmit Data Byte 2 */
#define I3C_TDWR_TDB3_Pos                   (24UL)
#define I3C_TDWR_TDB3_Msk                   (0xFFUL << I3C_TDWR_TDB3_Pos)           /*!< 0xFF000000 */
#define I3C_TDWR_TDB3                       I3C_TDWR_TDB3_Msk                       /*!< Transmit Data Byte 3 */

/*******************  Bit definition for I3C_IBIDR register  ******************/
#define I3C_IBIDR_IBIDBx_Pos                (0UL)
#define I3C_IBIDR_IBIDBx_Msk                (0xFFFFFFFFUL << I3C_IBIDR_IBIDBx_Pos)  /*!< 0xFFFFFFFF */
#define I3C_IBIDR_IBIDBx                    I3C_IBIDR_IBIDBx_Msk                    /*!< IBI Data Byte, full double word */
#define I3C_IBIDR_IBIDB0_Pos                (0UL)
#define I3C_IBIDR_IBIDB0_Msk                (0xFFUL << I3C_IBIDR_IBIDB0_Pos)        /*!< 0x000000FF */
#define I3C_IBIDR_IBIDB0                    I3C_IBIDR_IBIDB0_Msk                    /*!< IBI Data Byte 0 */
#define I3C_IBIDR_IBIDB1_Pos                (8UL)
#define I3C_IBIDR_IBIDB1_Msk                (0xFFUL << I3C_IBIDR_IBIDB1_Pos)        /*!< 0x0000FF00 */
#define I3C_IBIDR_IBIDB1                    I3C_IBIDR_IBIDB1_Msk                    /*!< IBI Data Byte 1 */
#define I3C_IBIDR_IBIDB2_Pos                (16UL)
#define I3C_IBIDR_IBIDB2_Msk                (0xFFUL << I3C_IBIDR_IBIDB2_Pos)        /*!< 0x00FF0000 */
#define I3C_IBIDR_IBIDB2                    I3C_IBIDR_IBIDB2_Msk                    /*!< IBI Data Byte 2 */
#define I3C_IBIDR_IBIDB3_Pos                (24UL)
#define I3C_IBIDR_IBIDB3_Msk                (0xFFUL << I3C_IBIDR_IBIDB3_Pos)        /*!< 0xFF000000 */
#define I3C_IBIDR_IBIDB3                    I3C_IBIDR_IBIDB3_Msk                    /*!< IBI Data Byte 3 */

/******************  Bit definition for I3C_TGTTDR register  ******************/
#define I3C_TGTTDR_TGTTDCNT_Pos             (0UL)
#define I3C_TGTTDR_TGTTDCNT_Msk             (0xFFFFUL << I3C_TGTTDR_TGTTDCNT_Pos)   /*!< 0x0000FFFF */
#define I3C_TGTTDR_TGTTDCNT                 I3C_TGTTDR_TGTTDCNT_Msk                 /*!< Target Transmit Data Counter */
#define I3C_TGTTDR_PRELOAD_Pos              (16UL)
#define I3C_TGTTDR_PRELOAD_Msk              (0x1UL << I3C_TGTTDR_PRELOAD_Pos)       /*!< 0x00010000 */
#define I3C_TGTTDR_PRELOAD                  I3C_TGTTDR_PRELOAD_Msk                  /*!< Transmit FIFO Preload Enable/Status */

/*******************  Bit definition for I3C_SR register  *********************/
#define I3C_SR_XDCNT_Pos                    (0UL)
#define I3C_SR_XDCNT_Msk                    (0xFFFFUL << I3C_SR_XDCNT_Pos)          /*!< 0x0000FFFF */
#define I3C_SR_XDCNT                        I3C_SR_XDCNT_Msk                        /*!< Transfer Data Byte Count status */
#define I3C_SR_ABT_Pos                      (17UL)
#define I3C_SR_ABT_Msk                      (0x1UL << I3C_SR_ABT_Pos)               /*!< 0x00020000 */
#define I3C_SR_ABT                          I3C_SR_ABT_Msk                          /*!< Target Abort Indication */
#define I3C_SR_DIR_Pos                      (18UL)
#define I3C_SR_DIR_Msk                      (0x1UL << I3C_SR_DIR_Pos)               /*!< 0x00040000 */
#define I3C_SR_DIR                          I3C_SR_DIR_Msk                          /*!< Message Direction */
#define I3C_SR_MID_Pos                      (24UL)
#define I3C_SR_MID_Msk                      (0xFFUL << I3C_SR_MID_Pos)              /*!< 0xFF000000 */
#define I3C_SR_MID                          I3C_SR_MID_Msk                          /*!< Message Identifier */

/*******************  Bit definition for I3C_SER register  ********************/
#define I3C_SER_CODERR_Pos                  (0UL)
#define I3C_SER_CODERR_Msk                  (0xFUL << I3C_SER_CODERR_Pos)           /*!< 0x0000000F */
#define I3C_SER_CODERR                      I3C_SER_CODERR_Msk                      /*!< Protocol Error Code */
#define I3C_SER_CODERR_0                    (0x1UL << I3C_SER_CODERR_Pos)           /*!< 0x00000001 */
#define I3C_SER_CODERR_1                    (0x2UL << I3C_SER_CODERR_Pos)           /*!< 0x00000002 */
#define I3C_SER_CODERR_2                    (0x4UL << I3C_SER_CODERR_Pos)           /*!< 0x00000004 */
#define I3C_SER_CODERR_3                    (0x8UL << I3C_SER_CODERR_Pos)           /*!< 0x00000008 */
#define I3C_SER_PERR_Pos                    (4UL)
#define I3C_SER_PERR_Msk                    (0x1UL << I3C_SER_PERR_Pos)             /*!< 0x00000010 */
#define I3C_SER_PERR                        I3C_SER_PERR_Msk                        /*!< Protocol Error */
#define I3C_SER_STALL_Pos                   (5UL)
#define I3C_SER_STALL_Msk                   (0x1UL << I3C_SER_STALL_Pos)            /*!< 0x00000020 */
#define I3C_SER_STALL                       I3C_SER_STALL_Msk                       /*!< SCL Stall Error */
#define I3C_SER_DOVR_Pos                    (6UL)
#define I3C_SER_DOVR_Msk                    (0x1UL << I3C_SER_DOVR_Pos)             /*!< 0x00000040 */
#define I3C_SER_DOVR                        I3C_SER_DOVR_Msk                        /*!< RX/TX FIFO Overrun */
#define I3C_SER_COVR_Pos                    (7UL)
#define I3C_SER_COVR_Msk                    (0x1UL << I3C_SER_COVR_Pos)             /*!< 0x00000080 */
#define I3C_SER_COVR                        I3C_SER_COVR_Msk                        /*!< Status/Control FIFO Overrun */
#define I3C_SER_ANACK_Pos                   (8UL)
#define I3C_SER_ANACK_Msk                   (0x1UL << I3C_SER_ANACK_Pos)            /*!< 0x00000100 */
#define I3C_SER_ANACK                       I3C_SER_ANACK_Msk                       /*!< Address Not Acknowledged */
#define I3C_SER_DNACK_Pos                   (9UL)
#define I3C_SER_DNACK_Msk                   (0x1UL << I3C_SER_DNACK_Pos)            /*!< 0x00000200 */
#define I3C_SER_DNACK                       I3C_SER_DNACK_Msk                       /*!< Data Not Acknowledged */
#define I3C_SER_DERR_Pos                    (10UL)
#define I3C_SER_DERR_Msk                    (0x1UL << I3C_SER_DERR_Pos)             /*!< 0x00000400 */
#define I3C_SER_DERR                        I3C_SER_DERR_Msk                        /*!< Data Error during the controller-role hand-off procedure */

/*******************  Bit definition for I3C_RMR register  ********************/
#define I3C_RMR_IBIRDCNT_Pos                (0UL)
#define I3C_RMR_IBIRDCNT_Msk                (0x7UL << I3C_RMR_IBIRDCNT_Pos)         /*!< 0x00000007 */
#define I3C_RMR_IBIRDCNT                    I3C_RMR_IBIRDCNT_Msk                    /*!< Data Count when reading IBI data */
#define I3C_RMR_RCODE_Pos                   (8UL)
#define I3C_RMR_RCODE_Msk                   (0xFFUL << I3C_RMR_RCODE_Pos)           /*!< 0x0000FF00 */
#define I3C_RMR_RCODE                       I3C_RMR_RCODE_Msk                       /*!< CCC code of received command */
#define I3C_RMR_RADD_Pos                    (17UL)
#define I3C_RMR_RADD_Msk                    (0x7FUL << I3C_RMR_RADD_Pos)            /*!< 0x00FE0000 */
#define I3C_RMR_RADD                        I3C_RMR_RADD_Msk                        /*!< Target Address Received during accepted IBI or Controller-role request */

/*******************  Bit definition for I3C_EVR register  ********************/
#define I3C_EVR_CFEF_Pos                    (0UL)
#define I3C_EVR_CFEF_Msk                    (0x1UL << I3C_EVR_CFEF_Pos)             /*!< 0x00000001 */
#define I3C_EVR_CFEF                        I3C_EVR_CFEF_Msk                        /*!< Control FIFO Empty Flag */
#define I3C_EVR_TXFEF_Pos                   (1UL)
#define I3C_EVR_TXFEF_Msk                   (0x1UL << I3C_EVR_TXFEF_Pos)            /*!< 0x00000002 */
#define I3C_EVR_TXFEF                       I3C_EVR_TXFEF_Msk                       /*!< TX FIFO Empty Flag */
#define I3C_EVR_CFNFF_Pos                   (2UL)
#define I3C_EVR_CFNFF_Msk                   (0x1UL << I3C_EVR_CFNFF_Pos)            /*!< 0x00000004 */
#define I3C_EVR_CFNFF                       I3C_EVR_CFNFF_Msk                       /*!< Control FIFO Not Full Flag */
#define I3C_EVR_SFNEF_Pos                   (3UL)
#define I3C_EVR_SFNEF_Msk                   (0x1UL << I3C_EVR_SFNEF_Pos)            /*!< 0x00000008 */
#define I3C_EVR_SFNEF                       I3C_EVR_SFNEF_Msk                       /*!< Status FIFO Not Empty Flag */
#define I3C_EVR_TXFNFF_Pos                  (4UL)
#define I3C_EVR_TXFNFF_Msk                  (0x1UL << I3C_EVR_TXFNFF_Pos)           /*!< 0x00000010 */
#define I3C_EVR_TXFNFF                      I3C_EVR_TXFNFF_Msk                      /*!< TX FIFO Not Full Flag */
#define I3C_EVR_RXFNEF_Pos                  (5UL)
#define I3C_EVR_RXFNEF_Msk                  (0x1UL << I3C_EVR_RXFNEF_Pos)           /*!< 0x00000020 */
#define I3C_EVR_RXFNEF                      I3C_EVR_RXFNEF_Msk                      /*!< RX FIFO Not Empty Flag */
#define I3C_EVR_TXLASTF_Pos                 (6UL)
#define I3C_EVR_TXLASTF_Msk                 (0x1UL << I3C_EVR_TXLASTF_Pos)          /*!< 0x00000040 */
#define I3C_EVR_TXLASTF                     I3C_EVR_TXLASTF_Msk                     /*!< Last TX byte available in FIFO */
#define I3C_EVR_RXLASTF_Pos                 (7UL)
#define I3C_EVR_RXLASTF_Msk                 (0x1UL << I3C_EVR_RXLASTF_Pos)          /*!< 0x00000080 */
#define I3C_EVR_RXLASTF                     I3C_EVR_RXLASTF_Msk                     /*!< Last RX byte read from FIFO */
#define I3C_EVR_FCF_Pos                     (9UL)
#define I3C_EVR_FCF_Msk                     (0x1UL << I3C_EVR_FCF_Pos)              /*!< 0x00000200 */
#define I3C_EVR_FCF                         I3C_EVR_FCF_Msk                         /*!< Frame Complete Flag */
#define I3C_EVR_RXTGTENDF_Pos               (10UL)
#define I3C_EVR_RXTGTENDF_Msk               (0x1UL << I3C_EVR_RXTGTENDF_Pos)        /*!< 0x00000400 */
#define I3C_EVR_RXTGTENDF                   I3C_EVR_RXTGTENDF_Msk                   /*!< Reception Target End Flag */
#define I3C_EVR_ERRF_Pos                    (11UL)
#define I3C_EVR_ERRF_Msk                    (0x1UL << I3C_EVR_ERRF_Pos)             /*!< 0x00000800 */
#define I3C_EVR_ERRF                        I3C_EVR_ERRF_Msk                        /*!< Error Flag */
#define I3C_EVR_IBIF_Pos                    (15UL)
#define I3C_EVR_IBIF_Msk                    (0x1UL << I3C_EVR_IBIF_Pos)             /*!< 0x00008000 */
#define I3C_EVR_IBIF                        I3C_EVR_IBIF_Msk                        /*!< IBI Flag */
#define I3C_EVR_IBIENDF_Pos                 (16UL)
#define I3C_EVR_IBIENDF_Msk                 (0x1UL << I3C_EVR_IBIENDF_Pos)          /*!< 0x00010000 */
#define I3C_EVR_IBIENDF                     I3C_EVR_IBIENDF_Msk                     /*!< IBI End Flag */
#define I3C_EVR_CRF_Pos                     (17UL)
#define I3C_EVR_CRF_Msk                     (0x1UL << I3C_EVR_CRF_Pos)              /*!< 0x00020000 */
#define I3C_EVR_CRF                         I3C_EVR_CRF_Msk                         /*!< Controller-role Request Flag */
#define I3C_EVR_CRUPDF_Pos                  (18UL)
#define I3C_EVR_CRUPDF_Msk                  (0x1UL << I3C_EVR_CRUPDF_Pos)           /*!< 0x00040000 */
#define I3C_EVR_CRUPDF                      I3C_EVR_CRUPDF_Msk                      /*!< Controller-role Update Flag */
#define I3C_EVR_HJF_Pos                     (19UL)
#define I3C_EVR_HJF_Msk                     (0x1UL << I3C_EVR_HJF_Pos)              /*!< 0x00080000 */
#define I3C_EVR_HJF                         I3C_EVR_HJF_Msk                         /*!< Hot Join Flag */
#define I3C_EVR_WKPF_Pos                    (21UL)
#define I3C_EVR_WKPF_Msk                    (0x1UL << I3C_EVR_WKPF_Pos)             /*!< 0x00200000 */
#define I3C_EVR_WKPF                        I3C_EVR_WKPF_Msk                        /*!< Wake Up Flag */
#define I3C_EVR_GETF_Pos                    (22UL)
#define I3C_EVR_GETF_Msk                    (0x1UL << I3C_EVR_GETF_Pos)             /*!< 0x00400000 */
#define I3C_EVR_GETF                        I3C_EVR_GETF_Msk                        /*!< Get type CCC received Flag */
#define I3C_EVR_STAF_Pos                    (23UL)
#define I3C_EVR_STAF_Msk                    (0x1UL << I3C_EVR_STAF_Pos)             /*!< 0x00800000 */
#define I3C_EVR_STAF                        I3C_EVR_STAF_Msk                        /*!< Get Status Flag */
#define I3C_EVR_DAUPDF_Pos                  (24UL)
#define I3C_EVR_DAUPDF_Msk                  (0x1UL << I3C_EVR_DAUPDF_Pos)           /*!< 0x01000000 */
#define I3C_EVR_DAUPDF                      I3C_EVR_DAUPDF_Msk                      /*!< Dynamic Address Update Flag */
#define I3C_EVR_MWLUPDF_Pos                 (25UL)
#define I3C_EVR_MWLUPDF_Msk                 (0x1UL << I3C_EVR_MWLUPDF_Pos)          /*!< 0x02000000 */
#define I3C_EVR_MWLUPDF                     I3C_EVR_MWLUPDF_Msk                     /*!< Max Write Length Update Flag */
#define I3C_EVR_MRLUPDF_Pos                 (26UL)
#define I3C_EVR_MRLUPDF_Msk                 (0x1UL << I3C_EVR_MRLUPDF_Pos)          /*!< 0x04000000 */
#define I3C_EVR_MRLUPDF                     I3C_EVR_MRLUPDF_Msk                     /*!< Max Read Length Update Flag */
#define I3C_EVR_RSTF_Pos                    (27UL)
#define I3C_EVR_RSTF_Msk                    (0x1UL << I3C_EVR_RSTF_Pos)             /*!< 0x08000000 */
#define I3C_EVR_RSTF                        I3C_EVR_RSTF_Msk                        /*!< Reset Flag, due to Reset pattern received */
#define I3C_EVR_ASUPDF_Pos                  (28UL)
#define I3C_EVR_ASUPDF_Msk                  (0x1UL << I3C_EVR_ASUPDF_Pos)           /*!< 0x10000000 */
#define I3C_EVR_ASUPDF                      I3C_EVR_ASUPDF_Msk                      /*!< Activity State Flag */
#define I3C_EVR_INTUPDF_Pos                 (29UL)
#define I3C_EVR_INTUPDF_Msk                 (0x1UL << I3C_EVR_INTUPDF_Pos)          /*!< 0x20000000 */
#define I3C_EVR_INTUPDF                     I3C_EVR_INTUPDF_Msk                     /*!< Interrupt Update Flag */
#define I3C_EVR_DEFF_Pos                    (30UL)
#define I3C_EVR_DEFF_Msk                    (0x1UL << I3C_EVR_DEFF_Pos)             /*!< 0x40000000 */
#define I3C_EVR_DEFF                        I3C_EVR_DEFF_Msk                        /*!< List of Targets Command Received Flag */
#define I3C_EVR_GRPF_Pos                    (31UL)
#define I3C_EVR_GRPF_Msk                    (0x1UL << I3C_EVR_GRPF_Pos)             /*!< 0x80000000 */
#define I3C_EVR_GRPF                        I3C_EVR_GRPF_Msk                        /*!< List of Group Addresses Command Received Flag */

/*******************  Bit definition for I3C_IER register  ********************/
#define I3C_IER_CFNFIE_Pos                  (2UL)
#define I3C_IER_CFNFIE_Msk                  (0x1UL << I3C_IER_CFNFIE_Pos)           /*!< 0x00000004 */
#define I3C_IER_CFNFIE                      I3C_IER_CFNFIE_Msk                      /*!< Control FIFO Not Full Interrupt Enable */
#define I3C_IER_SFNEIE_Pos                  (3UL)
#define I3C_IER_SFNEIE_Msk                  (0x1UL << I3C_IER_SFNEIE_Pos)           /*!< 0x00000008 */
#define I3C_IER_SFNEIE                      I3C_IER_SFNEIE_Msk                      /*!< Status FIFO Not Empty Interrupt Enable */
#define I3C_IER_TXFNFIE_Pos                 (4UL)
#define I3C_IER_TXFNFIE_Msk                 (0x1UL << I3C_IER_TXFNFIE_Pos)          /*!< 0x00000010 */
#define I3C_IER_TXFNFIE                     I3C_IER_TXFNFIE_Msk                     /*!< TX FIFO Not Full Interrupt Enable */
#define I3C_IER_RXFNEIE_Pos                 (5UL)
#define I3C_IER_RXFNEIE_Msk                 (0x1UL << I3C_IER_RXFNEIE_Pos)          /*!< 0x00000020 */
#define I3C_IER_RXFNEIE                     I3C_IER_RXFNEIE_Msk                     /*!< RX FIFO Not Empty Interrupt Enable */
#define I3C_IER_FCIE_Pos                    (9UL)
#define I3C_IER_FCIE_Msk                    (0x1UL << I3C_IER_FCIE_Pos)             /*!< 0x00000200 */
#define I3C_IER_FCIE                        I3C_IER_FCIE_Msk                        /*!< Frame Complete Interrupt Enable */
#define I3C_IER_RXTGTENDIE_Pos              (10UL)
#define I3C_IER_RXTGTENDIE_Msk              (0x1UL << I3C_IER_RXTGTENDIE_Pos)       /*!< 0x00000400 */
#define I3C_IER_RXTGTENDIE                  I3C_IER_RXTGTENDIE_Msk                  /*!< Reception Target End Interrupt Enable */
#define I3C_IER_ERRIE_Pos                   (11UL)
#define I3C_IER_ERRIE_Msk                   (0x1UL << I3C_IER_ERRIE_Pos)            /*!< 0x00000800 */
#define I3C_IER_ERRIE                       I3C_IER_ERRIE_Msk                       /*!< Error Interrupt Enable */
#define I3C_IER_IBIIE_Pos                   (15UL)
#define I3C_IER_IBIIE_Msk                   (0x1UL << I3C_IER_IBIIE_Pos)            /*!< 0x00008000 */
#define I3C_IER_IBIIE                       I3C_IER_IBIIE_Msk                       /*!< IBI Interrupt Enable */
#define I3C_IER_IBIENDIE_Pos                (16UL)
#define I3C_IER_IBIENDIE_Msk                (0x1UL << I3C_IER_IBIENDIE_Pos)         /*!< 0x00010000 */
#define I3C_IER_IBIENDIE                    I3C_IER_IBIENDIE_Msk                    /*!< IBI End Interrupt Enable */
#define I3C_IER_CRIE_Pos                    (17UL)
#define I3C_IER_CRIE_Msk                    (0x1UL << I3C_IER_CRIE_Pos)             /*!< 0x00020000 */
#define I3C_IER_CRIE                        I3C_IER_CRIE_Msk                        /*!< Controller-role Interrupt Enable */
#define I3C_IER_CRUPDIE_Pos                 (18UL)
#define I3C_IER_CRUPDIE_Msk                 (0x1UL << I3C_IER_CRUPDIE_Pos)          /*!< 0x00040000 */
#define I3C_IER_CRUPDIE                     I3C_IER_CRUPDIE_Msk                     /*!< Controller-role Update Interrupt Enable */
#define I3C_IER_HJIE_Pos                    (19UL)
#define I3C_IER_HJIE_Msk                    (0x1UL << I3C_IER_HJIE_Pos)             /*!< 0x00080000 */
#define I3C_IER_HJIE                        I3C_IER_HJIE_Msk                        /*!< Hot Join Interrupt Enable */
#define I3C_IER_WKPIE_Pos                   (21UL)
#define I3C_IER_WKPIE_Msk                   (0x1UL << I3C_IER_WKPIE_Pos)            /*!< 0x00200000 */
#define I3C_IER_WKPIE                       I3C_IER_WKPIE_Msk                       /*!< Wake Up Interrupt Enable */
#define I3C_IER_GETIE_Pos                   (22UL)
#define I3C_IER_GETIE_Msk                   (0x1UL << I3C_IER_GETIE_Pos)            /*!< 0x00400000 */
#define I3C_IER_GETIE                       I3C_IER_GETIE_Msk                       /*!< Get type CCC received Interrupt Enable */
#define I3C_IER_STAIE_Pos                   (23UL)
#define I3C_IER_STAIE_Msk                   (0x1UL << I3C_IER_STAIE_Pos)            /*!< 0x00800000 */
#define I3C_IER_STAIE                       I3C_IER_STAIE_Msk                       /*!< Get Status Interrupt Enable */
#define I3C_IER_DAUPDIE_Pos                 (24UL)
#define I3C_IER_DAUPDIE_Msk                 (0x1UL << I3C_IER_DAUPDIE_Pos)          /*!< 0x01000000 */
#define I3C_IER_DAUPDIE                     I3C_IER_DAUPDIE_Msk                     /*!< Dynamic Address Update Interrupt Enable */
#define I3C_IER_MWLUPDIE_Pos                (25UL)
#define I3C_IER_MWLUPDIE_Msk                (0x1UL << I3C_IER_MWLUPDIE_Pos)         /*!< 0x02000000 */
#define I3C_IER_MWLUPDIE                    I3C_IER_MWLUPDIE_Msk                    /*!< Max Write Length Update Interrupt Enable */
#define I3C_IER_MRLUPDIE_Pos                (26UL)
#define I3C_IER_MRLUPDIE_Msk                (0x1UL << I3C_IER_MRLUPDIE_Pos)         /*!< 0x04000000 */
#define I3C_IER_MRLUPDIE                    I3C_IER_MRLUPDIE_Msk                    /*!< Max Read Length Update Interrupt Enable */
#define I3C_IER_RSTIE_Pos                   (27UL)
#define I3C_IER_RSTIE_Msk                   (0x1UL << I3C_IER_RSTIE_Pos)            /*!< 0x08000000 */
#define I3C_IER_RSTIE                       I3C_IER_RSTIE_Msk                       /*!< Reset Interrupt Enabled, due to Reset pattern received */
#define I3C_IER_ASUPDIE_Pos                 (28UL)
#define I3C_IER_ASUPDIE_Msk                 (0x1UL << I3C_IER_ASUPDIE_Pos)          /*!< 0x10000000 */
#define I3C_IER_ASUPDIE                     I3C_IER_ASUPDIE_Msk                     /*!< Activity State Interrupt Enable */
#define I3C_IER_INTUPDIE_Pos                (29UL)
#define I3C_IER_INTUPDIE_Msk                (0x1UL << I3C_IER_INTUPDIE_Pos)         /*!< 0x20000000 */
#define I3C_IER_INTUPDIE                    I3C_IER_INTUPDIE_Msk                    /*!< Interrupt Update Interrupt Enable */
#define I3C_IER_DEFIE_Pos                   (30UL)
#define I3C_IER_DEFIE_Msk                   (0x1UL << I3C_IER_DEFIE_Pos)            /*!< 0x40000000 */
#define I3C_IER_DEFIE                       I3C_IER_DEFIE_Msk                       /*!< List of Targets Command Received Interrupt Enable */
#define I3C_IER_GRPIE_Pos                   (31UL)
#define I3C_IER_GRPIE_Msk                   (0x1UL << I3C_IER_GRPIE_Pos)            /*!< 0x80000000 */
#define I3C_IER_GRPIE                       I3C_IER_GRPIE_Msk                       /*!< List of Group Addresses Command Received Interrupt Enable */

/*******************  Bit definition for I3C_CEVR register  *******************/
#define I3C_CEVR_CFCF_Pos                   (9UL)
#define I3C_CEVR_CFCF_Msk                   (0x1UL << I3C_CEVR_CFCF_Pos)            /*!< 0x00000200 */
#define I3C_CEVR_CFCF                       I3C_CEVR_CFCF_Msk                       /*!< Frame Complete Clear Flag */
#define I3C_CEVR_CRXTGTENDF_Pos             (10UL)
#define I3C_CEVR_CRXTGTENDF_Msk             (0x1UL << I3C_CEVR_CRXTGTENDF_Pos)      /*!< 0x00000400 */
#define I3C_CEVR_CRXTGTENDF                 I3C_CEVR_CRXTGTENDF_Msk                 /*!< Reception Target End Clear Flag */
#define I3C_CEVR_CERRF_Pos                  (11UL)
#define I3C_CEVR_CERRF_Msk                  (0x1UL << I3C_CEVR_CERRF_Pos)           /*!< 0x00000800 */
#define I3C_CEVR_CERRF                      I3C_CEVR_CERRF_Msk                      /*!< Error Clear Flag */
#define I3C_CEVR_CIBIF_Pos                  (15UL)
#define I3C_CEVR_CIBIF_Msk                  (0x1UL << I3C_CEVR_CIBIF_Pos)           /*!< 0x00008000 */
#define I3C_CEVR_CIBIF                      I3C_CEVR_CIBIF_Msk                      /*!< IBI Clear Flag */
#define I3C_CEVR_CIBIENDF_Pos               (16UL)
#define I3C_CEVR_CIBIENDF_Msk               (0x1UL << I3C_CEVR_CIBIENDF_Pos)        /*!< 0x00010000 */
#define I3C_CEVR_CIBIENDF                   I3C_CEVR_CIBIENDF_Msk                   /*!< IBI End Clear Flag */
#define I3C_CEVR_CCRF_Pos                   (17UL)
#define I3C_CEVR_CCRF_Msk                   (0x1UL << I3C_CEVR_CCRF_Pos)            /*!< 0x00020000 */
#define I3C_CEVR_CCRF                       I3C_CEVR_CCRF_Msk                       /*!< Controller-role Clear Flag */
#define I3C_CEVR_CCRUPDF_Pos                (18UL)
#define I3C_CEVR_CCRUPDF_Msk                (0x1UL << I3C_CEVR_CCRUPDF_Pos)         /*!< 0x00040000 */
#define I3C_CEVR_CCRUPDF                    I3C_CEVR_CCRUPDF_Msk                    /*!< Controller-role Update Clear Flag */
#define I3C_CEVR_CHJF_Pos                   (19UL)
#define I3C_CEVR_CHJF_Msk                   (0x1UL << I3C_CEVR_CHJF_Pos)            /*!< 0x00080000 */
#define I3C_CEVR_CHJF                       I3C_CEVR_CHJF_Msk                       /*!< Hot Join Clear Flag */
#define I3C_CEVR_CWKPF_Pos                  (21UL)
#define I3C_CEVR_CWKPF_Msk                  (0x1UL << I3C_CEVR_CWKPF_Pos)           /*!< 0x00200000 */
#define I3C_CEVR_CWKPF                      I3C_CEVR_CWKPF_Msk                      /*!< Wake Up Clear Flag */
#define I3C_CEVR_CGETF_Pos                  (22UL)
#define I3C_CEVR_CGETF_Msk                  (0x1UL << I3C_CEVR_CGETF_Pos)           /*!< 0x00400000 */
#define I3C_CEVR_CGETF                      I3C_CEVR_CGETF_Msk                      /*!< Get type CCC received Clear Flag */
#define I3C_CEVR_CSTAF_Pos                  (23UL)
#define I3C_CEVR_CSTAF_Msk                  (0x1UL << I3C_CEVR_CSTAF_Pos)           /*!< 0x00800000 */
#define I3C_CEVR_CSTAF                      I3C_CEVR_CSTAF_Msk                      /*!< Get Status Clear Flag */
#define I3C_CEVR_CDAUPDF_Pos                (24UL)
#define I3C_CEVR_CDAUPDF_Msk                (0x1UL << I3C_CEVR_CDAUPDF_Pos)         /*!< 0x01000000 */
#define I3C_CEVR_CDAUPDF                    I3C_CEVR_CDAUPDF_Msk                    /*!< Dynamic Address Update Clear Flag */
#define I3C_CEVR_CMWLUPDF_Pos               (25UL)
#define I3C_CEVR_CMWLUPDF_Msk               (0x1UL << I3C_CEVR_CMWLUPDF_Pos)        /*!< 0x02000000 */
#define I3C_CEVR_CMWLUPDF                   I3C_CEVR_CMWLUPDF_Msk                   /*!< Max Write Length Update Clear Flag */
#define I3C_CEVR_CMRLUPDF_Pos               (26UL)
#define I3C_CEVR_CMRLUPDF_Msk               (0x1UL << I3C_CEVR_CMRLUPDF_Pos)        /*!< 0x04000000 */
#define I3C_CEVR_CMRLUPDF                   I3C_CEVR_CMRLUPDF_Msk                   /*!< Max Read Length Update Clear Flag */
#define I3C_CEVR_CRSTF_Pos                  (27UL)
#define I3C_CEVR_CRSTF_Msk                  (0x1UL << I3C_CEVR_CRSTF_Pos)           /*!< 0x08000000 */
#define I3C_CEVR_CRSTF                      I3C_CEVR_CRSTF_Msk                      /*!< Reset Flag, due to Reset pattern received */
#define I3C_CEVR_CASUPDF_Pos                (28UL)
#define I3C_CEVR_CASUPDF_Msk                (0x1UL << I3C_CEVR_CASUPDF_Pos)         /*!< 0x10000000 */
#define I3C_CEVR_CASUPDF                    I3C_CEVR_CASUPDF_Msk                    /*!< Activity State Clear Flag */
#define I3C_CEVR_CINTUPDF_Pos               (29UL)
#define I3C_CEVR_CINTUPDF_Msk               (0x1UL << I3C_CEVR_CINTUPDF_Pos)        /*!< 0x20000000 */
#define I3C_CEVR_CINTUPDF                   I3C_CEVR_CINTUPDF_Msk                   /*!< Interrupt Update Clear Flag */
#define I3C_CEVR_CDEFF_Pos                  (30UL)
#define I3C_CEVR_CDEFF_Msk                  (0x1UL << I3C_CEVR_CDEFF_Pos)           /*!< 0x40000000 */
#define I3C_CEVR_CDEFF                      I3C_CEVR_CDEFF_Msk                      /*!< List of Targets Command Received Clear Flag */
#define I3C_CEVR_CGRPF_Pos                  (31UL)
#define I3C_CEVR_CGRPF_Msk                  (0x1UL << I3C_CEVR_CGRPF_Pos)           /*!< 0x80000000 */
#define I3C_CEVR_CGRPF                      I3C_CEVR_CGRPF_Msk                      /*!< List of Group Addresses Command Received Clear Flag */

/*******************  Bit definition for I3C_MISR register  *******************/
#define I3C_MISR_CFNFMIS_Pos                (2UL)
#define I3C_MISR_CFNFMIS_Msk                (0x1UL << I3C_MISR_CFNFMIS_Pos)         /*!< 0x00000004 */
#define I3C_MISR_CFNFMIS                    I3C_MISR_CFNFMIS_Msk                    /*!< Control FIFO Not Full Mask Interrupt Status */
#define I3C_MISR_SFNEMIS_Pos                (3UL)
#define I3C_MISR_SFNEMIS_Msk                (0x1UL << I3C_MISR_SFNEMIS_Pos)         /*!< 0x00000008 */
#define I3C_MISR_SFNEMIS                    I3C_MISR_SFNEMIS_Msk                    /*!< Status FIFO Not Empty Mask Interrupt Status */
#define I3C_MISR_TXFNFMIS_Pos               (4UL)
#define I3C_MISR_TXFNFMIS_Msk               (0x1UL << I3C_MISR_TXFNFMIS_Pos)        /*!< 0x00000010 */
#define I3C_MISR_TXFNFMIS                   I3C_MISR_TXFNFMIS_Msk                   /*!< TX FIFO Not Full Mask Interrupt Status */
#define I3C_MISR_RXFNEMIS_Pos               (5UL)
#define I3C_MISR_RXFNEMIS_Msk               (0x1UL << I3C_MISR_RXFNEMIS_Pos)        /*!< 0x00000020 */
#define I3C_MISR_RXFNEMIS                   I3C_MISR_RXFNEMIS_Msk                   /*!< RX FIFO Not Empty Mask Interrupt Status */
#define I3C_MISR_FCMIS_Pos                  (9UL)
#define I3C_MISR_FCMIS_Msk                  (0x1UL << I3C_MISR_FCMIS_Pos)           /*!< 0x00000200 */
#define I3C_MISR_FCMIS                      I3C_MISR_FCMIS_Msk                      /*!< Frame Complete Mask Interrupt Status */
#define I3C_MISR_RXTGTENDMIS_Pos            (10UL)
#define I3C_MISR_RXTGTENDMIS_Msk            (0x1UL << I3C_MISR_RXTGTENDMIS_Pos)     /*!< 0x00000400 */
#define I3C_MISR_RXTGTENDMIS                I3C_MISR_RXTGTENDMIS_Msk                /*!< Reception Target End Mask Interrupt Status */
#define I3C_MISR_ERRMIS_Pos                 (11UL)
#define I3C_MISR_ERRMIS_Msk                 (0x1UL << I3C_MISR_ERRMIS_Pos)          /*!< 0x00000800 */
#define I3C_MISR_ERRMIS                     I3C_MISR_ERRMIS_Msk                     /*!< Error Mask Interrupt Status */
#define I3C_MISR_IBIMIS_Pos                 (15UL)
#define I3C_MISR_IBIMIS_Msk                 (0x1UL << I3C_MISR_IBIMIS_Pos)          /*!< 0x00008000 */
#define I3C_MISR_IBIMIS                     I3C_MISR_IBIMIS_Msk                     /*!< IBI Mask Interrupt Status */
#define I3C_MISR_IBIENDMIS_Pos              (16UL)
#define I3C_MISR_IBIENDMIS_Msk              (0x1UL << I3C_MISR_IBIENDMIS_Pos)       /*!< 0x00010000 */
#define I3C_MISR_IBIENDMIS                  I3C_MISR_IBIENDMIS_Msk                  /*!< IBI End Mask Interrupt Status */
#define I3C_MISR_CRMIS_Pos                  (17UL)
#define I3C_MISR_CRMIS_Msk                  (0x1UL << I3C_MISR_CRMIS_Pos)           /*!< 0x00020000 */
#define I3C_MISR_CRMIS                      I3C_MISR_CRMIS_Msk                      /*!< Controller-role Mask Interrupt Status */
#define I3C_MISR_CRUPDMIS_Pos               (18UL)
#define I3C_MISR_CRUPDMIS_Msk               (0x1UL << I3C_MISR_CRUPDMIS_Pos)        /*!< 0x00040000 */
#define I3C_MISR_CRUPDMIS                   I3C_MISR_CRUPDMIS_Msk                   /*!< Controller-role Update Mask Interrupt Status */
#define I3C_MISR_HJMIS_Pos                  (19UL)
#define I3C_MISR_HJMIS_Msk                  (0x1UL << I3C_MISR_HJMIS_Pos)           /*!< 0x00080000 */
#define I3C_MISR_HJMIS                      I3C_MISR_HJMIS_Msk                      /*!< Hot Join Mask Interrupt Status */
#define I3C_MISR_WKPMIS_Pos                 (21UL)
#define I3C_MISR_WKPMIS_Msk                 (0x1UL << I3C_MISR_WKPMIS_Pos)          /*!< 0x00200000 */
#define I3C_MISR_WKPMIS                     I3C_MISR_WKPMIS_Msk                     /*!< Wake Up Mask Interrupt Status */
#define I3C_MISR_GETMIS_Pos                 (22UL)
#define I3C_MISR_GETMIS_Msk                 (0x1UL << I3C_MISR_GETMIS_Pos)          /*!< 0x00400000 */
#define I3C_MISR_GETMIS                     I3C_MISR_GETMIS_Msk                     /*!< Get type CCC received Mask Interrupt Status */
#define I3C_MISR_STAMIS_Pos                 (23UL)
#define I3C_MISR_STAMIS_Msk                 (0x1UL << I3C_MISR_STAMIS_Pos)          /*!< 0x00800000 */
#define I3C_MISR_STAMIS                     I3C_MISR_STAMIS_Msk                     /*!< Get Status Mask Interrupt Status */
#define I3C_MISR_DAUPDMIS_Pos               (24UL)
#define I3C_MISR_DAUPDMIS_Msk               (0x1UL << I3C_MISR_DAUPDMIS_Pos)        /*!< 0x01000000 */
#define I3C_MISR_DAUPDMIS                   I3C_MISR_DAUPDMIS_Msk                   /*!< Dynamic Address Update Mask Interrupt Status */
#define I3C_MISR_MWLUPDMIS_Pos              (25UL)
#define I3C_MISR_MWLUPDMIS_Msk              (0x1UL << I3C_MISR_MWLUPDMIS_Pos)       /*!< 0x02000000 */
#define I3C_MISR_MWLUPDMIS                  I3C_MISR_MWLUPDMIS_Msk                  /*!< Max Write Length Update Mask Interrupt Status */
#define I3C_MISR_MRLUPDMIS_Pos              (26UL)
#define I3C_MISR_MRLUPDMIS_Msk              (0x1UL << I3C_MISR_MRLUPDMIS_Pos)       /*!< 0x04000000 */
#define I3C_MISR_MRLUPDMIS                  I3C_MISR_MRLUPDMIS_Msk                  /*!< Max Read Length Update Mask Interrupt Status */
#define I3C_MISR_RSTMIS_Pos                 (27UL)
#define I3C_MISR_RSTMIS_Msk                 (0x1UL << I3C_MISR_RSTMIS_Pos)          /*!< 0x08000000 */
#define I3C_MISR_RSTMIS                     I3C_MISR_RSTMIS_Msk                     /*!< Reset Mask Interrupt Status, due to Reset pattern received */
#define I3C_MISR_ASUPDMIS_Pos               (28UL)
#define I3C_MISR_ASUPDMIS_Msk               (0x1UL << I3C_MISR_ASUPDMIS_Pos)        /*!< 0x10000000 */
#define I3C_MISR_ASUPDMIS                   I3C_MISR_ASUPDMIS_Msk                   /*!< Activity State Mask Interrupt Status */
#define I3C_MISR_INTUPDMIS_Pos              (29UL)
#define I3C_MISR_INTUPDMIS_Msk              (0x1UL << I3C_MISR_INTUPDMIS_Pos)       /*!< 0x20000000 */
#define I3C_MISR_INTUPDMIS                  I3C_MISR_INTUPDMIS_Msk                  /*!< Interrupt Update Mask Interrupt Status */
#define I3C_MISR_DEFMIS_Pos                 (30UL)
#define I3C_MISR_DEFMIS_Msk                 (0x1UL << I3C_MISR_DEFMIS_Pos)          /*!< 0x40000000 */
#define I3C_MISR_DEFMIS                     I3C_MISR_DEFMIS_Msk                     /*!< List of Targets Command Received Mask Interrupt Status */
#define I3C_MISR_GRPMIS_Pos                 (31UL)
#define I3C_MISR_GRPMIS_Msk                 (0x1UL << I3C_MISR_GRPMIS_Pos)          /*!< 0x80000000 */
#define I3C_MISR_GRPMIS                     I3C_MISR_GRPMIS_Msk                     /*!< List of Group Addresses Command Received Mask Interrupt Status */

/******************  Bit definition for I3C_DEVR0 register  *******************/
#define I3C_DEVR0_DAVAL_Pos                 (0UL)
#define I3C_DEVR0_DAVAL_Msk                 (0x1UL << I3C_DEVR0_DAVAL_Pos)          /*!< 0x00000001 */
#define I3C_DEVR0_DAVAL                     I3C_DEVR0_DAVAL_Msk                     /*!< Dynamic Address Validity */
#define I3C_DEVR0_DA_Pos                    (1UL)
#define I3C_DEVR0_DA_Msk                    (0x7FUL << I3C_DEVR0_DA_Pos)            /*!< 0x000000FE */
#define I3C_DEVR0_DA                        I3C_DEVR0_DA_Msk                        /*!< Own Target Device Address */
#define I3C_DEVR0_IBIEN_Pos                 (16UL)
#define I3C_DEVR0_IBIEN_Msk                 (0x1UL << I3C_DEVR0_IBIEN_Pos)          /*!< 0x00010000 */
#define I3C_DEVR0_IBIEN                     I3C_DEVR0_IBIEN_Msk                     /*!< IBI Enable */
#define I3C_DEVR0_CREN_Pos                  (17UL)
#define I3C_DEVR0_CREN_Msk                  (0x1UL << I3C_DEVR0_CREN_Pos)           /*!< 0x00020000 */
#define I3C_DEVR0_CREN                      I3C_DEVR0_CREN_Msk                      /*!< Controller-role Enable */
#define I3C_DEVR0_HJEN_Pos                  (19UL)
#define I3C_DEVR0_HJEN_Msk                  (0x1UL << I3C_DEVR0_HJEN_Pos)           /*!< 0x00080000 */
#define I3C_DEVR0_HJEN                      I3C_DEVR0_HJEN_Msk                      /*!< Hot Join Enable */
#define I3C_DEVR0_AS_Pos                    (20UL)
#define I3C_DEVR0_AS_Msk                    (0x3UL << I3C_DEVR0_AS_Pos)             /*!< 0x00300000 */
#define I3C_DEVR0_AS                        I3C_DEVR0_AS_Msk                        /*!< Activity State value update after ENTAx received */
#define I3C_DEVR0_AS_0                      (0x1UL << I3C_DEVR0_AS_Pos)             /*!< 0x00100000 */
#define I3C_DEVR0_AS_1                      (0x2UL << I3C_DEVR0_AS_Pos)             /*!< 0x00200000 */
#define I3C_DEVR0_RSTACT_Pos                (22UL)
#define I3C_DEVR0_RSTACT_Msk                (0x3UL << I3C_DEVR0_RSTACT_Pos)         /*!< 0x00C000000 */
#define I3C_DEVR0_RSTACT                    I3C_DEVR0_RSTACT_Msk                    /*!< Reset Action value update after RSTACT received */
#define I3C_DEVR0_RSTACT_0                  (0x1UL << I3C_DEVR0_RSTACT_Pos)         /*!< 0x00400000 */
#define I3C_DEVR0_RSTACT_1                  (0x2UL << I3C_DEVR0_RSTACT_Pos)         /*!< 0x00800000 */
#define I3C_DEVR0_RSTVAL_Pos                (24UL)
#define I3C_DEVR0_RSTVAL_Msk                (0x1UL << I3C_DEVR0_RSTVAL_Pos)         /*!< 0x01000000 */
#define I3C_DEVR0_RSTVAL                    I3C_DEVR0_RSTVAL_Msk                    /*!< Reset Action Valid */

/******************  Bit definition for I3C_DEVRX register  *******************/
#define I3C_DEVRX_DA_Pos                    (1UL)
#define I3C_DEVRX_DA_Msk                    (0x7FUL << I3C_DEVRX_DA_Pos)            /*!< 0x000000FE */
#define I3C_DEVRX_DA                        I3C_DEVRX_DA_Msk                        /*!< Dynamic Address Target x */
#define I3C_DEVRX_IBIACK_Pos                (16UL)
#define I3C_DEVRX_IBIACK_Msk                (0x1UL << I3C_DEVRX_IBIACK_Pos)         /*!< 0x00010000 */
#define I3C_DEVRX_IBIACK                    I3C_DEVRX_IBIACK_Msk                    /*!< IBI Acknowledge from Target x */
#define I3C_DEVRX_CRACK_Pos                 (17UL)
#define I3C_DEVRX_CRACK_Msk                 (0x1UL << I3C_DEVRX_CRACK_Pos)          /*!< 0x00020000 */
#define I3C_DEVRX_CRACK                     I3C_DEVRX_CRACK_Msk                     /*!< Controller-role Acknowledge from Target x */
#define I3C_DEVRX_IBIDEN_Pos                (18UL)
#define I3C_DEVRX_IBIDEN_Msk                (0x1UL << I3C_DEVRX_IBIDEN_Pos)         /*!< 0x00040000 */
#define I3C_DEVRX_IBIDEN                    I3C_DEVRX_IBIDEN_Msk                    /*!< IBI Additional Data Enable */
#define I3C_DEVRX_SUSP_Pos                  (19UL)
#define I3C_DEVRX_SUSP_Msk                  (0x1UL << I3C_DEVRX_SUSP_Pos)           /*!< 0x00080000 */
#define I3C_DEVRX_SUSP                      I3C_DEVRX_SUSP_Msk                      /*!< Suspended Transfer */
#define I3C_DEVRX_DIS_Pos                   (31UL)
#define I3C_DEVRX_DIS_Msk                   (0x1UL << I3C_DEVRX_DIS_Pos)            /*!< 0x80000000 */
#define I3C_DEVRX_DIS                       I3C_DEVRX_DIS_Msk                       /*!< Disable Register access */

/******************  Bit definition for I3C_MAXRLR register  ******************/
#define I3C_MAXRLR_MRL_Pos                  (0UL)
#define I3C_MAXRLR_MRL_Msk                  (0xFFFFUL << I3C_MAXRLR_MRL_Pos)        /*!< 0x0000FFFF */
#define I3C_MAXRLR_MRL                      I3C_MAXRLR_MRL_Msk                      /*!< Maximum Read Length */
#define I3C_MAXRLR_IBIP_Pos                 (16UL)
#define I3C_MAXRLR_IBIP_Msk                 (0x7UL << I3C_MAXRLR_IBIP_Pos)          /*!< 0x00070000 */
#define I3C_MAXRLR_IBIP                     I3C_MAXRLR_IBIP_Msk                     /*!< IBI Payload size */
#define I3C_MAXRLR_IBIP_0                   (0x1UL << I3C_MAXRLR_IBIP_Pos)          /*!< 0x00010000 */
#define I3C_MAXRLR_IBIP_1                   (0x2UL << I3C_MAXRLR_IBIP_Pos)          /*!< 0x00020000 */
#define I3C_MAXRLR_IBIP_2                   (0x4UL << I3C_MAXRLR_IBIP_Pos)          /*!< 0x00040000 */

/******************  Bit definition for I3C_MAXWLR register  ******************/
#define I3C_MAXWLR_MWL_Pos                  (0UL)
#define I3C_MAXWLR_MWL_Msk                  (0xFFFFUL << I3C_MAXWLR_MWL_Pos)        /*!< 0x0000FFFF */
#define I3C_MAXWLR_MWL                      I3C_MAXWLR_MWL_Msk                      /*!< Maximum Write Length */

/****************  Bit definition for I3C_TIMINGR0 register  ******************/
#define I3C_TIMINGR0_SCLL_PP_Pos            (0UL)
#define I3C_TIMINGR0_SCLL_PP_Msk            (0xFFUL << I3C_TIMINGR0_SCLL_PP_Pos)    /*!< 0x000000FF */
#define I3C_TIMINGR0_SCLL_PP                I3C_TIMINGR0_SCLL_PP_Msk                /*!< SCL Low duration during I3C Push-Pull phases */
#define I3C_TIMINGR0_SCLH_I3C_Pos           (8UL)
#define I3C_TIMINGR0_SCLH_I3C_Msk           (0xFFUL << I3C_TIMINGR0_SCLH_I3C_Pos)   /*!< 0x0000FF00 */
#define I3C_TIMINGR0_SCLH_I3C               I3C_TIMINGR0_SCLH_I3C_Msk               /*!< SCL High duration during I3C Open-drain and Push-Pull phases */
#define I3C_TIMINGR0_SCLL_OD_Pos            (16UL)
#define I3C_TIMINGR0_SCLL_OD_Msk            (0xFFUL << I3C_TIMINGR0_SCLL_OD_Pos)    /*!< 0x00FF0000 */
#define I3C_TIMINGR0_SCLL_OD                I3C_TIMINGR0_SCLL_OD_Msk                /*!< SCL Low duration during  I3C Open-drain phases and I2C transfer */
#define I3C_TIMINGR0_SCLH_I2C_Pos           (24UL)
#define I3C_TIMINGR0_SCLH_I2C_Msk           (0xFFUL << I3C_TIMINGR0_SCLH_I2C_Pos)   /*!< 0xFF000000 */
#define I3C_TIMINGR0_SCLH_I2C               I3C_TIMINGR0_SCLH_I2C_Msk               /*!< SCL High duration during I2C transfer */

/****************  Bit definition for I3C_TIMINGR1 register  ******************/
#define I3C_TIMINGR1_AVAL_Pos               (0UL)
#define I3C_TIMINGR1_AVAL_Msk               (0xFFUL << I3C_TIMINGR1_AVAL_Pos)       /*!< 0x000000FF */
#define I3C_TIMINGR1_AVAL                   I3C_TIMINGR1_AVAL_Msk                   /*!< Timing for I3C Bus Idle or Available condition */
#define I3C_TIMINGR1_ASNCR_Pos              (8UL)
#define I3C_TIMINGR1_ASNCR_Msk              (0x3UL << I3C_TIMINGR1_ASNCR_Pos)       /*!< 0x00000300 */
#define I3C_TIMINGR1_ASNCR                  I3C_TIMINGR1_ASNCR_Msk                  /*!< Activity State of the New Controller */
#define I3C_TIMINGR1_ASNCR_0                (0x1UL << I3C_TIMINGR1_ASNCR_Pos)       /*!< 0x00000100 */
#define I3C_TIMINGR1_ASNCR_1                (0x2UL << I3C_TIMINGR1_ASNCR_Pos)       /*!< 0x00000200 */
#define I3C_TIMINGR1_FREE_Pos               (16UL)
#define I3C_TIMINGR1_FREE_Msk               (0x7FUL << I3C_TIMINGR1_FREE_Pos)       /*!< 0x007F0000 */
#define I3C_TIMINGR1_FREE                   I3C_TIMINGR1_FREE_Msk                   /*!< Timing for I3C Bus Free condition */
#define I3C_TIMINGR1_SDA_HD_Pos             (28UL)
#define I3C_TIMINGR1_SDA_HD_Msk             (0x3UL << I3C_TIMINGR1_SDA_HD_Pos)      /*!< 0x30000000 */
#define I3C_TIMINGR1_SDA_HD                 I3C_TIMINGR1_SDA_HD_Msk                 /*!< SDA Hold Duration */
#define I3C_TIMINGR1_SDA_HD_0               (0x1UL << I3C_TIMINGR1_SDA_HD_Pos)      /*!< 0x10000000 */
#define I3C_TIMINGR1_SDA_HD_1               (0x2UL << I3C_TIMINGR1_SDA_HD_Pos)      /*!< 0x20000000 */

/****************  Bit definition for I3C_TIMINGR2 register  ******************/
#define I3C_TIMINGR2_STALLT_Pos             (0UL)
#define I3C_TIMINGR2_STALLT_Msk             (0x1UL << I3C_TIMINGR2_STALLT_Pos)      /*!< 0x00000001 */
#define I3C_TIMINGR2_STALLT                 I3C_TIMINGR2_STALLT_Msk                 /*!< Stall on T bit */
#define I3C_TIMINGR2_STALLD_Pos             (1UL)
#define I3C_TIMINGR2_STALLD_Msk             (0x1UL << I3C_TIMINGR2_STALLD_Pos)      /*!< 0x00000002 */
#define I3C_TIMINGR2_STALLD                 I3C_TIMINGR2_STALLD_Msk                 /*!< Stall on PAR bit of data bytes */
#define I3C_TIMINGR2_STALLC_Pos             (2UL)
#define I3C_TIMINGR2_STALLC_Msk             (0x1UL << I3C_TIMINGR2_STALLC_Pos)      /*!< 0x00000004 */
#define I3C_TIMINGR2_STALLC                 I3C_TIMINGR2_STALLC_Msk                 /*!< Stall on PAR bit of CCC byte */
#define I3C_TIMINGR2_STALLA_Pos             (3UL)
#define I3C_TIMINGR2_STALLA_Msk             (0x1UL << I3C_TIMINGR2_STALLA_Pos)      /*!< 0x00000008 */
#define I3C_TIMINGR2_STALLA                 I3C_TIMINGR2_STALLA_Msk                 /*!< Stall on ACK bit */
#define I3C_TIMINGR2_STALLR_Pos             (4UL)
#define I3C_TIMINGR2_STALLR_Msk             (0x1UL << I3C_TIMINGR2_STALLR_Pos)      /*!< 0x00000010 */
#define I3C_TIMINGR2_STALLR                 I3C_TIMINGR2_STALLR_Msk                 /*!< Stall on I2C Read ACK bit */
#define I3C_TIMINGR2_STALLS_Pos             (5UL)
#define I3C_TIMINGR2_STALLS_Msk             (0x1UL << I3C_TIMINGR2_STALLS_Pos)      /*!< 0x00000020 */
#define I3C_TIMINGR2_STALLS                 I3C_TIMINGR2_STALLS_Msk                 /*!< Stall on I2C Write ACK bit */
#define I3C_TIMINGR2_STALLL_Pos             (6UL)
#define I3C_TIMINGR2_STALLL_Msk             (0x1UL << I3C_TIMINGR2_STALLL_Pos)      /*!< 0x00000040 */
#define I3C_TIMINGR2_STALLL                 I3C_TIMINGR2_STALLL_Msk                 /*!< Stall on I2C Address ACK bit */
#define I3C_TIMINGR2_STALL_Pos              (8UL)
#define I3C_TIMINGR2_STALL_Msk              (0xFFUL << I3C_TIMINGR2_STALL_Pos)      /*!< 0x0000FF00 */
#define I3C_TIMINGR2_STALL                  I3C_TIMINGR2_STALL_Msk                  /*!< Controller Stall duration */

/*******************  Bit definition for I3C_BCR register  ********************/
#define I3C_BCR_BCR_Pos                     (0UL)
#define I3C_BCR_BCR_Msk                     (0xFFUL << I3C_BCR_BCR_Pos)             /*!< 0x000000FF */
#define I3C_BCR_BCR                         I3C_BCR_BCR_Msk                         /*!< Bus Characteristics */
#define I3C_BCR_BCR0_Pos                    (0UL)
#define I3C_BCR_BCR0_Msk                    (0x1UL << I3C_BCR_BCR0_Pos)             /*!< 0x00000001 */
#define I3C_BCR_BCR0                        I3C_BCR_BCR0_Msk                        /*!< Max Data Speed Limitation */
#define I3C_BCR_BCR1_Pos                    (1UL)
#define I3C_BCR_BCR1_Msk                    (0x1UL << I3C_BCR_BCR1_Pos)             /*!< 0x00000002 */
#define I3C_BCR_BCR1                        I3C_BCR_BCR1_Msk                        /*!< IBI Request capable */
#define I3C_BCR_BCR2_Pos                    (2UL)
#define I3C_BCR_BCR2_Msk                    (0x1UL << I3C_BCR_BCR2_Pos)             /*!< 0x00000004 */
#define I3C_BCR_BCR2                        I3C_BCR_BCR2_Msk                        /*!< IBI Payload additional Mandatory Data Byte */
#define I3C_BCR_BCR3_Pos                    (3UL)
#define I3C_BCR_BCR3_Msk                    (0x1UL << I3C_BCR_BCR3_Pos)             /*!< 0x00000008 */
#define I3C_BCR_BCR3                        I3C_BCR_BCR3_Msk                        /*!< Offline capable */
#define I3C_BCR_BCR4_Pos                    (4UL)
#define I3C_BCR_BCR4_Msk                    (0x1UL << I3C_BCR_BCR4_Pos)             /*!< 0x00000010 */
#define I3C_BCR_BCR4                        I3C_BCR_BCR4_Msk                        /*!< Virtual target support */
#define I3C_BCR_BCR5_Pos                    (5UL)
#define I3C_BCR_BCR5_Msk                    (0x1UL << I3C_BCR_BCR5_Pos)             /*!< 0x00000020 */
#define I3C_BCR_BCR5                        I3C_BCR_BCR5_Msk                        /*!< Advanced capabilities */
#define I3C_BCR_BCR6_Pos                    (6UL)
#define I3C_BCR_BCR6_Msk                    (0x1UL << I3C_BCR_BCR6_Pos)             /*!< 0x00000040 */
#define I3C_BCR_BCR6                        I3C_BCR_BCR6_Msk                        /*!< Device Role shared during Dynamic Address Assignment */

/*******************  Bit definition for I3C_DCR register  ********************/
#define I3C_DCR_DCR_Pos                     (0UL)
#define I3C_DCR_DCR_Msk                     (0xFFUL << I3C_DCR_DCR_Pos)             /*!< 0x000000FF */
#define I3C_DCR_DCR                         I3C_DCR_DCR_Msk                         /*!< Devices Characteristics */

/*****************  Bit definition for I3C_GETCAPR register  ******************/
#define I3C_GETCAPR_CAPPEND_Pos             (14UL)
#define I3C_GETCAPR_CAPPEND_Msk             (0x1UL << I3C_GETCAPR_CAPPEND_Pos)      /*!< 0x00004000 */
#define I3C_GETCAPR_CAPPEND                 I3C_GETCAPR_CAPPEND_Msk                 /*!< IBI Request with Mandatory Data Byte */

/*****************  Bit definition for I3C_CRCAPR register  *******************/
#define I3C_CRCAPR_CAPDHOFF_Pos             (3UL)
#define I3C_CRCAPR_CAPDHOFF_Msk             (0x1UL << I3C_CRCAPR_CAPDHOFF_Pos)      /*!< 0x00000008 */
#define I3C_CRCAPR_CAPDHOFF                 I3C_CRCAPR_CAPDHOFF_Msk                 /*!< Controller-role handoff needed */
#define I3C_CRCAPR_CAPGRP_Pos               (9UL)
#define I3C_CRCAPR_CAPGRP_Msk               (0x1UL << I3C_CRCAPR_CAPGRP_Pos)        /*!< 0x00000200 */
#define I3C_CRCAPR_CAPGRP                   I3C_CRCAPR_CAPGRP_Msk                   /*!< Group Address handoff supported */

/****************  Bit definition for I3C_GETMXDSR register  ******************/
#define I3C_GETMXDSR_HOFFAS_Pos             (0UL)
#define I3C_GETMXDSR_HOFFAS_Msk             (0x3UL << I3C_GETMXDSR_HOFFAS_Pos)      /*!< 0x00000003 */
#define I3C_GETMXDSR_HOFFAS                 I3C_GETMXDSR_HOFFAS_Msk                 /*!< Handoff Activity State */
#define I3C_GETMXDSR_HOFFAS_0               (0x1UL << I3C_GETMXDSR_HOFFAS_Pos)      /*!< 0x00000001 */
#define I3C_GETMXDSR_HOFFAS_1               (0x2UL << I3C_GETMXDSR_HOFFAS_Pos)      /*!< 0x00000002 */
#define I3C_GETMXDSR_FMT_Pos                (8UL)
#define I3C_GETMXDSR_FMT_Msk                (0x3UL << I3C_GETMXDSR_FMT_Pos)         /*!< 0x00000300 */
#define I3C_GETMXDSR_FMT                    I3C_GETMXDSR_FMT_Msk                    /*!< Get Max Data Speed response in format 2 */
#define I3C_GETMXDSR_FMT_0                  (0x1UL << I3C_GETMXDSR_FMT_Pos)         /*!< 0x00000100 */
#define I3C_GETMXDSR_FMT_1                  (0x2UL << I3C_GETMXDSR_FMT_Pos)         /*!< 0x00000200 */
#define I3C_GETMXDSR_RDTURN_Pos             (16UL)
#define I3C_GETMXDSR_RDTURN_Msk             (0xFFUL << I3C_GETMXDSR_RDTURN_Pos)     /*!< 0x00FF0000 */
#define I3C_GETMXDSR_RDTURN                 I3C_GETMXDSR_RDTURN_Msk                 /*!< Max Read Turnaround Middle Byte  */
#define I3C_GETMXDSR_TSCO_Pos               (24UL)
#define I3C_GETMXDSR_TSCO_Msk               (0x1UL << I3C_GETMXDSR_TSCO_Pos)        /*!< 0x01000000 */
#define I3C_GETMXDSR_TSCO                   I3C_GETMXDSR_TSCO_Msk                   /*!< Clock-to-data Turnaround time */

/******************  Bit definition for I3C_EPIDR register  *******************/
#define I3C_EPIDR_MIPIID_Pos                (12UL)
#define I3C_EPIDR_MIPIID_Msk                (0xFUL << I3C_EPIDR_MIPIID_Pos)         /*!< 0x0000F000 */
#define I3C_EPIDR_MIPIID                    I3C_EPIDR_MIPIID_Msk                    /*!< MIPI Instance ID */
#define I3C_EPIDR_IDTSEL_Pos                (16UL)
#define I3C_EPIDR_IDTSEL_Msk                (0x1UL << I3C_EPIDR_IDTSEL_Pos)         /*!< 0x00010000 */
#define I3C_EPIDR_IDTSEL                    I3C_EPIDR_IDTSEL_Msk                    /*!< ID Type Selector */
#define I3C_EPIDR_MIPIMID_Pos               (17UL)
#define I3C_EPIDR_MIPIMID_Msk               (0x7FFFUL << I3C_EPIDR_MIPIMID_Pos)     /*!< 0xFFFE0000 */
#define I3C_EPIDR_MIPIMID                   I3C_EPIDR_MIPIMID_Msk                   /*!< MIPI Manufacturer ID */

/******************************************************************************/
/*                                                                            */
/*                                 ICACHE                                     */
/*                                                                            */
/******************************************************************************/
/******************  Bit definition for ICACHE_CR register  *******************/
#define ICACHE_CR_EN_Pos                    (0UL)
#define ICACHE_CR_EN_Msk                    (0x1UL << ICACHE_CR_EN_Pos)             /*!< 0x00000001 */
#define ICACHE_CR_EN                        ICACHE_CR_EN_Msk                        /*!< Enable */
#define ICACHE_CR_CACHEINV_Pos              (1UL)
#define ICACHE_CR_CACHEINV_Msk              (0x1UL << ICACHE_CR_CACHEINV_Pos)       /*!< 0x00000002 */
#define ICACHE_CR_CACHEINV                  ICACHE_CR_CACHEINV_Msk                  /*!< Cache invalidation */
#define ICACHE_CR_WAYSEL_Pos                (2UL)
#define ICACHE_CR_WAYSEL_Msk                (0x1UL << ICACHE_CR_WAYSEL_Pos)         /*!< 0x00000004 */
#define ICACHE_CR_WAYSEL                    ICACHE_CR_WAYSEL_Msk                    /*!< Ways selection */
#define ICACHE_CR_HITMEN_Pos                (16UL)
#define ICACHE_CR_HITMEN_Msk                (0x1UL << ICACHE_CR_HITMEN_Pos)         /*!< 0x00010000 */
#define ICACHE_CR_HITMEN                    ICACHE_CR_HITMEN_Msk                    /*!< Hit monitor enable */
#define ICACHE_CR_MISSMEN_Pos               (17UL)
#define ICACHE_CR_MISSMEN_Msk               (0x1UL << ICACHE_CR_MISSMEN_Pos)        /*!< 0x00020000 */
#define ICACHE_CR_MISSMEN                   ICACHE_CR_MISSMEN_Msk                   /*!< Miss monitor enable */
#define ICACHE_CR_HITMRST_Pos               (18UL)
#define ICACHE_CR_HITMRST_Msk               (0x1UL << ICACHE_CR_HITMRST_Pos)        /*!< 0x00040000 */
#define ICACHE_CR_HITMRST                   ICACHE_CR_HITMRST_Msk                   /*!< Hit monitor reset */
#define ICACHE_CR_MISSMRST_Pos              (19UL)
#define ICACHE_CR_MISSMRST_Msk              (0x1UL << ICACHE_CR_MISSMRST_Pos)       /*!< 0x00080000 */
#define ICACHE_CR_MISSMRST                  ICACHE_CR_MISSMRST_Msk                  /*!< Miss monitor reset */

/******************  Bit definition for ICACHE_SR register  *******************/
#define ICACHE_SR_BUSYF_Pos                 (0UL)
#define ICACHE_SR_BUSYF_Msk                 (0x1UL << ICACHE_SR_BUSYF_Pos)          /*!< 0x00000001 */
#define ICACHE_SR_BUSYF                     ICACHE_SR_BUSYF_Msk                     /*!< Busy flag */
#define ICACHE_SR_BSYENDF_Pos               (1UL)
#define ICACHE_SR_BSYENDF_Msk               (0x1UL << ICACHE_SR_BSYENDF_Pos)        /*!< 0x00000002 */
#define ICACHE_SR_BSYENDF                   ICACHE_SR_BSYENDF_Msk                   /*!< Busy end flag */
#define ICACHE_SR_ERRF_Pos                  (2UL)
#define ICACHE_SR_ERRF_Msk                  (0x1UL << ICACHE_SR_ERRF_Pos)           /*!< 0x00000004 */
#define ICACHE_SR_ERRF                      ICACHE_SR_ERRF_Msk                      /*!< Cache error flag */

/******************  Bit definition for ICACHE_IER register  ******************/
#define ICACHE_IER_BSYENDIE_Pos             (1UL)
#define ICACHE_IER_BSYENDIE_Msk             (0x1UL << ICACHE_IER_BSYENDIE_Pos)      /*!< 0x00000002 */
#define ICACHE_IER_BSYENDIE                 ICACHE_IER_BSYENDIE_Msk                 /*!< Busy end interrupt enable */
#define ICACHE_IER_ERRIE_Pos                (2UL)
#define ICACHE_IER_ERRIE_Msk                (0x1UL << ICACHE_IER_ERRIE_Pos)         /*!< 0x00000004 */
#define ICACHE_IER_ERRIE                    ICACHE_IER_ERRIE_Msk                    /*!< Cache error interrupt enable */

/******************  Bit definition for ICACHE_FCR register  ******************/
#define ICACHE_FCR_CBSYENDF_Pos             (1UL)
#define ICACHE_FCR_CBSYENDF_Msk             (0x1UL << ICACHE_FCR_CBSYENDF_Pos)      /*!< 0x00000002 */
#define ICACHE_FCR_CBSYENDF                 ICACHE_FCR_CBSYENDF_Msk                 /*!< Busy end flag clear */
#define ICACHE_FCR_CERRF_Pos                (2UL)
#define ICACHE_FCR_CERRF_Msk                (0x1UL << ICACHE_FCR_CERRF_Pos)         /*!< 0x00000004 */
#define ICACHE_FCR_CERRF                    ICACHE_FCR_CERRF_Msk                    /*!< Cache error flag clear */

/******************  Bit definition for ICACHE_HMONR register  ****************/
#define ICACHE_HMONR_HITMON_Pos             (0UL)
#define ICACHE_HMONR_HITMON_Msk             (0xFFFFFFFFUL << ICACHE_HMONR_HITMON_Pos) /*!< 0xFFFFFFFF */
#define ICACHE_HMONR_HITMON                 ICACHE_HMONR_HITMON_Msk                 /*!< Cache hit monitor register */

/******************  Bit definition for ICACHE_MMONR register  ****************/
#define ICACHE_MMONR_MISSMON_Pos            (0UL)
#define ICACHE_MMONR_MISSMON_Msk            (0xFFFFUL << ICACHE_MMONR_MISSMON_Pos)  /*!< 0x0000FFFF */
#define ICACHE_MMONR_MISSMON                ICACHE_MMONR_MISSMON_Msk                /*!< Cache miss monitor register */

/******************  Bit definition for ICACHE_CRRx register  *****************/
#define ICACHE_CRRx_BASEADDR_Pos            (0UL)
#define ICACHE_CRRx_BASEADDR_Msk            (0xFFUL << ICACHE_CRRx_BASEADDR_Pos)    /*!< 0x000000FF */
#define ICACHE_CRRx_BASEADDR                ICACHE_CRRx_BASEADDR_Msk                /*!< Base address of region X to remap */
#define ICACHE_CRRx_RSIZE_Pos               (9UL)
#define ICACHE_CRRx_RSIZE_Msk               (0x7UL << ICACHE_CRRx_RSIZE_Pos)        /*!< 0x00000E00 */
#define ICACHE_CRRx_RSIZE                   ICACHE_CRRx_RSIZE_Msk                   /*!< Region X size */
#define ICACHE_CRRx_RSIZE_0                 (0x1UL << ICACHE_CRRx_RSIZE_Pos)        /*!< 0x00000200 */
#define ICACHE_CRRx_RSIZE_1                 (0x2UL << ICACHE_CRRx_RSIZE_Pos)        /*!< 0x00000400 */
#define ICACHE_CRRx_RSIZE_2                 (0x4UL << ICACHE_CRRx_RSIZE_Pos)        /*!< 0x00000800 */
#define ICACHE_CRRx_REN_Pos                 (15UL)
#define ICACHE_CRRx_REN_Msk                 (0x1UL << ICACHE_CRRx_REN_Pos)          /*!< 0x00008000 */
#define ICACHE_CRRx_REN                     ICACHE_CRRx_REN_Msk                     /*!< Region X enable */
#define ICACHE_CRRx_REMAPADDR_Pos           (16UL)
#define ICACHE_CRRx_REMAPADDR_Msk           (0x7FFUL << ICACHE_CRRx_REMAPADDR_Pos)  /*!< 0x07FF0000 */
#define ICACHE_CRRx_REMAPADDR               ICACHE_CRRx_REMAPADDR_Msk               /*!< Remap address of Region X to be remapped */
#define ICACHE_CRRx_MSTSEL_Pos              (28UL)
#define ICACHE_CRRx_MSTSEL_Msk              (0x1UL << ICACHE_CRRx_MSTSEL_Pos)       /*!< 0x10000000 */
#define ICACHE_CRRx_MSTSEL                  ICACHE_CRRx_MSTSEL_Msk                  /*!< Region X AHB cache master selection */
#define ICACHE_CRRx_HBURST_Pos              (31UL)
#define ICACHE_CRRx_HBURST_Msk              (0x1UL << ICACHE_CRRx_HBURST_Pos)       /*!< 0x80000000 */
#define ICACHE_CRRx_HBURST                  ICACHE_CRRx_HBURST_Msk                  /*!< Region X output burst type */

/******************************************************************************/
/*                                                                            */
/*                           Independent WATCHDOG                             */
/*                                                                            */
/******************************************************************************/
/*******************  Bit definition for IWDG_KR register  ********************/
#define IWDG_KR_KEY_Pos                     (0UL)
#define IWDG_KR_KEY_Msk                     (0xFFFFUL << IWDG_KR_KEY_Pos)           /*!< 0x0000FFFF */
#define IWDG_KR_KEY                         IWDG_KR_KEY_Msk                         /*!<Key value (write only, read 0000h)  */

/*******************  Bit definition for IWDG_PR register  ********************/
#define IWDG_PR_PR_Pos                      (0UL)
#define IWDG_PR_PR_Msk                      (0xFUL << IWDG_PR_PR_Pos)               /*!< 0x0000000F */
#define IWDG_PR_PR                          IWDG_PR_PR_Msk                          /*!<PR[3:0] (Prescaler divider)         */
#define IWDG_PR_PR_0                        (0x1UL << IWDG_PR_PR_Pos)               /*!< 0x00000001 */
#define IWDG_PR_PR_1                        (0x2UL << IWDG_PR_PR_Pos)               /*!< 0x00000002 */
#define IWDG_PR_PR_2                        (0x4UL << IWDG_PR_PR_Pos)               /*!< 0x00000004 */
#define IWDG_PR_PR_3                        (0x8UL << IWDG_PR_PR_Pos)               /*!< 0x00000008 */

/*******************  Bit definition for IWDG_RLR register  *******************/
#define IWDG_RLR_RL_Pos                     (0UL)
#define IWDG_RLR_RL_Msk                     (0xFFFUL << IWDG_RLR_RL_Pos)            /*!< 0x00000FFF */
#define IWDG_RLR_RL                         IWDG_RLR_RL_Msk                         /*!<Watchdog counter reload value        */

/*******************  Bit definition for IWDG_SR register  ********************/
#define IWDG_SR_PVU_Pos                     (0UL)
#define IWDG_SR_PVU_Msk                     (0x1UL << IWDG_SR_PVU_Pos)              /*!< 0x00000001 */
#define IWDG_SR_PVU                         IWDG_SR_PVU_Msk                         /*!< Watchdog prescaler value update */
#define IWDG_SR_RVU_Pos                     (1UL)
#define IWDG_SR_RVU_Msk                     (0x1UL << IWDG_SR_RVU_Pos)              /*!< 0x00000002 */
#define IWDG_SR_RVU                         IWDG_SR_RVU_Msk                         /*!< Watchdog counter reload value update */
#define IWDG_SR_WVU_Pos                     (2UL)
#define IWDG_SR_WVU_Msk                     (0x1UL << IWDG_SR_WVU_Pos)              /*!< 0x00000004 */
#define IWDG_SR_WVU                         IWDG_SR_WVU_Msk                         /*!< Watchdog counter window value update */
#define IWDG_SR_EWU_Pos                     (3UL)
#define IWDG_SR_EWU_Msk                     (0x1UL << IWDG_SR_EWU_Pos)              /*!< 0x00000008 */
#define IWDG_SR_EWU                         IWDG_SR_EWU_Msk                         /*!< Watchdog interrupt comparator value update */
#define IWDG_SR_ONF_Pos                     (8UL)
#define IWDG_SR_ONF_Msk                     (0x1UL << IWDG_SR_ONF_Pos)              /*!< 0x000001000 */
#define IWDG_SR_ONF                         IWDG_SR_ONF_Msk                         /*!< Watchdog enable status bit */
#define IWDG_SR_EWIF_Pos                    (14UL)
#define IWDG_SR_EWIF_Msk                    (0x1UL << IWDG_SR_EWIF_Pos)             /*!< 0x00004000 */
#define IWDG_SR_EWIF                        IWDG_SR_EWIF_Msk                        /*!< Watchdog early interrupt flag */

/******************  Bit definition for IWDG_WINR register  *******************/
#define IWDG_WINR_WIN_Pos                   (0UL)
#define IWDG_WINR_WIN_Msk                   (0xFFFUL << IWDG_WINR_WIN_Pos)          /*!< 0x00000FFF */
#define IWDG_WINR_WIN                       IWDG_WINR_WIN_Msk                       /*!< Watchdog counter window value */

/******************  Bit definition for IWDG_EWCR register  *******************/
#define IWDG_EWCR_EWIT_Pos                  (0UL)
#define IWDG_EWCR_EWIT_Msk                  (0xFFFUL << IWDG_EWCR_EWIT_Pos)         /*!< 0x00000FFF */
#define IWDG_EWCR_EWIT                      IWDG_EWCR_EWIT_Msk                      /*!< Watchdog early wakeup comparator value */
#define IWDG_EWCR_EWIC_Pos                  (14UL)
#define IWDG_EWCR_EWIC_Msk                  (0x1UL << IWDG_EWCR_EWIC_Pos)           /*!< 0x00000FFF */
#define IWDG_EWCR_EWIC                      IWDG_EWCR_EWIC_Msk                      /*!< Watchdog early wakeup comparator value */
#define IWDG_EWCR_EWIE_Pos                  (15UL)
#define IWDG_EWCR_EWIE_Msk                  (0x1UL << IWDG_EWCR_EWIE_Pos)           /*!< 0x00000FFF */
#define IWDG_EWCR_EWIE                      IWDG_EWCR_EWIE_Msk                      /*!< Watchdog early wakeup comparator value */

/******************************************************************************/
/*                                                                            */
/*                         Low Power Timer (LPTIM)                            */
/*                                                                            */
/******************************************************************************/
/******************  Bit definition for LPTIM_ISR register  *******************/
#define LPTIM_ISR_CC1IF_Pos                 (0UL)
#define LPTIM_ISR_CC1IF_Msk                 (0x1UL << LPTIM_ISR_CC1IF_Pos)            /*!< 0x00000001 */
#define LPTIM_ISR_CC1IF                     LPTIM_ISR_CC1IF_Msk                       /*!< Capture/Compare 1 interrupt flag */
#define LPTIM_ISR_ARRM_Pos                  (1UL)
#define LPTIM_ISR_ARRM_Msk                  (0x1UL << LPTIM_ISR_ARRM_Pos)           /*!< 0x00000002 */
#define LPTIM_ISR_ARRM                      LPTIM_ISR_ARRM_Msk                      /*!< Autoreload match */
#define LPTIM_ISR_EXTTRIG_Pos               (2UL)
#define LPTIM_ISR_EXTTRIG_Msk               (0x1UL << LPTIM_ISR_EXTTRIG_Pos)        /*!< 0x00000004 */
#define LPTIM_ISR_EXTTRIG                   LPTIM_ISR_EXTTRIG_Msk                   /*!< External trigger edge event */
#define LPTIM_ISR_CMP1OK_Pos                (3UL)
#define LPTIM_ISR_CMP1OK_Msk                (0x1UL << LPTIM_ISR_CMP1OK_Pos)         /*!< 0x00000008 */
#define LPTIM_ISR_CMP1OK                    LPTIM_ISR_CMP1OK_Msk                    /*!< Compare register 1 update OK */
#define LPTIM_ISR_ARROK_Pos                 (4UL)
#define LPTIM_ISR_ARROK_Msk                 (0x1UL << LPTIM_ISR_ARROK_Pos)          /*!< 0x00000010 */
#define LPTIM_ISR_ARROK                     LPTIM_ISR_ARROK_Msk                     /*!< Autoreload register update OK */
#define LPTIM_ISR_UP_Pos                    (5UL)
#define LPTIM_ISR_UP_Msk                    (0x1UL << LPTIM_ISR_UP_Pos)             /*!< 0x00000020 */
#define LPTIM_ISR_UP                        LPTIM_ISR_UP_Msk                        /*!< Counter direction change down to up */
#define LPTIM_ISR_DOWN_Pos                  (6UL)
#define LPTIM_ISR_DOWN_Msk                  (0x1UL << LPTIM_ISR_DOWN_Pos)           /*!< 0x00000040 */
#define LPTIM_ISR_DOWN                      LPTIM_ISR_DOWN_Msk                      /*!< Counter direction change up to down */
#define LPTIM_ISR_UE_Pos                    (7UL)
#define LPTIM_ISR_UE_Msk                    (0x1UL << LPTIM_ISR_UE_Pos)             /*!< 0x00000080 */
#define LPTIM_ISR_UE                        LPTIM_ISR_UE_Msk                        /*!< Update event */
#define LPTIM_ISR_REPOK_Pos                 (8UL)
#define LPTIM_ISR_REPOK_Msk                 (0x1UL << LPTIM_ISR_REPOK_Pos)          /*!< 0x00000100 */
#define LPTIM_ISR_REPOK                     LPTIM_ISR_REPOK_Msk                     /*!< Repetition register update OK */
#define LPTIM_ISR_CC2IF_Pos                 (9UL)
#define LPTIM_ISR_CC2IF_Msk                 (0x1UL << LPTIM_ISR_CC2IF_Pos)          /*!< 0x00000200 */
#define LPTIM_ISR_CC2IF                     LPTIM_ISR_CC2IF_Msk                     /*!< Capture/Compare 2 interrupt flag */
#define LPTIM_ISR_CC1OF_Pos                 (12UL)
#define LPTIM_ISR_CC1OF_Msk                 (0x1UL << LPTIM_ISR_CC1OF_Pos)          /*!< 0x00001000 */
#define LPTIM_ISR_CC1OF                     LPTIM_ISR_CC1OF_Msk                     /*!< Capture/Compare 1 over-capture flag */
#define LPTIM_ISR_CC2OF_Pos                 (13UL)
#define LPTIM_ISR_CC2OF_Msk                 (0x1UL << LPTIM_ISR_CC2OF_Pos)          /*!< 0x00002000 */
#define LPTIM_ISR_CC2OF                     LPTIM_ISR_CC2OF_Msk                     /*!< Capture/Compare 2 over-capture flag */
#define LPTIM_ISR_CMP2OK_Pos                (19UL)
#define LPTIM_ISR_CMP2OK_Msk                (0x1UL << LPTIM_ISR_CMP2OK_Pos)         /*!< 0x00080000 */
#define LPTIM_ISR_CMP2OK                    LPTIM_ISR_CMP2OK_Msk                    /*!< Compare register 2 update OK */
#define LPTIM_ISR_DIEROK_Pos                (24UL)
#define LPTIM_ISR_DIEROK_Msk                (0x1UL << LPTIM_ISR_DIEROK_Pos)         /*!< 0x01000000 */
#define LPTIM_ISR_DIEROK                    LPTIM_ISR_DIEROK_Msk                    /*!< DMA & interrupt enable update OK */

/******************  Bit definition for LPTIM_ICR register  *******************/
#define LPTIM_ICR_CC1CF_Pos                 (0UL)
#define LPTIM_ICR_CC1CF_Msk                 (0x1UL << LPTIM_ICR_CC1CF_Pos)          /*!< 0x00000001 */
#define LPTIM_ICR_CC1CF                     LPTIM_ICR_CC1CF_Msk                     /*!< Capture/Compare 1 clear flag  */
#define LPTIM_ICR_ARRMCF_Pos                (1UL)
#define LPTIM_ICR_ARRMCF_Msk                (0x1UL << LPTIM_ICR_ARRMCF_Pos)         /*!< 0x00000002 */
#define LPTIM_ICR_ARRMCF                    LPTIM_ICR_ARRMCF_Msk                    /*!< Autoreload match clear flag */
#define LPTIM_ICR_EXTTRIGCF_Pos             (2UL)
#define LPTIM_ICR_EXTTRIGCF_Msk             (0x1UL << LPTIM_ICR_EXTTRIGCF_Pos)      /*!< 0x00000004 */
#define LPTIM_ICR_EXTTRIGCF                 LPTIM_ICR_EXTTRIGCF_Msk                 /*!< External trigger edge event clear flag */
#define LPTIM_ICR_CMP1OKCF_Pos              (3UL)
#define LPTIM_ICR_CMP1OKCF_Msk              (0x1UL << LPTIM_ICR_CMP1OKCF_Pos)       /*!< 0x00000008 */
#define LPTIM_ICR_CMP1OKCF                  LPTIM_ICR_CMP1OKCF_Msk                  /*!< Compare register 1 update OK clear flag */
#define LPTIM_ICR_ARROKCF_Pos               (4UL)
#define LPTIM_ICR_ARROKCF_Msk               (0x1UL << LPTIM_ICR_ARROKCF_Pos)        /*!< 0x00000010 */
#define LPTIM_ICR_ARROKCF                   LPTIM_ICR_ARROKCF_Msk                   /*!< Autoreload register update OK clear flag */
#define LPTIM_ICR_UPCF_Pos                  (5UL)
#define LPTIM_ICR_UPCF_Msk                  (0x1UL << LPTIM_ICR_UPCF_Pos)           /*!< 0x00000020 */
#define LPTIM_ICR_UPCF                      LPTIM_ICR_UPCF_Msk                      /*!< Counter direction change down to up clear flag */
#define LPTIM_ICR_DOWNCF_Pos                (6UL)
#define LPTIM_ICR_DOWNCF_Msk                (0x1UL << LPTIM_ICR_DOWNCF_Pos)         /*!< 0x00000040 */
#define LPTIM_ICR_DOWNCF                    LPTIM_ICR_DOWNCF_Msk                    /*!< Counter direction change up to down clear flag */
#define LPTIM_ICR_UECF_Pos                  (7UL)
#define LPTIM_ICR_UECF_Msk                  (0x1UL << LPTIM_ICR_UECF_Pos)           /*!< 0x00000080 */
#define LPTIM_ICR_UECF                      LPTIM_ICR_UECF_Msk                      /*!< Update event clear flag */
#define LPTIM_ICR_REPOKCF_Pos               (8UL)
#define LPTIM_ICR_REPOKCF_Msk               (0x1UL << LPTIM_ICR_REPOKCF_Pos)        /*!< 0x00000100 */
#define LPTIM_ICR_REPOKCF                   LPTIM_ICR_REPOKCF_Msk                   /*!< Repetition register update OK clear flag */
#define LPTIM_ICR_CC2CF_Pos                 (9UL)
#define LPTIM_ICR_CC2CF_Msk                 (0x1UL << LPTIM_ICR_CC2CF_Pos)          /*!< 0x00000200 */
#define LPTIM_ICR_CC2CF                     LPTIM_ICR_CC2CF_Msk                     /*!< Capture/Compare 2 clear flag  */
#define LPTIM_ICR_CC1OCF_Pos                (12UL)
#define LPTIM_ICR_CC1OCF_Msk                (0x1UL << LPTIM_ICR_CC1OCF_Pos)         /*!< 0x00001000 */
#define LPTIM_ICR_CC1OCF                    LPTIM_ICR_CC1OCF_Msk                    /*!< Capture/Compare 1 over-capture clear flag */
#define LPTIM_ICR_CC2OCF_Pos                (13UL)
#define LPTIM_ICR_CC2OCF_Msk                (0x1UL << LPTIM_ICR_CC2OCF_Pos)         /*!< 0x00002000 */
#define LPTIM_ICR_CC2OCF                    LPTIM_ICR_CC2OCF_Msk                    /*!< Capture/Compare 2 over-capture clear flag */
#define LPTIM_ICR_CMP2OKCF_Pos              (19UL)
#define LPTIM_ICR_CMP2OKCF_Msk              (0x1UL << LPTIM_ICR_CMP2OKCF_Pos)       /*!< 0x00080000 */
#define LPTIM_ICR_CMP2OKCF                  LPTIM_ICR_CMP2OKCF_Msk                  /*!< Compare register 2 update OK clear flag */
#define LPTIM_ICR_DIEROKCF_Pos              (24UL)
#define LPTIM_ICR_DIEROKCF_Msk              (0x1UL << LPTIM_ICR_DIEROKCF_Pos)       /*!< 0x01000000 */
#define LPTIM_ICR_DIEROKCF                  LPTIM_ICR_DIEROKCF_Msk                  /*!< Interrupt enable register update OK clear flag */
/******************  Bit definition for LPTIM_DIER register *******************/
#define LPTIM_DIER_CC1IE_Pos                (0UL)
#define LPTIM_DIER_CC1IE_Msk                (0x1UL << LPTIM_DIER_CC1IE_Pos)         /*!< 0x00000001 */
#define LPTIM_DIER_CC1IE                    LPTIM_DIER_CC1IE_Msk                    /*!< Compare/Compare interrupt enable */
#define LPTIM_DIER_ARRMIE_Pos               (1UL)
#define LPTIM_DIER_ARRMIE_Msk               (0x1UL << LPTIM_DIER_ARRMIE_Pos)        /*!< 0x00000002 */
#define LPTIM_DIER_ARRMIE                   LPTIM_DIER_ARRMIE_Msk                   /*!< Autoreload match interrupt enable */
#define LPTIM_DIER_EXTTRIGIE_Pos            (2UL)
#define LPTIM_DIER_EXTTRIGIE_Msk            (0x1UL << LPTIM_DIER_EXTTRIGIE_Pos)     /*!< 0x00000004 */
#define LPTIM_DIER_EXTTRIGIE                LPTIM_DIER_EXTTRIGIE_Msk                /*!< External trigger edge event interrupt enable */
#define LPTIM_DIER_CMP1OKIE_Pos             (3UL)
#define LPTIM_DIER_CMP1OKIE_Msk             (0x1UL << LPTIM_DIER_CMP1OKIE_Pos)      /*!< 0x00000008 */
#define LPTIM_DIER_CMP1OKIE                 LPTIM_DIER_CMP1OKIE_Msk                 /*!< Compare register 1 update OK interrupt enable */
#define LPTIM_DIER_ARROKIE_Pos              (4UL)
#define LPTIM_DIER_ARROKIE_Msk              (0x1UL << LPTIM_DIER_ARROKIE_Pos)       /*!< 0x00000010 */
#define LPTIM_DIER_ARROKIE                  LPTIM_DIER_ARROKIE_Msk                  /*!< Autoreload register update OK interrupt enable */
#define LPTIM_DIER_UPIE_Pos                 (5UL)
#define LPTIM_DIER_UPIE_Msk                 (0x1UL << LPTIM_DIER_UPIE_Pos)          /*!< 0x00000020 */
#define LPTIM_DIER_UPIE                     LPTIM_DIER_UPIE_Msk                     /*!< Counter direction change down to up interrupt enable */
#define LPTIM_DIER_DOWNIE_Pos               (6UL)
#define LPTIM_DIER_DOWNIE_Msk               (0x1UL << LPTIM_DIER_DOWNIE_Pos)        /*!< 0x00000040 */
#define LPTIM_DIER_DOWNIE                   LPTIM_DIER_DOWNIE_Msk                   /*!< Counter direction change up to down interrupt enable */
#define LPTIM_DIER_UEIE_Pos                 (7UL)
#define LPTIM_DIER_UEIE_Msk                 (0x1UL << LPTIM_DIER_UEIE_Pos)          /*!< 0x00000080 */
#define LPTIM_DIER_UEIE                     LPTIM_DIER_UEIE_Msk                     /*!< Update event interrupt enable */
#define LPTIM_DIER_REPOKIE_Pos              (8UL)
#define LPTIM_DIER_REPOKIE_Msk              (0x1UL << LPTIM_DIER_REPOKIE_Pos)       /*!< 0x00000100 */
#define LPTIM_DIER_REPOKIE                  LPTIM_DIER_REPOKIE_Msk                  /*!< Repetition register update OK interrupt enable */
#define LPTIM_DIER_CC2IE_Pos                (9UL)
#define LPTIM_DIER_CC2IE_Msk                (0x1UL << LPTIM_DIER_CC2IE_Pos)         /*!< 0x00000200 */
#define LPTIM_DIER_CC2IE                    LPTIM_DIER_CC2IE_Msk                    /*!< Capture/Compare 2 interrupt interrupt enable */
#define LPTIM_DIER_CC1OIE_Pos               (12UL)
#define LPTIM_DIER_CC1OIE_Msk               (0x1UL << LPTIM_DIER_CC1OIE_Pos)        /*!< 0x00001000 */
#define LPTIM_DIER_CC1OIE                   LPTIM_DIER_CC1OIE_Msk                   /*!< Capture/Compare 1 over-capture interrupt enable */
#define LPTIM_DIER_CC2OIE_Pos               (13UL)
#define LPTIM_DIER_CC2OIE_Msk               (0x1UL << LPTIM_DIER_CC2OIE_Pos)        /*!< 0x00002000 */
#define LPTIM_DIER_CC2OIE                   LPTIM_DIER_CC2OIE_Msk                   /*!< Capture/Compare 2 over-capture interrupt enable */
#define LPTIM_DIER_CC1DE_Pos                (16UL)
#define LPTIM_DIER_CC1DE_Msk                (0x1UL << LPTIM_DIER_CC1DE_Pos)         /*!< 0x00010000 */
#define LPTIM_DIER_CC1DE                    LPTIM_DIER_CC1DE_Msk                    /*!< Capture/Compare 1 DMA request enable */
#define LPTIM_DIER_CMP2OKIE_Pos             (19UL)
#define LPTIM_DIER_CMP2OKIE_Msk             (0x1UL << LPTIM_DIER_CMP2OKIE_Pos)      /*!< 0x00080000 */
#define LPTIM_DIER_CMP2OKIE                 LPTIM_DIER_CMP2OKIE_Msk                 /*!< Compare register 2 update OK interrupt enable */
#define LPTIM_DIER_UEDE_Pos                 (23UL)
#define LPTIM_DIER_UEDE_Msk                 (0x1UL << LPTIM_DIER_UEDE_Pos)          /*!< 0x00800000 */
#define LPTIM_DIER_UEDE                     LPTIM_DIER_UEDE_Msk                     /*!< Update event DMA request enable */
#define LPTIM_DIER_CC2DE_Pos                (25UL)
#define LPTIM_DIER_CC2DE_Msk                (0x1UL << LPTIM_DIER_CC2DE_Pos)         /*!< 0x02000000 */
#define LPTIM_DIER_CC2DE                    LPTIM_DIER_CC2DE_Msk                    /*!< Capture/Compare 2 DMA request enable */

/******************  Bit definition for LPTIM_CFGR register *******************/
#define LPTIM_CFGR_CKSEL_Pos                (0UL)
#define LPTIM_CFGR_CKSEL_Msk                (0x1UL << LPTIM_CFGR_CKSEL_Pos)         /*!< 0x00000001 */
#define LPTIM_CFGR_CKSEL                    LPTIM_CFGR_CKSEL_Msk                    /*!< Clock selector */
#define LPTIM_CFGR_CKPOL_Pos                (1UL)
#define LPTIM_CFGR_CKPOL_Msk                (0x3UL << LPTIM_CFGR_CKPOL_Pos)         /*!< 0x00000006 */
#define LPTIM_CFGR_CKPOL                    LPTIM_CFGR_CKPOL_Msk                    /*!< CKPOL[1:0] bits (Clock polarity) */
#define LPTIM_CFGR_CKPOL_0                  (0x1UL << LPTIM_CFGR_CKPOL_Pos)         /*!< 0x00000002 */
#define LPTIM_CFGR_CKPOL_1                  (0x2UL << LPTIM_CFGR_CKPOL_Pos)         /*!< 0x00000004 */
#define LPTIM_CFGR_CKFLT_Pos                (3UL)
#define LPTIM_CFGR_CKFLT_Msk                (0x3UL << LPTIM_CFGR_CKFLT_Pos)         /*!< 0x00000018 */
#define LPTIM_CFGR_CKFLT                    LPTIM_CFGR_CKFLT_Msk                    /*!< CKFLT[1:0] bits (Configurable digital filter for external clock) */
#define LPTIM_CFGR_CKFLT_0                  (0x1UL << LPTIM_CFGR_CKFLT_Pos)         /*!< 0x00000008 */
#define LPTIM_CFGR_CKFLT_1                  (0x2UL << LPTIM_CFGR_CKFLT_Pos)         /*!< 0x00000010 */
#define LPTIM_CFGR_TRGFLT_Pos               (6UL)
#define LPTIM_CFGR_TRGFLT_Msk               (0x3UL << LPTIM_CFGR_TRGFLT_Pos)        /*!< 0x000000C0 */
#define LPTIM_CFGR_TRGFLT                   LPTIM_CFGR_TRGFLT_Msk                   /*!< TRGFLT[1:0] bits (Configurable digital filter for trigger) */
#define LPTIM_CFGR_TRGFLT_0                 (0x1UL << LPTIM_CFGR_TRGFLT_Pos)        /*!< 0x00000040 */
#define LPTIM_CFGR_TRGFLT_1                 (0x2UL << LPTIM_CFGR_TRGFLT_Pos)        /*!< 0x00000080 */
#define LPTIM_CFGR_PRESC_Pos                (9UL)
#define LPTIM_CFGR_PRESC_Msk                (0x7UL << LPTIM_CFGR_PRESC_Pos)         /*!< 0x00000E00 */
#define LPTIM_CFGR_PRESC                    LPTIM_CFGR_PRESC_Msk                    /*!< PRESC[2:0] bits (Clock prescaler) */
#define LPTIM_CFGR_PRESC_0                  (0x1UL << LPTIM_CFGR_PRESC_Pos)         /*!< 0x00000200 */
#define LPTIM_CFGR_PRESC_1                  (0x2UL << LPTIM_CFGR_PRESC_Pos)         /*!< 0x00000400 */
#define LPTIM_CFGR_PRESC_2                  (0x4UL << LPTIM_CFGR_PRESC_Pos)         /*!< 0x00000800 */
#define LPTIM_CFGR_TRIGSEL_Pos              (13UL)
#define LPTIM_CFGR_TRIGSEL_Msk              (0x7UL << LPTIM_CFGR_TRIGSEL_Pos)       /*!< 0x0000E000 */
#define LPTIM_CFGR_TRIGSEL                  LPTIM_CFGR_TRIGSEL_Msk                  /*!< TRIGSEL[2:0]] bits (Trigger selector) */
#define LPTIM_CFGR_TRIGSEL_0                (0x1UL << LPTIM_CFGR_TRIGSEL_Pos)       /*!< 0x00002000 */
#define LPTIM_CFGR_TRIGSEL_1                (0x2UL << LPTIM_CFGR_TRIGSEL_Pos)       /*!< 0x00004000 */
#define LPTIM_CFGR_TRIGSEL_2                (0x4UL << LPTIM_CFGR_TRIGSEL_Pos)       /*!< 0x00008000 */
#define LPTIM_CFGR_TRIGEN_Pos               (17UL)
#define LPTIM_CFGR_TRIGEN_Msk               (0x3UL << LPTIM_CFGR_TRIGEN_Pos)        /*!< 0x00060000 */
#define LPTIM_CFGR_TRIGEN                   LPTIM_CFGR_TRIGEN_Msk                   /*!< TRIGEN[1:0] bits (Trigger enable and polarity) */
#define LPTIM_CFGR_TRIGEN_0                 (0x1UL << LPTIM_CFGR_TRIGEN_Pos)        /*!< 0x00020000 */
#define LPTIM_CFGR_TRIGEN_1                 (0x2UL << LPTIM_CFGR_TRIGEN_Pos)        /*!< 0x00040000 */
#define LPTIM_CFGR_TIMOUT_Pos               (19UL)
#define LPTIM_CFGR_TIMOUT_Msk               (0x1UL << LPTIM_CFGR_TIMOUT_Pos)        /*!< 0x00080000 */
#define LPTIM_CFGR_TIMOUT                   LPTIM_CFGR_TIMOUT_Msk                   /*!< Timout enable */
#define LPTIM_CFGR_WAVE_Pos                 (20UL)
#define LPTIM_CFGR_WAVE_Msk                 (0x1UL << LPTIM_CFGR_WAVE_Pos)          /*!< 0x00100000 */
#define LPTIM_CFGR_WAVE                     LPTIM_CFGR_WAVE_Msk                     /*!< Waveform shape */
#define LPTIM_CFGR_WAVPOL_Pos               (21UL)
#define LPTIM_CFGR_WAVPOL_Msk               (0x1UL << LPTIM_CFGR_WAVPOL_Pos)        /*!< 0x00200000 */
#define LPTIM_CFGR_WAVPOL                   LPTIM_CFGR_WAVPOL_Msk                   /*!< Waveform shape */
#define LPTIM_CFGR_PRELOAD_Pos              (22UL)
#define LPTIM_CFGR_PRELOAD_Msk              (0x1UL << LPTIM_CFGR_PRELOAD_Pos)       /*!< 0x00400000 */
#define LPTIM_CFGR_PRELOAD                  LPTIM_CFGR_PRELOAD_Msk                  /*!< Reg update mode */
#define LPTIM_CFGR_COUNTMODE_Pos            (23UL)
#define LPTIM_CFGR_COUNTMODE_Msk            (0x1UL << LPTIM_CFGR_COUNTMODE_Pos)     /*!< 0x00800000 */
#define LPTIM_CFGR_COUNTMODE                LPTIM_CFGR_COUNTMODE_Msk                /*!< Counter mode enable */
#define LPTIM_CFGR_ENC_Pos                  (24UL)
#define LPTIM_CFGR_ENC_Msk                  (0x1UL << LPTIM_CFGR_ENC_Pos)           /*!< 0x01000000 */
#define LPTIM_CFGR_ENC                      LPTIM_CFGR_ENC_Msk                      /*!< Encoder mode enable */

/******************  Bit definition for LPTIM_CR register  ********************/
#define LPTIM_CR_ENABLE_Pos                 (0UL)
#define LPTIM_CR_ENABLE_Msk                 (0x1UL << LPTIM_CR_ENABLE_Pos)          /*!< 0x00000001 */
#define LPTIM_CR_ENABLE                     LPTIM_CR_ENABLE_Msk                     /*!< LPTIMer enable */
#define LPTIM_CR_SNGSTRT_Pos                (1UL)
#define LPTIM_CR_SNGSTRT_Msk                (0x1UL << LPTIM_CR_SNGSTRT_Pos)         /*!< 0x00000002 */
#define LPTIM_CR_SNGSTRT                    LPTIM_CR_SNGSTRT_Msk                    /*!< Timer start in single mode */
#define LPTIM_CR_CNTSTRT_Pos                (2UL)
#define LPTIM_CR_CNTSTRT_Msk                (0x1UL << LPTIM_CR_CNTSTRT_Pos)         /*!< 0x00000004 */
#define LPTIM_CR_CNTSTRT                    LPTIM_CR_CNTSTRT_Msk                    /*!< Timer start in continuous mode */
#define LPTIM_CR_COUNTRST_Pos               (3UL)
#define LPTIM_CR_COUNTRST_Msk               (0x1UL << LPTIM_CR_COUNTRST_Pos)        /*!< 0x00000008 */
#define LPTIM_CR_COUNTRST                   LPTIM_CR_COUNTRST_Msk                   /*!< Timer Counter reset in synchronous mode*/
#define LPTIM_CR_RSTARE_Pos                 (4UL)
#define LPTIM_CR_RSTARE_Msk                 (0x1UL << LPTIM_CR_RSTARE_Pos)          /*!< 0x00000010 */
#define LPTIM_CR_RSTARE                     LPTIM_CR_RSTARE_Msk                     /*!< Timer Counter reset after read enable (asynchronously)*/

/******************  Bit definition for LPTIM_CCR1 register  ******************/
#define LPTIM_CCR1_CCR1_Pos                 (0UL)
#define LPTIM_CCR1_CCR1_Msk                 (0xFFFFUL << LPTIM_CCR1_CCR1_Pos)       /*!< 0x0000FFFF */
#define LPTIM_CCR1_CCR1                     LPTIM_CCR1_CCR1_Msk                     /*!< Compare register 1 */

/******************  Bit definition for LPTIM_ARR register  *******************/
#define LPTIM_ARR_ARR_Pos                   (0UL)
#define LPTIM_ARR_ARR_Msk                   (0xFFFFUL << LPTIM_ARR_ARR_Pos)         /*!< 0x0000FFFF */
#define LPTIM_ARR_ARR                       LPTIM_ARR_ARR_Msk                       /*!< Auto reload register */

/******************  Bit definition for LPTIM_CNT register  *******************/
#define LPTIM_CNT_CNT_Pos                   (0UL)
#define LPTIM_CNT_CNT_Msk                   (0xFFFFUL << LPTIM_CNT_CNT_Pos)         /*!< 0x0000FFFF */
#define LPTIM_CNT_CNT                       LPTIM_CNT_CNT_Msk                       /*!< Counter register */

/******************  Bit definition for LPTIM_CFGR2 register  *****************/
#define LPTIM_CFGR2_IN1SEL_Pos              (0UL)
#define LPTIM_CFGR2_IN1SEL_Msk              (0x3UL << LPTIM_CFGR2_IN1SEL_Pos)       /*!< 0x00000003 */
#define LPTIM_CFGR2_IN1SEL                  LPTIM_CFGR2_IN1SEL_Msk                  /*!< IN1SEL[1:0] bits (Remap selection) */
#define LPTIM_CFGR2_IN1SEL_0                (0x1UL << LPTIM_CFGR2_IN1SEL_Pos)       /*!< 0x00000001 */
#define LPTIM_CFGR2_IN1SEL_1                (0x2UL << LPTIM_CFGR2_IN1SEL_Pos)       /*!< 0x00000002 */
#define LPTIM_CFGR2_IN2SEL_Pos              (4UL)
#define LPTIM_CFGR2_IN2SEL_Msk              (0x3UL << LPTIM_CFGR2_IN2SEL_Pos)       /*!< 0x00000030 */
#define LPTIM_CFGR2_IN2SEL                  LPTIM_CFGR2_IN2SEL_Msk                  /*!< IN2SEL[5:4] bits (Remap selection) */
#define LPTIM_CFGR2_IN2SEL_0                (0x1UL << LPTIM_CFGR2_IN2SEL_Pos)       /*!< 0x00000010 */
#define LPTIM_CFGR2_IN2SEL_1                (0x2UL << LPTIM_CFGR2_IN2SEL_Pos)       /*!< 0x00000020 */
#define LPTIM_CFGR2_IC1SEL_Pos              (16UL)
#define LPTIM_CFGR2_IC1SEL_Msk              (0x3UL << LPTIM_CFGR2_IC1SEL_Pos)       /*!< 0x00000003 */
#define LPTIM_CFGR2_IC1SEL                  LPTIM_CFGR2_IC1SEL_Msk                  /*!< IC1SEL[17:16] bits */
#define LPTIM_CFGR2_IC1SEL_0                (0x1UL << LPTIM_CFGR2_IC1SEL_Pos)       /*!< 0x00010000 */
#define LPTIM_CFGR2_IC1SEL_1                (0x2UL << LPTIM_CFGR2_IC1SEL_Pos)       /*!< 0x00020000 */
#define LPTIM_CFGR2_IC2SEL_Pos              (20UL)
#define LPTIM_CFGR2_IC2SEL_Msk              (0x3UL << LPTIM_CFGR2_IC2SEL_Pos)       /*!< 0x00000030 */
#define LPTIM_CFGR2_IC2SEL                  LPTIM_CFGR2_IC2SEL_Msk                  /*!< IC2SEL[21:20] bits */
#define LPTIM_CFGR2_IC2SEL_0                (0x1UL << LPTIM_CFGR2_IC2SEL_Pos)       /*!< 0x00100000 */
#define LPTIM_CFGR2_IC2SEL_1                (0x2UL << LPTIM_CFGR2_IC2SEL_Pos)       /*!< 0x00200000 */

/******************  Bit definition for LPTIM_RCR register  *******************/
#define LPTIM_RCR_REP_Pos                   (0UL)
#define LPTIM_RCR_REP_Msk                   (0xFFUL << LPTIM_RCR_REP_Pos)           /*!< 0x000000FF */
#define LPTIM_RCR_REP                       LPTIM_RCR_REP_Msk                       /*!< Repetition register value */

/*****************  Bit definition for LPTIM_CCMR1 register  ******************/
#define LPTIM_CCMR1_CC1SEL_Pos              (0UL)
#define LPTIM_CCMR1_CC1SEL_Msk              (0x1UL << LPTIM_CCMR1_CC1SEL_Pos)       /*!< 0x00000001 */
#define LPTIM_CCMR1_CC1SEL                  LPTIM_CCMR1_CC1SEL_Msk                  /*!< Capture/Compare 1 selection */
#define LPTIM_CCMR1_CC1E_Pos                (1UL)
#define LPTIM_CCMR1_CC1E_Msk                (0x1UL << LPTIM_CCMR1_CC1E_Pos)         /*!< 0x00000002 */
#define LPTIM_CCMR1_CC1E                    LPTIM_CCMR1_CC1E_Msk                    /*!< Capture/Compare 1 output enable */
#define LPTIM_CCMR1_CC1P_Pos                (2UL)
#define LPTIM_CCMR1_CC1P_Msk                (0x3UL << LPTIM_CCMR1_CC1P_Pos)         /*!< 0x0000000C */
#define LPTIM_CCMR1_CC1P                    LPTIM_CCMR1_CC1P_Msk                    /*!< Capture/Compare 1 output polarity */
#define LPTIM_CCMR1_CC1P_0                  (0x1UL << LPTIM_CCMR1_CC1P_Pos)         /*!< 0x00000004 */
#define LPTIM_CCMR1_CC1P_1                  (0x2UL << LPTIM_CCMR1_CC1P_Pos)         /*!< 0x00000008 */
#define LPTIM_CCMR1_IC1PSC_Pos              (8UL)
#define LPTIM_CCMR1_IC1PSC_Msk              (0x3UL << LPTIM_CCMR1_IC1PSC_Pos)       /*!< 0x00000300 */
#define LPTIM_CCMR1_IC1PSC                  LPTIM_CCMR1_IC1PSC_Msk                  /*!< Input capture 1 prescaler */
#define LPTIM_CCMR1_IC1PSC_0                (0x1UL << LPTIM_CCMR1_IC1PSC_Pos)       /*!< 0x00000100 */
#define LPTIM_CCMR1_IC1PSC_1                (0x2UL << LPTIM_CCMR1_IC1PSC_Pos)       /*!< 0x00000200 */
#define LPTIM_CCMR1_IC1F_Pos                (12UL)
#define LPTIM_CCMR1_IC1F_Msk                (0x3UL << LPTIM_CCMR1_IC1F_Pos)         /*!< 0x00003000 */
#define LPTIM_CCMR1_IC1F                    LPTIM_CCMR1_IC1F_Msk                    /*!< Input capture 1 filter */
#define LPTIM_CCMR1_IC1F_0                  (0x1UL << LPTIM_CCMR1_IC1F_Pos)         /*!< 0x00001000 */
#define LPTIM_CCMR1_IC1F_1                  (0x2UL << LPTIM_CCMR1_IC1F_Pos)         /*!< 0x00002000 */
#define LPTIM_CCMR1_CC2SEL_Pos              (16UL)
#define LPTIM_CCMR1_CC2SEL_Msk              (0x1UL << LPTIM_CCMR1_CC2SEL_Pos)       /*!< 0x00010000 */
#define LPTIM_CCMR1_CC2SEL                  LPTIM_CCMR1_CC2SEL_Msk                  /*!< Capture/Compare 2 selection */
#define LPTIM_CCMR1_CC2E_Pos                (17UL)
#define LPTIM_CCMR1_CC2E_Msk                (0x1UL << LPTIM_CCMR1_CC2E_Pos)         /*!< 0x00020000 */
#define LPTIM_CCMR1_CC2E                    LPTIM_CCMR1_CC2E_Msk                    /*!< Capture/Compare 2 output enable */
#define LPTIM_CCMR1_CC2P_Pos                (18UL)
#define LPTIM_CCMR1_CC2P_Msk                (0x3UL << LPTIM_CCMR1_CC2P_Pos)         /*!< 0x000C0000 */
#define LPTIM_CCMR1_CC2P                    LPTIM_CCMR1_CC2P_Msk                    /*!< Capture/Compare 2 output polarity */
#define LPTIM_CCMR1_CC2P_0                  (0x1UL << LPTIM_CCMR1_CC2P_Pos)         /*!< 0x00040000 */
#define LPTIM_CCMR1_CC2P_1                  (0x2UL << LPTIM_CCMR1_CC2P_Pos)         /*!< 0x00080000 */
#define LPTIM_CCMR1_IC2PSC_Pos              (24UL)
#define LPTIM_CCMR1_IC2PSC_Msk              (0x3UL << LPTIM_CCMR1_IC2PSC_Pos)       /*!< 0x03000000 */
#define LPTIM_CCMR1_IC2PSC                  LPTIM_CCMR1_IC2PSC_Msk                  /*!< Input capture 2 prescaler */
#define LPTIM_CCMR1_IC2PSC_0                (0x1UL << LPTIM_CCMR1_IC2PSC_Pos)       /*!< 0x01000000 */
#define LPTIM_CCMR1_IC2PSC_1                (0x2UL << LPTIM_CCMR1_IC2PSC_Pos)       /*!< 0x02000000 */
#define LPTIM_CCMR1_IC2F_Pos                (28UL)
#define LPTIM_CCMR1_IC2F_Msk                (0x3UL << LPTIM_CCMR1_IC2F_Pos)         /*!< 0x30000000 */
#define LPTIM_CCMR1_IC2F                    LPTIM_CCMR1_IC2F_Msk                    /*!< Input capture 2 filter */
#define LPTIM_CCMR1_IC2F_0                  (0x1UL << LPTIM_CCMR1_IC2F_Pos)         /*!< 0x10000000 */
#define LPTIM_CCMR1_IC2F_1                  (0x2UL << LPTIM_CCMR1_IC2F_Pos)         /*!< 0x20000000 */

/******************  Bit definition for LPTIM_CCR2 register  ******************/
#define LPTIM_CCR2_CCR2_Pos                 (0UL)
#define LPTIM_CCR2_CCR2_Msk                 (0xFFFFUL << LPTIM_CCR2_CCR2_Pos)       /*!< 0x0000FFFF */
#define LPTIM_CCR2_CCR2                     LPTIM_CCR2_CCR2_Msk                     /*!< Compare register 2 */

/******************************************************************************/
/*                                                                            */
/*                                 MDF/ADF                                    */
/*                                                                            */
/******************************************************************************/
/*******************  Bit definition for MDF/ADF_GCR register  ********************/
#define MDF_GCR_TRGO_Pos                    (0UL)
#define MDF_GCR_TRGO_Msk                    (0x1UL << MDF_GCR_TRGO_Pos)             /*!< 0x00000001 */
#define MDF_GCR_TRGO                        MDF_GCR_TRGO_Msk                        /*!<Trigger output control */

/*******************  Bit definition for MDF/ADF_CKGCR register  ********************/
#define MDF_CKGCR_CKGDEN_Pos                (0UL)
#define MDF_CKGCR_CKGDEN_Msk                (0x1UL << MDF_CKGCR_CKGDEN_Pos)         /*!< 0x00000001 */
#define MDF_CKGCR_CKGDEN                    MDF_CKGCR_CKGDEN_Msk                    /*!<CKGDEN dividers enable */
#define MDF_CKGCR_CCK0EN_Pos                (1UL)
#define MDF_CKGCR_CCK0EN_Msk                (0x1UL << MDF_CKGCR_CCK0EN_Pos)         /*!< 0x00000002 */
#define MDF_CKGCR_CCK0EN                    MDF_CKGCR_CCK0EN_Msk                    /*!<CCK0 clock enable */
#define MDF_CKGCR_CCK1EN_Pos                (2UL)
#define MDF_CKGCR_CCK1EN_Msk                (0x1UL << MDF_CKGCR_CCK1EN_Pos)         /*!< 0x00000004 */
#define MDF_CKGCR_CCK1EN                    MDF_CKGCR_CCK1EN_Msk                    /*!<CCK1 clock enable */
#define MDF_CKGCR_CKGMOD_Pos                (4UL)
#define MDF_CKGCR_CKGMOD_Msk                (0x1UL << MDF_CKGCR_CKGMOD_Pos)         /*!< 0x00000010 */
#define MDF_CKGCR_CKGMOD                    MDF_CKGCR_CKGMOD_Msk                    /*!<Clock genartor mode */
#define MDF_CKGCR_CCK0DIR_Pos               (5UL)
#define MDF_CKGCR_CCK0DIR_Msk               (0x1UL << MDF_CKGCR_CCK0DIR_Pos)        /*!< 0x00000020 */
#define MDF_CKGCR_CCK0DIR                   MDF_CKGCR_CCK0DIR_Msk                   /*!<CCK0 clock direction */
#define MDF_CKGCR_CCK1DIR_Pos               (6UL)
#define MDF_CKGCR_CCK1DIR_Msk               (0x1UL << MDF_CKGCR_CCK1DIR_Pos)        /*!< 0x00000040 */
#define MDF_CKGCR_CCK1DIR                   MDF_CKGCR_CCK1DIR_Msk                   /*!<CCK1 clock direction */
#define MDF_CKGCR_TRGSENS_Pos               (8UL)
#define MDF_CKGCR_TRGSENS_Msk               (0x1UL << MDF_CKGCR_TRGSENS_Pos)        /*!< 0x00000100 */
#define MDF_CKGCR_TRGSENS                   MDF_CKGCR_TRGSENS_Msk                   /*!<CKGEN trigger sensitivity selection */
#define MDF_CKGCR_TRGSRC_Pos                (12UL)
#define MDF_CKGCR_TRGSRC_Msk                (0xFUL << MDF_CKGCR_TRGSRC_Pos)         /*!< 0x0000F000 */
#define MDF_CKGCR_TRGSRC                    MDF_CKGCR_TRGSRC_Msk                    /*!<Digital Filter trigger signal selection */
#define MDF_CKGCR_TRGSRC_0                  (0x1UL << MDF_CKGCR_TRGSRC_Pos)         /*!< 0x00001000 */
#define MDF_CKGCR_TRGSRC_1                  (0x2UL << MDF_CKGCR_TRGSRC_Pos)         /*!< 0x00002000 */
#define MDF_CKGCR_TRGSRC_2                  (0x4UL << MDF_CKGCR_TRGSRC_Pos)         /*!< 0x00004000 */
#define MDF_CKGCR_TRGSRC_3                  (0x8UL << MDF_CKGCR_TRGSRC_Pos)         /*!< 0x00008000 */
#define MDF_CKGCR_CCKDIV_Pos                (16UL)
#define MDF_CKGCR_CCKDIV_Msk                (0xFUL << MDF_CKGCR_CCKDIV_Pos)         /*!< 0x000F0000 */
#define MDF_CKGCR_CCKDIV                    MDF_CKGCR_CCKDIV_Msk                    /*!<Divider to control the MDF_CCK clock */
#define MDF_CKGCR_PROCDIV_Pos               (24UL)
#define MDF_CKGCR_PROCDIV_Msk               (0x7FUL << MDF_CKGCR_PROCDIV_Pos)       /*!< 0x7F000000 */
#define MDF_CKGCR_PROCDIV                   MDF_CKGCR_PROCDIV_Msk                   /*!<Divider to control the serial interface clock */
#define MDF_CKGCR_CKGACTIVE_Pos             (31UL)
#define MDF_CKGCR_CKGACTIVE_Msk             (0x1UL << MDF_CKGCR_CKGACTIVE_Pos)      /*!< 0x80000000 */
#define MDF_CKGCR_CKGACTIVE                 MDF_CKGCR_CKGACTIVE_Msk                 /*!<Clock generator active flag */

/*******************  Bit definition for MDF/ADF_TRGISELR register  ********************/
#define MDF_TRGISELR_TRGISEL_Pos            (0UL)
#define MDF_TRGISELR_TRGISEL_Msk            (0x3UL << MDF_TRGISELR_TRGISEL_Pos)     /*!< 0x00000003 */
#define MDF_TRGISELR_TRGISEL                MDF_TRGISELR_TRGISEL_Msk                /*!<Trigger input selection */
#define MDF_TRGISELR_TRGISEL_0              (0x1UL << MDF_TRGISELR_TRGISEL_Pos)     /*!< 0x00000001 */
#define MDF_TRGISELR_TRGISEL_1              (0x2UL << MDF_TRGISELR_TRGISEL_Pos)     /*!< 0x00000010 */

/*******************  Bit definition for MDF/ADF_SITFxCR register  ********************/
#define MDF_SITFCR_SITFEN_Pos               (0UL)
#define MDF_SITFCR_SITFEN_Msk               (0x1UL << MDF_SITFCR_SITFEN_Pos)        /*!< 0x00000001 */
#define MDF_SITFCR_SITFEN                   MDF_SITFCR_SITFEN_Msk                   /*!<Serial interface enable */
#define MDF_SITFCR_SCKSRC_Pos               (1UL)
#define MDF_SITFCR_SCKSRC_Msk               (0x3UL << MDF_SITFCR_SCKSRC_Pos)        /*!< 0x00000006 */
#define MDF_SITFCR_SCKSRC                   MDF_SITFCR_SCKSRC_Msk                   /*!<Serial clock source */
#define MDF_SITFCR_SCKSRC_0                 (0x1UL << MDF_SITFCR_SCKSRC_Pos)
#define MDF_SITFCR_SCKSRC_1                 (0x2UL << MDF_SITFCR_SCKSRC_Pos)
#define MDF_SITFCR_SITFMOD_Pos              (4UL)
#define MDF_SITFCR_SITFMOD_Msk              (0x3UL << MDF_SITFCR_SITFMOD_Pos)       /*!< 0x00000030 */
#define MDF_SITFCR_SITFMOD                  MDF_SITFCR_SITFMOD_Msk                  /*!<Serial interface type */
#define MDF_SITFCR_SITFMOD_0                (0x1UL << MDF_SITFCR_SITFMOD_Pos)       /*!< 0x00000010 */
#define MDF_SITFCR_SITFMOD_1                (0x2UL << MDF_SITFCR_SITFMOD_Pos)       /*!< 0x00000020 */
#define MDF_SITFCR_STH_Pos                  (8UL)
#define MDF_SITFCR_STH_Msk                  (0x1FUL << MDF_SITFCR_STH_Pos)          /*!< 0x00001F00 */
#define MDF_SITFCR_STH                      MDF_SITFCR_STH_Msk                      /*!<Manchester Symbol threshold / SPI threshold */
#define MDF_SITFCR_SITFACTIVE_Pos           (31UL)
#define MDF_SITFCR_SITFACTIVE_Msk           (0x1UL << MDF_SITFCR_SITFACTIVE_Pos)    /*!< 0x80000000 */
#define MDF_SITFCR_SITFACTIVE               MDF_SITFCR_SITFACTIVE_Msk               /*!<Serial interface active flag */

/*******************  Bit definition for MDF/ADF_BSMXxCR register  ********************/
#define MDF_BSMXCR_BSSEL_Pos                (0UL)
#define MDF_BSMXCR_BSSEL_Msk                (0x1FUL << MDF_BSMXCR_BSSEL_Pos)        /*!< 0x0000001F */
#define MDF_BSMXCR_BSSEL                    MDF_BSMXCR_BSSEL_Msk                    /*!<Bit Streal selection */
#define MDF_BSMXCR_BSSEL_0                  (0x1UL  << MDF_BSMXCR_BSSEL_Pos)        /*!< 0x00000001 */
#define MDF_BSMXCR_BSSEL_1                  (0x2UL  << MDF_BSMXCR_BSSEL_Pos)        /*!< 0x00000002 */
#define MDF_BSMXCR_BSSEL_2                  (0x4UL  << MDF_BSMXCR_BSSEL_Pos)        /*!< 0x00000004 */
#define MDF_BSMXCR_BSSEL_3                  (0x8UL  << MDF_BSMXCR_BSSEL_Pos)        /*!< 0x00000008 */
#define MDF_BSMXCR_BSSEL_4                  (0x10UL  << MDF_BSMXCR_BSSEL_Pos)       /*!< 0x00000010 */
#define MDF_BSMXCR_BSMXACTIVE_Pos           (31UL)
#define MDF_BSMXCR_BSMXACTIVE_Msk           (0x1UL << MDF_BSMXCR_BSMXACTIVE_Pos)    /*!< 0x80000000 */
#define MDF_BSMXCR_BSMXACTIVE               MDF_BSMXCR_BSMXACTIVE_Msk               /*!<Bit Streal activation flag */

/*******************  Bit definition for MDF/ADF_DFLTxCR register  ********************/
#define MDF_DFLTCR_DFLTEN_Pos               (0UL)
#define MDF_DFLTCR_DFLTEN_Msk               (0x1UL << MDF_DFLTCR_DFLTEN_Pos)        /*!< 0x00000001 */
#define MDF_DFLTCR_DFLTEN                   MDF_DFLTCR_DFLTEN_Msk                   /*!<Digital filter enable */
#define MDF_DFLTCR_DMAEN_Pos                (1UL)
#define MDF_DFLTCR_DMAEN_Msk                (0x1UL << MDF_DFLTCR_DMAEN_Pos)         /*!< 0x00000002 */
#define MDF_DFLTCR_DMAEN                    MDF_DFLTCR_DMAEN_Msk                    /*!<DMA request enable */
#define MDF_DFLTCR_FTH_Pos                  (2UL)
#define MDF_DFLTCR_FTH_Msk                  (0x1UL << MDF_DFLTCR_FTH_Pos)           /*!< 0x00000004 */
#define MDF_DFLTCR_FTH                      MDF_DFLTCR_FTH_Msk                      /*!<RXFIFO Threshold selection */
#define MDF_DFLTCR_ACQMOD_Pos               (4UL)
#define MDF_DFLTCR_ACQMOD_Msk               (0x7UL << MDF_DFLTCR_ACQMOD_Pos)        /*!< 0x00000004 */
#define MDF_DFLTCR_ACQMOD                   MDF_DFLTCR_ACQMOD_Msk                   /*!<Digital filter trigger mode */
#define MDF_DFLTCR_ACQMOD_0                 (0x1UL << MDF_DFLTCR_ACQMOD_Pos)        /*!< 0x00000010 */
#define MDF_DFLTCR_ACQMOD_1                 (0x2UL << MDF_DFLTCR_ACQMOD_Pos)        /*!< 0x00000020 */
#define MDF_DFLTCR_ACQMOD_2                 (0x4UL << MDF_DFLTCR_ACQMOD_Pos)        /*!< 0x00000040 */
#define MDF_DFLTCR_TRGSENS_Pos              (8UL)
#define MDF_DFLTCR_TRGSENS_Msk              (0x1UL << MDF_DFLTCR_TRGSENS_Pos)       /*!< 0x00000004 */
#define MDF_DFLTCR_TRGSENS                  MDF_DFLTCR_TRGSENS_Msk                  /*!<Digital filter trigger sensitivity selection */
#define MDF_DFLTCR_TRGSRC_Pos               (12UL)
#define MDF_DFLTCR_TRGSRC_Msk               (0xFUL << MDF_DFLTCR_TRGSRC_Pos)        /*!< 0x00000004 */
#define MDF_DFLTCR_TRGSRC                   MDF_DFLTCR_TRGSRC_Msk                   /*!<Digital filter trigger signal selection */
#define MDF_DFLTCR_TRGSRC_0                 (0x1UL << MDF_DFLTCR_TRGSRC_Pos)        /*!< 0x00001000 */
#define MDF_DFLTCR_TRGSRC_1                 (0x2UL << MDF_DFLTCR_TRGSRC_Pos)        /*!< 0x00002000 */
#define MDF_DFLTCR_TRGSRC_2                 (0x4UL << MDF_DFLTCR_TRGSRC_Pos)        /*!< 0x00004000 */
#define MDF_DFLTCR_TRGSRC_3                 (0x8UL << MDF_DFLTCR_TRGSRC_Pos)        /*!< 0x00008000 */
#define MDF_DFLTCR_NBDIS_Pos                (20UL)
#define MDF_DFLTCR_NBDIS_Msk                (0xFFUL << MDF_DFLTCR_NBDIS_Pos)        /*!< 0x00000004 */
#define MDF_DFLTCR_NBDIS                    MDF_DFLTCR_NBDIS_Msk                    /*!<Number of samples to be discard */
#define MDF_DFLTCR_DFLTRUN_Pos              (30UL)
#define MDF_DFLTCR_DFLTRUN_Msk              (0x1UL << MDF_DFLTCR_DFLTRUN_Pos)       /*!< 0x00000004 */
#define MDF_DFLTCR_DFLTRUN                  MDF_DFLTCR_DFLTRUN_Msk                  /*!<Digital filter run status flag */
#define MDF_DFLTCR_DFLTACTIVE_Pos           (31UL)
#define MDF_DFLTCR_DFLTACTIVE_Msk           (0x1UL << MDF_DFLTCR_DFLTACTIVE_Pos)    /*!< 0x00000004 */
#define MDF_DFLTCR_DFLTACTIVE               MDF_DFLTCR_DFLTACTIVE_Msk               /*!<Digital filter active flag */

/*******************  Bit definition for MDF/ADF_DFLTxCICR register  ********************/
#define MDF_DFLTCICR_DATSRC_Pos             (0UL)
#define MDF_DFLTCICR_DATSRC_Msk             (0x3UL << MDF_DFLTCICR_DATSRC_Pos)      /*!< 0x00000003 */
#define MDF_DFLTCICR_DATSRC                 MDF_DFLTCICR_DATSRC_Msk                 /*!<Source Data for the digital filter */
#define MDF_DFLTCICR_DATSRC_0               (0x1UL << MDF_DFLTCICR_DATSRC_Pos)      /*!< 0x00000001 */
#define MDF_DFLTCICR_DATSRC_1               (0x2UL << MDF_DFLTCICR_DATSRC_Pos)      /*!< 0x00000002 */
#define MDF_DFLTCICR_CICMOD_Pos             (4UL)
#define MDF_DFLTCICR_CICMOD_Msk             (0x7UL << MDF_DFLTCICR_CICMOD_Pos)      /*!< 0x00000070 */
#define MDF_DFLTCICR_CICMOD                 MDF_DFLTCICR_CICMOD_Msk                 /*!<Select the CIC Mode*/
#define MDF_DFLTCICR_CICMOD_0               (0x1UL << MDF_DFLTCICR_CICMOD_Pos)      /*!< 0x00000010 */
#define MDF_DFLTCICR_CICMOD_1               (0x2UL << MDF_DFLTCICR_CICMOD_Pos)      /*!< 0x00000020 */
#define MDF_DFLTCICR_CICMOD_2               (0x4UL << MDF_DFLTCICR_CICMOD_Pos)      /*!< 0x00000030 */
#define MDF_DFLTCICR_MCICD_Pos              (8UL)
#define MDF_DFLTCICR_MCICD_Msk              (0x1FFUL << MDF_DFLTCICR_MCICD_Pos)     /*!< 0x0001FF00 */
#define MDF_DFLTCICR_MCICD                  MDF_DFLTCICR_MCICD_Msk                  /*!<CIC decimation ratio selection*/
#define MDF_DFLTCICR_SCALE_Pos              (20UL)
#define MDF_DFLTCICR_SCALE_Msk              (0x3FUL << MDF_DFLTCICR_SCALE_Pos)      /*!< 0x03F00000 */
#define MDF_DFLTCICR_SCALE                  MDF_DFLTCICR_SCALE_Msk                  /*!<Scaling factor selection*/

/*******************  Bit definition for MDF/ADF_DFLTxRSFR register  ********************/
#define MDF_DFLTRSFR_RSFLTBYP_Pos           (0UL)
#define MDF_DFLTRSFR_RSFLTBYP_Msk           (0x1UL << MDF_DFLTRSFR_RSFLTBYP_Pos)    /*!< 0x00000001 */
#define MDF_DFLTRSFR_RSFLTBYP               MDF_DFLTRSFR_RSFLTBYP_Msk               /*!<Reshape filter bypass*/
#define MDF_DFLTRSFR_RSFLTD_Pos             (4UL)
#define MDF_DFLTRSFR_RSFLTD_Msk             (0x1UL << MDF_DFLTRSFR_RSFLTD_Pos)      /*!< 0x00000010 */
#define MDF_DFLTRSFR_RSFLTD                 MDF_DFLTRSFR_RSFLTD_Msk                 /*!<Reshape filter decimation ratio*/
#define MDF_DFLTRSFR_HPFBYP_Pos             (7UL)
#define MDF_DFLTRSFR_HPFBYP_Msk             (0x1UL << MDF_DFLTRSFR_HPFBYP_Pos)      /*!< 0x00000080 */
#define MDF_DFLTRSFR_HPFBYP                 MDF_DFLTRSFR_HPFBYP_Msk                 /*!<High-pass filter bypass*/
#define MDF_DFLTRSFR_HPFC_Pos               (8UL)
#define MDF_DFLTRSFR_HPFC_Msk               (0x3UL << MDF_DFLTRSFR_HPFC_Pos)        /*!< 0x00000080 */
#define MDF_DFLTRSFR_HPFC                   MDF_DFLTRSFR_HPFC_Msk                   /*!<High-pass filter cut-off frequency*/
#define MDF_DFLTRSFR_HPFC_0                 (0x1UL << MDF_DFLTRSFR_HPFC_Pos)
#define MDF_DFLTRSFR_HPFC_1                 (0x2UL << MDF_DFLTRSFR_HPFC_Pos)

/*******************  Bit definition for MDF/ADF_DLYxCR register  ********************/
#define MDF_DLYCR_SKPDLY_Pos                (0UL)
#define MDF_DLYCR_SKPDLY_Msk                (0x7FUL << MDF_DLYCR_SKPDLY_Pos)        /*!< 0x0000007F */
#define MDF_DLYCR_SKPDLY                    MDF_DLYCR_SKPDLY_Msk                    /*!<Delay to apply to a bitstream*/
#define MDF_DLYCR_SKPBF_Pos                 (31UL)
#define MDF_DLYCR_SKPBF_Msk                 (0x1UL << MDF_DLYCR_SKPBF_Pos)          /*!< 0x80000000 */
#define MDF_DLYCR_SKPBF                     MDF_DLYCR_SKPBF_Msk                     /*!<DSkip Busy Flag*/

/*******************  Bit definition for MDF/ADF_DFLTIER register  ********************/
#define MDF_DFLTIER_FTHIE_Pos               (0UL)
#define MDF_DFLTIER_FTHIE_Msk               (0x1UL << MDF_DFLTIER_FTHIE_Pos)        /*!< 0x00000001 */
#define MDF_DFLTIER_FTHIE                   MDF_DFLTIER_FTHIE_Msk                   /*!<RXFIFO threshold interrupt enable*/
#define MDF_DFLTIER_DOVRIE_Pos              (1UL)
#define MDF_DFLTIER_DOVRIE_Msk              (0x1UL << MDF_DFLTIER_DOVRIE_Pos)       /*!< 0x00000002 */
#define MDF_DFLTIER_DOVRIE                  MDF_DFLTIER_DOVRIE_Msk                  /*!<Data overflow interrupt enable*/
#define MDF_DFLTIER_SATIE_Pos               (9UL)
#define MDF_DFLTIER_SATIE_Msk               (0x1UL << MDF_DFLTIER_SATIE_Pos)        /*!< 0x00000200 */
#define MDF_DFLTIER_SATIE                   MDF_DFLTIER_SATIE_Msk                   /*!<Saturation detection interrupt enable*/
#define MDF_DFLTIER_CKABIE_Pos              (10UL)
#define MDF_DFLTIER_CKABIE_Msk              (0x1UL << MDF_DFLTIER_CKABIE_Pos)       /*!< 0x00000400 */
#define MDF_DFLTIER_CKABIE                  MDF_DFLTIER_CKABIE_Msk                  /*!<Clock absence detection interrupt enable*/
#define MDF_DFLTIER_RFOVRIE_Pos             (11UL)
#define MDF_DFLTIER_RFOVRIE_Msk             (0x1UL << MDF_DFLTIER_RFOVRIE_Pos)      /*!< 0x00000800 */
#define MDF_DFLTIER_RFOVRIE                 MDF_DFLTIER_RFOVRIE_Msk                 /*!<reshape filter overrun interrupt enable*/
#define MDF_DFLTIER_SDDETIE_Pos             (12UL)
#define MDF_DFLTIER_SDDETIE_Msk             (0x1UL << MDF_DFLTIER_SDDETIE_Pos)      /*!< 0x00001000 */
#define MDF_DFLTIER_SDDETIE                 MDF_DFLTIER_SDDETIE_Msk                 /*!<SAD interrupt enable*/
#define MDF_DFLTIER_SDLVLIE_Pos             (13UL)
#define MDF_DFLTIER_SDLVLIE_Msk             (0x1UL << MDF_DFLTIER_SDLVLIE_Pos)      /*!< 0x00002000 */
#define MDF_DFLTIER_SDLVLIE                 MDF_DFLTIER_SDLVLIE_Msk                 /*!<Sound level value ready interrupt enable*/

/*******************  Bit definition for MDF/ADF_DFLTISR register  ********************/
#define MDF_DFLTISR_FTHF_Pos                (0UL)
#define MDF_DFLTISR_FTHF_Msk                (0x1UL << MDF_DFLTISR_FTHF_Pos)         /*!< 0x00000001 */
#define MDF_DFLTISR_FTHF                    MDF_DFLTISR_FTHF_Msk                    /*!<RXFIFO threshold interrupt flag*/
#define MDF_DFLTISR_DOVRF_Pos               (1UL)
#define MDF_DFLTISR_DOVRF_Msk               (0x1UL << MDF_DFLTISR_DOVRF_Pos)        /*!< 0x00000002 */
#define MDF_DFLTISR_DOVRF                   MDF_DFLTISR_DOVRF_Msk                   /*!<Data overflow interrupt flag*/
#define MDF_DFLTISR_RXNEF_Pos               (3UL)
#define MDF_DFLTISR_RXNEF_Msk               (0x1UL << MDF_DFLTISR_RXNEF_Pos)        /*!< 0x00000008 */
#define MDF_DFLTISR_RXNEF                   MDF_DFLTISR_RXNEF_Msk                   /*!<Snapshot data ready interrupt flag*/
#define MDF_DFLTISR_SATF_Pos                (9UL)
#define MDF_DFLTISR_SATF_Msk                (0x1UL << MDF_DFLTISR_SATF_Pos)         /*!< 0x00000200 */
#define MDF_DFLTISR_SATF                    MDF_DFLTISR_SATF_Msk                    /*!<Saturation detection interrupt flag*/
#define MDF_DFLTISR_CKABF_Pos               (10UL)
#define MDF_DFLTISR_CKABF_Msk               (0x1UL << MDF_DFLTISR_CKABF_Pos)        /*!< 0x00000400 */
#define MDF_DFLTISR_CKABF                   MDF_DFLTISR_CKABF_Msk                   /*!<Clock absence detection interrupt flag*/
#define MDF_DFLTISR_RFOVRF_Pos              (11UL)
#define MDF_DFLTISR_RFOVRF_Msk              (0x1UL << MDF_DFLTISR_RFOVRF_Pos)       /*!< 0x00000800 */
#define MDF_DFLTISR_RFOVRF                  MDF_DFLTISR_RFOVRF_Msk                  /*!<reshape filter overrun interrupt flag*/
#define MDF_DFLTISR_SDDETF_Pos              (12UL)
#define MDF_DFLTISR_SDDETF_Msk              (0x1UL << MDF_DFLTISR_SDDETF_Pos)        /*!< 0x00001000 */
#define MDF_DFLTISR_SDDETF                  MDF_DFLTISR_SDDETF_Msk                  /*!<SAD interrupt flag*/
#define MDF_DFLTISR_SDLVLF_Pos              (13UL)
#define MDF_DFLTISR_SDLVLF_Msk              (0x1UL << MDF_DFLTISR_SDLVLF_Pos)       /*!< 0x00002000 */
#define MDF_DFLTISR_SDLVLF                  MDF_DFLTISR_SDLVLF_Msk                  /*!<Sound level value ready interrupt flag*/

/*******************  Bit definition for MDF/ADF_SADCR register  ********************/
#define MDF_SADCR_SADEN_Pos                 (0UL)
#define MDF_SADCR_SADEN_Msk                 (0x1UL << MDF_SADCR_SADEN_Pos)          /*!< 0x00000001 */
#define MDF_SADCR_SADEN                     MDF_SADCR_SADEN_Msk                     /*!<SAD enable*/
#define MDF_SADCR_DATCAP_Pos                (1UL)
#define MDF_SADCR_DATCAP_Msk                (0x3UL << MDF_SADCR_DATCAP_Pos)         /*!< 0x00000003 */
#define MDF_SADCR_DATCAP                    MDF_SADCR_DATCAP_Msk                    /*!<SAD data capture mode*/
#define MDF_SADCR_DATCAP_0                  (0x1UL << MDF_SADCR_DATCAP_Pos)         /*!< 0x00000002 */
#define MDF_SADCR_DATCAP_1                  (0x2UL << MDF_SADCR_DATCAP_Pos)         /*!< 0x00000004 */
#define MDF_SADCR_DETCFG_Pos                (3UL)
#define MDF_SADCR_DETCFG_Msk                (0x1UL << MDF_SADCR_DETCFG_Pos)         /*!< 0x00000008 */
#define MDF_SADCR_DETCFG                    MDF_SADCR_DETCFG_Msk                    /*!<SAD trigger event configuration*/
#define MDF_SADCR_SADST_Pos                 (4UL)
#define MDF_SADCR_SADST_Msk                 (0x3UL << MDF_SADCR_SADST_Pos)          /*!< 0x00000030 */
#define MDF_SADCR_SADST                     MDF_SADCR_SADST_Msk                     /*!<SAD state*/
#define MDF_SADCR_HYSTEN_Pos                (7UL)
#define MDF_SADCR_HYSTEN_Msk                (0x1UL << MDF_SADCR_HYSTEN_Pos)         /*!< 0x00000080 */
#define MDF_SADCR_HYSTEN                    MDF_SADCR_HYSTEN_Msk                    /*!<Hysteresis enable*/
#define MDF_SADCR_FRSIZE_Pos                (8UL)
#define MDF_SADCR_FRSIZE_Msk                (0x7UL << MDF_SADCR_FRSIZE_Pos)         /*!< 0x00000700 */
#define MDF_SADCR_FRSIZE                    MDF_SADCR_FRSIZE_Msk                    /*!<Frame size*/
#define MDF_SADCR_FRSIZE_0                  (0x1UL << MDF_SADCR_FRSIZE_Pos)         /*!< 0x00000100 */
#define MDF_SADCR_FRSIZE_1                  (0x2UL << MDF_SADCR_FRSIZE_Pos)         /*!< 0x00000200 */
#define MDF_SADCR_FRSIZE_2                  (0x4UL << MDF_SADCR_FRSIZE_Pos)         /*!< 0x00000300 */
#define MDF_SADCR_SADMOD_Pos                (12UL)
#define MDF_SADCR_SADMOD_Msk                (0x3UL << MDF_SADCR_SADMOD_Pos)         /*!< 0x00003000 */
#define MDF_SADCR_SADMOD                    MDF_SADCR_SADMOD_Msk                    /*!<SAD working mode*/
#define MDF_SADCR_SADMOD_0                  (0x1UL << MDF_SADCR_SADMOD_Pos)         /*!< 0x00001000 */
#define MDF_SADCR_SADMOD_1                  (0x2UL << MDF_SADCR_SADMOD_Pos)         /*!< 0x00002000 */
#define MDF_SADCR_SADACTIVE_Pos             (31UL)
#define MDF_SADCR_SADACTIVE_Msk             (0x1UL << MDF_SADCR_SADACTIVE_Pos)      /*!< 0x80000000 */
#define MDF_SADCR_SADACTIVE                 MDF_SADCR_SADACTIVE_Msk                 /*!<SAD active flag*/

/*******************  Bit definition for MDF/ADF_SADCFGR register  ********************/
#define MDF_SADCFGR_SNTHR_Pos               (0UL)
#define MDF_SADCFGR_SNTHR_Msk               (0xFUL << MDF_SADCFGR_SNTHR_Pos)        /*!< 0x0000000F */
#define MDF_SADCFGR_SNTHR                   MDF_SADCFGR_SNTHR_Msk                   /*!<Signal to noise threshold*/
#define MDF_SADCFGR_SNTHR_0                 (0x1UL << MDF_SADCFGR_SNTHR_Pos)        /*!< 0x00000001 */
#define MDF_SADCFGR_SNTHR_1                 (0x2UL << MDF_SADCFGR_SNTHR_Pos)        /*!< 0x00000002 */
#define MDF_SADCFGR_SNTHR_2                 (0x4UL << MDF_SADCFGR_SNTHR_Pos)        /*!< 0x00000004 */
#define MDF_SADCFGR_SNTHR_3                 (0x8UL << MDF_SADCFGR_SNTHR_Pos)        /*!< 0x00000008 */
#define MDF_SADCFGR_ANSLP_Pos               (4UL)
#define MDF_SADCFGR_ANSLP_Msk               (0x7UL << MDF_SADCFGR_ANSLP_Pos)        /*!< 0x00000070 */
#define MDF_SADCFGR_ANSLP                   MDF_SADCFGR_ANSLP_Msk                   /*!<Ambiant noise slope control*/
#define MDF_SADCFGR_LFRNB_Pos               (8UL)
#define MDF_SADCFGR_LFRNB_Msk               (0x7UL << MDF_SADCFGR_LFRNB_Pos)        /*!< 0x00000700 */
#define MDF_SADCFGR_LFRNB                   MDF_SADCFGR_LFRNB_Msk                   /*!<Number of learning frames*/
#define MDF_SADCFGR_LFRNB_0                 (0x1UL << MDF_SADCFGR_LFRNB_Pos)        /*!< 0x00000100 */
#define MDF_SADCFGR_LFRNB_1                 (0x2UL << MDF_SADCFGR_LFRNB_Pos)        /*!< 0x00000200 */
#define MDF_SADCFGR_LFRNB_2                 (0x4UL << MDF_SADCFGR_LFRNB_Pos)        /*!< 0x00000400 */
#define MDF_SADCFGR_HGOVR_Pos               (12UL)
#define MDF_SADCFGR_HGOVR_Msk               (0x7UL << MDF_SADCFGR_HGOVR_Pos)        /*!< 0x00007000 */
#define MDF_SADCFGR_HGOVR                   MDF_SADCFGR_HGOVR_Msk                   /*!<Hangover time window*/
#define MDF_SADCFGR_HGOVR_0                 (0x1UL << MDF_SADCFGR_HGOVR_Pos)        /*!< 0x00001000 */
#define MDF_SADCFGR_HGOVR_1                 (0x2UL << MDF_SADCFGR_HGOVR_Pos)        /*!< 0x00002000 */
#define MDF_SADCFGR_HGOVR_2                 (0x4UL << MDF_SADCFGR_HGOVR_Pos)        /*!< 0x00004000 */
#define MDF_SADCFGR_ANMIN_Pos               (16UL)
#define MDF_SADCFGR_ANMIN_Msk               (0x1FFFUL << MDF_SADCFGR_ANMIN_Pos)     /*!< 0x1FFF0000 */
#define MDF_SADCFGR_ANMIN                   MDF_SADCFGR_ANMIN_Msk                   /*!<Hangover time window*/

/*******************  Bit definition for MDF/ADF_SADSDLVR register  ********************/
#define MDF_SADSDLVR_SDLVL_Pos              (0UL)
#define MDF_SADSDLVR_SDLVL_Msk              (0x7FFFUL << MDF_SADSDLVR_SDLVL_Pos)    /*!< 0x00007FFF */
#define MDF_SADSDLVR_SDLVL                  MDF_SADSDLVR_SDLVL_Msk                  /*!<Short term sound level*/

/*******************  Bit definition for MDF/ADF_SADANLVR register  ********************/
#define MDF_SADANLVR_ANLVL_Pos              (0UL)
#define MDF_SADANLVR_ANLVL_Msk              (0x7FFFUL << MDF_SADANLVR_ANLVL_Pos)    /*!< 0x00007FFF */
#define MDF_SADANLVR_ANLVL                  MDF_SADANLVR_ANLVL_Msk                  /*!<Ambiant noise level estimation*/

/*******************  Bit definition for MDF/ADF_DFLTDR register  ********************/
#define MDF_DFLTDR_DR_Pos                   (8UL)
#define MDF_DFLTDR_DR_Msk                   (0xFFFFFFUL << MDF_DFLTDR_DR_Pos)       /*!< 0xFFFFFF00 */
#define MDF_DFLTDR_DR                       MDF_DFLTDR_DR_Msk                       /*!<MCIC decimation counter*/

/******************************************************************************/
/*                                                                            */
/*                         Operational Amplifier (OPAMP)                      */
/*                                                                            */
/******************************************************************************/
/*********************  Bit definition for OPAMPx_CSR register  ***************/
#define OPAMP_CSR_OPAEN_Pos                 (0UL)
#define OPAMP_CSR_OPAEN_Msk                 (0x1UL << OPAMP_CSR_OPAEN_Pos)            /*!< 0x00000001 */
#define OPAMP_CSR_OPAEN                     OPAMP_CSR_OPAEN_Msk                       /*!< OPAMP enable */
#define OPAMP_CSR_OPALPM_Pos                (1UL)
#define OPAMP_CSR_OPALPM_Msk                (0x1UL << OPAMP_CSR_OPALPM_Pos)           /*!< 0x00000002 */
#define OPAMP_CSR_OPALPM                    OPAMP_CSR_OPALPM_Msk                      /*!< Operational amplifier Low Power Mode */
#define OPAMP_CSR_OPAMODE_Pos               (2UL)
#define OPAMP_CSR_OPAMODE_Msk               (0x3UL << OPAMP_CSR_OPAMODE_Pos)          /*!< 0x0000000C */
#define OPAMP_CSR_OPAMODE                   OPAMP_CSR_OPAMODE_Msk                     /*!< Operational amplifier PGA mode */
#define OPAMP_CSR_OPAMODE_0                 (0x1UL << OPAMP_CSR_OPAMODE_Pos)          /*!< 0x00000004 */
#define OPAMP_CSR_OPAMODE_1                 (0x2UL << OPAMP_CSR_OPAMODE_Pos)          /*!< 0x00000008 */
#define OPAMP_CSR_PGA_GAIN_Pos              (4UL)
#define OPAMP_CSR_PGA_GAIN_Msk              (0x3UL << OPAMP_CSR_PGA_GAIN_Pos)         /*!< 0x00000030 */
#define OPAMP_CSR_PGA_GAIN                  OPAMP_CSR_PGA_GAIN_Msk                    /*!< Operational amplifier Programmable amplifier gain value */
#define OPAMP_CSR_PGA_GAIN_0                (0x1UL << OPAMP_CSR_PGA_GAIN_Pos)         /*!< 0x00000010 */
#define OPAMP_CSR_PGA_GAIN_1                (0x2UL << OPAMP_CSR_PGA_GAIN_Pos)         /*!< 0x00000020 */
#define OPAMP_CSR_VM_SEL_Pos                (8UL)
#define OPAMP_CSR_VM_SEL_Msk                (0x3UL << OPAMP_CSR_VM_SEL_Pos)           /*!< 0x00000300 */
#define OPAMP_CSR_VM_SEL                    OPAMP_CSR_VM_SEL_Msk                      /*!< Inverting input selection */
#define OPAMP_CSR_VM_SEL_0                  (0x1UL << OPAMP_CSR_VM_SEL_Pos)           /*!< 0x00000100 */
#define OPAMP_CSR_VM_SEL_1                  (0x2UL << OPAMP_CSR_VM_SEL_Pos)           /*!< 0x00000200 */
#define OPAMP_CSR_VP_SEL_Pos                (10UL)
#define OPAMP_CSR_VP_SEL_Msk                (0x1UL << OPAMP_CSR_VP_SEL_Pos)           /*!< 0x00000400 */
#define OPAMP_CSR_VP_SEL                    OPAMP_CSR_VP_SEL_Msk                      /*!< Non inverted input selection */
#define OPAMP_CSR_CALON_Pos                 (12UL)
#define OPAMP_CSR_CALON_Msk                 (0x1UL << OPAMP_CSR_CALON_Pos)            /*!< 0x00001000 */
#define OPAMP_CSR_CALON                     OPAMP_CSR_CALON_Msk                       /*!< Calibration mode enable */
#define OPAMP_CSR_CALSEL_Pos                (13UL)
#define OPAMP_CSR_CALSEL_Msk                (0x1UL << OPAMP_CSR_CALSEL_Pos)           /*!< 0x00002000 */
#define OPAMP_CSR_CALSEL                    OPAMP_CSR_CALSEL_Msk                      /*!< Calibration selection */
#define OPAMP_CSR_USERTRIM_Pos              (14UL)
#define OPAMP_CSR_USERTRIM_Msk              (0x1UL << OPAMP_CSR_USERTRIM_Pos)         /*!< 0x00004000 */
#define OPAMP_CSR_USERTRIM                  OPAMP_CSR_USERTRIM_Msk                    /*!< User trimming enable */
#define OPAMP_CSR_CALOUT_Pos                (15UL)
#define OPAMP_CSR_CALOUT_Msk                (0x1UL << OPAMP_CSR_CALOUT_Pos)           /*!< 0x00008000 */
#define OPAMP_CSR_CALOUT                    OPAMP_CSR_CALOUT_Msk                      /*!< Operational amplifier calibration output */
#define OPAMP_CSR_HSM_Pos                   (30UL)
#define OPAMP_CSR_HSM_Msk                   (0x1UL << OPAMP_CSR_HSM_Pos)              /*!< 0x40000000 */
#define OPAMP_CSR_HSM                       OPAMP_CSR_HSM_Msk                         /*!< Operational amplifier high speed mode */
#define OPAMP_CSR_OPARANGE_Pos              (31UL)
#define OPAMP_CSR_OPARANGE_Msk              (0x1UL << OPAMP_CSR_OPARANGE_Pos)         /*!< 0x80000000 */
#define OPAMP_CSR_OPARANGE                  OPAMP_CSR_OPARANGE_Msk                    /*!< Operational amplifier range setting */

/*******************  Bit definition for OPAMPx_OTR register  ******************/
#define OPAMP_OTR_TRIMOFFSETN_Pos           (0UL)
#define OPAMP_OTR_TRIMOFFSETN_Msk           (0x1FUL << OPAMP_OTR_TRIMOFFSETN_Pos)     /*!< 0x0000001F */
#define OPAMP_OTR_TRIMOFFSETN               OPAMP_OTR_TRIMOFFSETN_Msk                 /*!< Trim for NMOS differential pairs */
#define OPAMP_OTR_TRIMOFFSETP_Pos           (8UL)
#define OPAMP_OTR_TRIMOFFSETP_Msk           (0x1FUL << OPAMP_OTR_TRIMOFFSETP_Pos)     /*!< 0x00001F00 */
#define OPAMP_OTR_TRIMOFFSETP               OPAMP_OTR_TRIMOFFSETP_Msk                 /*!< Trim for PMOS differential pairs */

/*******************  Bit definition for OPAMPx_LPOTR register  ****************/
#define OPAMP_LPOTR_TRIMLPOFFSETN_Pos       (0UL)
#define OPAMP_LPOTR_TRIMLPOFFSETN_Msk       (0x1FUL << OPAMP_LPOTR_TRIMLPOFFSETN_Pos) /*!< 0x0000001F */
#define OPAMP_LPOTR_TRIMLPOFFSETN           OPAMP_LPOTR_TRIMLPOFFSETN_Msk             /*!< Trim for NMOS differential pairs */
#define OPAMP_LPOTR_TRIMLPOFFSETP_Pos       (8UL)
#define OPAMP_LPOTR_TRIMLPOFFSETP_Msk       (0x1FUL << OPAMP_LPOTR_TRIMLPOFFSETP_Pos) /*!< 0x00001F00 */
#define OPAMP_LPOTR_TRIMLPOFFSETP           OPAMP_LPOTR_TRIMLPOFFSETP_Msk             /*!< Trim for PMOS differential pairs */

/******************************************************************************/
/*                                                                            */
/*                             Power Control                                  */
/*                                                                            */
/******************************************************************************/
/********************  Bit definition for PWR_CR1 register  *******************/
#define PWR_CR1_LPMS_Pos                    (0UL)
#define PWR_CR1_LPMS_Msk                    (0x7UL << PWR_CR1_LPMS_Pos)             /*!< 0x00000007 */
#define PWR_CR1_LPMS                        PWR_CR1_LPMS_Msk                        /*!< LPMS[2:0] Low-power mode selection field     */
#define PWR_CR1_LPMS_0                      (0x1UL << PWR_CR1_LPMS_Pos)             /*!< 0x00000001 */
#define PWR_CR1_LPMS_1                      (0x2UL << PWR_CR1_LPMS_Pos)             /*!< 0x00000002 */
#define PWR_CR1_LPMS_2                      (0x4UL << PWR_CR1_LPMS_Pos)             /*!< 0x00000004 */
#define PWR_CR1_RRSB1_Pos                   (4UL)
#define PWR_CR1_RRSB1_Msk                   (0x1UL << PWR_CR1_RRSB1_Pos)            /*!< 0x00000010 */
#define PWR_CR1_RRSB1                       PWR_CR1_RRSB1_Msk                       /*!< SRAM2 page 1 Retention in Standby            */
#define PWR_CR1_RRSB2_Pos                   (5UL)
#define PWR_CR1_RRSB2_Msk                   (0x1UL << PWR_CR1_RRSB2_Pos)            /*!< 0x00000020 */
#define PWR_CR1_RRSB2                       PWR_CR1_RRSB2_Msk                       /*!< SRAM2 page 2 Retention in Standby            */
#define PWR_CR1_RRSB3_Pos                   (6UL)
#define PWR_CR1_RRSB3_Msk                   (0x1UL << PWR_CR1_RRSB3_Pos)            /*!< 0x00000040 */
#define PWR_CR1_RRSB3                       PWR_CR1_RRSB3_Msk                       /*!< SRAM2 page 3 Retention in Standby            */
#define PWR_CR1_ULPMEN_Pos                  (7UL)
#define PWR_CR1_ULPMEN_Msk                  (0x1UL << PWR_CR1_ULPMEN_Pos)           /*!< 0x00000080 */
#define PWR_CR1_ULPMEN                      PWR_CR1_ULPMEN_Msk                      /*!< BOR ultra-low power mode in Standby/Shutdown */
#define PWR_CR1_SRAM1PD_Pos                 (8UL)
#define PWR_CR1_SRAM1PD_Msk                 (0x1UL << PWR_CR1_SRAM1PD_Pos)          /*!< 0x00000100 */
#define PWR_CR1_SRAM1PD                     PWR_CR1_SRAM1PD_Msk                     /*!< SRAM1 (192 KB) power-down in Run mode        */
#define PWR_CR1_SRAM2PD_Pos                 (9UL)
#define PWR_CR1_SRAM2PD_Msk                 (0x1UL << PWR_CR1_SRAM2PD_Pos)          /*!< 0x00000200 */
#define PWR_CR1_SRAM2PD                     PWR_CR1_SRAM2PD_Msk                     /*!< SRAM2 (64 KB) power-down in Run mode         */

/********************  Bit definition for PWR_CR2 register  *******************/
#define PWR_CR2_SRAM1PDS1_Pos               (0UL)
#define PWR_CR2_SRAM1PDS1_Msk               (0x1UL << PWR_CR2_SRAM1PDS1_Pos)        /*!< 0x00000001 */
#define PWR_CR2_SRAM1PDS1                   PWR_CR2_SRAM1PDS1_Msk                   /*!< SRAM1 page 1 (16 KB) power-down in Stop modes (Stop 0, 1, 2, 3)           */
#define PWR_CR2_SRAM1PDS2_Pos               (1UL)
#define PWR_CR2_SRAM1PDS2_Msk               (0x1UL << PWR_CR2_SRAM1PDS2_Pos)        /*!< 0x00000002 */
#define PWR_CR2_SRAM1PDS2                   PWR_CR2_SRAM1PDS2_Msk                   /*!< SRAM1 page 2 (16 KB) power-down in Stop modes (Stop 0, 1, 2, 3)           */
#define PWR_CR2_SRAM1PDS3_Pos               (2UL)
#define PWR_CR2_SRAM1PDS3_Msk               (0x1UL << PWR_CR2_SRAM1PDS3_Pos)        /*!< 0x00000004 */
#define PWR_CR2_SRAM1PDS3                   PWR_CR2_SRAM1PDS3_Msk                   /*!< SRAM1 page 3 (32 KB) power-down in Stop modes (Stop 0, 1, 2, 3)           */
#define PWR_CR2_SRAM1PDS4_Pos               (3UL)
#define PWR_CR2_SRAM1PDS4_Msk               (0x1UL << PWR_CR2_SRAM1PDS4_Pos)        /*!< 0x00000008 */
#define PWR_CR2_SRAM1PDS4                   PWR_CR2_SRAM1PDS4_Msk                   /*!< SRAM1 page 4 (32 KB) power-down in Stop modes (Stop 0, 1, 2, 3)           */
#define PWR_CR2_SRAM1PDS5_Pos               (4UL)
#define PWR_CR2_SRAM1PDS5_Msk               (0x1UL << PWR_CR2_SRAM1PDS5_Pos)        /*!< 0x00000010 */
#define PWR_CR2_SRAM1PDS5                   PWR_CR2_SRAM1PDS5_Msk                   /*!< SRAM1 page 5 (32 KB) power-down in Stop modes (Stop 0, 1, 2, 3)           */
#define PWR_CR2_SRAM1PDS6_Pos               (5UL)
#define PWR_CR2_SRAM1PDS6_Msk               (0x1UL << PWR_CR2_SRAM1PDS6_Pos)        /*!< 0x00000020 */
#define PWR_CR2_SRAM1PDS6                   PWR_CR2_SRAM1PDS6_Msk                   /*!< SRAM1 page 6 (32 KB) power-down in Stop modes (Stop 0, 1, 2, 3)           */
#define PWR_CR2_SRAM1PDS7_Pos               (6UL)
#define PWR_CR2_SRAM1PDS7_Msk               (0x1UL << PWR_CR2_SRAM1PDS7_Pos)        /*!< 0x00000040 */
#define PWR_CR2_SRAM1PDS7                   PWR_CR2_SRAM1PDS7_Msk                   /*!< SRAM1 page 7 (32 KB) power-down in Stop modes (Stop 0, 1, 2, 3)           */
#define PWR_CR2_SRAM2PDS1_Pos               (16UL)
#define PWR_CR2_SRAM2PDS1_Msk               (0x1UL << PWR_CR2_SRAM2PDS1_Pos)        /*!< 0x00010000 */
#define PWR_CR2_SRAM2PDS1                   PWR_CR2_SRAM2PDS1_Msk                   /*!< SRAM2 page 1 (8 KB) power-down in Stop modes (Stop 0, 1, 2, 3)            */
#define PWR_CR2_SRAM2PDS2_Pos               (17UL)
#define PWR_CR2_SRAM2PDS2_Msk               (0x1UL << PWR_CR2_SRAM2PDS2_Pos)        /*!< 0x00020000 */
#define PWR_CR2_SRAM2PDS2                   PWR_CR2_SRAM2PDS2_Msk                   /*!< SRAM2 page 2 (24 KB) power-down in Stop modes (Stop 0, 1, 2, 3)           */
#define PWR_CR2_SRAM2PDS3_Pos               (18UL)
#define PWR_CR2_SRAM2PDS3_Msk               (0x1UL << PWR_CR2_SRAM2PDS3_Pos)        /*!< 0x00040000 */
#define PWR_CR2_SRAM2PDS3                   PWR_CR2_SRAM2PDS3_Msk                   /*!< SRAM2 page 3 (32 KB) power-down in Stop modes (Stop 0, 1, 2, 3)           */
#define PWR_CR2_ICRAMPDS_Pos                (25UL)
#define PWR_CR2_ICRAMPDS_Msk                (0x1UL << PWR_CR2_ICRAMPDS_Pos)         /*!< 0x02000000 */
#define PWR_CR2_ICRAMPDS                    PWR_CR2_ICRAMPDS_Msk                    /*!< ICACHE SRAM power-down in Stop modes (Stop 0, 1, 2, 3)                    */
#define PWR_CR2_PRAMPDS_Pos                 (26UL)
#define PWR_CR2_PRAMPDS_Msk                 (0x1UL << PWR_CR2_PRAMPDS_Pos)          /*!< 0x04000000 */
#define PWR_CR2_PRAMPDS                     PWR_CR2_PRAMPDS_Msk                     /*!< FDCAN and USB peripherals SRAM power-down in Stop modes (Stop 0, 1, 2, 3) */
#define PWR_CR2_PKARAMPDS_Pos               (27UL)
#define PWR_CR2_PKARAMPDS_Msk               (0x1UL << PWR_CR2_PKARAMPDS_Pos)        /*!< 0x08000000 */
#define PWR_CR2_PKARAMPDS                   PWR_CR2_PKARAMPDS_Msk                   /*!< PKA32 SRAM power-down in Stop modes (Stop 0, 1)                           */
#define PWR_CR2_SRAMFWU_Pos                 (28UL)
#define PWR_CR2_SRAMFWU_Msk                 (0x1UL << PWR_CR2_SRAMFWU_Pos)          /*!< 0x10000000 */
#define PWR_CR2_SRAMFWU                     PWR_CR2_SRAMFWU_Msk                     /*!< SRAM fast wakeup from Stop modes (Stop 0, 1)                              */
#define PWR_CR2_FLASHFWU_Pos                (29UL)
#define PWR_CR2_FLASHFWU_Msk                (0x1UL << PWR_CR2_FLASHFWU_Pos)         /*!< 0x20000000 */
#define PWR_CR2_FLASHFWU                    PWR_CR2_FLASHFWU_Msk                    /*!< Flash memory fast wakeup from Stop modes (Stop 0, 1)                      */

/********************  Bit definition for PWR_CR3 register  *******************/
#define PWR_CR3_REGSEL_Pos                  (1UL)
#define PWR_CR3_REGSEL_Msk                  (0x1UL << PWR_CR3_REGSEL_Pos)           /*!< 0x00000002 */
#define PWR_CR3_REGSEL                      PWR_CR3_REGSEL_Msk                      /*!< Regulator selection */
#define PWR_CR3_FSTEN_Pos                   (2UL)
#define PWR_CR3_FSTEN_Msk                   (0x1UL << PWR_CR3_FSTEN_Pos)            /*!< 0x00000004 */
#define PWR_CR3_FSTEN                       PWR_CR3_FSTEN_Msk                       /*!< Fast soft start     */

/*******************  Bit definition for PWR_VOSR register  *******************/
#define PWR_VOSR_R1EN_Pos                   (0UL)
#define PWR_VOSR_R1EN_Msk                   (0x1UL << PWR_VOSR_R1EN_Pos)            /*!< 0x00000001 */
#define PWR_VOSR_R1EN                       PWR_VOSR_R1EN_Msk                       /*!< Voltage scaling range 1 selection      */
#define PWR_VOSR_R2EN_Pos                   (1UL)
#define PWR_VOSR_R2EN_Msk                   (0x1UL << PWR_VOSR_R2EN_Pos)            /*!< 0x00000002 */
#define PWR_VOSR_R2EN                       PWR_VOSR_R2EN_Msk                       /*!< Voltage scaling range 2 selection      */
#define PWR_VOSR_BOOSTEN_Pos                (8UL)
#define PWR_VOSR_BOOSTEN_Msk                (0x1UL << PWR_VOSR_BOOSTEN_Pos)         /*!< 0x00000100 */
#define PWR_VOSR_BOOSTEN                    PWR_VOSR_BOOSTEN_Msk                    /*!< EPOD booster enable                    */
#define PWR_VOSR_R1RDY_Pos                  (16UL)
#define PWR_VOSR_R1RDY_Msk                  (0x1UL << PWR_VOSR_R1RDY_Pos)           /*!< 0x00010000 */
#define PWR_VOSR_R1RDY                      PWR_VOSR_R1RDY_Msk                      /*!< Ready bit for Vcore range 1 selection  */
#define PWR_VOSR_R2RDY_Pos                  (17UL)
#define PWR_VOSR_R2RDY_Msk                  (0x1UL << PWR_VOSR_R2RDY_Pos)           /*!< 0x00020000 */
#define PWR_VOSR_R2RDY                      PWR_VOSR_R2RDY_Msk                      /*!< Ready bit for Vcore range 2 selection  */
#define PWR_VOSR_BOOSTRDY_Pos               (24UL)
#define PWR_VOSR_BOOSTRDY_Msk               (0x1UL << PWR_VOSR_BOOSTRDY_Pos)        /*!< 0x04000000 */
#define PWR_VOSR_BOOSTRDY                   PWR_VOSR_BOOSTRDY_Msk                   /*!< EPOD booster ready                     */

/*******************  Bit definition for PWR_SVMCR register  ******************/
#define PWR_SVMCR_PVDE_Pos                  (4UL)
#define PWR_SVMCR_PVDE_Msk                  (0x1UL << PWR_SVMCR_PVDE_Pos)           /*!< 0x00000010 */
#define PWR_SVMCR_PVDE                      PWR_SVMCR_PVDE_Msk                      /*!< Programmable voltage detector enable                            */
#define PWR_SVMCR_PVDLS_Pos                 (5UL)
#define PWR_SVMCR_PVDLS_Msk                 (0x7UL << PWR_SVMCR_PVDLS_Pos)          /*!< 0x000000E0 */
#define PWR_SVMCR_PVDLS                     PWR_SVMCR_PVDLS_Msk                     /*!< PVDLS[2:0] Programmable voltage detector level selection field  */
#define PWR_SVMCR_PVDLS_0                   (0x1UL << PWR_SVMCR_PVDLS_Pos)          /*!< 0x00000020 */
#define PWR_SVMCR_PVDLS_1                   (0x2UL << PWR_SVMCR_PVDLS_Pos)          /*!< 0x00000040 */
#define PWR_SVMCR_PVDLS_2                   (0x4UL << PWR_SVMCR_PVDLS_Pos)          /*!< 0x00000080 */
#define PWR_SVMCR_UVMEN_Pos                 (24UL)
#define PWR_SVMCR_UVMEN_Msk                 (0x1UL << PWR_SVMCR_UVMEN_Pos)          /*!< 0x01000000 */
#define PWR_SVMCR_UVMEN                     PWR_SVMCR_UVMEN_Msk                     /*!< VDDUSB Independent USB supply voltage monitor enable            */
#define PWR_SVMCR_IO2VMEN_Pos               (25UL)
#define PWR_SVMCR_IO2VMEN_Msk               (0x1UL << PWR_SVMCR_IO2VMEN_Pos)        /*!< 0x02000000 */
#define PWR_SVMCR_IO2VMEN                   PWR_SVMCR_IO2VMEN_Msk                   /*!< VDDIO2 Independent I/Os voltage monitor enable                  */
#define PWR_SVMCR_AVM1EN_Pos                (26UL)
#define PWR_SVMCR_AVM1EN_Msk                (0x1UL << PWR_SVMCR_AVM1EN_Pos)         /*!< 0x04000000 */
#define PWR_SVMCR_AVM1EN                    PWR_SVMCR_AVM1EN_Msk                    /*!< VDDA Independent analog supply voltage monitor 1 enable         */
#define PWR_SVMCR_AVM2EN_Pos                (27UL)
#define PWR_SVMCR_AVM2EN_Msk                (0x1UL << PWR_SVMCR_AVM2EN_Pos)         /*!< 0x08000000 */
#define PWR_SVMCR_AVM2EN                    PWR_SVMCR_AVM2EN_Msk                    /*!< VDDA Independent analog supply voltage monitor 2 enable         */
#define PWR_SVMCR_USV_Pos                   (28UL)
#define PWR_SVMCR_USV_Msk                   (0x1UL << PWR_SVMCR_USV_Pos)            /*!< 0x10000000 */
#define PWR_SVMCR_USV                       PWR_SVMCR_USV_Msk                       /*!< VDDUSB Independent USB supply valid                             */
#define PWR_SVMCR_IO2SV_Pos                 (29UL)
#define PWR_SVMCR_IO2SV_Msk                 (0x1UL << PWR_SVMCR_IO2SV_Pos)          /*!< 0x20000000 */
#define PWR_SVMCR_IO2SV                     PWR_SVMCR_IO2SV_Msk                     /*!< VDDIO2 Independent I/Os supply valid                            */
#define PWR_SVMCR_ASV_Pos                   (30UL)
#define PWR_SVMCR_ASV_Msk                   (0x1UL << PWR_SVMCR_ASV_Pos)            /*!< 0x40000000 */
#define PWR_SVMCR_ASV                       PWR_SVMCR_ASV_Msk                       /*!< VDDA Independent analog supply valid                            */

/*******************  Bit definition for PWR_WUCR1 register  ******************/
#define PWR_WUCR1_WUPEN1_Pos                (0UL)
#define PWR_WUCR1_WUPEN1_Msk                (0x1UL << PWR_WUCR1_WUPEN1_Pos)         /*!< 0x00000001 */
#define PWR_WUCR1_WUPEN1                    PWR_WUCR1_WUPEN1_Msk                    /*!< Wakeup line WKUP1 enable  */
#define PWR_WUCR1_WUPEN2_Pos                (1UL)
#define PWR_WUCR1_WUPEN2_Msk                (0x1UL << PWR_WUCR1_WUPEN2_Pos)         /*!< 0x00000002 */
#define PWR_WUCR1_WUPEN2                    PWR_WUCR1_WUPEN2_Msk                    /*!< Wakeup line WKUP2 enable  */
#define PWR_WUCR1_WUPEN3_Pos                (2UL)
#define PWR_WUCR1_WUPEN3_Msk                (0x1UL << PWR_WUCR1_WUPEN3_Pos)         /*!< 0x00000004 */
#define PWR_WUCR1_WUPEN3                    PWR_WUCR1_WUPEN3_Msk                    /*!< Wakeup line WKUP3 enable  */
#define PWR_WUCR1_WUPEN4_Pos                (3UL)
#define PWR_WUCR1_WUPEN4_Msk                (0x1UL << PWR_WUCR1_WUPEN4_Pos)         /*!< 0x00000008 */
#define PWR_WUCR1_WUPEN4                    PWR_WUCR1_WUPEN4_Msk                    /*!< Wakeup line WKUP4 enable  */
#define PWR_WUCR1_WUPEN5_Pos                (4UL)
#define PWR_WUCR1_WUPEN5_Msk                (0x1UL << PWR_WUCR1_WUPEN5_Pos)         /*!< 0x00000010 */
#define PWR_WUCR1_WUPEN5                    PWR_WUCR1_WUPEN5_Msk                    /*!< Wakeup line WKUP5 enable  */
#define PWR_WUCR1_WUPEN6_Pos                (5UL)
#define PWR_WUCR1_WUPEN6_Msk                (0x1UL << PWR_WUCR1_WUPEN6_Pos)         /*!< 0x00000020 */
#define PWR_WUCR1_WUPEN6                    PWR_WUCR1_WUPEN6_Msk                    /*!< Wakeup line WKUP6 enable  */
#define PWR_WUCR1_WUPEN7_Pos                (6UL)
#define PWR_WUCR1_WUPEN7_Msk                (0x1UL << PWR_WUCR1_WUPEN7_Pos)         /*!< 0x00000040 */
#define PWR_WUCR1_WUPEN7                    PWR_WUCR1_WUPEN7_Msk                    /*!< Wakeup line WKUP7 enable  */
#define PWR_WUCR1_WUPEN8_Pos                (7UL)
#define PWR_WUCR1_WUPEN8_Msk                (0x1UL << PWR_WUCR1_WUPEN8_Pos)         /*!< 0x00000080 */
#define PWR_WUCR1_WUPEN8                    PWR_WUCR1_WUPEN8_Msk                    /*!< Wakeup line WKUP8 enable  */
#define PWR_WUCR1_WUPEN9_Pos                (8UL)
#define PWR_WUCR1_WUPEN9_Msk                (0x1UL << PWR_WUCR1_WUPEN9_Pos)         /*!< 0x00000100 */
#define PWR_WUCR1_WUPEN9                    PWR_WUCR1_WUPEN9_Msk                    /*!< Wakeup line WKUP9 enable  */
#define PWR_WUCR1_WUPEN10_Pos               (9UL)
#define PWR_WUCR1_WUPEN10_Msk               (0x1UL << PWR_WUCR1_WUPEN10_Pos)        /*!< 0x00000200 */
#define PWR_WUCR1_WUPEN10                   PWR_WUCR1_WUPEN10_Msk                   /*!< Wakeup line WKUP10 enable */

/*******************  Bit definition for PWR_WUCR2 register  ******************/
#define PWR_WUCR2_WUPP1_Pos                 (0UL)
#define PWR_WUCR2_WUPP1_Msk                 (0x1UL << PWR_WUCR2_WUPP1_Pos)          /*!< 0x00000001 */
#define PWR_WUCR2_WUPP1                     PWR_WUCR2_WUPP1_Msk                     /*!< Wakeup line WKUP1 polarity */
#define PWR_WUCR2_WUPP2_Pos                 (1UL)
#define PWR_WUCR2_WUPP2_Msk                 (0x1UL << PWR_WUCR2_WUPP2_Pos)          /*!< 0x00000002 */
#define PWR_WUCR2_WUPP2                     PWR_WUCR2_WUPP2_Msk                     /*!< Wakeup line WKUP2 polarity */
#define PWR_WUCR2_WUPP3_Pos                 (2UL)
#define PWR_WUCR2_WUPP3_Msk                 (0x1UL << PWR_WUCR2_WUPP3_Pos)          /*!< 0x00000004 */
#define PWR_WUCR2_WUPP3                     PWR_WUCR2_WUPP3_Msk                     /*!< Wakeup line WKUP3 polarity */
#define PWR_WUCR2_WUPP4_Pos                 (3UL)
#define PWR_WUCR2_WUPP4_Msk                 (0x1UL << PWR_WUCR2_WUPP4_Pos)          /*!< 0x00000008 */
#define PWR_WUCR2_WUPP4                     PWR_WUCR2_WUPP4_Msk                     /*!< Wakeup line WKUP4 polarity */
#define PWR_WUCR2_WUPP5_Pos                 (4UL)
#define PWR_WUCR2_WUPP5_Msk                 (0x1UL << PWR_WUCR2_WUPP5_Pos)          /*!< 0x00000010 */
#define PWR_WUCR2_WUPP5                     PWR_WUCR2_WUPP5_Msk                     /*!< Wakeup line WKUP5 polarity */
#define PWR_WUCR2_WUPP6_Pos                 (5UL)
#define PWR_WUCR2_WUPP6_Msk                 (0x1UL << PWR_WUCR2_WUPP6_Pos)          /*!< 0x00000020 */
#define PWR_WUCR2_WUPP6                     PWR_WUCR2_WUPP6_Msk                     /*!< Wakeup line WKUP6 polarity */
#define PWR_WUCR2_WUPP7_Pos                 (6UL)
#define PWR_WUCR2_WUPP7_Msk                 (0x1UL << PWR_WUCR2_WUPP7_Pos)          /*!< 0x00000040 */
#define PWR_WUCR2_WUPP7                     PWR_WUCR2_WUPP7_Msk                     /*!< Wakeup line WKUP7 polarity */
#define PWR_WUCR2_WUPP8_Pos                 (7UL)
#define PWR_WUCR2_WUPP8_Msk                 (0x1UL << PWR_WUCR2_WUPP8_Pos)          /*!< 0x00000080 */
#define PWR_WUCR2_WUPP8                     PWR_WUCR2_WUPP8_Msk                     /*!< Wakeup line WKUP8 polarity */

/*******************  Bit definition for PWR_WUCR3 register  ******************/
#define PWR_WUCR3_WUSEL1_Pos                (0UL)
#define PWR_WUCR3_WUSEL1_Msk                (0x3UL << PWR_WUCR3_WUSEL1_Pos)         /*!< 0x00000003 */
#define PWR_WUCR3_WUSEL1                    PWR_WUCR3_WUSEL1_Msk                    /*!< Wakeup line WKUP1 selection field */
#define PWR_WUCR3_WUSEL1_0                  (0x1UL << PWR_WUCR3_WUSEL1_Pos)         /*!< 0x00000001 */
#define PWR_WUCR3_WUSEL1_1                  (0x2UL << PWR_WUCR3_WUSEL1_Pos)         /*!< 0x00000002 */
#define PWR_WUCR3_WUSEL2_Pos                (2UL)
#define PWR_WUCR3_WUSEL2_Msk                (0x3UL << PWR_WUCR3_WUSEL2_Pos)         /*!< 0x0000000C */
#define PWR_WUCR3_WUSEL2                    PWR_WUCR3_WUSEL2_Msk                    /*!< Wakeup line WKUP2 selection field */
#define PWR_WUCR3_WUSEL2_0                  (0x1UL << PWR_WUCR3_WUSEL2_Pos)         /*!< 0x00000004 */
#define PWR_WUCR3_WUSEL2_1                  (0x2UL << PWR_WUCR3_WUSEL2_Pos)         /*!< 0x00000008 */
#define PWR_WUCR3_WUSEL3_Pos                (4UL)
#define PWR_WUCR3_WUSEL3_Msk                (0x3UL << PWR_WUCR3_WUSEL3_Pos)         /*!< 0x00000030 */
#define PWR_WUCR3_WUSEL3                    PWR_WUCR3_WUSEL3_Msk                    /*!< Wakeup line WKUP3 selection field */
#define PWR_WUCR3_WUSEL3_0                  (0x1UL << PWR_WUCR3_WUSEL3_Pos)         /*!< 0x00000010 */
#define PWR_WUCR3_WUSEL3_1                  (0x2UL << PWR_WUCR3_WUSEL3_Pos)         /*!< 0x00000020 */
#define PWR_WUCR3_WUSEL4_Pos                (6UL)
#define PWR_WUCR3_WUSEL4_Msk                (0x3UL << PWR_WUCR3_WUSEL4_Pos)         /*!< 0x000000C0 */
#define PWR_WUCR3_WUSEL4                    PWR_WUCR3_WUSEL4_Msk                    /*!< Wakeup line WKUP4 selection field */
#define PWR_WUCR3_WUSEL4_0                  (0x1UL << PWR_WUCR3_WUSEL4_Pos)         /*!< 0x00000040 */
#define PWR_WUCR3_WUSEL4_1                  (0x2UL << PWR_WUCR3_WUSEL4_Pos)         /*!< 0x00000080 */
#define PWR_WUCR3_WUSEL5_Pos                (8UL)
#define PWR_WUCR3_WUSEL5_Msk                (0x3UL << PWR_WUCR3_WUSEL5_Pos)         /*!< 0x00000300 */
#define PWR_WUCR3_WUSEL5                    PWR_WUCR3_WUSEL5_Msk                    /*!< Wakeup line WKUP5 selection field */
#define PWR_WUCR3_WUSEL5_0                  (0x1UL << PWR_WUCR3_WUSEL5_Pos)         /*!< 0x00000100 */
#define PWR_WUCR3_WUSEL5_1                  (0x2UL << PWR_WUCR3_WUSEL5_Pos)         /*!< 0x00000200 */
#define PWR_WUCR3_WUSEL6_Pos                (10UL)
#define PWR_WUCR3_WUSEL6_Msk                (0x3UL << PWR_WUCR3_WUSEL6_Pos)         /*!< 0x00000C00 */
#define PWR_WUCR3_WUSEL6                    PWR_WUCR3_WUSEL6_Msk                    /*!< Wakeup line WKUP6 selection field */
#define PWR_WUCR3_WUSEL6_0                  (0x1UL << PWR_WUCR3_WUSEL6_Pos)         /*!< 0x00000400 */
#define PWR_WUCR3_WUSEL6_1                  (0x2UL << PWR_WUCR3_WUSEL6_Pos)         /*!< 0x00000800 */
#define PWR_WUCR3_WUSEL7_Pos                (12UL)
#define PWR_WUCR3_WUSEL7_Msk                (0x3UL << PWR_WUCR3_WUSEL7_Pos)         /*!< 0x00003000 */
#define PWR_WUCR3_WUSEL7                    PWR_WUCR3_WUSEL7_Msk                    /*!< Wakeup line WKUP7 selection field */
#define PWR_WUCR3_WUSEL7_0                  (0x1UL << PWR_WUCR3_WUSEL7_Pos)         /*!< 0x00001000 */
#define PWR_WUCR3_WUSEL7_1                  (0x2UL << PWR_WUCR3_WUSEL7_Pos)         /*!< 0x00002000 */
#define PWR_WUCR3_WUSEL8_Pos                (14UL)
#define PWR_WUCR3_WUSEL8_Msk                (0x3UL << PWR_WUCR3_WUSEL8_Pos)         /*!< 0x0000C000 */
#define PWR_WUCR3_WUSEL8                    PWR_WUCR3_WUSEL8_Msk                    /*!< Wakeup line WKUP8 selection field */
#define PWR_WUCR3_WUSEL8_0                  (0x1UL << PWR_WUCR3_WUSEL8_Pos)         /*!< 0x00004000 */
#define PWR_WUCR3_WUSEL8_1                  (0x2UL << PWR_WUCR3_WUSEL8_Pos)         /*!< 0x00008000 */

/*******************  Bit definition for PWR_BDCR register  *******************/
#define PWR_BDCR_VBE_Pos                    (0UL)
#define PWR_BDCR_VBE_Msk                    (0x1UL << PWR_BDCR_VBE_Pos)             /*!< 0x00000001 */
#define PWR_BDCR_VBE                        PWR_BDCR_VBE_Msk                        /*!< VBAT charging enable             */
#define PWR_BDCR_VBRS_Pos                   (1UL)
#define PWR_BDCR_VBRS_Msk                   (0x1UL << PWR_BDCR_VBRS_Pos)            /*!< 0x00000002 */
#define PWR_BDCR_VBRS                       PWR_BDCR_VBRS_Msk                       /*!< VBAT charging resistor selection */

/********************  Bit definition for PWR_DBPR register  ******************/
#define PWR_DBPR_DBP_Pos                    (0UL)
#define PWR_DBPR_DBP_Msk                    (0x1UL << PWR_DBPR_DBP_Pos)             /*!< 0x00000001 */
#define PWR_DBPR_DBP                        PWR_DBPR_DBP_Msk                        /*!< Disable backup domain write protection */

/*******************  Bit definition for PWR_SECCFGR register  ****************/
#define PWR_SECCFGR_WUP1SEC_Pos             (0UL)
#define PWR_SECCFGR_WUP1SEC_Msk             (0x1UL << PWR_SECCFGR_WUP1SEC_Pos)      /*!< 0x00000001 */
#define PWR_SECCFGR_WUP1SEC                 PWR_SECCFGR_WUP1SEC_Msk                 /*!< WUP1 secure protection                             */
#define PWR_SECCFGR_WUP2SEC_Pos             (1UL)
#define PWR_SECCFGR_WUP2SEC_Msk             (0x1UL << PWR_SECCFGR_WUP2SEC_Pos)      /*!< 0x00000002 */
#define PWR_SECCFGR_WUP2SEC                 PWR_SECCFGR_WUP2SEC_Msk                 /*!< WUP2 secure protection                             */
#define PWR_SECCFGR_WUP3SEC_Pos             (2UL)
#define PWR_SECCFGR_WUP3SEC_Msk             (0x1UL << PWR_SECCFGR_WUP3SEC_Pos)      /*!< 0x00000004 */
#define PWR_SECCFGR_WUP3SEC                 PWR_SECCFGR_WUP3SEC_Msk                 /*!< WUP3 secure protection                             */
#define PWR_SECCFGR_WUP4SEC_Pos             (3UL)
#define PWR_SECCFGR_WUP4SEC_Msk             (0x1UL << PWR_SECCFGR_WUP4SEC_Pos)      /*!< 0x00000008 */
#define PWR_SECCFGR_WUP4SEC                 PWR_SECCFGR_WUP4SEC_Msk                 /*!< WUP4 secure protection                             */
#define PWR_SECCFGR_WUP5SEC_Pos             (4UL)
#define PWR_SECCFGR_WUP5SEC_Msk             (0x1UL << PWR_SECCFGR_WUP5SEC_Pos)      /*!< 0x00000010 */
#define PWR_SECCFGR_WUP5SEC                 PWR_SECCFGR_WUP5SEC_Msk                 /*!< WUP5 secure protection                             */
#define PWR_SECCFGR_WUP6SEC_Pos             (5UL)
#define PWR_SECCFGR_WUP6SEC_Msk             (0x1UL << PWR_SECCFGR_WUP6SEC_Pos)      /*!< 0x00000020 */
#define PWR_SECCFGR_WUP6SEC                 PWR_SECCFGR_WUP6SEC_Msk                 /*!< WUP6 secure protection                             */
#define PWR_SECCFGR_WUP7SEC_Pos             (6UL)
#define PWR_SECCFGR_WUP7SEC_Msk             (0x1UL << PWR_SECCFGR_WUP7SEC_Pos)      /*!< 0x00000040 */
#define PWR_SECCFGR_WUP7SEC                 PWR_SECCFGR_WUP7SEC_Msk                 /*!< WUP7 secure protection                             */
#define PWR_SECCFGR_WUP8SEC_Pos             (7UL)
#define PWR_SECCFGR_WUP8SEC_Msk             (0x1UL << PWR_SECCFGR_WUP8SEC_Pos)      /*!< 0x00000080 */
#define PWR_SECCFGR_WUP8SEC                 PWR_SECCFGR_WUP8SEC_Msk                 /*!< WUP8 secure protection                             */
#define PWR_SECCFGR_WUP9SEC_Pos             (8UL)
#define PWR_SECCFGR_WUP9SEC_Msk             (0x1UL << PWR_SECCFGR_WUP9SEC_Pos)      /*!< 0x00000100 */
#define PWR_SECCFGR_WUP9SEC                 PWR_SECCFGR_WUP9SEC_Msk                 /*!< WUP9 secure protection                             */
#define PWR_SECCFGR_WUP10SEC_Pos            (9UL)
#define PWR_SECCFGR_WUP10SEC_Msk            (0x1UL << PWR_SECCFGR_WUP10SEC_Pos)     /*!< 0x00000200 */
#define PWR_SECCFGR_WUP10SEC                PWR_SECCFGR_WUP10SEC_Msk                /*!< WUP10 secure protection                            */
#define PWR_SECCFGR_LPMSEC_Pos              (12UL)
#define PWR_SECCFGR_LPMSEC_Msk              (0x1UL << PWR_SECCFGR_LPMSEC_Pos)       /*!< 0x00001000 */
#define PWR_SECCFGR_LPMSEC                  PWR_SECCFGR_LPMSEC_Msk                  /*!< Low-power modes secure protection                  */
#define PWR_SECCFGR_VDMSEC_Pos              (13UL)
#define PWR_SECCFGR_VDMSEC_Msk              (0x1UL << PWR_SECCFGR_VDMSEC_Pos)       /*!< 0x00002000 */
#define PWR_SECCFGR_VDMSEC                  PWR_SECCFGR_VDMSEC_Msk                  /*!< Voltage detection and monitoring secure protection */
#define PWR_SECCFGR_VBSEC_Pos               (14UL)
#define PWR_SECCFGR_VBSEC_Msk               (0x1UL << PWR_SECCFGR_VBSEC_Pos)        /*!< 0x00004000 */
#define PWR_SECCFGR_VBSEC                   PWR_SECCFGR_VBSEC_Msk                   /*!< Backup domain secure protection                    */
#define PWR_SECCFGR_APCSEC_Pos              (15UL)
#define PWR_SECCFGR_APCSEC_Msk              (0x1UL << PWR_SECCFGR_APCSEC_Pos)       /*!< 0x00008000 */
#define PWR_SECCFGR_APCSEC                  PWR_SECCFGR_APCSEC_Msk                  /*!< Pull-up/pull-down secure protection                */

/*******************  Bit definition for PWR_PRIVCFGR register  ***************/
#define PWR_PRIVCFGR_SPRIV_Pos              (0UL)
#define PWR_PRIVCFGR_SPRIV_Msk              (0x1UL << PWR_PRIVCFGR_SPRIV_Pos)       /*!< 0x00000001 */
#define PWR_PRIVCFGR_SPRIV                  PWR_PRIVCFGR_SPRIV_Msk                  /*!< PWR secure functions privilege configuration     */
#define PWR_PRIVCFGR_NSPRIV_Pos             (1UL)
#define PWR_PRIVCFGR_NSPRIV_Msk             (0x1UL << PWR_PRIVCFGR_NSPRIV_Pos)      /*!< 0x00000002 */
#define PWR_PRIVCFGR_NSPRIV                 PWR_PRIVCFGR_NSPRIV_Msk                 /*!< PWR non-secure functions privilege configuration */

/**********************  Bit definition for PWR_SR register  ******************/
#define PWR_SR_CSSF_Pos                     (0UL)
#define PWR_SR_CSSF_Msk                     (0x1UL << PWR_SR_CSSF_Pos)              /*!< 0x00000001 */
#define PWR_SR_CSSF                         PWR_SR_CSSF_Msk                         /*!< Clear Stop and Standby/Shutdown flags */
#define PWR_SR_STOPF_Pos                    (1UL)
#define PWR_SR_STOPF_Msk                    (0x1UL << PWR_SR_STOPF_Pos)             /*!< 0x00000002 */
#define PWR_SR_STOPF                        PWR_SR_STOPF_Msk                        /*!< Stop flag                             */
#define PWR_SR_SBF_Pos                      (2UL)
#define PWR_SR_SBF_Msk                      (0x1UL << PWR_SR_SBF_Pos)               /*!< 0x00000004 */
#define PWR_SR_SBF                          PWR_SR_SBF_Msk                          /*!< Standby flag                          */

/********************  Bit definition for PWR_SVMSR register  *****************/
#define PWR_SVMSR_REGS_Pos                  (1UL)
#define PWR_SVMSR_REGS_Msk                  (0x1UL << PWR_SVMSR_REGS_Pos)           /*!< 0x00000002 */
#define PWR_SVMSR_REGS                      PWR_SVMSR_REGS_Msk                      /*!< Regulator status                       */
#define PWR_SVMSR_PVDO_Pos                  (4UL)
#define PWR_SVMSR_PVDO_Msk                  (0x1UL << PWR_SVMSR_PVDO_Pos)           /*!< 0x00000010 */
#define PWR_SVMSR_PVDO                      PWR_SVMSR_PVDO_Msk                      /*!< VDD voltage detector output            */
#define PWR_SVMSR_VDDUSBRDY_Pos             (24UL)
#define PWR_SVMSR_VDDUSBRDY_Msk             (0x1UL << PWR_SVMSR_VDDUSBRDY_Pos)      /*!< 0x01000000 */
#define PWR_SVMSR_VDDUSBRDY                 PWR_SVMSR_VDDUSBRDY_Msk                 /*!< VDDUSB ready                           */
#define PWR_SVMSR_VDDIO2RDY_Pos             (25UL)
#define PWR_SVMSR_VDDIO2RDY_Msk             (0x1UL << PWR_SVMSR_VDDIO2RDY_Pos)      /*!< 0x02000000 */
#define PWR_SVMSR_VDDIO2RDY                 PWR_SVMSR_VDDIO2RDY_Msk                 /*!< VDDIO2 ready                           */
#define PWR_SVMSR_VDDA1RDY_Pos              (26UL)
#define PWR_SVMSR_VDDA1RDY_Msk              (0x1UL << PWR_SVMSR_VDDA1RDY_Pos)       /*!< 0x04000000 */
#define PWR_SVMSR_VDDA1RDY                  PWR_SVMSR_VDDA1RDY_Msk                  /*!< VDDA ready versus 1.6V voltage monitor */
#define PWR_SVMSR_VDDA2RDY_Pos              (27UL)
#define PWR_SVMSR_VDDA2RDY_Msk              (0x1UL << PWR_SVMSR_VDDA2RDY_Pos)       /*!< 0x08000000 */
#define PWR_SVMSR_VDDA2RDY                  PWR_SVMSR_VDDA2RDY_Msk                  /*!< VDDA ready versus 1.8V voltage monitor */

/*********************  Bit definition for PWR_WUSR register  *****************/
#define PWR_WUSR_WUF1_Pos                   (0UL)
#define PWR_WUSR_WUF1_Msk                   (0x1UL << PWR_WUSR_WUF1_Pos)            /*!< 0x00000001 */
#define PWR_WUSR_WUF1                       PWR_WUSR_WUF1_Msk                       /*!< Wakeup flag 1  */
#define PWR_WUSR_WUF2_Pos                   (1UL)
#define PWR_WUSR_WUF2_Msk                   (0x1UL << PWR_WUSR_WUF2_Pos)            /*!< 0x00000002 */
#define PWR_WUSR_WUF2                       PWR_WUSR_WUF2_Msk                       /*!< Wakeup flag 2  */
#define PWR_WUSR_WUF3_Pos                   (2UL)
#define PWR_WUSR_WUF3_Msk                   (0x1UL << PWR_WUSR_WUF3_Pos)            /*!< 0x00000004 */
#define PWR_WUSR_WUF3                       PWR_WUSR_WUF3_Msk                       /*!< Wakeup flag 3  */
#define PWR_WUSR_WUF4_Pos                   (3UL)
#define PWR_WUSR_WUF4_Msk                   (0x1UL << PWR_WUSR_WUF4_Pos)            /*!< 0x00000008 */
#define PWR_WUSR_WUF4                       PWR_WUSR_WUF4_Msk                       /*!< Wakeup flag 4  */
#define PWR_WUSR_WUF5_Pos                   (4UL)
#define PWR_WUSR_WUF5_Msk                   (0x1UL << PWR_WUSR_WUF5_Pos)            /*!< 0x00000010 */
#define PWR_WUSR_WUF5                       PWR_WUSR_WUF5_Msk                       /*!< Wakeup flag 5  */
#define PWR_WUSR_WUF6_Pos                   (5UL)
#define PWR_WUSR_WUF6_Msk                   (0x1UL << PWR_WUSR_WUF6_Pos)            /*!< 0x00000020 */
#define PWR_WUSR_WUF6                       PWR_WUSR_WUF6_Msk                       /*!< Wakeup flag 6  */
#define PWR_WUSR_WUF7_Pos                   (6UL)
#define PWR_WUSR_WUF7_Msk                   (0x1UL << PWR_WUSR_WUF7_Pos)            /*!< 0x00000040 */
#define PWR_WUSR_WUF7                       PWR_WUSR_WUF7_Msk                       /*!< Wakeup flag 7  */
#define PWR_WUSR_WUF8_Pos                   (7UL)
#define PWR_WUSR_WUF8_Msk                   (0x1UL << PWR_WUSR_WUF8_Pos)            /*!< 0x00000080 */
#define PWR_WUSR_WUF8                       PWR_WUSR_WUF8_Msk                       /*!< Wakeup flag 8  */
#define PWR_WUSR_WUF9_Pos                   (8UL)
#define PWR_WUSR_WUF9_Msk                   (0x1UL << PWR_WUSR_WUF9_Pos)            /*!< 0x00000100 */
#define PWR_WUSR_WUF9                       PWR_WUSR_WUF9_Msk                       /*!< Wakeup flag 9  */
#define PWR_WUSR_WUF10_Pos                  (9UL)
#define PWR_WUSR_WUF10_Msk                  (0x1UL << PWR_WUSR_WUF10_Pos)           /*!< 0x00000200 */
#define PWR_WUSR_WUF10                      PWR_WUSR_WUF10_Msk                      /*!< Wakeup flag 10 */

/*********************  Bit definition for PWR_WUSCR register  ****************/
#define PWR_WUSCR_CWUF1_Pos                 (0UL)
#define PWR_WUSCR_CWUF1_Msk                 (0x1UL << PWR_WUSCR_CWUF1_Pos)          /*!< 0x00000001*/
#define PWR_WUSCR_CWUF1                     PWR_WUSCR_CWUF1_Msk                     /*!< Wakeup clear flag 1  */
#define PWR_WUSCR_CWUF2_Pos                 (1UL)
#define PWR_WUSCR_CWUF2_Msk                 (0x1UL << PWR_WUSCR_CWUF2_Pos)          /*!< 0x00000002 */
#define PWR_WUSCR_CWUF2                     PWR_WUSCR_CWUF2_Msk                     /*!< Wakeup clear flag 2  */
#define PWR_WUSCR_CWUF3_Pos                 (2UL)
#define PWR_WUSCR_CWUF3_Msk                 (0x1UL << PWR_WUSCR_CWUF3_Pos)          /*!< 0x00000004 */
#define PWR_WUSCR_CWUF3                     PWR_WUSCR_CWUF3_Msk                     /*!< Wakeup clear flag 3  */
#define PWR_WUSCR_CWUF4_Pos                 (3UL)
#define PWR_WUSCR_CWUF4_Msk                 (0x1UL << PWR_WUSCR_CWUF4_Pos)          /*!< 0x00000008 */
#define PWR_WUSCR_CWUF4                     PWR_WUSCR_CWUF4_Msk                     /*!< Wakeup clear flag 4  */
#define PWR_WUSCR_CWUF5_Pos                 (4UL)
#define PWR_WUSCR_CWUF5_Msk                 (0x1UL << PWR_WUSCR_CWUF5_Pos)          /*!< 0x00000010 */
#define PWR_WUSCR_CWUF5                     PWR_WUSCR_CWUF5_Msk                     /*!< Wakeup clear flag 5  */
#define PWR_WUSCR_CWUF6_Pos                 (5UL)
#define PWR_WUSCR_CWUF6_Msk                 (0x1UL << PWR_WUSCR_CWUF6_Pos)          /*!< 0x00000020 */
#define PWR_WUSCR_CWUF6                     PWR_WUSCR_CWUF6_Msk                     /*!< Wakeup clear flag 6  */
#define PWR_WUSCR_CWUF7_Pos                 (6UL)
#define PWR_WUSCR_CWUF7_Msk                 (0x1UL << PWR_WUSCR_CWUF7_Pos)          /*!< 0x00000040 */
#define PWR_WUSCR_CWUF7                     PWR_WUSCR_CWUF7_Msk                     /*!< Wakeup clear flag 7  */
#define PWR_WUSCR_CWUF8_Pos                 (7UL)
#define PWR_WUSCR_CWUF8_Msk                 (0x1UL << PWR_WUSCR_CWUF8_Pos)          /*!< 0x00000080 */
#define PWR_WUSCR_CWUF8                     PWR_WUSCR_CWUF8_Msk                     /*!< Wakeup clear flag 8  */
#define PWR_WUSCR_CWUF9_Pos                 (8UL)
#define PWR_WUSCR_CWUF9_Msk                 (0x1UL << PWR_WUSCR_CWUF9_Pos)          /*!< 0x00000100 */
#define PWR_WUSCR_CWUF9                     PWR_WUSCR_CWUF9_Msk                     /*!< Wakeup clear flag 9  */
#define PWR_WUSCR_CWUF10_Pos                (9UL)
#define PWR_WUSCR_CWUF10_Msk                (0x1UL << PWR_WUSCR_CWUF10_Pos)         /*!< 0x00000200 */
#define PWR_WUSCR_CWUF10                    PWR_WUSCR_CWUF10_Msk                    /*!< Wakeup clear flag 10 */

/*********************  Bit definition for PWR_APCR register  *****************/
#define PWR_APCR_APC_Pos                    (0UL)
#define PWR_APCR_APC_Msk                    (0x1UL << PWR_APCR_APC_Pos)             /*!< 0x00000001 */
#define PWR_APCR_APC                        PWR_APCR_APC_Msk                        /*!< Apply pull-up and pull-down configuration */

/********************  Bit definition for PWR_PUCRA register  *****************/
#define PWR_PUCRA_PU0_Pos                   (0UL)
#define PWR_PUCRA_PU0_Msk                   (0x1UL << PWR_PUCRA_PU0_Pos)            /*!< 0x00000001 */
#define PWR_PUCRA_PU0                       PWR_PUCRA_PU0_Msk                       /*!< Apply pull-up for PA0  */
#define PWR_PUCRA_PU1_Pos                   (1UL)
#define PWR_PUCRA_PU1_Msk                   (0x1UL << PWR_PUCRA_PU1_Pos)            /*!< 0x00000002 */
#define PWR_PUCRA_PU1                       PWR_PUCRA_PU1_Msk                       /*!< Apply pull-up for PA1  */
#define PWR_PUCRA_PU2_Pos                   (2UL)
#define PWR_PUCRA_PU2_Msk                   (0x1UL << PWR_PUCRA_PU2_Pos)            /*!< 0x00000004 */
#define PWR_PUCRA_PU2                       PWR_PUCRA_PU2_Msk                       /*!< Apply pull-up for PA2  */
#define PWR_PUCRA_PU3_Pos                   (3UL)
#define PWR_PUCRA_PU3_Msk                   (0x1UL << PWR_PUCRA_PU3_Pos)            /*!< 0x00000008 */
#define PWR_PUCRA_PU3                       PWR_PUCRA_PU3_Msk                       /*!< Apply pull-up for PA3  */
#define PWR_PUCRA_PU4_Pos                   (4UL)
#define PWR_PUCRA_PU4_Msk                   (0x1UL << PWR_PUCRA_PU4_Pos)            /*!< 0x00000010 */
#define PWR_PUCRA_PU4                       PWR_PUCRA_PU4_Msk                       /*!< Apply pull-up for PA4  */
#define PWR_PUCRA_PU5_Pos                   (5UL)
#define PWR_PUCRA_PU5_Msk                   (0x1UL << PWR_PUCRA_PU5_Pos)            /*!< 0x00000020 */
#define PWR_PUCRA_PU5                       PWR_PUCRA_PU5_Msk                       /*!< Apply pull-up for PA5  */
#define PWR_PUCRA_PU6_Pos                   (6UL)
#define PWR_PUCRA_PU6_Msk                   (0x1UL << PWR_PUCRA_PU6_Pos)            /*!< 0x00000040 */
#define PWR_PUCRA_PU6                       PWR_PUCRA_PU6_Msk                       /*!< Apply pull-up for PA6  */
#define PWR_PUCRA_PU7_Pos                   (7UL)
#define PWR_PUCRA_PU7_Msk                   (0x1UL << PWR_PUCRA_PU7_Pos)            /*!< 0x00000080 */
#define PWR_PUCRA_PU7                       PWR_PUCRA_PU7_Msk                       /*!< Apply pull-up for PA7  */
#define PWR_PUCRA_PU8_Pos                   (8UL)
#define PWR_PUCRA_PU8_Msk                   (0x1UL << PWR_PUCRA_PU8_Pos)            /*!< 0x00000100 */
#define PWR_PUCRA_PU8                       PWR_PUCRA_PU8_Msk                       /*!< Apply pull-up for PA8  */
#define PWR_PUCRA_PU9_Pos                   (9UL)
#define PWR_PUCRA_PU9_Msk                   (0x1UL << PWR_PUCRA_PU9_Pos)            /*!< 0x00000200 */
#define PWR_PUCRA_PU9                       PWR_PUCRA_PU9_Msk                       /*!< Apply pull-up for PA9  */
#define PWR_PUCRA_PU10_Pos                  (10UL)
#define PWR_PUCRA_PU10_Msk                  (0x1UL << PWR_PUCRA_PU10_Pos)           /*!< 0x00000400 */
#define PWR_PUCRA_PU10                      PWR_PUCRA_PU10_Msk                      /*!< Apply pull-up for PA10 */
#define PWR_PUCRA_PU11_Pos                  (11UL)
#define PWR_PUCRA_PU11_Msk                  (0x1UL << PWR_PUCRA_PU11_Pos)           /*!< 0x00000800 */
#define PWR_PUCRA_PU11                      PWR_PUCRA_PU11_Msk                      /*!< Apply pull-up for PA11 */
#define PWR_PUCRA_PU12_Pos                  (12UL)
#define PWR_PUCRA_PU12_Msk                  (0x1UL << PWR_PUCRA_PU12_Pos)           /*!< 0x00001000 */
#define PWR_PUCRA_PU12                      PWR_PUCRA_PU12_Msk                      /*!< Apply pull-up for PA12 */
#define PWR_PUCRA_PU13_Pos                  (13UL)
#define PWR_PUCRA_PU13_Msk                  (0x1UL << PWR_PUCRA_PU13_Pos)           /*!< 0x00002000 */
#define PWR_PUCRA_PU13                      PWR_PUCRA_PU13_Msk                      /*!< Apply pull-up for PA13 */
#define PWR_PUCRA_PU15_Pos                  (15UL)
#define PWR_PUCRA_PU15_Msk                  (0x1UL << PWR_PUCRA_PU15_Pos)           /*!< 0x00008000 */
#define PWR_PUCRA_PU15                      PWR_PUCRA_PU15_Msk                      /*!< Apply pull-up for PA15 */

/********************  Bit definition for PWR_PDCRA register  *****************/
#define PWR_PDCRA_PD0_Pos                   (0UL)
#define PWR_PDCRA_PD0_Msk                   (0x1UL << PWR_PDCRA_PD0_Pos)            /*!< 0x00000001 */
#define PWR_PDCRA_PD0                       PWR_PDCRA_PD0_Msk                       /*!< Apply pull-down for PA0  */
#define PWR_PDCRA_PD1_Pos                   (1UL)
#define PWR_PDCRA_PD1_Msk                   (0x1UL << PWR_PDCRA_PD1_Pos)            /*!< 0x00000002 */
#define PWR_PDCRA_PD1                       PWR_PDCRA_PD1_Msk                       /*!< Apply pull-down for PA1  */
#define PWR_PDCRA_PD2_Pos                   (2UL)
#define PWR_PDCRA_PD2_Msk                   (0x1UL << PWR_PDCRA_PD2_Pos)            /*!< 0x00000004 */
#define PWR_PDCRA_PD2                       PWR_PDCRA_PD2_Msk                       /*!< Apply pull-down for PA2  */
#define PWR_PDCRA_PD3_Pos                   (3UL)
#define PWR_PDCRA_PD3_Msk                   (0x1UL << PWR_PDCRA_PD3_Pos)            /*!< 0x00000008 */
#define PWR_PDCRA_PD3                       PWR_PDCRA_PD3_Msk                       /*!< Apply pull-down for PA3  */
#define PWR_PDCRA_PD4_Pos                   (4UL)
#define PWR_PDCRA_PD4_Msk                   (0x1UL << PWR_PDCRA_PD4_Pos)            /*!< 0x00000010 */
#define PWR_PDCRA_PD4                       PWR_PDCRA_PD4_Msk                       /*!< Apply pull-down for PA4  */
#define PWR_PDCRA_PD5_Pos                   (5UL)
#define PWR_PDCRA_PD5_Msk                   (0x1UL << PWR_PDCRA_PD5_Pos)            /*!< 0x00000020 */
#define PWR_PDCRA_PD5                       PWR_PDCRA_PD5_Msk                       /*!< Apply pull-down for PA5  */
#define PWR_PDCRA_PD6_Pos                   (6UL)
#define PWR_PDCRA_PD6_Msk                   (0x1UL << PWR_PDCRA_PD6_Pos)            /*!< 0x00000040 */
#define PWR_PDCRA_PD6                       PWR_PDCRA_PD6_Msk                       /*!< Apply pull-down for PA6  */
#define PWR_PDCRA_PD7_Pos                   (7UL)
#define PWR_PDCRA_PD7_Msk                   (0x1UL << PWR_PDCRA_PD7_Pos)            /*!< 0x00000080 */
#define PWR_PDCRA_PD7                       PWR_PDCRA_PD7_Msk                       /*!< Apply pull-down for PA7  */
#define PWR_PDCRA_PD8_Pos                   (8UL)
#define PWR_PDCRA_PD8_Msk                   (0x1UL << PWR_PDCRA_PD8_Pos)            /*!< 0x00000100 */
#define PWR_PDCRA_PD8                       PWR_PDCRA_PD8_Msk                       /*!< Apply pull-down for PA8  */
#define PWR_PDCRA_PD9_Pos                   (9UL)
#define PWR_PDCRA_PD9_Msk                   (0x1UL << PWR_PDCRA_PD9_Pos)            /*!< 0x00000200 */
#define PWR_PDCRA_PD9                       PWR_PDCRA_PD9_Msk                       /*!< Apply pull-down for PA9  */
#define PWR_PDCRA_PD10_Pos                  (10UL)
#define PWR_PDCRA_PD10_Msk                  (0x1UL << PWR_PDCRA_PD10_Pos)           /*!< 0x00000400 */
#define PWR_PDCRA_PD10                      PWR_PDCRA_PD10_Msk                      /*!< Apply pull-down for PA10 */
#define PWR_PDCRA_PD11_Pos                  (11UL)
#define PWR_PDCRA_PD11_Msk                  (0x1UL << PWR_PDCRA_PD11_Pos)           /*!< 0x00000800 */
#define PWR_PDCRA_PD11                      PWR_PDCRA_PD11_Msk                      /*!< Apply pull-down for PA11 */
#define PWR_PDCRA_PD12_Pos                  (12UL)
#define PWR_PDCRA_PD12_Msk                  (0x1UL << PWR_PDCRA_PD12_Pos)           /*!< 0x00001000 */
#define PWR_PDCRA_PD12                      PWR_PDCRA_PD12_Msk                      /*!< Apply pull-down for PA12 */
#define PWR_PDCRA_PD14_Pos                  (14UL)
#define PWR_PDCRA_PD14_Msk                  (0x1UL << PWR_PDCRA_PD14_Pos)           /*!< 0x00004000 */
#define PWR_PDCRA_PD14                      PWR_PDCRA_PD14_Msk                      /*!< Apply pull-down for PA14 */

/********************  Bit definition for PWR_PUCRB register  *****************/
#define PWR_PUCRB_PU0_Pos                   (0UL)
#define PWR_PUCRB_PU0_Msk                   (0x1UL << PWR_PUCRB_PU0_Pos)            /*!< 0x00000001 */
#define PWR_PUCRB_PU0                       PWR_PUCRB_PU0_Msk                       /*!< Apply pull-up for PB0  */
#define PWR_PUCRB_PU1_Pos                   (1UL)
#define PWR_PUCRB_PU1_Msk                   (0x1UL << PWR_PUCRB_PU1_Pos)            /*!< 0x00000002 */
#define PWR_PUCRB_PU1                       PWR_PUCRB_PU1_Msk                       /*!< Apply pull-up for PB1  */
#define PWR_PUCRB_PU2_Pos                   (2UL)
#define PWR_PUCRB_PU2_Msk                   (0x1UL << PWR_PUCRB_PU2_Pos)            /*!< 0x00000004 */
#define PWR_PUCRB_PU2                       PWR_PUCRB_PU2_Msk                       /*!< Apply pull-up for PB2  */
#define PWR_PUCRB_PU3_Pos                   (3UL)
#define PWR_PUCRB_PU3_Msk                   (0x1UL << PWR_PUCRB_PU3_Pos)            /*!< 0x00000008 */
#define PWR_PUCRB_PU3                       PWR_PUCRB_PU3_Msk                       /*!< Apply pull-up for PB3  */
#define PWR_PUCRB_PU4_Pos                   (4UL)
#define PWR_PUCRB_PU4_Msk                   (0x1UL << PWR_PUCRB_PU4_Pos)            /*!< 0x00000010 */
#define PWR_PUCRB_PU4                       PWR_PUCRB_PU4_Msk                       /*!< Apply pull-up for PB4  */
#define PWR_PUCRB_PU5_Pos                   (5UL)
#define PWR_PUCRB_PU5_Msk                   (0x1UL << PWR_PUCRB_PU5_Pos)            /*!< 0x00000020 */
#define PWR_PUCRB_PU5                       PWR_PUCRB_PU5_Msk                       /*!< Apply pull-up for PB5  */
#define PWR_PUCRB_PU6_Pos                   (6UL)
#define PWR_PUCRB_PU6_Msk                   (0x1UL << PWR_PUCRB_PU6_Pos)            /*!< 0x00000040 */
#define PWR_PUCRB_PU6                       PWR_PUCRB_PU6_Msk                       /*!< Apply pull-up for PB6  */
#define PWR_PUCRB_PU7_Pos                   (7UL)
#define PWR_PUCRB_PU7_Msk                   (0x1UL << PWR_PUCRB_PU7_Pos)            /*!< 0x00000080 */
#define PWR_PUCRB_PU7                       PWR_PUCRB_PU7_Msk                       /*!< Apply pull-up for PB7  */
#define PWR_PUCRB_PU8_Pos                   (8UL)
#define PWR_PUCRB_PU8_Msk                   (0x1UL << PWR_PUCRB_PU8_Pos)            /*!< 0x00000100 */
#define PWR_PUCRB_PU8                       PWR_PUCRB_PU8_Msk                       /*!< Apply pull-up for PB8  */
#define PWR_PUCRB_PU9_Pos                   (9UL)
#define PWR_PUCRB_PU9_Msk                   (0x1UL << PWR_PUCRB_PU9_Pos)            /*!< 0x00000200 */
#define PWR_PUCRB_PU9                       PWR_PUCRB_PU9_Msk                       /*!< Apply pull-up for PB9  */
#define PWR_PUCRB_PU10_Pos                  (10UL)
#define PWR_PUCRB_PU10_Msk                  (0x1UL << PWR_PUCRB_PU10_Pos)           /*!< 0x00000400 */
#define PWR_PUCRB_PU10                      PWR_PUCRB_PU10_Msk                      /*!< Apply pull-up for PB10 */
#define PWR_PUCRB_PU11_Pos                  (11UL)
#define PWR_PUCRB_PU11_Msk                  (0x1UL << PWR_PUCRB_PU11_Pos)           /*!< 0x00000800 */
#define PWR_PUCRB_PU11                      PWR_PUCRB_PU11_Msk                      /*!< Apply pull-up for PB11 */
#define PWR_PUCRB_PU12_Pos                  (12UL)
#define PWR_PUCRB_PU12_Msk                  (0x1UL << PWR_PUCRB_PU12_Pos)           /*!< 0x00001000 */
#define PWR_PUCRB_PU12                      PWR_PUCRB_PU12_Msk                      /*!< Apply pull-up for PB12 */
#define PWR_PUCRB_PU13_Pos                  (13UL)
#define PWR_PUCRB_PU13_Msk                  (0x1UL << PWR_PUCRB_PU13_Pos)           /*!< 0x00002000 */
#define PWR_PUCRB_PU13                      PWR_PUCRB_PU13_Msk                      /*!< Apply pull-up for PB13 */
#define PWR_PUCRB_PU14_Pos                  (14UL)
#define PWR_PUCRB_PU14_Msk                  (0x1UL << PWR_PUCRB_PU14_Pos)           /*!< 0x00004000 */
#define PWR_PUCRB_PU14                      PWR_PUCRB_PU14_Msk                      /*!< Apply pull-up for PB14 */
#define PWR_PUCRB_PU15_Pos                  (15UL)
#define PWR_PUCRB_PU15_Msk                  (0x1UL << PWR_PUCRB_PU15_Pos)           /*!< 0x00008000 */
#define PWR_PUCRB_PU15                      PWR_PUCRB_PU15_Msk                      /*!< Apply pull-up for PB15 */

/********************  Bit definition for PWR_PDCRB register  *****************/
#define PWR_PDCRB_PD0_Pos                   (0UL)
#define PWR_PDCRB_PD0_Msk                   (0x1UL << PWR_PDCRB_PD0_Pos)            /*!< 0x00000001 */
#define PWR_PDCRB_PD0                       PWR_PDCRB_PD0_Msk                       /*!< Apply pull-down for PB0  */
#define PWR_PDCRB_PD1_Pos                   (1UL)
#define PWR_PDCRB_PD1_Msk                   (0x1UL << PWR_PDCRB_PD1_Pos)            /*!< 0x00000002 */
#define PWR_PDCRB_PD1                       PWR_PDCRB_PD1_Msk                       /*!< Apply pull-down for PB1  */
#define PWR_PDCRB_PD2_Pos                   (2UL)
#define PWR_PDCRB_PD2_Msk                   (0x1UL << PWR_PDCRB_PD2_Pos)            /*!< 0x00000004 */
#define PWR_PDCRB_PD2                       PWR_PDCRB_PD2_Msk                       /*!< Apply pull-down for PB2  */
#define PWR_PDCRB_PD3_Pos                   (3UL)
#define PWR_PDCRB_PD3_Msk                   (0x1UL << PWR_PDCRB_PD3_Pos)            /*!< 0x00000008 */
#define PWR_PDCRB_PD3                       PWR_PDCRB_PD3_Msk                       /*!< Apply pull-down for PB3  */
#define PWR_PDCRB_PD5_Pos                   (5UL)
#define PWR_PDCRB_PD5_Msk                   (0x1UL << PWR_PDCRB_PD5_Pos)            /*!< 0x00000020 */
#define PWR_PDCRB_PD5                       PWR_PDCRB_PD5_Msk                       /*!< Apply pull-down for PB5  */
#define PWR_PDCRB_PD6_Pos                   (6UL)
#define PWR_PDCRB_PD6_Msk                   (0x1UL << PWR_PDCRB_PD6_Pos)            /*!< 0x00000040 */
#define PWR_PDCRB_PD6                       PWR_PDCRB_PD6_Msk                       /*!< Apply pull-down for PB6  */
#define PWR_PDCRB_PD7_Pos                   (7UL)
#define PWR_PDCRB_PD7_Msk                   (0x1UL << PWR_PDCRB_PD7_Pos)            /*!< 0x00000080 */
#define PWR_PDCRB_PD7                       PWR_PDCRB_PD7_Msk                       /*!< Apply pull-down for PB7  */
#define PWR_PDCRB_PD8_Pos                   (8UL)
#define PWR_PDCRB_PD8_Msk                   (0x1UL << PWR_PDCRB_PD8_Pos)            /*!< 0x00000100 */
#define PWR_PDCRB_PD8                       PWR_PDCRB_PD8_Msk                       /*!< Apply pull-down for PB8  */
#define PWR_PDCRB_PD9_Pos                   (9UL)
#define PWR_PDCRB_PD9_Msk                   (0x1UL << PWR_PDCRB_PD9_Pos)            /*!< 0x00000200 */
#define PWR_PDCRB_PD9                       PWR_PDCRB_PD9_Msk                       /*!< Apply pull-down for PB9  */
#define PWR_PDCRB_PD10_Pos                  (10UL)
#define PWR_PDCRB_PD10_Msk                  (0x1UL << PWR_PDCRB_PD10_Pos)           /*!< 0x00000400 */
#define PWR_PDCRB_PD10                      PWR_PDCRB_PD10_Msk                      /*!< Apply pull-down for PB10 */
#define PWR_PDCRB_PD11_Pos                  (11UL)
#define PWR_PDCRB_PD11_Msk                  (0x1UL << PWR_PDCRB_PD11_Pos)           /*!< 0x00000800 */
#define PWR_PDCRB_PD11                      PWR_PDCRB_PD11_Msk                      /*!< Apply pull-down for PB11 */
#define PWR_PDCRB_PD12_Pos                  (12UL)
#define PWR_PDCRB_PD12_Msk                  (0x1UL << PWR_PDCRB_PD12_Pos)           /*!< 0x00001000 */
#define PWR_PDCRB_PD12                      PWR_PDCRB_PD12_Msk                      /*!< Apply pull-down for PB12 */
#define PWR_PDCRB_PD13_Pos                  (13UL)
#define PWR_PDCRB_PD13_Msk                  (0x1UL << PWR_PDCRB_PD13_Pos)           /*!< 0x00002000 */
#define PWR_PDCRB_PD13                      PWR_PDCRB_PD13_Msk                      /*!< Apply pull-down for PB13 */
#define PWR_PDCRB_PD14_Pos                  (14UL)
#define PWR_PDCRB_PD14_Msk                  (0x1UL << PWR_PDCRB_PD14_Pos)           /*!< 0x00004000 */
#define PWR_PDCRB_PD14                      PWR_PDCRB_PD14_Msk                      /*!< Apply pull-down for PB14 */
#define PWR_PDCRB_PD15_Pos                  (15UL)
#define PWR_PDCRB_PD15_Msk                  (0x1UL << PWR_PDCRB_PD15_Pos)           /*!< 0x00008000 */
#define PWR_PDCRB_PD15                      PWR_PDCRB_PD15_Msk                      /*!< Apply pull-down for PB15 */

/********************  Bit definition for PWR_PUCRC register  *****************/
#define PWR_PUCRC_PU0_Pos                   (0UL)
#define PWR_PUCRC_PU0_Msk                   (0x1UL << PWR_PUCRC_PU0_Pos)            /*!< 0x00000001 */
#define PWR_PUCRC_PU0                       PWR_PUCRC_PU0_Msk                       /*!< Apply pull-up for PC0  */
#define PWR_PUCRC_PU1_Pos                   (1UL)
#define PWR_PUCRC_PU1_Msk                   (0x1UL << PWR_PUCRC_PU1_Pos)            /*!< 0x00000002 */
#define PWR_PUCRC_PU1                       PWR_PUCRC_PU1_Msk                       /*!< Apply pull-up for PC1  */
#define PWR_PUCRC_PU2_Pos                   (2UL)
#define PWR_PUCRC_PU2_Msk                   (0x1UL << PWR_PUCRC_PU2_Pos)            /*!< 0x00000004 */
#define PWR_PUCRC_PU2                       PWR_PUCRC_PU2_Msk                       /*!< Apply pull-up for PC2  */
#define PWR_PUCRC_PU3_Pos                   (3UL)
#define PWR_PUCRC_PU3_Msk                   (0x1UL << PWR_PUCRC_PU3_Pos)            /*!< 0x00000008 */
#define PWR_PUCRC_PU3                       PWR_PUCRC_PU3_Msk                       /*!< Apply pull-up for PC3  */
#define PWR_PUCRC_PU4_Pos                   (4UL)
#define PWR_PUCRC_PU4_Msk                   (0x1UL << PWR_PUCRC_PU4_Pos)            /*!< 0x00000010 */
#define PWR_PUCRC_PU4                       PWR_PUCRC_PU4_Msk                       /*!< Apply pull-up for PC4  */
#define PWR_PUCRC_PU5_Pos                   (5UL)
#define PWR_PUCRC_PU5_Msk                   (0x1UL << PWR_PUCRC_PU5_Pos)            /*!< 0x00000020 */
#define PWR_PUCRC_PU5                       PWR_PUCRC_PU5_Msk                       /*!< Apply pull-up for PC5  */
#define PWR_PUCRC_PU6_Pos                   (6UL)
#define PWR_PUCRC_PU6_Msk                   (0x1UL << PWR_PUCRC_PU6_Pos)            /*!< 0x00000040 */
#define PWR_PUCRC_PU6                       PWR_PUCRC_PU6_Msk                       /*!< Apply pull-up for PC6  */
#define PWR_PUCRC_PU7_Pos                   (7UL)
#define PWR_PUCRC_PU7_Msk                   (0x1UL << PWR_PUCRC_PU7_Pos)            /*!< 0x00000080 */
#define PWR_PUCRC_PU7                       PWR_PUCRC_PU7_Msk                       /*!< Apply pull-up for PC7  */
#define PWR_PUCRC_PU8_Pos                   (8UL)
#define PWR_PUCRC_PU8_Msk                   (0x1UL << PWR_PUCRC_PU8_Pos)            /*!< 0x00000100 */
#define PWR_PUCRC_PU8                       PWR_PUCRC_PU8_Msk                       /*!< Apply pull-up for PC8  */
#define PWR_PUCRC_PU9_Pos                   (9UL)
#define PWR_PUCRC_PU9_Msk                   (0x1UL << PWR_PUCRC_PU9_Pos)            /*!< 0x00000200 */
#define PWR_PUCRC_PU9                       PWR_PUCRC_PU9_Msk                       /*!< Apply pull-up for PC9  */
#define PWR_PUCRC_PU10_Pos                  (10UL)
#define PWR_PUCRC_PU10_Msk                  (0x1UL << PWR_PUCRC_PU10_Pos)           /*!< 0x00000400 */
#define PWR_PUCRC_PU10                      PWR_PUCRC_PU10_Msk                      /*!< Apply pull-up for PC10 */
#define PWR_PUCRC_PU11_Pos                  (11UL)
#define PWR_PUCRC_PU11_Msk                  (0x1UL << PWR_PUCRC_PU11_Pos)           /*!< 0x00000800 */
#define PWR_PUCRC_PU11                      PWR_PUCRC_PU11_Msk                      /*!< Apply pull-up for PC11 */
#define PWR_PUCRC_PU12_Pos                  (12UL)
#define PWR_PUCRC_PU12_Msk                  (0x1UL << PWR_PUCRC_PU12_Pos)           /*!< 0x00001000 */
#define PWR_PUCRC_PU12                      PWR_PUCRC_PU12_Msk                      /*!< Apply pull-up for PC12 */
#define PWR_PUCRC_PU13_Pos                  (13UL)
#define PWR_PUCRC_PU13_Msk                  (0x1UL << PWR_PUCRC_PU13_Pos)           /*!< 0x00002000 */
#define PWR_PUCRC_PU13                      PWR_PUCRC_PU13_Msk                      /*!< Apply pull-up for PC13 */
#define PWR_PUCRC_PU14_Pos                  (14UL)
#define PWR_PUCRC_PU14_Msk                  (0x1UL << PWR_PUCRC_PU14_Pos)           /*!< 0x00004000 */
#define PWR_PUCRC_PU14                      PWR_PUCRC_PU14_Msk                      /*!< Apply pull-up for PC14 */
#define PWR_PUCRC_PU15_Pos                  (15UL)
#define PWR_PUCRC_PU15_Msk                  (0x1UL << PWR_PUCRC_PU15_Pos)           /*!< 0x00008000 */
#define PWR_PUCRC_PU15                      PWR_PUCRC_PU15_Msk                      /*!< Apply pull-up for PC15 */

/********************  Bit definition for PWR_PDCRC register  *****************/
#define PWR_PDCRC_PD0_Pos                   (0UL)
#define PWR_PDCRC_PD0_Msk                   (0x1UL << PWR_PDCRC_PD0_Pos)            /*!< 0x00000001 */
#define PWR_PDCRC_PD0                       PWR_PDCRC_PD0_Msk                       /*!< Apply pull-down for PC0  */
#define PWR_PDCRC_PD1_Pos                   (1UL)
#define PWR_PDCRC_PD1_Msk                   (0x1UL << PWR_PDCRC_PD1_Pos)            /*!< 0x00000002 */
#define PWR_PDCRC_PD1                       PWR_PDCRC_PD1_Msk                       /*!< Apply pull-down for PC1  */
#define PWR_PDCRC_PD2_Pos                   (2UL)
#define PWR_PDCRC_PD2_Msk                   (0x1UL << PWR_PDCRC_PD2_Pos)            /*!< 0x00000004 */
#define PWR_PDCRC_PD2                       PWR_PDCRC_PD2_Msk                       /*!< Apply pull-down for PC2  */
#define PWR_PDCRC_PD3_Pos                   (3UL)
#define PWR_PDCRC_PD3_Msk                   (0x1UL << PWR_PDCRC_PD3_Pos)            /*!< 0x00000008 */
#define PWR_PDCRC_PD3                       PWR_PDCRC_PD3_Msk                       /*!< Apply pull-down for PC3  */
#define PWR_PDCRC_PD4_Pos                   (4UL)
#define PWR_PDCRC_PD4_Msk                   (0x1UL << PWR_PDCRC_PD4_Pos)            /*!< 0x00000010 */
#define PWR_PDCRC_PD4                       PWR_PDCRC_PD4_Msk                       /*!< Apply pull-down for PC4  */
#define PWR_PDCRC_PD5_Pos                   (5UL)
#define PWR_PDCRC_PD5_Msk                   (0x1UL << PWR_PDCRC_PD5_Pos)            /*!< 0x00000020 */
#define PWR_PDCRC_PD5                       PWR_PDCRC_PD5_Msk                       /*!< Apply pull-down for PC5  */
#define PWR_PDCRC_PD6_Pos                   (6UL)
#define PWR_PDCRC_PD6_Msk                   (0x1UL << PWR_PDCRC_PD6_Pos)            /*!< 0x00000040 */
#define PWR_PDCRC_PD6                       PWR_PDCRC_PD6_Msk                       /*!< Apply pull-down for PC6  */
#define PWR_PDCRC_PD7_Pos                   (7UL)
#define PWR_PDCRC_PD7_Msk                   (0x1UL << PWR_PDCRC_PD7_Pos)            /*!< 0x00000080 */
#define PWR_PDCRC_PD7                       PWR_PDCRC_PD7_Msk                       /*!< Apply pull-down for PC7  */
#define PWR_PDCRC_PD8_Pos                   (8UL)
#define PWR_PDCRC_PD8_Msk                   (0x1UL << PWR_PDCRC_PD8_Pos)            /*!< 0x00000100 */
#define PWR_PDCRC_PD8                       PWR_PDCRC_PD8_Msk                       /*!< Apply pull-down for PC8  */
#define PWR_PDCRC_PD9_Pos                   (9UL)
#define PWR_PDCRC_PD9_Msk                   (0x1UL << PWR_PDCRC_PD9_Pos)            /*!< 0x00000200 */
#define PWR_PDCRC_PD9                       PWR_PDCRC_PD9_Msk                       /*!< Apply pull-down for PC9  */
#define PWR_PDCRC_PD10_Pos                  (10UL)
#define PWR_PDCRC_PD10_Msk                  (0x1UL << PWR_PDCRC_PD10_Pos)           /*!< 0x00000400 */
#define PWR_PDCRC_PD10                      PWR_PDCRC_PD10_Msk                      /*!< Apply pull-down for PC10 */
#define PWR_PDCRC_PD11_Pos                  (11UL)
#define PWR_PDCRC_PD11_Msk                  (0x1UL << PWR_PDCRC_PD11_Pos)           /*!< 0x00000800 */
#define PWR_PDCRC_PD11                      PWR_PDCRC_PD11_Msk                      /*!< Apply pull-down for PC11 */
#define PWR_PDCRC_PD12_Pos                  (12UL)
#define PWR_PDCRC_PD12_Msk                  (0x1UL << PWR_PDCRC_PD12_Pos)           /*!< 0x00001000 */
#define PWR_PDCRC_PD12                      PWR_PDCRC_PD12_Msk                      /*!< Apply pull-down for PC12 */
#define PWR_PDCRC_PD13_Pos                  (13UL)
#define PWR_PDCRC_PD13_Msk                  (0x1UL << PWR_PDCRC_PD13_Pos)           /*!< 0x00002000 */
#define PWR_PDCRC_PD13                      PWR_PDCRC_PD13_Msk                      /*!< Apply pull-down for PC13 */
#define PWR_PDCRC_PD14_Pos                  (14UL)
#define PWR_PDCRC_PD14_Msk                  (0x1UL << PWR_PDCRC_PD14_Pos)           /*!< 0x00004000 */
#define PWR_PDCRC_PD14                      PWR_PDCRC_PD14_Msk                      /*!< Apply pull-down for PC14 */
#define PWR_PDCRC_PD15_Pos                  (15UL)
#define PWR_PDCRC_PD15_Msk                  (0x1UL << PWR_PDCRC_PD15_Pos)           /*!< 0x00008000 */
#define PWR_PDCRC_PD15                      PWR_PDCRC_PD15_Msk                      /*!< Apply pull-down for PC15 */

/********************  Bit definition for PWR_PUCRD register  *****************/
#define PWR_PUCRD_PU0_Pos                   (0UL)
#define PWR_PUCRD_PU0_Msk                   (0x1UL << PWR_PUCRD_PU0_Pos)            /*!< 0x00000001 */
#define PWR_PUCRD_PU0                       PWR_PUCRD_PU0_Msk                       /*!< Apply pull-up for PD0  */
#define PWR_PUCRD_PU1_Pos                   (1UL)
#define PWR_PUCRD_PU1_Msk                   (0x1UL << PWR_PUCRD_PU1_Pos)            /*!< 0x00000002 */
#define PWR_PUCRD_PU1                       PWR_PUCRD_PU1_Msk                       /*!< Apply pull-up for PD1  */
#define PWR_PUCRD_PU2_Pos                   (2UL)
#define PWR_PUCRD_PU2_Msk                   (0x1UL << PWR_PUCRD_PU2_Pos)            /*!< 0x00000004 */
#define PWR_PUCRD_PU2                       PWR_PUCRD_PU2_Msk                       /*!< Apply pull-up for PD2  */
#define PWR_PUCRD_PU3_Pos                   (3UL)
#define PWR_PUCRD_PU3_Msk                   (0x1UL << PWR_PUCRD_PU3_Pos)            /*!< 0x00000008 */
#define PWR_PUCRD_PU3                       PWR_PUCRD_PU3_Msk                       /*!< Apply pull-up for PD3  */
#define PWR_PUCRD_PU4_Pos                   (4UL)
#define PWR_PUCRD_PU4_Msk                   (0x1UL << PWR_PUCRD_PU4_Pos)            /*!< 0x00000010 */
#define PWR_PUCRD_PU4                       PWR_PUCRD_PU4_Msk                       /*!< Apply pull-up for PD4  */
#define PWR_PUCRD_PU5_Pos                   (5UL)
#define PWR_PUCRD_PU5_Msk                   (0x1UL << PWR_PUCRD_PU5_Pos)            /*!< 0x00000020 */
#define PWR_PUCRD_PU5                       PWR_PUCRD_PU5_Msk                       /*!< Apply pull-up for PD5  */
#define PWR_PUCRD_PU6_Pos                   (6UL)
#define PWR_PUCRD_PU6_Msk                   (0x1UL << PWR_PUCRD_PU6_Pos)            /*!< 0x00000040 */
#define PWR_PUCRD_PU6                       PWR_PUCRD_PU6_Msk                       /*!< Apply pull-up for PD6  */
#define PWR_PUCRD_PU7_Pos                   (7UL)
#define PWR_PUCRD_PU7_Msk                   (0x1UL << PWR_PUCRD_PU7_Pos)            /*!< 0x00000080 */
#define PWR_PUCRD_PU7                       PWR_PUCRD_PU7_Msk                       /*!< Apply pull-up for PD7  */
#define PWR_PUCRD_PU8_Pos                   (8UL)
#define PWR_PUCRD_PU8_Msk                   (0x1UL << PWR_PUCRD_PU8_Pos)            /*!< 0x00000100 */
#define PWR_PUCRD_PU8                       PWR_PUCRD_PU8_Msk                       /*!< Apply pull-up for PD8  */
#define PWR_PUCRD_PU9_Pos                   (9UL)
#define PWR_PUCRD_PU9_Msk                   (0x1UL << PWR_PUCRD_PU9_Pos)            /*!< 0x00000200 */
#define PWR_PUCRD_PU9                       PWR_PUCRD_PU9_Msk                       /*!< Apply pull-up for PD9  */
#define PWR_PUCRD_PU10_Pos                  (10UL)
#define PWR_PUCRD_PU10_Msk                  (0x1UL << PWR_PUCRD_PU10_Pos)           /*!< 0x00000400 */
#define PWR_PUCRD_PU10                      PWR_PUCRD_PU10_Msk                      /*!< Apply pull-up for PD10 */
#define PWR_PUCRD_PU11_Pos                  (11UL)
#define PWR_PUCRD_PU11_Msk                  (0x1UL << PWR_PUCRD_PU11_Pos)           /*!< 0x00000800 */
#define PWR_PUCRD_PU11                      PWR_PUCRD_PU11_Msk                      /*!< Apply pull-up for PD11 */
#define PWR_PUCRD_PU12_Pos                  (12UL)
#define PWR_PUCRD_PU12_Msk                  (0x1UL << PWR_PUCRD_PU12_Pos)           /*!< 0x00001000 */
#define PWR_PUCRD_PU12                      PWR_PUCRD_PU12_Msk                      /*!< Apply pull-up for PD12 */
#define PWR_PUCRD_PU13_Pos                  (13UL)
#define PWR_PUCRD_PU13_Msk                  (0x1UL << PWR_PUCRD_PU13_Pos)           /*!< 0x00002000 */
#define PWR_PUCRD_PU13                      PWR_PUCRD_PU13_Msk                      /*!< Apply pull-up for PD13 */
#define PWR_PUCRD_PU14_Pos                  (14UL)
#define PWR_PUCRD_PU14_Msk                  (0x1UL << PWR_PUCRD_PU14_Pos)           /*!< 0x00004000 */
#define PWR_PUCRD_PU14                      PWR_PUCRD_PU14_Msk                      /*!< Apply pull-up for PD14 */
#define PWR_PUCRD_PU15_Pos                  (15UL)
#define PWR_PUCRD_PU15_Msk                  (0x1UL << PWR_PUCRD_PU15_Pos)           /*!< 0x00008000 */
#define PWR_PUCRD_PU15                      PWR_PUCRD_PU15_Msk                      /*!< Apply pull-up for PD15 */

/********************  Bit definition for PWR_PDCRD register  *****************/
#define PWR_PDCRD_PD0_Pos                   (0UL)
#define PWR_PDCRD_PD0_Msk                   (0x1UL << PWR_PDCRD_PD0_Pos)            /*!< 0x00000001 */
#define PWR_PDCRD_PD0                       PWR_PDCRD_PD0_Msk                       /*!< Apply pull-down for PD0  */
#define PWR_PDCRD_PD1_Pos                   (1UL)
#define PWR_PDCRD_PD1_Msk                   (0x1UL << PWR_PDCRD_PD1_Pos)            /*!< 0x00000002 */
#define PWR_PDCRD_PD1                       PWR_PDCRD_PD1_Msk                       /*!< Apply pull-down for PD1  */
#define PWR_PDCRD_PD2_Pos                   (2UL)
#define PWR_PDCRD_PD2_Msk                   (0x1UL << PWR_PDCRD_PD2_Pos)            /*!< 0x00000004 */
#define PWR_PDCRD_PD2                       PWR_PDCRD_PD2_Msk                       /*!< Apply pull-down for PD2  */
#define PWR_PDCRD_PD3_Pos                   (3UL)
#define PWR_PDCRD_PD3_Msk                   (0x1UL << PWR_PDCRD_PD3_Pos)            /*!< 0x00000008 */
#define PWR_PDCRD_PD3                       PWR_PDCRD_PD3_Msk                       /*!< Apply pull-down for PD3  */
#define PWR_PDCRD_PD4_Pos                   (4UL)
#define PWR_PDCRD_PD4_Msk                   (0x1UL << PWR_PDCRD_PD4_Pos)            /*!< 0x00000010 */
#define PWR_PDCRD_PD4                       PWR_PDCRD_PD4_Msk                       /*!< Apply pull-down for PD4  */
#define PWR_PDCRD_PD5_Pos                   (5UL)
#define PWR_PDCRD_PD5_Msk                   (0x1UL << PWR_PDCRD_PD5_Pos)            /*!< 0x00000020 */
#define PWR_PDCRD_PD5                       PWR_PDCRD_PD5_Msk                       /*!< Apply pull-down for PD5  */
#define PWR_PDCRD_PD6_Pos                   (6UL)
#define PWR_PDCRD_PD6_Msk                   (0x1UL << PWR_PDCRD_PD6_Pos)            /*!< 0x00000040 */
#define PWR_PDCRD_PD6                       PWR_PDCRD_PD6_Msk                       /*!< Apply pull-down for PD6  */
#define PWR_PDCRD_PD7_Pos                   (7UL)
#define PWR_PDCRD_PD7_Msk                   (0x1UL << PWR_PDCRD_PD7_Pos)            /*!< 0x00000080 */
#define PWR_PDCRD_PD7                       PWR_PDCRD_PD7_Msk                       /*!< Apply pull-down for PD7  */
#define PWR_PDCRD_PD8_Pos                   (8UL)
#define PWR_PDCRD_PD8_Msk                   (0x1UL << PWR_PDCRD_PD8_Pos)            /*!< 0x00000100 */
#define PWR_PDCRD_PD8                       PWR_PDCRD_PD8_Msk                       /*!< Apply pull-down for PD8  */
#define PWR_PDCRD_PD9_Pos                   (9UL)
#define PWR_PDCRD_PD9_Msk                   (0x1UL << PWR_PDCRD_PD9_Pos)            /*!< 0x00000200 */
#define PWR_PDCRD_PD9                       PWR_PDCRD_PD9_Msk                       /*!< Apply pull-down for PD9  */
#define PWR_PDCRD_PD10_Pos                  (10UL)
#define PWR_PDCRD_PD10_Msk                  (0x1UL << PWR_PDCRD_PD10_Pos)           /*!< 0x00000400 */
#define PWR_PDCRD_PD10                      PWR_PDCRD_PD10_Msk                      /*!< Apply pull-down for PD10 */
#define PWR_PDCRD_PD11_Pos                  (11UL)
#define PWR_PDCRD_PD11_Msk                  (0x1UL << PWR_PDCRD_PD11_Pos)           /*!< 0x00000800 */
#define PWR_PDCRD_PD11                      PWR_PDCRD_PD11_Msk                      /*!< Apply pull-down for PD11 */
#define PWR_PDCRD_PD12_Pos                  (12UL)
#define PWR_PDCRD_PD12_Msk                  (0x1UL << PWR_PDCRD_PD12_Pos)           /*!< 0x00001000 */
#define PWR_PDCRD_PD12                      PWR_PDCRD_PD12_Msk                      /*!< Apply pull-down for PD12 */
#define PWR_PDCRD_PD13_Pos                  (13UL)
#define PWR_PDCRD_PD13_Msk                  (0x1UL << PWR_PDCRD_PD13_Pos)           /*!< 0x00002000 */
#define PWR_PDCRD_PD13                      PWR_PDCRD_PD13_Msk                      /*!< Apply pull-down for PD13 */
#define PWR_PDCRD_PD14_Pos                  (14UL)
#define PWR_PDCRD_PD14_Msk                  (0x1UL << PWR_PDCRD_PD14_Pos)           /*!< 0x00004000 */
#define PWR_PDCRD_PD14                      PWR_PDCRD_PD14_Msk                      /*!< Apply pull-down for PD14 */
#define PWR_PDCRD_PD15_Pos                  (15UL)
#define PWR_PDCRD_PD15_Msk                  (0x1UL << PWR_PDCRD_PD15_Pos)           /*!< 0x00008000 */
#define PWR_PDCRD_PD15                      PWR_PDCRD_PD15_Msk                      /*!< Apply pull-down for PD15 */

/********************  Bit definition for PWR_PUCRE register  *****************/
#define PWR_PUCRE_PU0_Pos                   (0UL)
#define PWR_PUCRE_PU0_Msk                   (0x1UL << PWR_PUCRE_PU0_Pos)            /*!< 0x00000001 */
#define PWR_PUCRE_PU0                       PWR_PUCRE_PU0_Msk                       /*!< Apply pull-up for PE0  */
#define PWR_PUCRE_PU1_Pos                   (1UL)
#define PWR_PUCRE_PU1_Msk                   (0x1UL << PWR_PUCRE_PU1_Pos)            /*!< 0x00000002 */
#define PWR_PUCRE_PU1                       PWR_PUCRE_PU1_Msk                       /*!< Apply pull-up for PE1  */
#define PWR_PUCRE_PU2_Pos                   (2UL)
#define PWR_PUCRE_PU2_Msk                   (0x1UL << PWR_PUCRE_PU2_Pos)            /*!< 0x00000004 */
#define PWR_PUCRE_PU2                       PWR_PUCRE_PU2_Msk                       /*!< Apply pull-up for PE2  */
#define PWR_PUCRE_PU3_Pos                   (3UL)
#define PWR_PUCRE_PU3_Msk                   (0x1UL << PWR_PUCRE_PU3_Pos)            /*!< 0x00000008 */
#define PWR_PUCRE_PU3                       PWR_PUCRE_PU3_Msk                       /*!< Apply pull-up for PE3  */
#define PWR_PUCRE_PU4_Pos                   (4UL)
#define PWR_PUCRE_PU4_Msk                   (0x1UL << PWR_PUCRE_PU4_Pos)            /*!< 0x00000010 */
#define PWR_PUCRE_PU4                       PWR_PUCRE_PU4_Msk                       /*!< Apply pull-up for PE4  */
#define PWR_PUCRE_PU5_Pos                   (5UL)
#define PWR_PUCRE_PU5_Msk                   (0x1UL << PWR_PUCRE_PU5_Pos)            /*!< 0x00000020 */
#define PWR_PUCRE_PU5                       PWR_PUCRE_PU5_Msk                       /*!< Apply pull-up for PE5  */
#define PWR_PUCRE_PU6_Pos                   (6UL)
#define PWR_PUCRE_PU6_Msk                   (0x1UL << PWR_PUCRE_PU6_Pos)            /*!< 0x00000040 */
#define PWR_PUCRE_PU6                       PWR_PUCRE_PU6_Msk                       /*!< Apply pull-up for PE6  */
#define PWR_PUCRE_PU7_Pos                   (7UL)
#define PWR_PUCRE_PU7_Msk                   (0x1UL << PWR_PUCRE_PU7_Pos)            /*!< 0x00000080 */
#define PWR_PUCRE_PU7                       PWR_PUCRE_PU7_Msk                       /*!< Apply pull-up for PE7  */
#define PWR_PUCRE_PU8_Pos                   (8UL)
#define PWR_PUCRE_PU8_Msk                   (0x1UL << PWR_PUCRE_PU8_Pos)            /*!< 0x00000100 */
#define PWR_PUCRE_PU8                       PWR_PUCRE_PU8_Msk                       /*!< Apply pull-up for PE8  */
#define PWR_PUCRE_PU9_Pos                   (9UL)
#define PWR_PUCRE_PU9_Msk                   (0x1UL << PWR_PUCRE_PU9_Pos)            /*!< 0x00000200 */
#define PWR_PUCRE_PU9                       PWR_PUCRE_PU9_Msk                       /*!< Apply pull-up for PE9  */
#define PWR_PUCRE_PU10_Pos                  (10UL)
#define PWR_PUCRE_PU10_Msk                  (0x1UL << PWR_PUCRE_PU10_Pos)           /*!< 0x00000400 */
#define PWR_PUCRE_PU10                      PWR_PUCRE_PU10_Msk                      /*!< Apply pull-up for PE10 */
#define PWR_PUCRE_PU11_Pos                  (11UL)
#define PWR_PUCRE_PU11_Msk                  (0x1UL << PWR_PUCRE_PU11_Pos)           /*!< 0x00000800 */
#define PWR_PUCRE_PU11                      PWR_PUCRE_PU11_Msk                      /*!< Apply pull-up for PE11 */
#define PWR_PUCRE_PU12_Pos                  (12UL)
#define PWR_PUCRE_PU12_Msk                  (0x1UL << PWR_PUCRE_PU12_Pos)           /*!< 0x00001000 */
#define PWR_PUCRE_PU12                      PWR_PUCRE_PU12_Msk                      /*!< Apply pull-up for PE12 */
#define PWR_PUCRE_PU13_Pos                  (13UL)
#define PWR_PUCRE_PU13_Msk                  (0x1UL << PWR_PUCRE_PU13_Pos)           /*!< 0x00002000 */
#define PWR_PUCRE_PU13                      PWR_PUCRE_PU13_Msk                      /*!< Apply pull-up for PE13 */
#define PWR_PUCRE_PU14_Pos                  (14UL)
#define PWR_PUCRE_PU14_Msk                  (0x1UL << PWR_PUCRE_PU14_Pos)           /*!< 0x00004000 */
#define PWR_PUCRE_PU14                      PWR_PUCRE_PU14_Msk                      /*!< Apply pull-up for PE14 */
#define PWR_PUCRE_PU15_Pos                  (15UL)
#define PWR_PUCRE_PU15_Msk                  (0x1UL << PWR_PUCRE_PU15_Pos)           /*!< 0x00008000 */
#define PWR_PUCRE_PU15                      PWR_PUCRE_PU15_Msk                      /*!< Apply pull-up for PE15 */

/********************  Bit definition for PWR_PDCRE register  *****************/
#define PWR_PDCRE_PD0_Pos                   (0UL)
#define PWR_PDCRE_PD0_Msk                   (0x1UL << PWR_PDCRE_PD0_Pos)            /*!< 0x00000001 */
#define PWR_PDCRE_PD0                       PWR_PDCRE_PD0_Msk                       /*!< Apply pull-down for PE0  */
#define PWR_PDCRE_PD1_Pos                   (1UL)
#define PWR_PDCRE_PD1_Msk                   (0x1UL << PWR_PDCRE_PD1_Pos)            /*!< 0x00000002 */
#define PWR_PDCRE_PD1                       PWR_PDCRE_PD1_Msk                       /*!< Apply pull-down for PE1  */
#define PWR_PDCRE_PD2_Pos                   (2UL)
#define PWR_PDCRE_PD2_Msk                   (0x1UL << PWR_PDCRE_PD2_Pos)            /*!< 0x00000004 */
#define PWR_PDCRE_PD2                       PWR_PDCRE_PD2_Msk                       /*!< Apply pull-down for PE2  */
#define PWR_PDCRE_PD3_Pos                   (3UL)
#define PWR_PDCRE_PD3_Msk                   (0x1UL << PWR_PDCRE_PD3_Pos)            /*!< 0x00000008 */
#define PWR_PDCRE_PD3                       PWR_PDCRE_PD3_Msk                       /*!< Apply pull-down for PE3  */
#define PWR_PDCRE_PD4_Pos                   (4UL)
#define PWR_PDCRE_PD4_Msk                   (0x1UL << PWR_PDCRE_PD4_Pos)            /*!< 0x00000010 */
#define PWR_PDCRE_PD4                       PWR_PDCRE_PD4_Msk                       /*!< Apply pull-down for PE4  */
#define PWR_PDCRE_PD5_Pos                   (5UL)
#define PWR_PDCRE_PD5_Msk                   (0x1UL << PWR_PDCRE_PD5_Pos)            /*!< 0x00000020 */
#define PWR_PDCRE_PD5                       PWR_PDCRE_PD5_Msk                       /*!< Apply pull-down for PE5  */
#define PWR_PDCRE_PD6_Pos                   (6UL)
#define PWR_PDCRE_PD6_Msk                   (0x1UL << PWR_PDCRE_PD6_Pos)            /*!< 0x00000040 */
#define PWR_PDCRE_PD6                       PWR_PDCRE_PD6_Msk                       /*!< Apply pull-down for PE6  */
#define PWR_PDCRE_PD7_Pos                   (7UL)
#define PWR_PDCRE_PD7_Msk                   (0x1UL << PWR_PDCRE_PD7_Pos)            /*!< 0x00000080 */
#define PWR_PDCRE_PD7                       PWR_PDCRE_PD7_Msk                       /*!< Apply pull-down for PE7  */
#define PWR_PDCRE_PD8_Pos                   (8UL)
#define PWR_PDCRE_PD8_Msk                   (0x1UL << PWR_PDCRE_PD8_Pos)            /*!< 0x00000100 */
#define PWR_PDCRE_PD8                       PWR_PDCRE_PD8_Msk                       /*!< Apply pull-down for PE8  */
#define PWR_PDCRE_PD9_Pos                   (9UL)
#define PWR_PDCRE_PD9_Msk                   (0x1UL << PWR_PDCRE_PD9_Pos)            /*!< 0x00000200 */
#define PWR_PDCRE_PD9                       PWR_PDCRE_PD9_Msk                       /*!< Apply pull-down for PE9  */
#define PWR_PDCRE_PD10_Pos                  (10UL)
#define PWR_PDCRE_PD10_Msk                  (0x1UL << PWR_PDCRE_PD10_Pos)           /*!< 0x00000400 */
#define PWR_PDCRE_PD10                      PWR_PDCRE_PD10_Msk                      /*!< Apply pull-down for PE10 */
#define PWR_PDCRE_PD11_Pos                  (11UL)
#define PWR_PDCRE_PD11_Msk                  (0x1UL << PWR_PDCRE_PD11_Pos)           /*!< 0x00000800 */
#define PWR_PDCRE_PD11                      PWR_PDCRE_PD11_Msk                      /*!< Apply pull-down for PE11 */
#define PWR_PDCRE_PD12_Pos                  (12UL)
#define PWR_PDCRE_PD12_Msk                  (0x1UL << PWR_PDCRE_PD12_Pos)           /*!< 0x00001000 */
#define PWR_PDCRE_PD12                      PWR_PDCRE_PD12_Msk                      /*!< Apply pull-down for PE12 */
#define PWR_PDCRE_PD13_Pos                  (13UL)
#define PWR_PDCRE_PD13_Msk                  (0x1UL << PWR_PDCRE_PD13_Pos)           /*!< 0x00002000 */
#define PWR_PDCRE_PD13                      PWR_PDCRE_PD13_Msk                      /*!< Apply pull-down for PE13 */
#define PWR_PDCRE_PD14_Pos                  (14UL)
#define PWR_PDCRE_PD14_Msk                  (0x1UL << PWR_PDCRE_PD14_Pos)           /*!< 0x00004000 */
#define PWR_PDCRE_PD14                      PWR_PDCRE_PD14_Msk                      /*!< Apply pull-down for PE14 */
#define PWR_PDCRE_PD15_Pos                  (15UL)
#define PWR_PDCRE_PD15_Msk                  (0x1UL << PWR_PDCRE_PD15_Pos)           /*!< 0x00008000 */
#define PWR_PDCRE_PD15                      PWR_PDCRE_PD15_Msk                      /*!< Apply pull-down for PE15 */

/********************  Bit definition for PWR_PUCRG register  *****************/
#define PWR_PUCRG_PU2_Pos                   (2UL)
#define PWR_PUCRG_PU2_Msk                   (0x1UL << PWR_PUCRG_PU2_Pos)            /*!< 0x00000004 */
#define PWR_PUCRG_PU2                       PWR_PUCRG_PU2_Msk                       /*!< Apply pull-up for PG2  */
#define PWR_PUCRG_PU3_Pos                   (3UL)
#define PWR_PUCRG_PU3_Msk                   (0x1UL << PWR_PUCRG_PU3_Pos)            /*!< 0x00000008 */
#define PWR_PUCRG_PU3                       PWR_PUCRG_PU3_Msk                       /*!< Apply pull-up for PG3  */
#define PWR_PUCRG_PU4_Pos                   (4UL)
#define PWR_PUCRG_PU4_Msk                   (0x1UL << PWR_PUCRG_PU4_Pos)            /*!< 0x00000010 */
#define PWR_PUCRG_PU4                       PWR_PUCRG_PU4_Msk                       /*!< Apply pull-up for PG4  */
#define PWR_PUCRG_PU5_Pos                   (5UL)
#define PWR_PUCRG_PU5_Msk                   (0x1UL << PWR_PUCRG_PU5_Pos)            /*!< 0x00000020 */
#define PWR_PUCRG_PU5                       PWR_PUCRG_PU5_Msk                       /*!< Apply pull-up for PG5  */
#define PWR_PUCRG_PU6_Pos                   (6UL)
#define PWR_PUCRG_PU6_Msk                   (0x1UL << PWR_PUCRG_PU6_Pos)            /*!< 0x00000040 */
#define PWR_PUCRG_PU6                       PWR_PUCRG_PU6_Msk                       /*!< Apply pull-up for PG6  */
#define PWR_PUCRG_PU7_Pos                   (7UL)
#define PWR_PUCRG_PU7_Msk                   (0x1UL << PWR_PUCRG_PU7_Pos)            /*!< 0x00000080 */
#define PWR_PUCRG_PU7                       PWR_PUCRG_PU7_Msk                       /*!< Apply pull-up for PG7  */
#define PWR_PUCRG_PU8_Pos                   (8UL)
#define PWR_PUCRG_PU8_Msk                   (0x1UL << PWR_PUCRG_PU8_Pos)            /*!< 0x00000100 */
#define PWR_PUCRG_PU8                       PWR_PUCRG_PU8_Msk                       /*!< Apply pull-up for PG8  */
#define PWR_PUCRG_PU9_Pos                   (9UL)
#define PWR_PUCRG_PU9_Msk                   (0x1UL << PWR_PUCRG_PU9_Pos)            /*!< 0x00000200 */
#define PWR_PUCRG_PU9                       PWR_PUCRG_PU9_Msk                       /*!< Apply pull-up for PG9  */
#define PWR_PUCRG_PU10_Pos                  (10UL)
#define PWR_PUCRG_PU10_Msk                  (0x1UL << PWR_PUCRG_PU10_Pos)           /*!< 0x00000400 */
#define PWR_PUCRG_PU10                      PWR_PUCRG_PU10_Msk                      /*!< Apply pull-up for PG10 */
#define PWR_PUCRG_PU11_Pos                  (11UL)
#define PWR_PUCRG_PU11_Msk                  (0x1UL << PWR_PUCRG_PU11_Pos)           /*!< 0x00000800 */
#define PWR_PUCRG_PU11                      PWR_PUCRG_PU11_Msk                      /*!< Apply pull-up for PG11 */
#define PWR_PUCRG_PU12_Pos                  (12UL)
#define PWR_PUCRG_PU12_Msk                  (0x1UL << PWR_PUCRG_PU12_Pos)           /*!< 0x00001000 */
#define PWR_PUCRG_PU12                      PWR_PUCRG_PU12_Msk                      /*!< Apply pull-up for PG12 */
#define PWR_PUCRG_PU13_Pos                  (13UL)
#define PWR_PUCRG_PU13_Msk                  (0x1UL << PWR_PUCRG_PU13_Pos)           /*!< 0x00002000 */
#define PWR_PUCRG_PU13                      PWR_PUCRG_PU13_Msk                      /*!< Apply pull-up for PG13 */
#define PWR_PUCRG_PU14_Pos                  (14UL)
#define PWR_PUCRG_PU14_Msk                  (0x1UL << PWR_PUCRG_PU14_Pos)           /*!< 0x00004000 */
#define PWR_PUCRG_PU14                      PWR_PUCRG_PU14_Msk                      /*!< Apply pull-up for PG14 */
#define PWR_PUCRG_PU15_Pos                  (15UL)
#define PWR_PUCRG_PU15_Msk                  (0x1UL << PWR_PUCRG_PU15_Pos)           /*!< 0x00008000 */
#define PWR_PUCRG_PU15                      PWR_PUCRG_PU15_Msk                      /*!< Apply pull-up for PG15 */

/********************  Bit definition for PWR_PDCRG register  *****************/
#define PWR_PDCRG_PD2_Pos                   (2UL)
#define PWR_PDCRG_PD2_Msk                   (0x1UL << PWR_PDCRG_PD2_Pos)            /*!< 0x00000004 */
#define PWR_PDCRG_PD2                       PWR_PDCRG_PD2_Msk                       /*!< Apply pull-down for PG2  */
#define PWR_PDCRG_PD3_Pos                   (3UL)
#define PWR_PDCRG_PD3_Msk                   (0x1UL << PWR_PDCRG_PD3_Pos)            /*!< 0x00000008 */
#define PWR_PDCRG_PD3                       PWR_PDCRG_PD3_Msk                       /*!< Apply pull-down for PG3  */
#define PWR_PDCRG_PD4_Pos                   (4UL)
#define PWR_PDCRG_PD4_Msk                   (0x1UL << PWR_PDCRG_PD4_Pos)            /*!< 0x00000010 */
#define PWR_PDCRG_PD4                       PWR_PDCRG_PD4_Msk                       /*!< Apply pull-down for PG4  */
#define PWR_PDCRG_PD5_Pos                   (5UL)
#define PWR_PDCRG_PD5_Msk                   (0x1UL << PWR_PDCRG_PD5_Pos)            /*!< 0x00000020 */
#define PWR_PDCRG_PD5                       PWR_PDCRG_PD5_Msk                       /*!< Apply pull-down for PG5  */
#define PWR_PDCRG_PD6_Pos                   (6UL)
#define PWR_PDCRG_PD6_Msk                   (0x1UL << PWR_PDCRG_PD6_Pos)            /*!< 0x00000040 */
#define PWR_PDCRG_PD6                       PWR_PDCRG_PD6_Msk                       /*!< Apply pull-down for PG6  */
#define PWR_PDCRG_PD7_Pos                   (7UL)
#define PWR_PDCRG_PD7_Msk                   (0x1UL << PWR_PDCRG_PD7_Pos)            /*!< 0x00000080 */
#define PWR_PDCRG_PD7                       PWR_PDCRG_PD7_Msk                       /*!< Apply pull-down for PG7  */
#define PWR_PDCRG_PD8_Pos                   (8UL)
#define PWR_PDCRG_PD8_Msk                   (0x1UL << PWR_PDCRG_PD8_Pos)            /*!< 0x00000100 */
#define PWR_PDCRG_PD8                       PWR_PDCRG_PD8_Msk                       /*!< Apply pull-down for PG8  */
#define PWR_PDCRG_PD9_Pos                   (9UL)
#define PWR_PDCRG_PD9_Msk                   (0x1UL << PWR_PDCRG_PD9_Pos)            /*!< 0x00000200 */
#define PWR_PDCRG_PD9                       PWR_PDCRG_PD9_Msk                       /*!< Apply pull-down for PG9  */
#define PWR_PDCRG_PD10_Pos                  (10UL)
#define PWR_PDCRG_PD10_Msk                  (0x1UL << PWR_PDCRG_PD10_Pos)           /*!< 0x00000400 */
#define PWR_PDCRG_PD10                      PWR_PDCRG_PD10_Msk                      /*!< Apply pull-down for PG10 */
#define PWR_PDCRG_PD11_Pos                  (11UL)
#define PWR_PDCRG_PD11_Msk                  (0x1UL << PWR_PDCRG_PD11_Pos)           /*!< 0x00000800 */
#define PWR_PDCRG_PD11                      PWR_PDCRG_PD11_Msk                      /*!< Apply pull-down for PG11 */
#define PWR_PDCRG_PD12_Pos                  (12UL)
#define PWR_PDCRG_PD12_Msk                  (0x1UL << PWR_PDCRG_PD12_Pos)           /*!< 0x00001000 */
#define PWR_PDCRG_PD12                      PWR_PDCRG_PD12_Msk                      /*!< Apply pull-down for PG12 */
#define PWR_PDCRG_PD13_Pos                  (13UL)
#define PWR_PDCRG_PD13_Msk                  (0x1UL << PWR_PDCRG_PD13_Pos)           /*!< 0x00002000 */
#define PWR_PDCRG_PD13                      PWR_PDCRG_PD13_Msk                      /*!< Apply pull-down for PG13 */
#define PWR_PDCRG_PD14_Pos                  (14UL)
#define PWR_PDCRG_PD14_Msk                  (0x1UL << PWR_PDCRG_PD14_Pos)           /*!< 0x00004000 */
#define PWR_PDCRG_PD14                      PWR_PDCRG_PD14_Msk                      /*!< Apply pull-down for PG14 */
#define PWR_PDCRG_PD15_Pos                  (15UL)
#define PWR_PDCRG_PD15_Msk                  (0x1UL << PWR_PDCRG_PD15_Pos)           /*!< 0x00008000 */
#define PWR_PDCRG_PD15                      PWR_PDCRG_PD15_Msk                      /*!< Apply pull-down for PG15 */

/********************  Bit definition for PWR_PUCRH register  *****************/
#define PWR_PUCRH_PU0_Pos                   (0UL)
#define PWR_PUCRH_PU0_Msk                   (0x1UL << PWR_PUCRH_PU0_Pos)            /*!< 0x00000001 */
#define PWR_PUCRH_PU0                       PWR_PUCRH_PU0_Msk                       /*!< Apply pull-up for PH0  */
#define PWR_PUCRH_PU1_Pos                   (1UL)
#define PWR_PUCRH_PU1_Msk                   (0x1UL << PWR_PUCRH_PU1_Pos)            /*!< 0x00000002 */
#define PWR_PUCRH_PU1                       PWR_PUCRH_PU1_Msk                       /*!< Apply pull-up for PH1  */
#define PWR_PUCRH_PU3_Pos                   (3UL)
#define PWR_PUCRH_PU3_Msk                   (0x1UL << PWR_PUCRH_PU3_Pos)            /*!< 0x00000008 */
#define PWR_PUCRH_PU3                       PWR_PUCRH_PU3_Msk                       /*!< Apply pull-up for PH3  */

/********************  Bit definition for PWR_PDCRH register  *****************/
#define PWR_PDCRH_PD0_Pos                   (0UL)
#define PWR_PDCRH_PD0_Msk                   (0x1UL << PWR_PDCRH_PD0_Pos)            /*!< 0x00000001 */
#define PWR_PDCRH_PD0                       PWR_PDCRH_PD0_Msk                       /*!< Apply pull-down for PH0  */
#define PWR_PDCRH_PD1_Pos                   (1UL)
#define PWR_PDCRH_PD1_Msk                   (0x1UL << PWR_PDCRH_PD1_Pos)            /*!< 0x00000002 */
#define PWR_PDCRH_PD1                       PWR_PDCRH_PD1_Msk                       /*!< Apply pull-down for PH1  */
#define PWR_PDCRH_PD3_Pos                   (3UL)
#define PWR_PDCRH_PD3_Msk                   (0x1UL << PWR_PDCRH_PD3_Pos)            /*!< 0x00000008 */
#define PWR_PDCRH_PD3                       PWR_PDCRH_PD3_Msk                       /*!< Apply pull-down for PH3  */

/********************  Bit definition for PWR_I3CPUCR1 register  *****************/
#define PWR_I3CPUCR1_PA1_I3CPU_Pos          (0UL)
#define PWR_I3CPUCR1_PA1_I3CPU_Msk          (0x1UL << PWR_I3CPUCR1_PA1_I3CPU_Pos)   /*!< 0x00000001 */
#define PWR_I3CPUCR1_PA1_I3CPU              PWR_I3CPUCR1_PA1_I3CPU_Msk              /*!< Port A pin 1 I3C pull-up  */
#define PWR_I3CPUCR1_PA6_I3CPU_Pos          (1UL)
#define PWR_I3CPUCR1_PA6_I3CPU_Msk          (0x1UL << PWR_I3CPUCR1_PA6_I3CPU_Pos)   /*!< 0x00000002 */
#define PWR_I3CPUCR1_PA6_I3CPU              PWR_I3CPUCR1_PA6_I3CPU_Msk              /*!< Port A pin 6 I3C pull-up  */
#define PWR_I3CPUCR1_PA7_I3CPU_Pos          (2UL)
#define PWR_I3CPUCR1_PA7_I3CPU_Msk          (0x1UL << PWR_I3CPUCR1_PA7_I3CPU_Pos)   /*!< 0x00000004 */
#define PWR_I3CPUCR1_PA7_I3CPU              PWR_I3CPUCR1_PA7_I3CPU_Msk              /*!< Port A pin 7 I3C pull-up  */
#define PWR_I3CPUCR1_PB2_I3CPU_Pos          (4UL)
#define PWR_I3CPUCR1_PB2_I3CPU_Msk          (0x1UL << PWR_I3CPUCR1_PB2_I3CPU_Pos)   /*!< 0x00000010 */
#define PWR_I3CPUCR1_PB2_I3CPU              PWR_I3CPUCR1_PB2_I3CPU_Msk              /*!< Port B pin 2 I3C pull-up  */
#define PWR_I3CPUCR1_PB6_I3CPU_Pos          (5UL)
#define PWR_I3CPUCR1_PB6_I3CPU_Msk          (0x1UL << PWR_I3CPUCR1_PB6_I3CPU_Pos)   /*!< 0x00000020 */
#define PWR_I3CPUCR1_PB6_I3CPU              PWR_I3CPUCR1_PB6_I3CPU_Msk              /*!< Port B pin 6 I3C pull-up  */
#define PWR_I3CPUCR1_PB8_I3CPU_Pos          (6UL)
#define PWR_I3CPUCR1_PB8_I3CPU_Msk          (0x1UL << PWR_I3CPUCR1_PB8_I3CPU_Pos)   /*!< 0x00000040 */
#define PWR_I3CPUCR1_PB8_I3CPU              PWR_I3CPUCR1_PB8_I3CPU_Msk              /*!< Port B pin 8 I3C pull-up  */
#define PWR_I3CPUCR1_PB9_I3CPU_Pos          (7UL)
#define PWR_I3CPUCR1_PB9_I3CPU_Msk          (0x1UL << PWR_I3CPUCR1_PB9_I3CPU_Pos)   /*!< 0x00000080 */
#define PWR_I3CPUCR1_PB9_I3CPU              PWR_I3CPUCR1_PB9_I3CPU_Msk              /*!< Port B pin 9 I3C pull-up  */
#define PWR_I3CPUCR1_PB10_I3CPU_Pos         (8UL)
#define PWR_I3CPUCR1_PB10_I3CPU_Msk         (0x1UL << PWR_I3CPUCR1_PB10_I3CPU_Pos)  /*!< 0x00000100 */
#define PWR_I3CPUCR1_PB10_I3CPU             PWR_I3CPUCR1_PB10_I3CPU_Msk             /*!< Port B pin 10 I3C pull-up */
#define PWR_I3CPUCR1_PB12_I3CPU_Pos         (9UL)
#define PWR_I3CPUCR1_PB12_I3CPU_Msk         (0x1UL << PWR_I3CPUCR1_PB12_I3CPU_Pos)  /*!< 0x00000200 */
#define PWR_I3CPUCR1_PB12_I3CPU             PWR_I3CPUCR1_PB12_I3CPU_Msk             /*!< Port B pin 12 I3C pull-up */
#define PWR_I3CPUCR1_PB13_I3CPU_Pos         (10UL)
#define PWR_I3CPUCR1_PB13_I3CPU_Msk         (0x1UL << PWR_I3CPUCR1_PB13_I3CPU_Pos)  /*!< 0x00000400 */
#define PWR_I3CPUCR1_PB13_I3CPU             PWR_I3CPUCR1_PB13_I3CPU_Msk             /*!< Port B pin 13 I3C pull-up */
#define PWR_I3CPUCR1_PB14_I3CPU_Pos         (11UL)
#define PWR_I3CPUCR1_PB14_I3CPU_Msk         (0x1UL << PWR_I3CPUCR1_PB14_I3CPU_Pos)  /*!< 0x00000800 */
#define PWR_I3CPUCR1_PB14_I3CPU             PWR_I3CPUCR1_PB14_I3CPU_Msk             /*!< Port B pin 14 I3C pull-up */

/********************  Bit definition for PWR_I3CPUCR2 register  *****************/
#define PWR_I3CPUCR2_PC0_I3CPU_Pos          (0UL)
#define PWR_I3CPUCR2_PC0_I3CPU_Msk          (0x1UL << PWR_I3CPUCR2_PC0_I3CPU_Pos)   /*!< 0x00000001 */
#define PWR_I3CPUCR2_PC0_I3CPU              PWR_I3CPUCR2_PC0_I3CPU_Msk              /*!< Port C pin 0 I3C pull-up  */
#define PWR_I3CPUCR2_PC1_I3CPU_Pos          (1UL)
#define PWR_I3CPUCR2_PC1_I3CPU_Msk          (0x1UL << PWR_I3CPUCR2_PC1_I3CPU_Pos)   /*!< 0x00000002 */
#define PWR_I3CPUCR2_PC1_I3CPU              PWR_I3CPUCR2_PC1_I3CPU_Msk              /*!< Port C pin 1 I3C pull-up  */
#define PWR_I3CPUCR2_PD12_I3CPU_Pos         (3UL)
#define PWR_I3CPUCR2_PD12_I3CPU_Msk         (0x1UL << PWR_I3CPUCR2_PD12_I3CPU_Pos)  /*!< 0x00000008 */
#define PWR_I3CPUCR2_PD12_I3CPU             PWR_I3CPUCR2_PD12_I3CPU_Msk             /*!< Port D pin 12 I3C pull-up */
#define PWR_I3CPUCR2_PD13_I3CPU_Pos         (4UL)
#define PWR_I3CPUCR2_PD13_I3CPU_Msk         (0x1UL << PWR_I3CPUCR2_PD13_I3CPU_Pos)  /*!< 0x00000010 */
#define PWR_I3CPUCR2_PD13_I3CPU             PWR_I3CPUCR2_PD13_I3CPU_Msk             /*!< Port D pin 13 I3C pull-up */
#define PWR_I3CPUCR2_PG7_I3CPU_Pos          (6UL)
#define PWR_I3CPUCR2_PG7_I3CPU_Msk          (0x1UL << PWR_I3CPUCR2_PG7_I3CPU_Pos)   /*!< 0x00000040 */
#define PWR_I3CPUCR2_PG7_I3CPU              PWR_I3CPUCR2_PG7_I3CPU_Msk              /*!< Port G pin 7 I3C pull-up  */
#define PWR_I3CPUCR2_PG8_I3CPU_Pos          (7UL)
#define PWR_I3CPUCR2_PG8_I3CPU_Msk          (0x1UL << PWR_I3CPUCR2_PG8_I3CPU_Pos)   /*!< 0x00000080 */
#define PWR_I3CPUCR2_PG8_I3CPU              PWR_I3CPUCR2_PG8_I3CPU_Msk              /*!< Port G pin 8 I3C pull-up  */
#define PWR_I3CPUCR2_PG13_I3CPU_Pos         (8UL)
#define PWR_I3CPUCR2_PG13_I3CPU_Msk         (0x1UL << PWR_I3CPUCR2_PG13_I3CPU_Pos)  /*!< 0x00000100 */
#define PWR_I3CPUCR2_PG13_I3CPU             PWR_I3CPUCR2_PG13_I3CPU_Msk             /*!< Port G pin 13 I3C pull-up */
#define PWR_I3CPUCR2_PG14_I3CPU_Pos         (9UL)
#define PWR_I3CPUCR2_PG14_I3CPU_Msk         (0x1UL << PWR_I3CPUCR2_PG14_I3CPU_Pos)  /*!< 0x00000200 */
#define PWR_I3CPUCR2_PG14_I3CPU             PWR_I3CPUCR2_PG14_I3CPU_Msk             /*!< Port G pin 14 I3C pull-up */
#define PWR_I3CPUCR2_PH3_I3CPU_Pos          (11UL)
#define PWR_I3CPUCR2_PH3_I3CPU_Msk          (0x1UL << PWR_I3CPUCR2_PH3_I3CPU_Pos)   /*!< 0x00000800 */
#define PWR_I3CPUCR2_PH3_I3CPU              PWR_I3CPUCR2_PH3_I3CPU_Msk              /*!< Port H pin 3 I3C pull-up  */

/******************************************************************************/
/*                                                                            */
/*                      SRAMs configuration controller                        */
/*                                                                            */
/******************************************************************************/
/*******************  Bit definition for RAMCFG_MxCR register  ******************/
#define RAMCFG_CR_PCE_Pos                   (0UL)
#define RAMCFG_CR_PCE_Msk                   (0x1UL << RAMCFG_CR_PCE_Pos)              /*!< 0x00000001 */
#define RAMCFG_CR_PCE                       RAMCFG_CR_PCE_Msk                         /*!< Parity check Enable */
#define RAMCFG_CR_ALE_Pos                   (4UL)
#define RAMCFG_CR_ALE_Msk                   (0x1UL << RAMCFG_CR_ALE_Pos)              /*!< 0x00000010 */
#define RAMCFG_CR_ALE                       RAMCFG_CR_ALE_Msk                         /*!< Address Latching Enable */
#define RAMCFG_CR_SRAMER_Pos                (8UL)
#define RAMCFG_CR_SRAMER_Msk                (0x1UL << RAMCFG_CR_SRAMER_Pos)           /*!< 0x00000100 */
#define RAMCFG_CR_SRAMER                    RAMCFG_CR_SRAMER_Msk                      /*!< Start Erase */

/*******************  Bit definition for RAMCFG_MxIER register  ******************/
#define RAMCFG_IER_PEIE_Pos                 (1UL)
#define RAMCFG_IER_PEIE_Msk                 (0x1UL << RAMCFG_IER_PEIE_Pos)            /*!< 0x00000001 */
#define RAMCFG_IER_PEIE                     RAMCFG_IER_PEIE_Msk                       /*!< Parity error interrupt enable */
#define RAMCFG_IER_PENMI_Pos                (3UL)
#define RAMCFG_IER_PENMI_Msk                (0x1UL << RAMCFG_IER_PENMI_Pos)           /*!< 0x00000004 */
#define RAMCFG_IER_PENMI                    RAMCFG_IER_PENMI_Msk                      /*!< Parity error NMI */

/*******************  Bit definition for RAMCFG_MxISR register  ******************/
#define RAMCFG_ISR_PED_Pos                  (1UL)
#define RAMCFG_ISR_PED_Msk                  (0x1UL << RAMCFG_ISR_PED_Pos)             /*!< 0x00000002 */
#define RAMCFG_ISR_PED                      RAMCFG_ISR_PED_Msk                        /*!< Parity error detected */
#define RAMCFG_ISR_SRAMBUSY_Pos             (8UL)
#define RAMCFG_ISR_SRAMBUSY_Msk             (0x1UL << RAMCFG_ISR_SRAMBUSY_Pos)        /*!< 0x00000100 */
#define RAMCFG_ISR_SRAMBUSY                 RAMCFG_ISR_SRAMBUSY_Msk                   /*!< SRAM busy with erase operation */

/*******************  Bit definition for RAMCFG_MxPEAR register  ******************/
#define RAMCFG_PEAR_PEA_Pos                 (0UL)
#define RAMCFG_PEAR_PEA_Msk                 (0xFFFFFFFFUL << RAMCFG_PEAR_PEA_Pos)     /*!< 0xFFFFFFFF */
#define RAMCFG_PEAR_PEA                     RAMCFG_PEAR_PEA_Msk                       /*!< Parity error address */

/*******************  Bit definition for RAMCFG_MxICR register  *****************/
#define RAMCFG_ICR_CPED_Pos                 (1UL)
#define RAMCFG_ICR_CPED_Msk                 (0x1UL << RAMCFG_ICR_CPED_Pos)            /*!< 0x00000002 */
#define RAMCFG_ICR_CPED                     RAMCFG_ICR_CPED_Msk                       /*!< Clear parity error detect bit */

/******************  Bit definition for RAMCFG_MxWPR1 register  *****************/
#define RAMCFG_WPR1_P0WP_Pos                (0UL)
#define RAMCFG_WPR1_P0WP_Msk                (0x1UL << RAMCFG_WPR1_P0WP_Pos)           /*!< 0x00000001 */
#define RAMCFG_WPR1_P0WP                    RAMCFG_WPR1_P0WP_Msk                      /*!< Write Protection Page 00 */
#define RAMCFG_WPR1_P1WP_Pos                (1UL)
#define RAMCFG_WPR1_P1WP_Msk                (0x1UL << RAMCFG_WPR1_P1WP_Pos)           /*!< 0x00000002 */
#define RAMCFG_WPR1_P1WP                    RAMCFG_WPR1_P1WP_Msk                      /*!< Write Protection Page 01 */
#define RAMCFG_WPR1_P2WP_Pos                (2UL)
#define RAMCFG_WPR1_P2WP_Msk                (0x1UL << RAMCFG_WPR1_P2WP_Pos)           /*!< 0x00000004 */
#define RAMCFG_WPR1_P2WP                    RAMCFG_WPR1_P2WP_Msk                      /*!< Write Protection Page 02 */
#define RAMCFG_WPR1_P3WP_Pos                (3UL)
#define RAMCFG_WPR1_P3WP_Msk                (0x1UL << RAMCFG_WPR1_P3WP_Pos)           /*!< 0x00000008 */
#define RAMCFG_WPR1_P3WP                    RAMCFG_WPR1_P3WP_Msk                      /*!< Write Protection Page 03 */
#define RAMCFG_WPR1_P4WP_Pos                (4UL)
#define RAMCFG_WPR1_P4WP_Msk                (0x1UL << RAMCFG_WPR1_P4WP_Pos)           /*!< 0x00000010 */
#define RAMCFG_WPR1_P4WP                    RAMCFG_WPR1_P4WP_Msk                      /*!< Write Protection Page 04 */
#define RAMCFG_WPR1_P5WP_Pos                (5UL)
#define RAMCFG_WPR1_P5WP_Msk                (0x1UL << RAMCFG_WPR1_P5WP_Pos)           /*!< 0x00000020 */
#define RAMCFG_WPR1_P5WP                    RAMCFG_WPR1_P5WP_Msk                      /*!< Write Protection Page 05 */
#define RAMCFG_WPR1_P6WP_Pos                (6UL)
#define RAMCFG_WPR1_P6WP_Msk                (0x1UL << RAMCFG_WPR1_P6WP_Pos)           /*!< 0x00000040 */
#define RAMCFG_WPR1_P6WP                    RAMCFG_WPR1_P6WP_Msk                      /*!< Write Protection Page 06 */
#define RAMCFG_WPR1_P7WP_Pos                (7UL)
#define RAMCFG_WPR1_P7WP_Msk                (0x1UL << RAMCFG_WPR1_P7WP_Pos)           /*!< 0x00000080 */
#define RAMCFG_WPR1_P7WP                    RAMCFG_WPR1_P7WP_Msk                      /*!< Write Protection Page 07 */
#define RAMCFG_WPR1_P8WP_Pos                (8UL)
#define RAMCFG_WPR1_P8WP_Msk                (0x1UL << RAMCFG_WPR1_P8WP_Pos)           /*!< 0x00000100 */
#define RAMCFG_WPR1_P8WP                    RAMCFG_WPR1_P8WP_Msk                      /*!< Write Protection Page 08 */
#define RAMCFG_WPR1_P9WP_Pos                (9UL)
#define RAMCFG_WPR1_P9WP_Msk                (0x1UL << RAMCFG_WPR1_P9WP_Pos)           /*!< 0x00000200 */
#define RAMCFG_WPR1_P9WP                    RAMCFG_WPR1_P9WP_Msk                      /*!< Write Protection Page 09 */
#define RAMCFG_WPR1_P10WP_Pos               (10UL)
#define RAMCFG_WPR1_P10WP_Msk               (0x1UL << RAMCFG_WPR1_P10WP_Pos)          /*!< 0x00000400 */
#define RAMCFG_WPR1_P10WP                   RAMCFG_WPR1_P10WP_Msk                     /*!< Write Protection Page 10 */
#define RAMCFG_WPR1_P11WP_Pos               (11UL)
#define RAMCFG_WPR1_P11WP_Msk               (0x1UL << RAMCFG_WPR1_P11WP_Pos)          /*!< 0x00000800 */
#define RAMCFG_WPR1_P11WP                   RAMCFG_WPR1_P11WP_Msk                     /*!< Write Protection Page 11 */
#define RAMCFG_WPR1_P12WP_Pos               (12UL)
#define RAMCFG_WPR1_P12WP_Msk               (0x1UL << RAMCFG_WPR1_P12WP_Pos)          /*!< 0x00001000 */
#define RAMCFG_WPR1_P12WP                   RAMCFG_WPR1_P12WP_Msk                     /*!< Write Protection Page 12 */
#define RAMCFG_WPR1_P13WP_Pos               (13UL)
#define RAMCFG_WPR1_P13WP_Msk               (0x1UL << RAMCFG_WPR1_P13WP_Pos)          /*!< 0x00002000 */
#define RAMCFG_WPR1_P13WP                   RAMCFG_WPR1_P13WP_Msk                     /*!< Write Protection Page 13 */
#define RAMCFG_WPR1_P14WP_Pos               (14UL)
#define RAMCFG_WPR1_P14WP_Msk               (0x1UL << RAMCFG_WPR1_P14WP_Pos)          /*!< 0x00004000 */
#define RAMCFG_WPR1_P14WP                   RAMCFG_WPR1_P14WP_Msk                     /*!< Write Protection Page 14 */
#define RAMCFG_WPR1_P15WP_Pos               (15UL)
#define RAMCFG_WPR1_P15WP_Msk               (0x1UL << RAMCFG_WPR1_P15WP_Pos)          /*!< 0x00008000 */
#define RAMCFG_WPR1_P15WP                   RAMCFG_WPR1_P15WP_Msk                     /*!< Write Protection Page 15 */
#define RAMCFG_WPR1_P16WP_Pos               (16UL)
#define RAMCFG_WPR1_P16WP_Msk               (0x1UL << RAMCFG_WPR1_P16WP_Pos)          /*!< 0x00010000 */
#define RAMCFG_WPR1_P16WP                   RAMCFG_WPR1_P16WP_Msk                     /*!< Write Protection Page 16 */
#define RAMCFG_WPR1_P17WP_Pos               (17UL)
#define RAMCFG_WPR1_P17WP_Msk               (0x1UL << RAMCFG_WPR1_P17WP_Pos)          /*!< 0x00020000 */
#define RAMCFG_WPR1_P17WP                   RAMCFG_WPR1_P17WP_Msk                     /*!< Write Protection Page 17 */
#define RAMCFG_WPR1_P18WP_Pos               (18UL)
#define RAMCFG_WPR1_P18WP_Msk               (0x1UL << RAMCFG_WPR1_P18WP_Pos)          /*!< 0x00040000 */
#define RAMCFG_WPR1_P18WP                   RAMCFG_WPR1_P18WP_Msk                     /*!< Write Protection Page 18 */
#define RAMCFG_WPR1_P19WP_Pos               (19UL)
#define RAMCFG_WPR1_P19WP_Msk               (0x1UL << RAMCFG_WPR1_P19WP_Pos)          /*!< 0x00080000 */
#define RAMCFG_WPR1_P19WP                   RAMCFG_WPR1_P19WP_Msk                     /*!< Write Protection Page 19 */
#define RAMCFG_WPR1_P20WP_Pos               (20UL)
#define RAMCFG_WPR1_P20WP_Msk               (0x1UL << RAMCFG_WPR1_P20WP_Pos)          /*!< 0x00100000 */
#define RAMCFG_WPR1_P20WP                   RAMCFG_WPR1_P20WP_Msk                     /*!< Write Protection Page 20 */
#define RAMCFG_WPR1_P21WP_Pos               (21UL)
#define RAMCFG_WPR1_P21WP_Msk               (0x1UL << RAMCFG_WPR1_P21WP_Pos)          /*!< 0x00200000 */
#define RAMCFG_WPR1_P21WP                   RAMCFG_WPR1_P21WP_Msk                     /*!< Write Protection Page 21 */
#define RAMCFG_WPR1_P22WP_Pos               (22UL)
#define RAMCFG_WPR1_P22WP_Msk               (0x1UL << RAMCFG_WPR1_P22WP_Pos)          /*!< 0x00400000 */
#define RAMCFG_WPR1_P22WP                   RAMCFG_WPR1_P22WP_Msk                     /*!< Write Protection Page 22 */
#define RAMCFG_WPR1_P23WP_Pos               (23UL)
#define RAMCFG_WPR1_P23WP_Msk               (0x1UL << RAMCFG_WPR1_P23WP_Pos)          /*!< 0x00800000 */
#define RAMCFG_WPR1_P23WP                   RAMCFG_WPR1_P23WP_Msk                     /*!< Write Protection Page 23 */
#define RAMCFG_WPR1_P24WP_Pos               (24UL)
#define RAMCFG_WPR1_P24WP_Msk               (0x1UL << RAMCFG_WPR1_P24WP_Pos)          /*!< 0x01000000 */
#define RAMCFG_WPR1_P24WP                   RAMCFG_WPR1_P24WP_Msk                     /*!< Write Protection Page 24 */
#define RAMCFG_WPR1_P25WP_Pos               (25UL)
#define RAMCFG_WPR1_P25WP_Msk               (0x1UL << RAMCFG_WPR1_P25WP_Pos)          /*!< 0x02000000 */
#define RAMCFG_WPR1_P25WP                   RAMCFG_WPR1_P25WP_Msk                     /*!< Write Protection Page 25 */
#define RAMCFG_WPR1_P26WP_Pos               (26UL)
#define RAMCFG_WPR1_P26WP_Msk               (0x1UL << RAMCFG_WPR1_P26WP_Pos)          /*!< 0x04000000 */
#define RAMCFG_WPR1_P26WP                   RAMCFG_WPR1_P26WP_Msk                     /*!< Write Protection Page 26 */
#define RAMCFG_WPR1_P27WP_Pos               (27UL)
#define RAMCFG_WPR1_P27WP_Msk               (0x1UL << RAMCFG_WPR1_P27WP_Pos)          /*!< 0x08000000 */
#define RAMCFG_WPR1_P27WP                   RAMCFG_WPR1_P27WP_Msk                     /*!< Write Protection Page 27 */
#define RAMCFG_WPR1_P28WP_Pos               (28UL)
#define RAMCFG_WPR1_P28WP_Msk               (0x1UL << RAMCFG_WPR1_P28WP_Pos)          /*!< 0x10000000 */
#define RAMCFG_WPR1_P28WP                   RAMCFG_WPR1_P28WP_Msk                     /*!< Write Protection Page 28 */
#define RAMCFG_WPR1_P29WP_Pos               (29UL)
#define RAMCFG_WPR1_P29WP_Msk               (0x1UL << RAMCFG_WPR1_P29WP_Pos)          /*!< 0x20000000 */
#define RAMCFG_WPR1_P29WP                   RAMCFG_WPR1_P29WP_Msk                     /*!< Write Protection Page 29 */
#define RAMCFG_WPR1_P30WP_Pos               (30UL)
#define RAMCFG_WPR1_P30WP_Msk               (0x1UL << RAMCFG_WPR1_P30WP_Pos)          /*!< 0x40000000 */
#define RAMCFG_WPR1_P30WP                   RAMCFG_WPR1_P30WP_Msk                     /*!< Write Protection Page 30 */
#define RAMCFG_WPR1_P31WP_Pos               (31UL)
#define RAMCFG_WPR1_P31WP_Msk               (0x1UL << RAMCFG_WPR1_P31WP_Pos)          /*!< 0x80000000 */
#define RAMCFG_WPR1_P31WP                   RAMCFG_WPR1_P31WP_Msk                     /*!< Write Protection Page 31 */

/******************  Bit definition for RAMCFG_MxWPR2 register  ****************/
#define RAMCFG_WPR2_P32WP_Pos               (0UL)
#define RAMCFG_WPR2_P32WP_Msk               (0x1UL << RAMCFG_WPR2_P32WP_Pos)          /*!< 0x00000001 */
#define RAMCFG_WPR2_P32WP                   RAMCFG_WPR2_P32WP_Msk                     /*!< Write Protection Page 32 */
#define RAMCFG_WPR2_P33WP_Pos               (1UL)
#define RAMCFG_WPR2_P33WP_Msk               (0x1UL << RAMCFG_WPR2_P33WP_Pos)          /*!< 0x00000002 */
#define RAMCFG_WPR2_P33WP                   RAMCFG_WPR2_P33WP_Msk                     /*!< Write Protection Page 33 */
#define RAMCFG_WPR2_P34WP_Pos               (2UL)
#define RAMCFG_WPR2_P34WP_Msk               (0x1UL << RAMCFG_WPR2_P34WP_Pos)          /*!< 0x00000004 */
#define RAMCFG_WPR2_P34WP                   RAMCFG_WPR2_P34WP_Msk                     /*!< Write Protection Page 34 */
#define RAMCFG_WPR2_P35WP_Pos               (3UL)
#define RAMCFG_WPR2_P35WP_Msk               (0x1UL << RAMCFG_WPR2_P35WP_Pos)          /*!< 0x00000008 */
#define RAMCFG_WPR2_P35WP                   RAMCFG_WPR2_P35WP_Msk                     /*!< Write Protection Page 35 */
#define RAMCFG_WPR2_P36WP_Pos               (4UL)
#define RAMCFG_WPR2_P36WP_Msk               (0x1UL << RAMCFG_WPR2_P36WP_Pos)          /*!< 0x00000010 */
#define RAMCFG_WPR2_P36WP                   RAMCFG_WPR2_P36WP_Msk                     /*!< Write Protection Page 36 */
#define RAMCFG_WPR2_P37WP_Pos               (5UL)
#define RAMCFG_WPR2_P37WP_Msk               (0x1UL << RAMCFG_WPR2_P37WP_Pos)          /*!< 0x00000020 */
#define RAMCFG_WPR2_P37WP                   RAMCFG_WPR2_P37WP_Msk                     /*!< Write Protection Page 37 */
#define RAMCFG_WPR2_P38WP_Pos               (6UL)
#define RAMCFG_WPR2_P38WP_Msk               (0x1UL << RAMCFG_WPR2_P38WP_Pos)          /*!< 0x00000040 */
#define RAMCFG_WPR2_P38WP                   RAMCFG_WPR2_P38WP_Msk                     /*!< Write Protection Page 38 */
#define RAMCFG_WPR2_P39WP_Pos               (7UL)
#define RAMCFG_WPR2_P39WP_Msk               (0x1UL << RAMCFG_WPR2_P39WP_Pos)          /*!< 0x00000080 */
#define RAMCFG_WPR2_P39WP                   RAMCFG_WPR2_P39WP_Msk                     /*!< Write Protection Page 39 */
#define RAMCFG_WPR2_P40WP_Pos               (8UL)
#define RAMCFG_WPR2_P40WP_Msk               (0x1UL << RAMCFG_WPR2_P40WP_Pos)          /*!< 0x00000100 */
#define RAMCFG_WPR2_P40WP                   RAMCFG_WPR2_P40WP_Msk                     /*!< Write Protection Page 40 */
#define RAMCFG_WPR2_P41WP_Pos               (9UL)
#define RAMCFG_WPR2_P41WP_Msk               (0x1UL << RAMCFG_WPR2_P41WP_Pos)          /*!< 0x00000200 */
#define RAMCFG_WPR2_P41WP                   RAMCFG_WPR2_P41WP_Msk                     /*!< Write Protection Page 41 */
#define RAMCFG_WPR2_P42WP_Pos               (10UL)
#define RAMCFG_WPR2_P42WP_Msk               (0x1UL << RAMCFG_WPR2_P42WP_Pos)          /*!< 0x00000400 */
#define RAMCFG_WPR2_P42WP                   RAMCFG_WPR2_P42WP_Msk                     /*!< Write Protection Page 42 */
#define RAMCFG_WPR2_P43WP_Pos               (11UL)
#define RAMCFG_WPR2_P43WP_Msk               (0x1UL << RAMCFG_WPR2_P43WP_Pos)          /*!< 0x00000800 */
#define RAMCFG_WPR2_P43WP                   RAMCFG_WPR2_P43WP_Msk                     /*!< Write Protection Page 43 */
#define RAMCFG_WPR2_P44WP_Pos               (12UL)
#define RAMCFG_WPR2_P44WP_Msk               (0x1UL << RAMCFG_WPR2_P44WP_Pos)          /*!< 0x00001000 */
#define RAMCFG_WPR2_P44WP                   RAMCFG_WPR2_P44WP_Msk                     /*!< Write Protection Page 44 */
#define RAMCFG_WPR2_P45WP_Pos               (13UL)
#define RAMCFG_WPR2_P45WP_Msk               (0x1UL << RAMCFG_WPR2_P45WP_Pos)          /*!< 0x00002000 */
#define RAMCFG_WPR2_P45WP                   RAMCFG_WPR2_P45WP_Msk                     /*!< Write Protection Page 45 */
#define RAMCFG_WPR2_P46WP_Pos               (14UL)
#define RAMCFG_WPR2_P46WP_Msk               (0x1UL << RAMCFG_WPR2_P46WP_Pos)          /*!< 0x00004000 */
#define RAMCFG_WPR2_P46WP                   RAMCFG_WPR2_P46WP_Msk                     /*!< Write Protection Page 46 */
#define RAMCFG_WPR2_P47WP_Pos               (15UL)
#define RAMCFG_WPR2_P47WP_Msk               (0x1UL << RAMCFG_WPR2_P47WP_Pos)          /*!< 0x00008000 */
#define RAMCFG_WPR2_P47WP                   RAMCFG_WPR2_P47WP_Msk                     /*!< Write Protection Page 47 */
#define RAMCFG_WPR2_P48WP_Pos               (16UL)
#define RAMCFG_WPR2_P48WP_Msk               (0x1UL << RAMCFG_WPR2_P48WP_Pos)          /*!< 0x00010000 */
#define RAMCFG_WPR2_P48WP                   RAMCFG_WPR2_P48WP_Msk                     /*!< Write Protection Page 48 */
#define RAMCFG_WPR2_P49WP_Pos               (17UL)
#define RAMCFG_WPR2_P49WP_Msk               (0x1UL << RAMCFG_WPR2_P49WP_Pos)          /*!< 0x00020000 */
#define RAMCFG_WPR2_P49WP                   RAMCFG_WPR2_P49WP_Msk                     /*!< Write Protection Page 49 */
#define RAMCFG_WPR2_P50WP_Pos               (18UL)
#define RAMCFG_WPR2_P50WP_Msk               (0x1UL << RAMCFG_WPR2_P50WP_Pos)          /*!< 0x00040000 */
#define RAMCFG_WPR2_P50WP                   RAMCFG_WPR2_P50WP_Msk                     /*!< Write Protection Page 50 */
#define RAMCFG_WPR2_P51WP_Pos               (19UL)
#define RAMCFG_WPR2_P51WP_Msk               (0x1UL << RAMCFG_WPR2_P51WP_Pos)          /*!< 0x00080000 */
#define RAMCFG_WPR2_P51WP                   RAMCFG_WPR2_P51WP_Msk                     /*!< Write Protection Page 51 */
#define RAMCFG_WPR2_P52WP_Pos               (20UL)
#define RAMCFG_WPR2_P52WP_Msk               (0x1UL << RAMCFG_WPR2_P52WP_Pos)          /*!< 0x00100000 */
#define RAMCFG_WPR2_P52WP                   RAMCFG_WPR2_P52WP_Msk                     /*!< Write Protection Page 52 */
#define RAMCFG_WPR2_P53WP_Pos               (21UL)
#define RAMCFG_WPR2_P53WP_Msk               (0x1UL << RAMCFG_WPR2_P53WP_Pos)          /*!< 0x00200000 */
#define RAMCFG_WPR2_P53WP                   RAMCFG_WPR2_P53WP_Msk                     /*!< Write Protection Page 53 */
#define RAMCFG_WPR2_P54WP_Pos               (22UL)
#define RAMCFG_WPR2_P54WP_Msk               (0x1UL << RAMCFG_WPR2_P54WP_Pos)          /*!< 0x00400000 */
#define RAMCFG_WPR2_P54WP                   RAMCFG_WPR2_P54WP_Msk                     /*!< Write Protection Page 54 */
#define RAMCFG_WPR2_P55WP_Pos               (23UL)
#define RAMCFG_WPR2_P55WP_Msk               (0x1UL << RAMCFG_WPR2_P55WP_Pos)          /*!< 0x00800000 */
#define RAMCFG_WPR2_P55WP                   RAMCFG_WPR2_P55WP_Msk                     /*!< Write Protection Page 55 */
#define RAMCFG_WPR2_P56WP_Pos               (25UL)
#define RAMCFG_WPR2_P56WP_Msk               (0x1UL << RAMCFG_WPR2_P56WP_Pos)          /*!< 0x01000000 */
#define RAMCFG_WPR2_P56WP                   RAMCFG_WPR2_P56WP_Msk                     /*!< Write Protection Page 56 */
#define RAMCFG_WPR2_P57WP_Pos               (26UL)
#define RAMCFG_WPR2_P57WP_Msk               (0x1UL << RAMCFG_WPR2_P57WP_Pos)          /*!< 0x02000000 */
#define RAMCFG_WPR2_P57WP                   RAMCFG_WPR2_P57WP_Msk                     /*!< Write Protection Page 57 */
#define RAMCFG_WPR2_P58WP_Pos               (27UL)
#define RAMCFG_WPR2_P58WP_Msk               (0x1UL << RAMCFG_WPR2_P58WP_Pos)          /*!< 0x04000000 */
#define RAMCFG_WPR2_P58WP                   RAMCFG_WPR2_P58WP_Msk                     /*!< Write Protection Page 58 */
#define RAMCFG_WPR2_P59WP_Pos               (28UL)
#define RAMCFG_WPR2_P59WP_Msk               (0x1UL << RAMCFG_WPR2_P59WP_Pos)          /*!< 0x08000000 */
#define RAMCFG_WPR2_P59WP                   RAMCFG_WPR2_P59WP_Msk                     /*!< Write Protection Page 59 */
#define RAMCFG_WPR2_P60WP_Pos               (29UL)
#define RAMCFG_WPR2_P60WP_Msk               (0x1UL << RAMCFG_WPR2_P60WP_Pos)          /*!< 0x10000000 */
#define RAMCFG_WPR2_P60WP                   RAMCFG_WPR2_P60WP_Msk                     /*!< Write Protection Page 60 */
#define RAMCFG_WPR2_P61WP_Pos               (30UL)
#define RAMCFG_WPR2_P61WP_Msk               (0x1UL << RAMCFG_WPR2_P61WP_Pos)          /*!< 0x20000000 */
#define RAMCFG_WPR2_P61WP                   RAMCFG_WPR2_P61WP_Msk                     /*!< Write Protection Page 61 */
#define RAMCFG_WPR2_P62WP_Pos               (31UL)
#define RAMCFG_WPR2_P62WP_Msk               (0x1UL << RAMCFG_WPR2_P62WP_Pos)          /*!< 0x40000000 */
#define RAMCFG_WPR2_P62WP                   RAMCFG_WPR2_P62WP_Msk                     /*!< Write Protection Page 62 */
#define RAMCFG_WPR2_P63WP_Pos               (31UL)
#define RAMCFG_WPR2_P63WP_Msk               (0x1UL << RAMCFG_WPR2_P63WP_Pos)          /*!< 0x80000000 */
#define RAMCFG_WPR2_P63WP                   RAMCFG_WPR2_P63WP_Msk                     /*!< Write Protection Page 63 */

/*****************  Bit definition for RAMCFG_MxPARKEYR register  **************/
#define RAMCFG_PARKEYR_PARKEY_Pos           (0UL)
#define RAMCFG_PARKEYR_PARKEY_Msk           (0xFFUL << RAMCFG_PARKEYR_PARKEY_Pos)     /*!< 0x000000FF */
#define RAMCFG_PARKEYR_PARKEY               RAMCFG_PARKEYR_PARKEY_Msk                 /*!< Parity write protection key */

/*****************  Bit definition for RAMCFG_MxERKEYR register  ***************/
#define RAMCFG_ERKEYR_ERASEKEY_Pos          (0UL)
#define RAMCFG_ERKEYR_ERASEKEY_Msk          (0xFFUL << RAMCFG_ERKEYR_ERASEKEY_Pos)    /*!< 0x000000FF */
#define RAMCFG_ERKEYR_ERASEKEY              RAMCFG_ERKEYR_ERASEKEY_Msk                /*!< Erase write protection key */

/******************************************************************************/
/*                                                                            */
/*                         Reset and Clock Control                            */
/*                                                                            */
/******************************************************************************/
/********************  Bit definition for RCC_CR register  ********************/
#define RCC_CR_MSISON_Pos                   (0UL)
#define RCC_CR_MSISON_Msk                   (0x1UL << RCC_CR_MSISON_Pos)            /*!< 0x00000001 */
#define RCC_CR_MSISON                       RCC_CR_MSISON_Msk                       /*!< Internal Multi Speed Oscillator System (MSIS) Clock Enable */
#define RCC_CR_MSIKERON_Pos                 (1UL)
#define RCC_CR_MSIKERON_Msk                 (0x1UL << RCC_CR_MSIKERON_Pos)          /*!< 0x00000002 */
#define RCC_CR_MSIKERON                     RCC_CR_MSIKERON_Msk                     /*!< MSI Enable for some peripheral Kernels */
#define RCC_CR_MSISRDY_Pos                  (2UL)
#define RCC_CR_MSISRDY_Msk                  (0x1UL << RCC_CR_MSISRDY_Pos)           /*!< 0x00000004 */
#define RCC_CR_MSISRDY                      RCC_CR_MSISRDY_Msk                      /*!< Internal Multi Speed Oscillator System (MSIS) Clock Ready Flag */
#define RCC_CR_MSIKON_Pos                   (3UL)
#define RCC_CR_MSIKON_Msk                   (0x1UL << RCC_CR_MSIKON_Pos)            /*!< 0x00000008 */
#define RCC_CR_MSIKON                       RCC_CR_MSIKON_Msk                       /*!< Internal Multi Speed Oscillator Kernel (MSIK) Enable */
#define RCC_CR_MSIKRDY_Pos                  (4UL)
#define RCC_CR_MSIKRDY_Msk                  (0x1UL << RCC_CR_MSIKRDY_Pos)           /*!< 0x00000010 */
#define RCC_CR_MSIKRDY                      RCC_CR_MSIKRDY_Msk                      /*!< Internal Multi Speed Oscillator Kernel (MSIK) Ready Flag */
#define RCC_CR_MSIPLL1EN_Pos                (5UL)
#define RCC_CR_MSIPLL1EN_Msk                (0x1UL << RCC_CR_MSIPLL1EN_Pos)         /*!< 0x00000020 */
#define RCC_CR_MSIPLL1EN                     RCC_CR_MSIPLL1EN_Msk                   /*!< MSIRC1 PLL-mode enable */
#define RCC_CR_MSIPLL0EN_Pos                (6UL)
#define RCC_CR_MSIPLL0EN_Msk                (0x1UL << RCC_CR_MSIPLL0EN_Pos)         /*!< 0x00000040 */
#define RCC_CR_MSIPLL0EN                    RCC_CR_MSIPLL0EN_Msk                    /*!< MSIRC0 PLL-mode enable */
#define RCC_CR_MSIPLL1FAST_Pos              (7UL)
#define RCC_CR_MSIPLL1FAST_Msk              (0x1UL << RCC_CR_MSIPLL1FAST_Pos)       /*!< 0x00000080 */
#define RCC_CR_MSIPLL1FAST                  RCC_CR_MSIPLL1FAST_Msk                  /*!< MSIRC1 PLL-mode fast startup */
#define RCC_CR_MSIPLL0FAST_Pos              (8UL)
#define RCC_CR_MSIPLL0FAST_Msk              (0x1UL << RCC_CR_MSIPLL0FAST_Pos)       /*!< 0x00000100 */
#define RCC_CR_MSIPLL0FAST                  RCC_CR_MSIPLL0FAST_Msk                  /*!< MSIRC0 PLL-mode fast startup */
#define RCC_CR_MSIPLL1RDY_Pos               (9UL)
#define RCC_CR_MSIPLL1RDY_Msk               (0x1UL << RCC_CR_MSIPLL1RDY_Pos)        /*!< 0x00000200 */
#define RCC_CR_MSIPLL1RDY                   RCC_CR_MSIPLL1RDY_Msk                   /*!< MSIRC1 PLL-mode ready flag */
#define RCC_CR_MSIPLL0RDY_Pos               (10UL)
#define RCC_CR_MSIPLL0RDY_Msk               (0x1UL << RCC_CR_MSIPLL0RDY_Pos)        /*!< 0x00000400 */
#define RCC_CR_MSIPLL0RDY                   RCC_CR_MSIPLL0RDY_Msk                   /*!< MSIRC0 PLL-mode ready flag */
#define RCC_CR_HSION_Pos                    (11UL)
#define RCC_CR_HSION_Msk                    (0x1UL << RCC_CR_HSION_Pos)             /*!< 0x00000800 */
#define RCC_CR_HSION                        RCC_CR_HSION_Msk                        /*!< Internal High Speed Oscillator (HSI16) Clock Enable */
#define RCC_CR_HSIKERON_Pos                 (12UL)
#define RCC_CR_HSIKERON_Msk                 (0x1UL << RCC_CR_HSIKERON_Pos)          /*!< 0x00001000 */
#define RCC_CR_HSIKERON                     RCC_CR_HSIKERON_Msk                     /*!< Internal High Speed Oscillator (HSI16) Clock Enable for some peripheral Kernels */
#define RCC_CR_HSIRDY_Pos                   (13UL)
#define RCC_CR_HSIRDY_Msk                   (0x1UL << RCC_CR_HSIRDY_Pos)            /*!< 0x00002000 */
#define RCC_CR_HSIRDY                       RCC_CR_HSIRDY_Msk                       /*!< Internal High Speed Oscillator (HSI16) Clock Ready Flag */
#define RCC_CR_HSI48ON_Pos                  (14UL)
#define RCC_CR_HSI48ON_Msk                  (0x1UL << RCC_CR_HSI48ON_Pos)           /*!< 0x00004000 */
#define RCC_CR_HSI48ON                      RCC_CR_HSI48ON_Msk                      /*!< Internal High Speed Oscillator (HSI48) Clock Enable */
#define RCC_CR_HSI48RDY_Pos                 (15UL)
#define RCC_CR_HSI48RDY_Msk                 (0x1UL << RCC_CR_HSI48RDY_Pos)          /*!< 0x00008000 */
#define RCC_CR_HSI48RDY                     RCC_CR_HSI48RDY_Msk                     /*!< Internal High Speed Oscillator (HSI48) Clock Ready Flag */
#define RCC_CR_HSEON_Pos                    (16UL)
#define RCC_CR_HSEON_Msk                    (0x1UL << RCC_CR_HSEON_Pos)             /*!< 0x00010000 */
#define RCC_CR_HSEON                        RCC_CR_HSEON_Msk                        /*!< External High Speed Oscillator (HSE) Clock Enable */
#define RCC_CR_HSERDY_Pos                   (17UL)
#define RCC_CR_HSERDY_Msk                   (0x1UL << RCC_CR_HSERDY_Pos)            /*!< 0x00020000 */
#define RCC_CR_HSERDY                       RCC_CR_HSERDY_Msk                       /*!< External High Speed Oscillator (HSE) Clock Ready */
#define RCC_CR_HSEBYP_Pos                   (18UL)
#define RCC_CR_HSEBYP_Msk                   (0x1UL << RCC_CR_HSEBYP_Pos)            /*!< 0x00040000 */
#define RCC_CR_HSEBYP                       RCC_CR_HSEBYP_Msk                       /*!< External High Speed Oscillator (HSE) Crystal Oscillator Bypass */
#define RCC_CR_HSECSSON_Pos                 (19UL)
#define RCC_CR_HSECSSON_Msk                 (0x1UL << RCC_CR_HSECSSON_Pos)          /*!< 0x00080000 */
#define RCC_CR_HSECSSON                     RCC_CR_HSECSSON_Msk                     /*!< External High Speed Oscillator (HSE) Clock Security System Enable */
#define RCC_CR_HSEEXT_Pos                   (20UL)
#define RCC_CR_HSEEXT_Msk                   (0x1UL << RCC_CR_HSEEXT_Pos)            /*!< 0x00100000 */
#define RCC_CR_HSEEXT                       RCC_CR_HSEEXT_Msk                       /*!< External High Speed Oscillator (HSE) External Clock Bypass Mode */

/********************  Bit definition for RCC_ICSCR1 register  ***************/
#define RCC_ICSCR1_MSICAL1_Pos              (0UL)
#define RCC_ICSCR1_MSICAL1_Msk              (0x3FUL << RCC_ICSCR1_MSICAL1_Pos)      /*!< 0x0000003F */
#define RCC_ICSCR1_MSICAL1                  RCC_ICSCR1_MSICAL1_Msk                  /*!< MSICAL1[5:0] bits: MSIRC1 clock Calibration */
#define RCC_ICSCR1_MSICAL1_0                (0x01UL << RCC_ICSCR1_MSICAL1_Pos)      /*!< 0x00000001 */
#define RCC_ICSCR1_MSICAL1_1                (0x02UL << RCC_ICSCR1_MSICAL1_Pos)      /*!< 0x00000002 */
#define RCC_ICSCR1_MSICAL1_2                (0x04UL << RCC_ICSCR1_MSICAL1_Pos)      /*!< 0x00000004 */
#define RCC_ICSCR1_MSICAL1_3                (0x08UL << RCC_ICSCR1_MSICAL1_Pos)      /*!< 0x00000008 */
#define RCC_ICSCR1_MSICAL1_4                (0x10UL << RCC_ICSCR1_MSICAL1_Pos)      /*!< 0x00000010 */
#define RCC_ICSCR1_MSICAL1_5                (0x20UL << RCC_ICSCR1_MSICAL1_Pos)      /*!< 0x00000020 */
#define RCC_ICSCR1_MSICAL0_Pos              (6UL)
#define RCC_ICSCR1_MSICAL0_Msk              (0x3FUL << RCC_ICSCR1_MSICAL0_Pos)      /*!< 0x00000FC0 */
#define RCC_ICSCR1_MSICAL0                  RCC_ICSCR1_MSICAL0_Msk                  /*!< MSICAL0[5:0] bits: MSIRC0 clock Calibration */
#define RCC_ICSCR1_MSICAL0_0                (0x01UL << RCC_ICSCR1_MSICAL0_Pos)      /*!< 0x00000040 */
#define RCC_ICSCR1_MSICAL0_1                (0x02UL << RCC_ICSCR1_MSICAL0_Pos)      /*!< 0x00000080 */
#define RCC_ICSCR1_MSICAL0_2                (0x04UL << RCC_ICSCR1_MSICAL0_Pos)      /*!< 0x00000100 */
#define RCC_ICSCR1_MSICAL0_3                (0x08UL << RCC_ICSCR1_MSICAL0_Pos)      /*!< 0x00000200 */
#define RCC_ICSCR1_MSICAL0_4                (0x10UL << RCC_ICSCR1_MSICAL0_Pos)      /*!< 0x00000400 */
#define RCC_ICSCR1_MSICAL0_5                (0x20UL << RCC_ICSCR1_MSICAL0_Pos)      /*!< 0x00000800 */
#define RCC_ICSCR1_MSIHSINDIV_Pos           (19UL)
#define RCC_ICSCR1_MSIHSINDIV_Msk           (0x1UL << RCC_ICSCR1_MSIHSINDIV_Pos)    /*!< 0x00080000 */
#define RCC_ICSCR1_MSIHSINDIV               RCC_ICSCR1_MSIHSINDIV_Msk               /*!< MSIRCx PLL-mode HSE input fast clock Division */
#define RCC_ICSCR1_MSIPLL1SEL_Pos           (20UL)
#define RCC_ICSCR1_MSIPLL1SEL_Msk           (0x1UL << RCC_ICSCR1_MSIPLL1SEL_Pos)    /*!< 0x00100000 */
#define RCC_ICSCR1_MSIPLL1SEL               RCC_ICSCR1_MSIPLL1SEL_Msk               /*!< MSIRC1 PLL-mode input clock Selection */
#define RCC_ICSCR1_MSIPLL0SEL_Pos           (21UL)
#define RCC_ICSCR1_MSIPLL0SEL_Msk           (0x1UL << RCC_ICSCR1_MSIPLL0SEL_Pos)    /*!< 0x00200000 */
#define RCC_ICSCR1_MSIPLL0SEL               RCC_ICSCR1_MSIPLL0SEL_Msk               /*!< MSIRC0 PLL-mode input clock Selection */
#define RCC_ICSCR1_MSIBIAS_Pos              (22UL)
#define RCC_ICSCR1_MSIBIAS_Msk              (0x1UL << RCC_ICSCR1_MSIBIAS_Pos)       /*!< 0x00400000 */
#define RCC_ICSCR1_MSIBIAS                  RCC_ICSCR1_MSIBIAS_Msk                  /*!< MSI BIAS mode selection */
#define RCC_ICSCR1_MSIRGSEL_Pos             (23UL)
#define RCC_ICSCR1_MSIRGSEL_Msk             (0x1UL << RCC_ICSCR1_MSIRGSEL_Pos)      /*!< 0x00800000 */
#define RCC_ICSCR1_MSIRGSEL                 RCC_ICSCR1_MSIRGSEL_Msk                 /*!< MSI clock range selection */
#define RCC_ICSCR1_MSIPLL1N_Pos             (24UL)
#define RCC_ICSCR1_MSIPLL1N_Msk             (0x3UL << RCC_ICSCR1_MSIPLL1N_Pos)      /*!< 0x03000000 */
#define RCC_ICSCR1_MSIPLL1N                 RCC_ICSCR1_MSIPLL1N_Msk                 /*!< MSIPLL1N[1:0] bits: MSIRC1 frequency selection in PLL-mode */
#define RCC_ICSCR1_MSIPLL1N_0               (0x1UL << RCC_ICSCR1_MSIPLL1N_Pos)      /*!< 0x01000000 */
#define RCC_ICSCR1_MSIPLL1N_1               (0x2UL << RCC_ICSCR1_MSIPLL1N_Pos)      /*!< 0x02000000 */
#define RCC_ICSCR1_MSIKDIV_Pos              (26UL)
#define RCC_ICSCR1_MSIKDIV_Msk              (0x3UL << RCC_ICSCR1_MSIKDIV_Pos)       /*!< 0x0C000000 */
#define RCC_ICSCR1_MSIKDIV                  RCC_ICSCR1_MSIKDIV_Msk                  /*!< MSIK Oscillator division */
#define RCC_ICSCR1_MSIKDIV_0                (0x1UL << RCC_ICSCR1_MSIKDIV_Pos)       /*!< 0x04000000 */
#define RCC_ICSCR1_MSIKDIV_1                (0x2UL << RCC_ICSCR1_MSIKDIV_Pos)       /*!< 0x08000000 */
#define RCC_ICSCR1_MSIKSEL_Pos              (28UL)
#define RCC_ICSCR1_MSIKSEL_Msk              (0x1UL << RCC_ICSCR1_MSIKSEL_Pos)       /*!< 0x10000000 */
#define RCC_ICSCR1_MSIKSEL                  RCC_ICSCR1_MSIKSEL_Msk                  /*!< MSIK clock source selection */
#define RCC_ICSCR1_MSISDIV_Pos              (29UL)
#define RCC_ICSCR1_MSISDIV_Msk              (0x3UL << RCC_ICSCR1_MSISDIV_Pos)       /*!< 0x60000000 */
#define RCC_ICSCR1_MSISDIV                  RCC_ICSCR1_MSISDIV_Msk                  /*!< MSIS Oscillator division */
#define RCC_ICSCR1_MSISDIV_0                (0x1UL << RCC_ICSCR1_MSISDIV_Pos)       /*!< 0x20000000 */
#define RCC_ICSCR1_MSISDIV_1                (0x2UL << RCC_ICSCR1_MSISDIV_Pos)       /*!< 0x40000000 */
#define RCC_ICSCR1_MSISSEL_Pos              (31UL)
#define RCC_ICSCR1_MSISSEL_Msk              (0x1UL << RCC_ICSCR1_MSISSEL_Pos)       /*!< 0x80000000 */
#define RCC_ICSCR1_MSISSEL                  RCC_ICSCR1_MSISSEL_Msk                  /*!< MSIS clock source selection */

/********************  Bit definition for RCC_ICSCR2 register  ***************/
#define RCC_ICSCR2_MSITRIM1_Pos             (0UL)
#define RCC_ICSCR2_MSITRIM1_Msk             (0x3FUL << RCC_ICSCR2_MSITRIM1_Pos)     /*!< 0x0000003F */
#define RCC_ICSCR2_MSITRIM1                 RCC_ICSCR2_MSITRIM1_Msk                 /*!< MSITRIM1[5:0] bits: MSIRC1 clock trimming */
#define RCC_ICSCR2_MSITRIM1_0               (0x01UL << RCC_ICSCR2_MSITRIM1_Pos)     /*!< 0x00000001 */
#define RCC_ICSCR2_MSITRIM1_1               (0x02UL << RCC_ICSCR2_MSITRIM1_Pos)     /*!< 0x00000002 */
#define RCC_ICSCR2_MSITRIM1_2               (0x04UL << RCC_ICSCR2_MSITRIM1_Pos)     /*!< 0x00000004 */
#define RCC_ICSCR2_MSITRIM1_3               (0x08UL << RCC_ICSCR2_MSITRIM1_Pos)     /*!< 0x00000008 */
#define RCC_ICSCR2_MSITRIM1_4               (0x10UL << RCC_ICSCR2_MSITRIM1_Pos)     /*!< 0x00000010 */
#define RCC_ICSCR2_MSITRIM1_5               (0x20UL << RCC_ICSCR2_MSITRIM1_Pos)     /*!< 0x00000020 */
#define RCC_ICSCR2_MSITRIM0_Pos             (6UL)
#define RCC_ICSCR2_MSITRIM0_Msk             (0x3FUL << RCC_ICSCR2_MSITRIM0_Pos)     /*!< 0x00000FC0 */
#define RCC_ICSCR2_MSITRIM0                 RCC_ICSCR2_MSITRIM0_Msk                 /*!< MSITRIM0[5:0] bits: MSIRC0 clock trimming */
#define RCC_ICSCR2_MSITRIM0_0               (0x01UL << RCC_ICSCR2_MSITRIM0_Pos)     /*!< 0x00000040 */
#define RCC_ICSCR2_MSITRIM0_1               (0x02UL << RCC_ICSCR2_MSITRIM0_Pos)     /*!< 0x00000080 */
#define RCC_ICSCR2_MSITRIM0_2               (0x04UL << RCC_ICSCR2_MSITRIM0_Pos)     /*!< 0x00000100 */
#define RCC_ICSCR2_MSITRIM0_3               (0x08UL << RCC_ICSCR2_MSITRIM0_Pos)     /*!< 0x00000200 */
#define RCC_ICSCR2_MSITRIM0_4               (0x10UL << RCC_ICSCR2_MSITRIM0_Pos)     /*!< 0x00000400 */
#define RCC_ICSCR2_MSITRIM0_5               (0x20UL << RCC_ICSCR2_MSITRIM0_Pos)     /*!< 0x00000800 */

/********************  Bit definition for RCC_ICSCR3 register  ***************/
#define RCC_ICSCR3_HSICAL_Pos               (0UL)
#define RCC_ICSCR3_HSICAL_Msk               (0xFFFUL << RCC_ICSCR3_HSICAL_Pos)    /*!< 0x00000FFF */
#define RCC_ICSCR3_HSICAL                   RCC_ICSCR3_HSICAL_Msk                 /*!< HSICAL[11:0] bits: HSI clock calibration */
#define RCC_ICSCR3_HSICAL_0                 (0x001UL << RCC_ICSCR3_HSICAL_Pos)    /*!< 0x00000001 */
#define RCC_ICSCR3_HSICAL_1                 (0x002UL << RCC_ICSCR3_HSICAL_Pos)    /*!< 0x00000002 */
#define RCC_ICSCR3_HSICAL_2                 (0x004UL << RCC_ICSCR3_HSICAL_Pos)    /*!< 0x00000004 */
#define RCC_ICSCR3_HSICAL_3                 (0x008UL << RCC_ICSCR3_HSICAL_Pos)    /*!< 0x00000008 */
#define RCC_ICSCR3_HSICAL_4                 (0x010UL << RCC_ICSCR3_HSICAL_Pos)    /*!< 0x00000010 */
#define RCC_ICSCR3_HSICAL_5                 (0x020UL << RCC_ICSCR3_HSICAL_Pos)    /*!< 0x00000020 */
#define RCC_ICSCR3_HSICAL_6                 (0x040UL << RCC_ICSCR3_HSICAL_Pos)    /*!< 0x00000040 */
#define RCC_ICSCR3_HSICAL_7                 (0x080UL << RCC_ICSCR3_HSICAL_Pos)    /*!< 0x00000080 */
#define RCC_ICSCR3_HSICAL_8                 (0x100UL << RCC_ICSCR3_HSICAL_Pos)    /*!< 0x00000100 */
#define RCC_ICSCR3_HSICAL_9                 (0x200UL << RCC_ICSCR3_HSICAL_Pos)    /*!< 0x00000200 */
#define RCC_ICSCR3_HSICAL_10                (0x400UL << RCC_ICSCR3_HSICAL_Pos)    /*!< 0x00000400 */
#define RCC_ICSCR3_HSICAL_11                (0x800UL << RCC_ICSCR3_HSICAL_Pos)    /*!< 0x00000800 */
#define RCC_ICSCR3_HSITRIM_Pos              (16UL)
#define RCC_ICSCR3_HSITRIM_Msk              (0x1FUL << RCC_ICSCR3_HSITRIM_Pos)    /*!< 0x001F0000 */
#define RCC_ICSCR3_HSITRIM                  RCC_ICSCR3_HSITRIM_Msk                /*!< HSITRIM[4:0] bits: HSI clock trimming */
#define RCC_ICSCR3_HSITRIM_0                (0x01UL << RCC_ICSCR3_HSITRIM_Pos)    /*!< 0x00010000 */
#define RCC_ICSCR3_HSITRIM_1                (0x02UL << RCC_ICSCR3_HSITRIM_Pos)    /*!< 0x00020000 */
#define RCC_ICSCR3_HSITRIM_2                (0x04UL << RCC_ICSCR3_HSITRIM_Pos)    /*!< 0x00040000 */
#define RCC_ICSCR3_HSITRIM_3                (0x08UL << RCC_ICSCR3_HSITRIM_Pos)    /*!< 0x00080000 */
#define RCC_ICSCR3_HSITRIM_4                (0x10UL << RCC_ICSCR3_HSITRIM_Pos)    /*!< 0x00100000 */

/********************  Bit definition for RCC_CRRCR register  *****************/
#define RCC_CRRCR_HSI48CAL_Pos              (0UL)
#define RCC_CRRCR_HSI48CAL_Msk              (0x1FFUL << RCC_CRRCR_HSI48CAL_Pos)     /*!< 0x000001FF */
#define RCC_CRRCR_HSI48CAL                  RCC_CRRCR_HSI48CAL_Msk                  /*!< HSI48CAL[8:0] bits: HSI48 Clock Calibration */
#define RCC_CRRCR_HSI48CAL_0                (0x001UL << RCC_CRRCR_HSI48CAL_Pos)     /*!< 0x00000001 */
#define RCC_CRRCR_HSI48CAL_1                (0x002UL << RCC_CRRCR_HSI48CAL_Pos)     /*!< 0x00000002 */
#define RCC_CRRCR_HSI48CAL_2                (0x004UL << RCC_CRRCR_HSI48CAL_Pos)     /*!< 0x00000004 */
#define RCC_CRRCR_HSI48CAL_3                (0x008UL << RCC_CRRCR_HSI48CAL_Pos)     /*!< 0x00000008 */
#define RCC_CRRCR_HSI48CAL_4                (0x010UL << RCC_CRRCR_HSI48CAL_Pos)     /*!< 0x00000010 */
#define RCC_CRRCR_HSI48CAL_5                (0x020UL << RCC_CRRCR_HSI48CAL_Pos)     /*!< 0x00000020 */
#define RCC_CRRCR_HSI48CAL_6                (0x040UL << RCC_CRRCR_HSI48CAL_Pos)     /*!< 0x00000040 */
#define RCC_CRRCR_HSI48CAL_7                (0x080UL << RCC_CRRCR_HSI48CAL_Pos)     /*!< 0x00000080 */
#define RCC_CRRCR_HSI48CAL_8                (0x100UL << RCC_CRRCR_HSI48CAL_Pos)     /*!< 0x00000100 */

/********************  Bit definition for RCC_CFGR1 register  ******************/
#define RCC_CFGR1_SW_Pos                    (0UL)
#define RCC_CFGR1_SW_Msk                    (0x3UL << RCC_CFGR1_SW_Pos)             /*!< 0x00000003 */
#define RCC_CFGR1_SW                        RCC_CFGR1_SW_Msk                        /*!< SW[1:0] bits : System clock Switch */
#define RCC_CFGR1_SW_0                      (0x1UL << RCC_CFGR1_SW_Pos)             /*!< 0x00000001 */
#define RCC_CFGR1_SW_1                      (0x2UL << RCC_CFGR1_SW_Pos)             /*!< 0x00000002 */
#define RCC_CFGR1_SWS_Pos                   (2UL)
#define RCC_CFGR1_SWS_Msk                   (0x3UL << RCC_CFGR1_SWS_Pos)            /*!< 0x0000000C */
#define RCC_CFGR1_SWS                       RCC_CFGR1_SWS_Msk                       /*!< SWS[1:0] bits : System Clock Switch Status */
#define RCC_CFGR1_SWS_0                     (0x1UL << RCC_CFGR1_SWS_Pos)            /*!< 0x00000004 */
#define RCC_CFGR1_SWS_1                     (0x2UL << RCC_CFGR1_SWS_Pos)            /*!< 0x00000008 */
#define RCC_CFGR1_STOPWUCK_Pos              (4UL)
#define RCC_CFGR1_STOPWUCK_Msk              (0x1UL << RCC_CFGR1_STOPWUCK_Pos)       /*!< 0x00000010 */
#define RCC_CFGR1_STOPWUCK                  RCC_CFGR1_STOPWUCK_Msk                  /*!< Wake Up from stop and CSS backup clock selection */
#define RCC_CFGR1_STOPKERWUCK_Pos           (5UL)
#define RCC_CFGR1_STOPKERWUCK_Msk           (0x1UL << RCC_CFGR1_STOPKERWUCK_Pos)    /*!< 0x00000020 */
#define RCC_CFGR1_STOPKERWUCK               RCC_CFGR1_STOPKERWUCK_Msk               /*!< Wakeup from Stop kernel clock automatic enable selection */
#define RCC_CFGR1_MCO2SEL_Pos               (16UL)
#define RCC_CFGR1_MCO2SEL_Msk               (0xFUL << RCC_CFGR1_MCO2SEL_Pos)       /*!< 0x000F0000 */
#define RCC_CFGR1_MCO2SEL                   RCC_CFGR1_MCO2SEL_Msk                  /*!< MCO2SEL [3:0] bits : Microcontroller Clock Output 2 (MCO2) Selection */
#define RCC_CFGR1_MCO2SEL_0                 (0x1UL << RCC_CFGR1_MCO2SEL_Pos)       /*!< 0x00010000 */
#define RCC_CFGR1_MCO2SEL_1                 (0x2UL << RCC_CFGR1_MCO2SEL_Pos)       /*!< 0x00020000 */
#define RCC_CFGR1_MCO2SEL_2                 (0x4UL << RCC_CFGR1_MCO2SEL_Pos)       /*!< 0x00040000 */
#define RCC_CFGR1_MCO2SEL_3                 (0x8UL << RCC_CFGR1_MCO2SEL_Pos)       /*!< 0x00080000 */
#define RCC_CFGR1_MCO2PRE_Pos               (20UL)
#define RCC_CFGR1_MCO2PRE_Msk               (0x7UL << RCC_CFGR1_MCO2PRE_Pos)       /*!< 0x00700000 */
#define RCC_CFGR1_MCO2PRE                   RCC_CFGR1_MCO2PRE_Msk                  /*!< MCO2PRE [2:0] bits : Microcontroller Clock Output 2 (MCO2) Prescaler */
#define RCC_CFGR1_MCO2PRE_0                 (0x1UL << RCC_CFGR1_MCO2PRE_Pos)       /*!< 0x00100000 */
#define RCC_CFGR1_MCO2PRE_1                 (0x2UL << RCC_CFGR1_MCO2PRE_Pos)       /*!< 0x00200000 */
#define RCC_CFGR1_MCO2PRE_2                 (0x4UL << RCC_CFGR1_MCO2PRE_Pos)       /*!< 0x00400000 */
#define RCC_CFGR1_MCOSEL_Pos                (24UL)
#define RCC_CFGR1_MCOSEL_Msk                (0xFUL << RCC_CFGR1_MCOSEL_Pos)        /*!< 0x0F000000 */
#define RCC_CFGR1_MCOSEL                    RCC_CFGR1_MCOSEL_Msk                   /*!< MCOSEL [3:0] bits : Microcontroller Clock Output (MCO) Selection */
#define RCC_CFGR1_MCOSEL_0                  (0x1UL << RCC_CFGR1_MCOSEL_Pos)        /*!< 0x01000000 */
#define RCC_CFGR1_MCOSEL_1                  (0x2UL << RCC_CFGR1_MCOSEL_Pos)        /*!< 0x02000000 */
#define RCC_CFGR1_MCOSEL_2                  (0x4UL << RCC_CFGR1_MCOSEL_Pos)        /*!< 0x04000000 */
#define RCC_CFGR1_MCOSEL_3                  (0x8UL << RCC_CFGR1_MCOSEL_Pos)        /*!< 0x08000000 */
#define RCC_CFGR1_MCOPRE_Pos                (28UL)
#define RCC_CFGR1_MCOPRE_Msk                (0x7UL << RCC_CFGR1_MCOPRE_Pos)        /*!< 0x70000000 */
#define RCC_CFGR1_MCOPRE                    RCC_CFGR1_MCOPRE_Msk                   /*!< MCOPRE [2:0] bits : Microcontroller Clock Output (MCO) Prescaler */
#define RCC_CFGR1_MCOPRE_0                  (0x1UL << RCC_CFGR1_MCOPRE_Pos)        /*!< 0x10000000 */
#define RCC_CFGR1_MCOPRE_1                  (0x2UL << RCC_CFGR1_MCOPRE_Pos)        /*!< 0x20000000 */
#define RCC_CFGR1_MCOPRE_2                  (0x4UL << RCC_CFGR1_MCOPRE_Pos)        /*!< 0x40000000 */

/********************  Bit definition for RCC_CFGR2 register  ******************/
#define RCC_CFGR2_HPRE_Pos                  (0UL)
#define RCC_CFGR2_HPRE_Msk                  (0xFUL << RCC_CFGR2_HPRE_Pos)           /*!< 0x0000000F */
#define RCC_CFGR2_HPRE                      RCC_CFGR2_HPRE_Msk                      /*!< HPRE[3:0] bits : AHB prescaler */
#define RCC_CFGR2_HPRE_0                    (0x1UL << RCC_CFGR2_HPRE_Pos)           /*!< 0x00000001 */
#define RCC_CFGR2_HPRE_1                    (0x2UL << RCC_CFGR2_HPRE_Pos)           /*!< 0x00000002 */
#define RCC_CFGR2_HPRE_2                    (0x4UL << RCC_CFGR2_HPRE_Pos)           /*!< 0x00000004 */
#define RCC_CFGR2_HPRE_3                    (0x8UL << RCC_CFGR2_HPRE_Pos)           /*!< 0x00000008 */
#define RCC_CFGR2_PPRE1_Pos                 (4UL)
#define RCC_CFGR2_PPRE1_Msk                 (0x7UL << RCC_CFGR2_PPRE1_Pos)          /*!< 0x00000070 */
#define RCC_CFGR2_PPRE1                     RCC_CFGR2_PPRE1_Msk                     /*!< PPRE1[2:0] bits : APB1 prescaler */
#define RCC_CFGR2_PPRE1_0                   (0x1UL << RCC_CFGR2_PPRE1_Pos)          /*!< 0x00000010 */
#define RCC_CFGR2_PPRE1_1                   (0x2UL << RCC_CFGR2_PPRE1_Pos)          /*!< 0x00000020 */
#define RCC_CFGR2_PPRE1_2                   (0x4UL << RCC_CFGR2_PPRE1_Pos)          /*!< 0x00000040 */
#define RCC_CFGR2_PPRE2_Pos                 (8UL)
#define RCC_CFGR2_PPRE2_Msk                 (0x7UL << RCC_CFGR2_PPRE2_Pos)          /*!< 0x00000700 */
#define RCC_CFGR2_PPRE2                     RCC_CFGR2_PPRE2_Msk                     /*!< PPRE2[2:0] bits : APB2 prescaler */
#define RCC_CFGR2_PPRE2_0                   (0x1UL << RCC_CFGR2_PPRE2_Pos)          /*!< 0x00000100 */
#define RCC_CFGR2_PPRE2_1                   (0x2UL << RCC_CFGR2_PPRE2_Pos)          /*!< 0x00000200 */
#define RCC_CFGR2_PPRE2_2                   (0x4UL << RCC_CFGR2_PPRE2_Pos)          /*!< 0x00000400 */

/********************  Bit definition for RCC_CFGR3 register  ******************/
#define RCC_CFGR3_PPRE3_Pos                 (4UL)
#define RCC_CFGR3_PPRE3_Msk                 (0x7UL << RCC_CFGR3_PPRE3_Pos)          /*!< 0x00000070 */
#define RCC_CFGR3_PPRE3                     RCC_CFGR3_PPRE3_Msk                     /*!< PPRE3[2:0] bits : APB3 prescaler */
#define RCC_CFGR3_PPRE3_0                   (0x1UL << RCC_CFGR3_PPRE3_Pos)          /*!< 0x00000010 */
#define RCC_CFGR3_PPRE3_1                   (0x2UL << RCC_CFGR3_PPRE3_Pos)          /*!< 0x00000020 */
#define RCC_CFGR3_PPRE3_2                   (0x4UL << RCC_CFGR3_PPRE3_Pos)          /*!< 0x00000040 */

/********************  Bit definition for RCC_CFGR4 register  ******************/
#define RCC_CFGR4_BOOSTSEL_Pos              (0UL)
#define RCC_CFGR4_BOOSTSEL_Msk              (0x3UL << RCC_CFGR4_BOOSTSEL_Pos)       /*!< 0x00000003 */
#define RCC_CFGR4_BOOSTSEL                  RCC_CFGR4_BOOSTSEL_Msk                  /*!< BOOSTSEL[1:0] bits : EPOD booster input clock source selection */
#define RCC_CFGR4_BOOSTSEL_0                (0x1UL << RCC_CFGR4_BOOSTSEL_Pos)       /*!< 0x00000001 */
#define RCC_CFGR4_BOOSTSEL_1                (0x2UL << RCC_CFGR4_BOOSTSEL_Pos)       /*!< 0x00000002 */
#define RCC_CFGR4_BOOSTDIV_Pos              (12UL)
#define RCC_CFGR4_BOOSTDIV_Msk              (0xFUL << RCC_CFGR4_BOOSTDIV_Pos)       /*!< 0x0000F000 */
#define RCC_CFGR4_BOOSTDIV                  RCC_CFGR4_BOOSTDIV_Msk                  /*!< BOOSTDIV[3:0] bits : EPOD booster input clock prescaler */
#define RCC_CFGR4_BOOSTDIV_0                (0x1UL << RCC_CFGR4_BOOSTDIV_Pos)       /*!< 0x00001000 */
#define RCC_CFGR4_BOOSTDIV_1                (0x2UL << RCC_CFGR4_BOOSTDIV_Pos)       /*!< 0x00002000 */
#define RCC_CFGR4_BOOSTDIV_2                (0x4UL << RCC_CFGR4_BOOSTDIV_Pos)       /*!< 0x00004000 */
#define RCC_CFGR4_BOOSTDIV_3                (0x8UL << RCC_CFGR4_BOOSTDIV_Pos)       /*!< 0x00008000 */

/********************  Bit definition for RCC_CIER register  ******************/
#define RCC_CIER_LSIRDYIE_Pos               (0UL)
#define RCC_CIER_LSIRDYIE_Msk               (0x1UL << RCC_CIER_LSIRDYIE_Pos)        /*!< 0x00000001 */
#define RCC_CIER_LSIRDYIE                   RCC_CIER_LSIRDYIE_Msk                   /*!< LSI Ready Interrupt Enable */
#define RCC_CIER_LSERDYIE_Pos               (1UL)
#define RCC_CIER_LSERDYIE_Msk               (0x1UL << RCC_CIER_LSERDYIE_Pos)        /*!< 0x00000002 */
#define RCC_CIER_LSERDYIE                   RCC_CIER_LSERDYIE_Msk                   /*!< LSE Ready Interrupt Enable */
#define RCC_CIER_MSISRDYIE_Pos              (2UL)
#define RCC_CIER_MSISRDYIE_Msk              (0x1UL << RCC_CIER_MSISRDYIE_Pos)       /*!< 0x00000004 */
#define RCC_CIER_MSISRDYIE                  RCC_CIER_MSISRDYIE_Msk                  /*!< MSIS Ready Interrupt Enable */
#define RCC_CIER_HSIRDYIE_Pos               (3UL)
#define RCC_CIER_HSIRDYIE_Msk               (0x1UL << RCC_CIER_HSIRDYIE_Pos)        /*!< 0x00000008 */
#define RCC_CIER_HSIRDYIE                   RCC_CIER_HSIRDYIE_Msk                   /*!< HSI16 Ready Interrupt Enable */
#define RCC_CIER_HSERDYIE_Pos               (4UL)
#define RCC_CIER_HSERDYIE_Msk               (0x1UL << RCC_CIER_HSERDYIE_Pos)        /*!< 0x00000010 */
#define RCC_CIER_HSERDYIE                   RCC_CIER_HSERDYIE_Msk                   /*!< HSE Ready Interrupt Enable */
#define RCC_CIER_HSI48RDYIE_Pos             (5UL)
#define RCC_CIER_HSI48RDYIE_Msk             (0x1UL << RCC_CIER_HSI48RDYIE_Pos)      /*!< 0x00000020 */
#define RCC_CIER_HSI48RDYIE                 RCC_CIER_HSI48RDYIE_Msk                 /*!< HSI48 Ready Interrupt Enable */
#define RCC_CIER_MSIPLL1RDYIE_Pos           (6UL)
#define RCC_CIER_MSIPLL1RDYIE_Msk           (0x1UL << RCC_CIER_MSIPLL1RDYIE_Pos)    /*!< 0x00000040 */
#define RCC_CIER_MSIPLL1RDYIE               RCC_CIER_MSIPLL1RDYIE_Msk               /*!< MSIRC1 PLL-mode Ready Interrupt Enable */
#define RCC_CIER_MSIPLL0RDYIE_Pos           (7UL)
#define RCC_CIER_MSIPLL0RDYIE_Msk           (0x1UL << RCC_CIER_MSIPLL0RDYIE_Pos)    /*!< 0x00000080 */
#define RCC_CIER_MSIPLL0RDYIE               RCC_CIER_MSIPLL0RDYIE_Msk               /*!< MSIRC0 PLL-mode Ready Interrupt Enable */
#define RCC_CIER_MSIPLLUIE_Pos              (8UL)
#define RCC_CIER_MSIPLLUIE_Msk              (0x1UL << RCC_CIER_MSIPLLUIE_Pos)       /*!< 0x00000100 */
#define RCC_CIER_MSIPLLUIE                  RCC_CIER_MSIPLLUIE_Msk                  /*!< MSI PLL-mode with LSE unlock Interrupt Enable*/
#define RCC_CIER_MSIPLLHSUIE_Pos            (9UL)
#define RCC_CIER_MSIPLLHSUIE_Msk            (0x1UL << RCC_CIER_MSIPLLHSUIE_Pos)     /*!< 0x00000200 */
#define RCC_CIER_MSIPLLHSUIE                RCC_CIER_MSIPLLHSUIE_Msk                /*!< MSI PLL-mode with HSE unlock Interrupt Enable */
#define RCC_CIER_MSIKRDYIE_Pos              (11UL)
#define RCC_CIER_MSIKRDYIE_Msk              (0x1UL << RCC_CIER_MSIKRDYIE_Pos)       /*!< 0x00000800 */
#define RCC_CIER_MSIKRDYIE                  RCC_CIER_MSIKRDYIE_Msk                  /*!< MSIK Ready Interrupt Enable */
#define RCC_CIER_LSECSSIE_Pos               (12UL)
#define RCC_CIER_LSECSSIE_Msk               (0x1UL << RCC_CIER_LSECSSIE_Pos)        /*!< 0x00001000 */
#define RCC_CIER_LSECSSIE                   RCC_CIER_LSECSSIE_Msk                   /*!< LSE Clock Security System Interrupt Enable */

/********************  Bit definition for RCC_CIFR register  ******************/
#define RCC_CIFR_LSIRDYF_Pos                (0UL)
#define RCC_CIFR_LSIRDYF_Msk                (0x1UL << RCC_CIFR_LSIRDYF_Pos)        /*!< 0x00000001 */
#define RCC_CIFR_LSIRDYF                    RCC_CIFR_LSIRDYF_Msk                   /*!< LSI Ready Interrupt Flag*/
#define RCC_CIFR_LSERDYF_Pos                (1UL)
#define RCC_CIFR_LSERDYF_Msk                (0x1UL << RCC_CIFR_LSERDYF_Pos)        /*!< 0x00000002 */
#define RCC_CIFR_LSERDYF                    RCC_CIFR_LSERDYF_Msk                   /*!< LSF Ready Interrupt Flag*/
#define RCC_CIFR_MSISRDYF_Pos               (2UL)
#define RCC_CIFR_MSISRDYF_Msk               (0x1UL << RCC_CIFR_MSISRDYF_Pos)       /*!< 0x00000004 */
#define RCC_CIFR_MSISRDYF                   RCC_CIFR_MSISRDYF_Msk                  /*!< MSIS Ready Interrupt Flag*/
#define RCC_CIFR_HSIRDYF_Pos                (3UL)
#define RCC_CIFR_HSIRDYF_Msk                (0x1UL << RCC_CIFR_HSIRDYF_Pos)        /*!< 0x00000008 */
#define RCC_CIFR_HSIRDYF                    RCC_CIFR_HSIRDYF_Msk                   /*!< HSI16 Ready Interrupt Flag*/
#define RCC_CIFR_HSERDYF_Pos                (4UL)
#define RCC_CIFR_HSERDYF_Msk                (0x1UL << RCC_CIFR_HSERDYF_Pos)        /*!< 0x00000010 */
#define RCC_CIFR_HSERDYF                    RCC_CIFR_HSERDYF_Msk                   /*!< HSF Ready Interrupt Flag*/
#define RCC_CIFR_HSI48RDYF_Pos              (5UL)
#define RCC_CIFR_HSI48RDYF_Msk              (0x1UL << RCC_CIFR_HSI48RDYF_Pos)      /*!< 0x00000020 */
#define RCC_CIFR_HSI48RDYF                  RCC_CIFR_HSI48RDYF_Msk                 /*!< HSI48 Ready Interrupt Flag*/
#define RCC_CIFR_MSIPLL1RDYF_Pos            (6UL)
#define RCC_CIFR_MSIPLL1RDYF_Msk            (0x1UL << RCC_CIFR_MSIPLL1RDYF_Pos)    /*!< 0x00000040 */
#define RCC_CIFR_MSIPLL1RDYF                RCC_CIFR_MSIPLL1RDYF_Msk               /*!< MSIRC1 PLL-mode Ready Interrupt Flag*/
#define RCC_CIFR_MSIPLL0RDYF_Pos            (7UL)
#define RCC_CIFR_MSIPLL0RDYF_Msk            (0x1UL << RCC_CIFR_MSIPLL0RDYF_Pos)    /*!< 0x00000080 */
#define RCC_CIFR_MSIPLL0RDYF                RCC_CIFR_MSIPLL0RDYF_Msk               /*!< MSIRC0 PLL-mode Ready Interrupt Flag*/
#define RCC_CIFR_MSIPLLUF_Pos               (8UL)
#define RCC_CIFR_MSIPLLUF_Msk               (0x1UL << RCC_CIFR_MSIPLLUF_Pos)       /*!< 0x00000100 */
#define RCC_CIFR_MSIPLLUF                   RCC_CIFR_MSIPLLUF_Msk                  /*!< MSI PLL-mode with HSE unlock Interrupt Flag*/
#define RCC_CIFR_MSIPLLHSUF_Pos             (9UL)
#define RCC_CIFR_MSIPLLHSUF_Msk             (0x1UL << RCC_CIFR_MSIPLLHSUF_Pos)     /*!< 0x00000200 */
#define RCC_CIFR_MSIPLLHSUF                 RCC_CIFR_MSIPLLHSUF_Msk                /*!< MSI PLL-mode with LSE unlock Interrupt Flag*/
#define RCC_CIFR_CSSF_Pos                   (10UL)
#define RCC_CIFR_CSSF_Msk                   (0x1UL << RCC_CIFR_CSSF_Pos)           /*!< 0x00000400 */
#define RCC_CIFR_CSSF                       RCC_CIFR_CSSF_Msk                      /*!< HSE Clock Security System Interrupt flag */
#define RCC_CIFR_MSIKRDYF_Pos               (11UL)
#define RCC_CIFR_MSIKRDYF_Msk               (0x1UL << RCC_CIFR_MSIKRDYF_Pos)       /*!< 0x00000800 */
#define RCC_CIFR_MSIKRDYF                   RCC_CIFR_MSIKRDYF_Msk                  /*!< MSIK Ready Interrupt Flag*/
#define RCC_CIFR_LSECSSF_Pos                (12UL)
#define RCC_CIFR_LSECSSF_Msk                (0x1UL << RCC_CIFR_LSECSSF_Pos)        /*!< 0x00001000 */
#define RCC_CIFR_LSECSSF                    RCC_CIFR_LSECSSF_Msk                   /*!< LSF Clock Security System Interrupt Flag*/

/********************  Bit definition for RCC_CICR register  ******************/
#define RCC_CICR_LSIRDYC_Pos                (0UL)
#define RCC_CICR_LSIRDYC_Msk                (0x1UL << RCC_CICR_LSIRDYC_Pos)        /*!< 0x00000001 */
#define RCC_CICR_LSIRDYC                    RCC_CICR_LSIRDYC_Msk                   /*!< LSI Ready Interrupt Clear*/
#define RCC_CICR_LSERDYC_Pos                (1UL)
#define RCC_CICR_LSERDYC_Msk                (0x1UL << RCC_CICR_LSERDYC_Pos)        /*!< 0x00000002 */
#define RCC_CICR_LSERDYC                    RCC_CICR_LSERDYC_Msk                   /*!< LSC Ready Interrupt Clear*/
#define RCC_CICR_MSISRDYC_Pos               (2UL)
#define RCC_CICR_MSISRDYC_Msk               (0x1UL << RCC_CICR_MSISRDYC_Pos)       /*!< 0x00000004 */
#define RCC_CICR_MSISRDYC                   RCC_CICR_MSISRDYC_Msk                  /*!< MSIS Ready Interrupt Clear*/
#define RCC_CICR_HSIRDYC_Pos                (3UL)
#define RCC_CICR_HSIRDYC_Msk                (0x1UL << RCC_CICR_HSIRDYC_Pos)        /*!< 0x00000008 */
#define RCC_CICR_HSIRDYC                    RCC_CICR_HSIRDYC_Msk                   /*!< HSI16 Ready Interrupt Clear*/
#define RCC_CICR_HSERDYC_Pos                (4UL)
#define RCC_CICR_HSERDYC_Msk                (0x1UL << RCC_CICR_HSERDYC_Pos)        /*!< 0x00000010 */
#define RCC_CICR_HSERDYC                    RCC_CICR_HSERDYC_Msk                   /*!< HSC Ready Interrupt Clear*/
#define RCC_CICR_HSI48RDYC_Pos              (5UL)
#define RCC_CICR_HSI48RDYC_Msk              (0x1UL << RCC_CICR_HSI48RDYC_Pos)      /*!< 0x00000020 */
#define RCC_CICR_HSI48RDYC                  RCC_CICR_HSI48RDYC_Msk                 /*!< HSI48 Ready Interrupt Clear*/
#define RCC_CICR_MSIPLL1RDYC_Pos            (6UL)
#define RCC_CICR_MSIPLL1RDYC_Msk            (0x1UL << RCC_CICR_MSIPLL1RDYC_Pos)    /*!< 0x00000040 */
#define RCC_CICR_MSIPLL1RDYC                RCC_CICR_MSIPLL1RDYC_Msk               /*!< MSIRC1 PLL-mode Ready Interrupt Clear*/
#define RCC_CICR_MSIPLL0RDYC_Pos            (7UL)
#define RCC_CICR_MSIPLL0RDYC_Msk            (0x1UL << RCC_CICR_MSIPLL0RDYC_Pos)    /*!< 0x00000080 */
#define RCC_CICR_MSIPLL0RDYC                RCC_CICR_MSIPLL0RDYC_Msk               /*!< MSIRC0 PLL-mode Ready Interrupt Clear*/
#define RCC_CICR_MSIPLLUC_Pos               (8UL)
#define RCC_CICR_MSIPLLUC_Msk               (0x1UL << RCC_CICR_MSIPLLUC_Pos)       /*!< 0x00000100 */
#define RCC_CICR_MSIPLLUC                   RCC_CICR_MSIPLLUC_Msk                  /*!< MSI PLL-mode with HSE unlock Interrupt Clear*/
#define RCC_CICR_MSIPLLHSUC_Pos             (9UL)
#define RCC_CICR_MSIPLLHSUC_Msk             (0x1UL << RCC_CICR_MSIPLLHSUC_Pos)     /*!< 0x00000200 */
#define RCC_CICR_MSIPLLHSUC                 RCC_CICR_MSIPLLHSUC_Msk                /*!< MSI PLL-mode with LSE unlock Interrupt Clear*/
#define RCC_CICR_CSSC_Pos                   (10UL)
#define RCC_CICR_CSSC_Msk                   (0x1UL << RCC_CICR_CSSC_Pos)           /*!< 0x00000400 */
#define RCC_CICR_CSSC                       RCC_CICR_CSSC_Msk                      /*!< HSE Clock Security System Interrupt flag */
#define RCC_CICR_MSIKRDYC_Pos               (11UL)
#define RCC_CICR_MSIKRDYC_Msk               (0x1UL << RCC_CICR_MSIKRDYC_Pos)       /*!< 0x00000800 */
#define RCC_CICR_MSIKRDYC                   RCC_CICR_MSIKRDYC_Msk                  /*!< MSIK Ready Interrupt Clear*/
#define RCC_CICR_LSECSSC_Pos                (12UL)
#define RCC_CICR_LSECSSC_Msk                (0x1UL << RCC_CICR_LSECSSC_Pos)        /*!< 0x00001000 */
#define RCC_CICR_LSECSSC                    RCC_CICR_LSECSSC_Msk                   /*!< LSE Clock Security System Interrupt Clear*/

/********************  Bit definition for RCC_AHB1RSTR1 register  **************/
#define RCC_AHB1RSTR1_GPDMA1RST_Pos         (0UL)
#define RCC_AHB1RSTR1_GPDMA1RST_Msk         (0x1UL << RCC_AHB1RSTR1_GPDMA1RST_Pos)     /*!< 0x00000001 */
#define RCC_AHB1RSTR1_GPDMA1RST             RCC_AHB1RSTR1_GPDMA1RST_Msk                /*!< GPDMA1 Reset */
#define RCC_AHB1RSTR1_ADF1RST_Pos           (3UL)
#define RCC_AHB1RSTR1_ADF1RST_Msk           (0x1UL << RCC_AHB1RSTR1_ADF1RST_Pos)       /*!< 0x00000008 */
#define RCC_AHB1RSTR1_ADF1RST               RCC_AHB1RSTR1_ADF1RST_Msk                  /*!< ADF1 Reset */
#define RCC_AHB1RSTR1_CRCRST_Pos            (12UL)
#define RCC_AHB1RSTR1_CRCRST_Msk            (0x1UL << RCC_AHB1RSTR1_CRCRST_Pos)        /*!< 0x00001000 */
#define RCC_AHB1RSTR1_CRCRST                RCC_AHB1RSTR1_CRCRST_Msk                   /*!< CRC Reset */
#define RCC_AHB1RSTR1_TSCRST_Pos            (16UL)
#define RCC_AHB1RSTR1_TSCRST_Msk            (0x1UL << RCC_AHB1RSTR1_TSCRST_Pos)        /*!< 0x00010000 */
#define RCC_AHB1RSTR1_TSCRST                RCC_AHB1RSTR1_TSCRST_Msk                   /*!< TSC Reset */
#define RCC_AHB1RSTR1_RAMCFGRST_Pos         (17UL)
#define RCC_AHB1RSTR1_RAMCFGRST_Msk         (0x1UL << RCC_AHB1RSTR1_RAMCFGRST_Pos)     /*!< 0x00020000 */
#define RCC_AHB1RSTR1_RAMCFGRST             RCC_AHB1RSTR1_RAMCFGRST_Msk                /*!< RAMCFG Reset */

/********************  Bit definition for RCC_AHB2RSTR1 register  **************/
#define RCC_AHB2RSTR1_GPIOARST_Pos          (0UL)
#define RCC_AHB2RSTR1_GPIOARST_Msk          (0x1UL << RCC_AHB2RSTR1_GPIOARST_Pos)     /*!< 0x00000001 */
#define RCC_AHB2RSTR1_GPIOARST              RCC_AHB2RSTR1_GPIOARST_Msk                /*!< IO port A Reset */
#define RCC_AHB2RSTR1_GPIOBRST_Pos          (1UL)
#define RCC_AHB2RSTR1_GPIOBRST_Msk          (0x1UL << RCC_AHB2RSTR1_GPIOBRST_Pos)     /*!< 0x00000002 */
#define RCC_AHB2RSTR1_GPIOBRST              RCC_AHB2RSTR1_GPIOBRST_Msk                /*!< IO port B Reset */
#define RCC_AHB2RSTR1_GPIOCRST_Pos          (2UL)
#define RCC_AHB2RSTR1_GPIOCRST_Msk          (0x1UL << RCC_AHB2RSTR1_GPIOCRST_Pos)     /*!< 0x00000004 */
#define RCC_AHB2RSTR1_GPIOCRST              RCC_AHB2RSTR1_GPIOCRST_Msk                /*!< IO port C Reset */
#define RCC_AHB2RSTR1_GPIODRST_Pos          (3UL)
#define RCC_AHB2RSTR1_GPIODRST_Msk          (0x1UL << RCC_AHB2RSTR1_GPIODRST_Pos)     /*!< 0x00000008 */
#define RCC_AHB2RSTR1_GPIODRST              RCC_AHB2RSTR1_GPIODRST_Msk                /*!< IO port D Reset */
#define RCC_AHB2RSTR1_GPIOERST_Pos          (4UL)
#define RCC_AHB2RSTR1_GPIOERST_Msk          (0x1UL << RCC_AHB2RSTR1_GPIOERST_Pos)     /*!< 0x00000010 */
#define RCC_AHB2RSTR1_GPIOERST              RCC_AHB2RSTR1_GPIOERST_Msk                /*!< IO port E Reset */
#define RCC_AHB2RSTR1_GPIOGRST_Pos          (6UL)
#define RCC_AHB2RSTR1_GPIOGRST_Msk          (0x1UL << RCC_AHB2RSTR1_GPIOGRST_Pos)     /*!< 0x00000040 */
#define RCC_AHB2RSTR1_GPIOGRST              RCC_AHB2RSTR1_GPIOGRST_Msk                /*!< IO port G Reset */
#define RCC_AHB2RSTR1_GPIOHRST_Pos          (7UL)
#define RCC_AHB2RSTR1_GPIOHRST_Msk          (0x1UL << RCC_AHB2RSTR1_GPIOHRST_Pos)     /*!< 0x00000080 */
#define RCC_AHB2RSTR1_GPIOHRST              RCC_AHB2RSTR1_GPIOHRST_Msk                /*!< IO port H Reset */
#define RCC_AHB2RSTR1_ADC12RST_Pos          (10UL)
#define RCC_AHB2RSTR1_ADC12RST_Msk          (0x1UL << RCC_AHB2RSTR1_ADC12RST_Pos)     /*!< 0x00000400 */
#define RCC_AHB2RSTR1_ADC12RST              RCC_AHB2RSTR1_ADC12RST_Msk                /*!< ADC12 Reset */
#define RCC_AHB2RSTR1_DAC1RST_Pos           (11UL)
#define RCC_AHB2RSTR1_DAC1RST_Msk           (0x1UL << RCC_AHB2RSTR1_DAC1RST_Pos)      /*!< 0x00000800 */
#define RCC_AHB2RSTR1_DAC1RST               RCC_AHB2RSTR1_DAC1RST_Msk                 /*!< DAC1 Reset */
#define RCC_AHB2RSTR1_AESRST_Pos            (16UL)
#define RCC_AHB2RSTR1_AESRST_Msk            (0x1UL << RCC_AHB2RSTR1_AESRST_Pos)       /*!< 0x00010000 */
#define RCC_AHB2RSTR1_AESRST                RCC_AHB2RSTR1_AESRST_Msk                  /*!< AES Reset */
#define RCC_AHB2RSTR1_HASHRST_Pos           (17UL)
#define RCC_AHB2RSTR1_HASHRST_Msk           (0x1UL << RCC_AHB2RSTR1_HASHRST_Pos)      /*!< 0x00020000 */
#define RCC_AHB2RSTR1_HASHRST               RCC_AHB2RSTR1_HASHRST_Msk                 /*!< Hash Reset */
#define RCC_AHB2RSTR1_RNGRST_Pos            (18UL)
#define RCC_AHB2RSTR1_RNGRST_Msk            (0x1UL << RCC_AHB2RSTR1_RNGRST_Pos)       /*!< 0x00040000 */
#define RCC_AHB2RSTR1_RNGRST                RCC_AHB2RSTR1_RNGRST_Msk                  /*!< RNG Reset */
#define RCC_AHB2RSTR1_PKARST_Pos            (19UL)
#define RCC_AHB2RSTR1_PKARST_Msk            (0x1UL << RCC_AHB2RSTR1_PKARST_Pos)       /*!< 0x00080000 */
#define RCC_AHB2RSTR1_PKARST                RCC_AHB2RSTR1_PKARST_Msk                  /*!< PKA reset */
#define RCC_AHB2RSTR1_SAESRST_Pos           (20UL)
#define RCC_AHB2RSTR1_SAESRST_Msk           (0x1UL << RCC_AHB2RSTR1_SAESRST_Pos)      /*!< 0x00100000 */
#define RCC_AHB2RSTR1_SAESRST               RCC_AHB2RSTR1_SAESRST_Msk                 /*!< SAES Reset */
#define RCC_AHB2RSTR1_CCBRST_Pos            (21UL)
#define RCC_AHB2RSTR1_CCBRST_Msk            (0x1UL << RCC_AHB2RSTR1_CCBRST_Pos)       /*!< 0x00200000 */
#define RCC_AHB2RSTR1_CCBRST                RCC_AHB2RSTR1_CCBRST_Msk                  /*!< CCB Reset */
#define RCC_AHB2RSTR1_SDMMC1RST_Pos         (27UL)
#define RCC_AHB2RSTR1_SDMMC1RST_Msk         (0x1UL << RCC_AHB2RSTR1_SDMMC1RST_Pos)    /*!< 0x08000000 */
#define RCC_AHB2RSTR1_SDMMC1RST             RCC_AHB2RSTR1_SDMMC1RST_Msk               /*!< SDMMC1 Reset */

/********************  Bit definition for RCC_AHB2RSTR2 register  **************/
#define RCC_AHB2RSTR2_OCTOSPI1RST_Pos       (4UL)
#define RCC_AHB2RSTR2_OCTOSPI1RST_Msk       (0x1UL << RCC_AHB2RSTR2_OCTOSPI1RST_Pos)  /*!< 0x00000010 */
#define RCC_AHB2RSTR2_OCTOSPI1RST           RCC_AHB2RSTR2_OCTOSPI1RST_Msk             /*!< OCTOSPI1 Reset */

/********************  Bit definition for RCC_APB1RSTR1 register  **************/
#define RCC_APB1RSTR1_TIM2RST_Pos           (0UL)
#define RCC_APB1RSTR1_TIM2RST_Msk           (0x1UL << RCC_APB1RSTR1_TIM2RST_Pos)      /*!< 0x00000001 */
#define RCC_APB1RSTR1_TIM2RST               RCC_APB1RSTR1_TIM2RST_Msk                 /*!< TIM2 Reset */
#define RCC_APB1RSTR1_TIM3RST_Pos           (1UL)
#define RCC_APB1RSTR1_TIM3RST_Msk           (0x1UL << RCC_APB1RSTR1_TIM3RST_Pos)      /*!< 0x00000002 */
#define RCC_APB1RSTR1_TIM3RST               RCC_APB1RSTR1_TIM3RST_Msk                 /*!< TIM3 Reset */
#define RCC_APB1RSTR1_TIM4RST_Pos           (2UL)
#define RCC_APB1RSTR1_TIM4RST_Msk           (0x1UL << RCC_APB1RSTR1_TIM4RST_Pos)      /*!< 0x00000004 */
#define RCC_APB1RSTR1_TIM4RST               RCC_APB1RSTR1_TIM4RST_Msk                 /*!< TIM4 Reset */
#define RCC_APB1RSTR1_TIM6RST_Pos           (4UL)
#define RCC_APB1RSTR1_TIM6RST_Msk           (0x1UL << RCC_APB1RSTR1_TIM6RST_Pos)      /*!< 0x00000010 */
#define RCC_APB1RSTR1_TIM6RST               RCC_APB1RSTR1_TIM6RST_Msk                 /*!< TIM6 Reset */
#define RCC_APB1RSTR1_TIM7RST_Pos           (5UL)
#define RCC_APB1RSTR1_TIM7RST_Msk           (0x1UL << RCC_APB1RSTR1_TIM7RST_Pos)      /*!< 0x00000020 */
#define RCC_APB1RSTR1_TIM7RST               RCC_APB1RSTR1_TIM7RST_Msk                 /*!< TIM7 Reset */
#define RCC_APB1RSTR1_SPI3RST_Pos           (8UL)
#define RCC_APB1RSTR1_SPI3RST_Msk           (0x1UL << RCC_APB1RSTR1_SPI3RST_Pos)      /*!< 0x00000100 */
#define RCC_APB1RSTR1_SPI3RST               RCC_APB1RSTR1_SPI3RST_Msk                 /*!< SPI3 Reset */
#define RCC_APB1RSTR1_SPI2RST_Pos           (14UL)
#define RCC_APB1RSTR1_SPI2RST_Msk           (0x1UL << RCC_APB1RSTR1_SPI2RST_Pos)      /*!< 0x00004000 */
#define RCC_APB1RSTR1_SPI2RST               RCC_APB1RSTR1_SPI2RST_Msk                 /*!< SPI2 Reset */
#define RCC_APB1RSTR1_USART3RST_Pos         (18UL)
#define RCC_APB1RSTR1_USART3RST_Msk         (0x1UL << RCC_APB1RSTR1_USART3RST_Pos)    /*!< 0x00040000 */
#define RCC_APB1RSTR1_USART3RST             RCC_APB1RSTR1_USART3RST_Msk               /*!< USART3 Reset */
#define RCC_APB1RSTR1_UART4RST_Pos          (19UL)
#define RCC_APB1RSTR1_UART4RST_Msk          (0x1UL << RCC_APB1RSTR1_UART4RST_Pos)     /*!< 0x00080000 */
#define RCC_APB1RSTR1_UART4RST              RCC_APB1RSTR1_UART4RST_Msk                /*!< UART4 Reset */
#define RCC_APB1RSTR1_UART5RST_Pos          (20UL)
#define RCC_APB1RSTR1_UART5RST_Msk          (0x1UL << RCC_APB1RSTR1_UART5RST_Pos)     /*!< 0x00100000 */
#define RCC_APB1RSTR1_UART5RST              RCC_APB1RSTR1_UART5RST_Msk                /*!< UART5 Reset */
#define RCC_APB1RSTR1_I2C1RST_Pos           (21UL)
#define RCC_APB1RSTR1_I2C1RST_Msk           (0x1UL << RCC_APB1RSTR1_I2C1RST_Pos)      /*!< 0x00200000 */
#define RCC_APB1RSTR1_I2C1RST               RCC_APB1RSTR1_I2C1RST_Msk                 /*!< I2C1 Reset */
#define RCC_APB1RSTR1_I2C2RST_Pos           (22UL)
#define RCC_APB1RSTR1_I2C2RST_Msk           (0x1UL << RCC_APB1RSTR1_I2C2RST_Pos)      /*!< 0x00400000 */
#define RCC_APB1RSTR1_I2C2RST               RCC_APB1RSTR1_I2C2RST_Msk                 /*!< I2C2 Reset */
#define RCC_APB1RSTR1_I3C1RST_Pos           (23UL)
#define RCC_APB1RSTR1_I3C1RST_Msk           (0x1UL << RCC_APB1RSTR1_I3C1RST_Pos)      /*!< 0x00800000 */
#define RCC_APB1RSTR1_I3C1RST               RCC_APB1RSTR1_I3C1RST_Msk                 /*!< I3C1 Reset */
#define RCC_APB1RSTR1_CRSRST_Pos            (24UL)
#define RCC_APB1RSTR1_CRSRST_Msk            (0x1UL << RCC_APB1RSTR1_CRSRST_Pos)       /*!< 0x01000000 */
#define RCC_APB1RSTR1_CRSRST                RCC_APB1RSTR1_CRSRST_Msk                  /*!< CRS Reset */
#define RCC_APB1RSTR1_OPAMPRST_Pos          (28UL)
#define RCC_APB1RSTR1_OPAMPRST_Msk          (0x1UL << RCC_APB1RSTR1_OPAMPRST_Pos)     /*!< 0x10000000 */
#define RCC_APB1RSTR1_OPAMPRST              RCC_APB1RSTR1_OPAMPRST_Msk                /*!< OPAMP Reset */
#define RCC_APB1RSTR1_VREFRST_Pos           (29UL)
#define RCC_APB1RSTR1_VREFRST_Msk           (0x1UL << RCC_APB1RSTR1_VREFRST_Pos)      /*!< 0x20000000 */
#define RCC_APB1RSTR1_VREFRST               RCC_APB1RSTR1_VREFRST_Msk                 /*!< VREFBUF Reset */

/********************  Bit definition for RCC_APB1RSTR2 register  **************/
#define RCC_APB1RSTR2_LPTIM2RST_Pos         (5UL)
#define RCC_APB1RSTR2_LPTIM2RST_Msk         (0x1UL << RCC_APB1RSTR2_LPTIM2RST_Pos)    /*!< 0x00000020 */
#define RCC_APB1RSTR2_LPTIM2RST             RCC_APB1RSTR2_LPTIM2RST_Msk               /*!< LPTIM2 Reset */
#define RCC_APB1RSTR2_FDCANRST_Pos          (9UL)
#define RCC_APB1RSTR2_FDCANRST_Msk          (0x1UL << RCC_APB1RSTR2_FDCANRST_Pos)     /*!< 0x00000200 */
#define RCC_APB1RSTR2_FDCANRST              RCC_APB1RSTR2_FDCANRST_Msk                /*!< FDCAN1 Reset */
#define RCC_APB1RSTR2_FDCAN1RST_Pos         RCC_APB1RSTR2_FDCANRST_Pos
#define RCC_APB1RSTR2_FDCAN1RST_Msk         RCC_APB1RSTR2_FDCANRST_Msk
#define RCC_APB1RSTR2_FDCAN1RST             RCC_APB1RSTR2_FDCANRST

/********************  Bit definition for RCC_APB2RSTR register  **************/
#define RCC_APB2RSTR_TIM1RST_Pos            (11UL)
#define RCC_APB2RSTR_TIM1RST_Msk            (0x1UL << RCC_APB2RSTR_TIM1RST_Pos)       /*!< 0x00000800 */
#define RCC_APB2RSTR_TIM1RST                RCC_APB2RSTR_TIM1RST_Msk                  /*!< TIM1 Reset */
#define RCC_APB2RSTR_SPI1RST_Pos            (12UL)
#define RCC_APB2RSTR_SPI1RST_Msk            (0x1UL << RCC_APB2RSTR_SPI1RST_Pos)       /*!< 0x00001000 */
#define RCC_APB2RSTR_SPI1RST                RCC_APB2RSTR_SPI1RST_Msk                  /*!< SPI1 Reset */
#define RCC_APB2RSTR_USART1RST_Pos          (14UL)
#define RCC_APB2RSTR_USART1RST_Msk          (0x1UL << RCC_APB2RSTR_USART1RST_Pos)     /*!< 0x00004000 */
#define RCC_APB2RSTR_USART1RST              RCC_APB2RSTR_USART1RST_Msk                /*!< USART1 Reset */
#define RCC_APB2RSTR_TIM15RST_Pos           (16UL)
#define RCC_APB2RSTR_TIM15RST_Msk           (0x1UL << RCC_APB2RSTR_TIM15RST_Pos)      /*!< 0x00010000 */
#define RCC_APB2RSTR_TIM15RST               RCC_APB2RSTR_TIM15RST_Msk                 /*!< TIM15 Reset */
#define RCC_APB2RSTR_TIM16RST_Pos           (17UL)
#define RCC_APB2RSTR_TIM16RST_Msk           (0x1UL << RCC_APB2RSTR_TIM16RST_Pos)      /*!< 0x00020000 */
#define RCC_APB2RSTR_TIM16RST               RCC_APB2RSTR_TIM16RST_Msk                 /*!< TIM16 Reset */
#define RCC_APB2RSTR_TIM17RST_Pos           (18UL)
#define RCC_APB2RSTR_TIM17RST_Msk           (0x1UL << RCC_APB2RSTR_TIM17RST_Pos)      /*!< 0x00040000 */
#define RCC_APB2RSTR_TIM17RST               RCC_APB2RSTR_TIM17RST_Msk                 /*!< TIM17 Reset */
#define RCC_APB2RSTR_SAI1RST_Pos            (21UL)
#define RCC_APB2RSTR_SAI1RST_Msk            (0x1UL << RCC_APB2RSTR_SAI1RST_Pos)       /*!< 0x00200000 */
#define RCC_APB2RSTR_SAI1RST                RCC_APB2RSTR_SAI1RST_Msk                  /*!< SAI1 Reset */
#define RCC_APB2RSTR_USB1RST_Pos            (24UL)
#define RCC_APB2RSTR_USB1RST_Msk            (0x1UL << RCC_APB2RSTR_USB1RST_Pos)       /*!< 0x01000000 */
#define RCC_APB2RSTR_USB1RST                RCC_APB2RSTR_USB1RST_Msk                  /*!< USB1 Reset */
#define RCC_APB2RSTR_I3C2RST_Pos            (27UL)
#define RCC_APB2RSTR_I3C2RST_Msk            (0x1UL << RCC_APB2RSTR_I3C2RST_Pos)       /*!< 0x08000000 */
#define RCC_APB2RSTR_I3C2RST                RCC_APB2RSTR_I3C2RST_Msk                  /*!< I3C2 Reset */

/********************  Bit definition for RCC_APB3RSTR register  **************/
#define RCC_APB3RSTR_SYSCFGRST_Pos          (1UL)
#define RCC_APB3RSTR_SYSCFGRST_Msk          (0x1UL << RCC_APB3RSTR_SYSCFGRST_Pos)     /*!< 0x00000002 */
#define RCC_APB3RSTR_SYSCFGRST              RCC_APB3RSTR_SYSCFGRST_Msk                /*!< SYSCFG Reset */
#define RCC_APB3RSTR_LPUART1RST_Pos         (6UL)
#define RCC_APB3RSTR_LPUART1RST_Msk         (0x1UL << RCC_APB3RSTR_LPUART1RST_Pos)    /*!< 0x00000040 */
#define RCC_APB3RSTR_LPUART1RST             RCC_APB3RSTR_LPUART1RST_Msk               /*!< LPUART1 Reset */
#define RCC_APB3RSTR_I2C3RST_Pos            (7UL)
#define RCC_APB3RSTR_I2C3RST_Msk            (0x1UL << RCC_APB3RSTR_I2C3RST_Pos)       /*!< 0x00000080 */
#define RCC_APB3RSTR_I2C3RST                RCC_APB3RSTR_I2C3RST_Msk                  /*!< I2C3 Reset */
#define RCC_APB3RSTR_LPTIM1RST_Pos          (11UL)
#define RCC_APB3RSTR_LPTIM1RST_Msk          (0x1UL << RCC_APB3RSTR_LPTIM1RST_Pos)     /*!< 0x00000800 */
#define RCC_APB3RSTR_LPTIM1RST              RCC_APB3RSTR_LPTIM1RST_Msk                /*!< LPTIM1 Reset */
#define RCC_APB3RSTR_LPTIM3RST_Pos          (12UL)
#define RCC_APB3RSTR_LPTIM3RST_Msk          (0x1UL << RCC_APB3RSTR_LPTIM3RST_Pos)     /*!< 0x00001000 */
#define RCC_APB3RSTR_LPTIM3RST              RCC_APB3RSTR_LPTIM3RST_Msk                /*!< LPTIM3 Reset */
#define RCC_APB3RSTR_LPTIM4RST_Pos          (13UL)
#define RCC_APB3RSTR_LPTIM4RST_Msk          (0x1UL << RCC_APB3RSTR_LPTIM4RST_Pos)     /*!< 0x00002000 */
#define RCC_APB3RSTR_LPTIM4RST              RCC_APB3RSTR_LPTIM4RST_Msk                /*!< LPTIM4 Reset */
#define RCC_APB3RSTR_COMPRST_Pos            (15UL)
#define RCC_APB3RSTR_COMPRST_Msk            (0x1UL << RCC_APB3RSTR_COMPRST_Pos)       /*!< 0x00008000 */
#define RCC_APB3RSTR_COMPRST                RCC_APB3RSTR_COMPRST_Msk                  /*!< COMP Reset */

/********************  Bit definition for RCC_AHB1ENR register  **************/
#define RCC_AHB1ENR1_GPDMA1EN_Pos           (0UL)
#define RCC_AHB1ENR1_GPDMA1EN_Msk           (0x1UL << RCC_AHB1ENR1_GPDMA1EN_Pos)      /*!< 0x00000001 */
#define RCC_AHB1ENR1_GPDMA1EN               RCC_AHB1ENR1_GPDMA1EN_Msk                 /*!< GPDMA1 Enable */
#define RCC_AHB1ENR1_ADF1EN_Pos             (3UL)
#define RCC_AHB1ENR1_ADF1EN_Msk             (0x1UL << RCC_AHB1ENR1_ADF1EN_Pos)        /*!< 0x00000008 */
#define RCC_AHB1ENR1_ADF1EN                 RCC_AHB1ENR1_ADF1EN_Msk                   /*!< ADF1 Enable */
#define RCC_AHB1ENR1_FLASHEN_Pos            (8UL)
#define RCC_AHB1ENR1_FLASHEN_Msk            (0x1UL << RCC_AHB1ENR1_FLASHEN_Pos)       /*!< 0x00000100 */
#define RCC_AHB1ENR1_FLASHEN                RCC_AHB1ENR1_FLASHEN_Msk                  /*!< FLASH Enable */
#define RCC_AHB1ENR1_CRCEN_Pos              (12UL)
#define RCC_AHB1ENR1_CRCEN_Msk              (0x1UL << RCC_AHB1ENR1_CRCEN_Pos)         /*!< 0x00001000 */
#define RCC_AHB1ENR1_CRCEN                  RCC_AHB1ENR1_CRCEN_Msk                    /*!< CRC Enable */
#define RCC_AHB1ENR1_TSCEN_Pos              (16UL)
#define RCC_AHB1ENR1_TSCEN_Msk              (0x1UL << RCC_AHB1ENR1_TSCEN_Pos)         /*!< 0x00010000 */
#define RCC_AHB1ENR1_TSCEN                  RCC_AHB1ENR1_TSCEN_Msk                    /*!< TSC Enable */
#define RCC_AHB1ENR1_RAMCFGEN_Pos           (17UL)
#define RCC_AHB1ENR1_RAMCFGEN_Msk           (0x1UL << RCC_AHB1ENR1_RAMCFGEN_Pos)      /*!< 0x00020000 */
#define RCC_AHB1ENR1_RAMCFGEN               RCC_AHB1ENR1_RAMCFGEN_Msk                 /*!< RAMCFG Enable */
#define RCC_AHB1ENR1_GTZC1EN_Pos            (24UL)
#define RCC_AHB1ENR1_GTZC1EN_Msk            (0x1UL << RCC_AHB1ENR1_GTZC1EN_Pos)       /*!< 0x01000000 */
#define RCC_AHB1ENR1_GTZC1EN                RCC_AHB1ENR1_GTZC1EN_Msk                  /*!< GTZC1 Enable */
#define RCC_AHB1ENR1_SRAM1EN_Pos            (31UL)
#define RCC_AHB1ENR1_SRAM1EN_Msk            (0x1UL << RCC_AHB1ENR1_SRAM1EN_Pos)       /*!< 0x80000000 */
#define RCC_AHB1ENR1_SRAM1EN                RCC_AHB1ENR1_SRAM1EN_Msk                  /*!< SRAM1 Enable */

/********************  Bit definition for RCC_AHB2ENR1 register  **************/
#define RCC_AHB2ENR1_GPIOAEN_Pos            (0UL)
#define RCC_AHB2ENR1_GPIOAEN_Msk            (0x1UL << RCC_AHB2ENR1_GPIOAEN_Pos)       /*!< 0x00000001 */
#define RCC_AHB2ENR1_GPIOAEN                RCC_AHB2ENR1_GPIOAEN_Msk                  /*!< IO port A Enable */
#define RCC_AHB2ENR1_GPIOBEN_Pos            (1UL)
#define RCC_AHB2ENR1_GPIOBEN_Msk            (0x1UL << RCC_AHB2ENR1_GPIOBEN_Pos)       /*!< 0x00000002 */
#define RCC_AHB2ENR1_GPIOBEN                RCC_AHB2ENR1_GPIOBEN_Msk                  /*!< IO port B Enable */
#define RCC_AHB2ENR1_GPIOCEN_Pos            (2UL)
#define RCC_AHB2ENR1_GPIOCEN_Msk            (0x1UL << RCC_AHB2ENR1_GPIOCEN_Pos)       /*!< 0x00000004 */
#define RCC_AHB2ENR1_GPIOCEN                RCC_AHB2ENR1_GPIOCEN_Msk                  /*!< IO port C Enable */
#define RCC_AHB2ENR1_GPIODEN_Pos            (3UL)
#define RCC_AHB2ENR1_GPIODEN_Msk            (0x1UL << RCC_AHB2ENR1_GPIODEN_Pos)       /*!< 0x00000008 */
#define RCC_AHB2ENR1_GPIODEN                RCC_AHB2ENR1_GPIODEN_Msk                  /*!< IO port D Enable */
#define RCC_AHB2ENR1_GPIOEEN_Pos            (4UL)
#define RCC_AHB2ENR1_GPIOEEN_Msk            (0x1UL << RCC_AHB2ENR1_GPIOEEN_Pos)       /*!< 0x00000010 */
#define RCC_AHB2ENR1_GPIOEEN                RCC_AHB2ENR1_GPIOEEN_Msk                  /*!< IO port E Enable */
#define RCC_AHB2ENR1_GPIOGEN_Pos            (6UL)
#define RCC_AHB2ENR1_GPIOGEN_Msk            (0x1UL << RCC_AHB2ENR1_GPIOGEN_Pos)       /*!< 0x00000040 */
#define RCC_AHB2ENR1_GPIOGEN                RCC_AHB2ENR1_GPIOGEN_Msk                  /*!< IO port G Enable */
#define RCC_AHB2ENR1_GPIOHEN_Pos            (7UL)
#define RCC_AHB2ENR1_GPIOHEN_Msk            (0x1UL << RCC_AHB2ENR1_GPIOHEN_Pos)       /*!< 0x00000080 */
#define RCC_AHB2ENR1_GPIOHEN                RCC_AHB2ENR1_GPIOHEN_Msk                  /*!< IO port H Enable */
#define RCC_AHB2ENR1_ADC12EN_Pos            (10UL)
#define RCC_AHB2ENR1_ADC12EN_Msk            (0x1UL << RCC_AHB2ENR1_ADC12EN_Pos)       /*!< 0x00000400 */
#define RCC_AHB2ENR1_ADC12EN                RCC_AHB2ENR1_ADC12EN_Msk                  /*!< ADC12 Enable */
#define RCC_AHB2ENR1_DAC1EN_Pos             (11UL)
#define RCC_AHB2ENR1_DAC1EN_Msk             (0x1UL << RCC_AHB2ENR1_DAC1EN_Pos)        /*!< 0x00000800 */
#define RCC_AHB2ENR1_DAC1EN                 RCC_AHB2ENR1_DAC1EN_Msk                   /*!< DAC1 Enable */
#define RCC_AHB2ENR1_AESEN_Pos              (16UL)
#define RCC_AHB2ENR1_AESEN_Msk              (0x1UL << RCC_AHB2ENR1_AESEN_Pos)         /*!< 0x00010000 */
#define RCC_AHB2ENR1_AESEN                  RCC_AHB2ENR1_AESEN_Msk                    /*!< AES Enable */
#define RCC_AHB2ENR1_HASHEN_Pos             (17UL)
#define RCC_AHB2ENR1_HASHEN_Msk             (0x1UL << RCC_AHB2ENR1_HASHEN_Pos)        /*!< 0x00020000 */
#define RCC_AHB2ENR1_HASHEN                 RCC_AHB2ENR1_HASHEN_Msk                   /*!< HASH Enable */
#define RCC_AHB2ENR1_RNGEN_Pos              (18UL)
#define RCC_AHB2ENR1_RNGEN_Msk              (0x1UL << RCC_AHB2ENR1_RNGEN_Pos)         /*!< 0x00040000 */
#define RCC_AHB2ENR1_RNGEN                  RCC_AHB2ENR1_RNGEN_Msk                    /*!< RNG Enable */
#define RCC_AHB2ENR1_PKAEN_Pos              (19UL)
#define RCC_AHB2ENR1_PKAEN_Msk              (0x1UL << RCC_AHB2ENR1_PKAEN_Pos)         /*!< 0x00080000 */
#define RCC_AHB2ENR1_PKAEN                  RCC_AHB2ENR1_PKAEN_Msk                    /*!< PKA Enable */
#define RCC_AHB2ENR1_SAESEN_Pos             (20UL)
#define RCC_AHB2ENR1_SAESEN_Msk             (0x1UL << RCC_AHB2ENR1_SAESEN_Pos)        /*!< 0x00100000 */
#define RCC_AHB2ENR1_SAESEN                 RCC_AHB2ENR1_SAESEN_Msk                   /*!< SAES Enable */
#define RCC_AHB2ENR1_CCBEN_Pos              (21UL)
#define RCC_AHB2ENR1_CCBEN_Msk              (0x1UL << RCC_AHB2ENR1_CCBEN_Pos)         /*!< 0x00200000 */
#define RCC_AHB2ENR1_CCBEN                  RCC_AHB2ENR1_CCBEN_Msk                    /*!< CCB Enable */
#define RCC_AHB2ENR1_SDMMC1EN_Pos           (27UL)
#define RCC_AHB2ENR1_SDMMC1EN_Msk           (0x1UL << RCC_AHB2ENR1_SDMMC1EN_Pos)      /*!< 0x08000000 */
#define RCC_AHB2ENR1_SDMMC1EN               RCC_AHB2ENR1_SDMMC1EN_Msk                 /*!< SDMMC1 Enable */
#define RCC_AHB2ENR1_SRAM2EN_Pos            (30UL)
#define RCC_AHB2ENR1_SRAM2EN_Msk            (0x1UL << RCC_AHB2ENR1_SRAM2EN_Pos)       /*!< 0x40000000 */
#define RCC_AHB2ENR1_SRAM2EN                RCC_AHB2ENR1_SRAM2EN_Msk                  /*!< SRAM2 Enable */

/********************  Bit definition for RCC_AHB2ENR2 register  **************/
#define RCC_AHB2ENR2_OCTOSPI1EN_Pos         (4UL)
#define RCC_AHB2ENR2_OCTOSPI1EN_Msk         (0x1UL << RCC_AHB2ENR2_OCTOSPI1EN_Pos)    /*!< 0x00000010 */
#define RCC_AHB2ENR2_OCTOSPI1EN             RCC_AHB2ENR2_OCTOSPI1EN_Msk               /*!< OCTOSPI1 Enable */

/********************  Bit definition for RCC_AHB1ENR2 register  **************/
#define RCC_AHB1ENR2_PWREN_Pos              (2UL)
#define RCC_AHB1ENR2_PWREN_Msk              (0x1UL << RCC_AHB1ENR2_PWREN_Pos)         /*!< 0x00000004 */
#define RCC_AHB1ENR2_PWREN                  RCC_AHB1ENR2_PWREN_Msk                    /*!< PWR Enable */

/********************  Bit definition for RCC_APB1ENR1 register  **************/
#define RCC_APB1ENR1_TIM2EN_Pos             (0UL)
#define RCC_APB1ENR1_TIM2EN_Msk             (0x1UL << RCC_APB1ENR1_TIM2EN_Pos)        /*!< 0x00000001 */
#define RCC_APB1ENR1_TIM2EN                 RCC_APB1ENR1_TIM2EN_Msk                   /*!< TIM2 Enable */
#define RCC_APB1ENR1_TIM3EN_Pos             (1UL)
#define RCC_APB1ENR1_TIM3EN_Msk             (0x1UL << RCC_APB1ENR1_TIM3EN_Pos)        /*!< 0x00000002 */
#define RCC_APB1ENR1_TIM3EN                 RCC_APB1ENR1_TIM3EN_Msk                   /*!< TIM3 Enable */
#define RCC_APB1ENR1_TIM4EN_Pos             (2UL)
#define RCC_APB1ENR1_TIM4EN_Msk             (0x1UL << RCC_APB1ENR1_TIM4EN_Pos)        /*!< 0x00000004 */
#define RCC_APB1ENR1_TIM4EN                 RCC_APB1ENR1_TIM4EN_Msk                   /*!< TIM4 Enable */
#define RCC_APB1ENR1_TIM6EN_Pos             (4UL)
#define RCC_APB1ENR1_TIM6EN_Msk             (0x1UL << RCC_APB1ENR1_TIM6EN_Pos)        /*!< 0x00000010 */
#define RCC_APB1ENR1_TIM6EN                 RCC_APB1ENR1_TIM6EN_Msk                   /*!< TIM6 Enable */
#define RCC_APB1ENR1_TIM7EN_Pos             (5UL)
#define RCC_APB1ENR1_TIM7EN_Msk             (0x1UL << RCC_APB1ENR1_TIM7EN_Pos)        /*!< 0x00000020 */
#define RCC_APB1ENR1_TIM7EN                 RCC_APB1ENR1_TIM7EN_Msk                   /*!< TIM7 Enable */
#define RCC_APB1ENR1_SPI3EN_Pos             (8UL)
#define RCC_APB1ENR1_SPI3EN_Msk             (0x1UL << RCC_APB1ENR1_SPI3EN_Pos)        /*!< 0x00000100 */
#define RCC_APB1ENR1_SPI3EN                 RCC_APB1ENR1_SPI3EN_Msk                   /*!< SPI3 Enable */
#define RCC_APB1ENR1_WWDGEN_Pos             (11UL)
#define RCC_APB1ENR1_WWDGEN_Msk             (0x1UL << RCC_APB1ENR1_WWDGEN_Pos)        /*!< 0x00000800 */
#define RCC_APB1ENR1_WWDGEN                 RCC_APB1ENR1_WWDGEN_Msk                   /*!< WWDG Enable */
#define RCC_APB1ENR1_SPI2EN_Pos             (14UL)
#define RCC_APB1ENR1_SPI2EN_Msk             (0x1UL << RCC_APB1ENR1_SPI2EN_Pos)        /*!< 0x00004000 */
#define RCC_APB1ENR1_SPI2EN                 RCC_APB1ENR1_SPI2EN_Msk                   /*!< SPI2 Enable */
#define RCC_APB1ENR1_USART3EN_Pos           (18UL)
#define RCC_APB1ENR1_USART3EN_Msk           (0x1UL << RCC_APB1ENR1_USART3EN_Pos)      /*!< 0x00040000 */
#define RCC_APB1ENR1_USART3EN               RCC_APB1ENR1_USART3EN_Msk                 /*!< USART3 Enable */
#define RCC_APB1ENR1_UART4EN_Pos            (19UL)
#define RCC_APB1ENR1_UART4EN_Msk            (0x1UL << RCC_APB1ENR1_UART4EN_Pos)       /*!< 0x00080000 */
#define RCC_APB1ENR1_UART4EN                RCC_APB1ENR1_UART4EN_Msk                  /*!< UART4 Enable */
#define RCC_APB1ENR1_UART5EN_Pos            (20UL)
#define RCC_APB1ENR1_UART5EN_Msk            (0x1UL << RCC_APB1ENR1_UART5EN_Pos)       /*!< 0x00100000 */
#define RCC_APB1ENR1_UART5EN                RCC_APB1ENR1_UART5EN_Msk                  /*!< UART5 Enable */
#define RCC_APB1ENR1_I2C1EN_Pos             (21UL)
#define RCC_APB1ENR1_I2C1EN_Msk             (0x1UL << RCC_APB1ENR1_I2C1EN_Pos)        /*!< 0x00200000 */
#define RCC_APB1ENR1_I2C1EN                 RCC_APB1ENR1_I2C1EN_Msk                   /*!< I2C1 Enable */
#define RCC_APB1ENR1_I2C2EN_Pos             (22UL)
#define RCC_APB1ENR1_I2C2EN_Msk             (0x1UL << RCC_APB1ENR1_I2C2EN_Pos)        /*!< 0x00400000 */
#define RCC_APB1ENR1_I2C2EN                 RCC_APB1ENR1_I2C2EN_Msk                   /*!< I2C2 Enable */
#define RCC_APB1ENR1_I3C1EN_Pos             (23UL)
#define RCC_APB1ENR1_I3C1EN_Msk             (0x1UL << RCC_APB1ENR1_I3C1EN_Pos)        /*!< 0x00800000 */
#define RCC_APB1ENR1_I3C1EN                 RCC_APB1ENR1_I3C1EN_Msk                   /*!< I3C1 Enable */
#define RCC_APB1ENR1_CRSEN_Pos              (24UL)
#define RCC_APB1ENR1_CRSEN_Msk              (0x1UL << RCC_APB1ENR1_CRSEN_Pos)         /*!< 0x01000000 */
#define RCC_APB1ENR1_CRSEN                  RCC_APB1ENR1_CRSEN_Msk                    /*!< CRS Enable */
#define RCC_APB1ENR1_OPAMPEN_Pos            (28UL)
#define RCC_APB1ENR1_OPAMPEN_Msk            (0x1UL << RCC_APB1ENR1_OPAMPEN_Pos)       /*!< 0x100000000 */
#define RCC_APB1ENR1_OPAMPEN                RCC_APB1ENR1_OPAMPEN_Msk                  /*!< OPAMP Enable */
#define RCC_APB1ENR1_VREFEN_Pos             (29UL)
#define RCC_APB1ENR1_VREFEN_Msk             (0x1UL << RCC_APB1ENR1_VREFEN_Pos)        /*!< 0x200000000 */
#define RCC_APB1ENR1_VREFEN                 RCC_APB1ENR1_VREFEN_Msk                   /*!< VREFBUF Enable */
#define RCC_APB1ENR1_RTCAPBEN_Pos           (30UL)
#define RCC_APB1ENR1_RTCAPBEN_Msk           (0x1UL << RCC_APB1ENR1_RTCAPBEN_Pos)      /*!< 0x400000000 */
#define RCC_APB1ENR1_RTCAPBEN               RCC_APB1ENR1_RTCAPBEN_Msk                 /*!< RTCAPB Enable */

/********************  Bit definition for RCC_APB1ENR2 register  **************/
#define RCC_APB1ENR2_LPTIM2EN_Pos           (5UL)
#define RCC_APB1ENR2_LPTIM2EN_Msk           (0x1UL << RCC_APB1ENR2_LPTIM2EN_Pos)      /*!< 0x00000020 */
#define RCC_APB1ENR2_LPTIM2EN               RCC_APB1ENR2_LPTIM2EN_Msk                 /*!< LPTIM2 Enable */
#define RCC_APB1ENR2_FDCANEN_Pos            (9UL)
#define RCC_APB1ENR2_FDCANEN_Msk            (0x1UL << RCC_APB1ENR2_FDCANEN_Pos)      /*!< 0x00000200 */
#define RCC_APB1ENR2_FDCANEN                RCC_APB1ENR2_FDCANEN_Msk                 /*!< FDCAN1 Enable */
#define RCC_APB1ENR2_FDCAN1EN_Pos           RCC_APB1ENR2_FDCANEN_Pos
#define RCC_APB1ENR2_FDCAN1EN_Msk           RCC_APB1ENR2_FDCANEN_Msk
#define RCC_APB1ENR2_FDCAN1EN               RCC_APB1ENR2_FDCANEN

/********************  Bit definition for RCC_APB2ENR register  **************/
#define RCC_APB2ENR_TIM1EN_Pos              (11UL)
#define RCC_APB2ENR_TIM1EN_Msk              (0x1UL << RCC_APB2ENR_TIM1EN_Pos)         /*!< 0x00000800 */
#define RCC_APB2ENR_TIM1EN                  RCC_APB2ENR_TIM1EN_Msk                    /*!< TIM1 Enable */
#define RCC_APB2ENR_SPI1EN_Pos              (12UL)
#define RCC_APB2ENR_SPI1EN_Msk              (0x1UL << RCC_APB2ENR_SPI1EN_Pos)         /*!< 0x00001000 */
#define RCC_APB2ENR_SPI1EN                  RCC_APB2ENR_SPI1EN_Msk                    /*!< SPI1 Enable */
#define RCC_APB2ENR_USART1EN_Pos            (14UL)
#define RCC_APB2ENR_USART1EN_Msk            (0x1UL << RCC_APB2ENR_USART1EN_Pos)       /*!< 0x00004000 */
#define RCC_APB2ENR_USART1EN                RCC_APB2ENR_USART1EN_Msk                  /*!< USART1 Enable */
#define RCC_APB2ENR_TIM15EN_Pos             (16UL)
#define RCC_APB2ENR_TIM15EN_Msk             (0x1UL << RCC_APB2ENR_TIM15EN_Pos)        /*!< 0x00010000 */
#define RCC_APB2ENR_TIM15EN                 RCC_APB2ENR_TIM15EN_Msk                   /*!< TIM15 Enable */
#define RCC_APB2ENR_TIM16EN_Pos             (17UL)
#define RCC_APB2ENR_TIM16EN_Msk             (0x1UL << RCC_APB2ENR_TIM16EN_Pos)        /*!< 0x00020000 */
#define RCC_APB2ENR_TIM16EN                 RCC_APB2ENR_TIM16EN_Msk                   /*!< TIM16 Enable */
#define RCC_APB2ENR_TIM17EN_Pos             (18UL)
#define RCC_APB2ENR_TIM17EN_Msk             (0x1UL << RCC_APB2ENR_TIM17EN_Pos)        /*!< 0x00040000 */
#define RCC_APB2ENR_TIM17EN                 RCC_APB2ENR_TIM17EN_Msk                   /*!< TIM17 Enable */
#define RCC_APB2ENR_SAI1EN_Pos              (21UL)
#define RCC_APB2ENR_SAI1EN_Msk              (0x1UL << RCC_APB2ENR_SAI1EN_Pos)         /*!< 0x00200000 */
#define RCC_APB2ENR_SAI1EN                  RCC_APB2ENR_SAI1EN_Msk                    /*!< SAI1 Enable */
#define RCC_APB2ENR_USB1EN_Pos              (24UL)
#define RCC_APB2ENR_USB1EN_Msk              (0x1UL << RCC_APB2ENR_USB1EN_Pos)         /*!< 0x01000000 */
#define RCC_APB2ENR_USB1EN                  RCC_APB2ENR_USB1EN_Msk                    /*!< USB1 Enable */
#define RCC_APB2ENR_I3C2EN_Pos              (27UL)
#define RCC_APB2ENR_I3C2EN_Msk              (0x1UL << RCC_APB2ENR_I3C2EN_Pos)         /*!< 0x08000000 */
#define RCC_APB2ENR_I3C2EN                  RCC_APB2ENR_I3C2EN_Msk                    /*!< I3C2 Enable */

/********************  Bit definition for RCC_APB3ENR register  **************/
#define RCC_APB3ENR_SYSCFGEN_Pos            (1UL)
#define RCC_APB3ENR_SYSCFGEN_Msk            (0x1UL << RCC_APB3ENR_SYSCFGEN_Pos)       /*!< 0x00000002 */
#define RCC_APB3ENR_SYSCFGEN                RCC_APB3ENR_SYSCFGEN_Msk                  /*!< SYSCFG Enable */
#define RCC_APB3ENR_LPUART1EN_Pos           (6UL)
#define RCC_APB3ENR_LPUART1EN_Msk           (0x1UL << RCC_APB3ENR_LPUART1EN_Pos)      /*!< 0x00000040 */
#define RCC_APB3ENR_LPUART1EN               RCC_APB3ENR_LPUART1EN_Msk                 /*!< LPUART1 Enable */
#define RCC_APB3ENR_I2C3EN_Pos              (7UL)
#define RCC_APB3ENR_I2C3EN_Msk              (0x1UL << RCC_APB3ENR_I2C3EN_Pos)         /*!< 0x00000080 */
#define RCC_APB3ENR_I2C3EN                  RCC_APB3ENR_I2C3EN_Msk                    /*!< I2C3 Enable */
#define RCC_APB3ENR_LPTIM1EN_Pos            (11UL)
#define RCC_APB3ENR_LPTIM1EN_Msk            (0x1UL << RCC_APB3ENR_LPTIM1EN_Pos)       /*!< 0x00000800 */
#define RCC_APB3ENR_LPTIM1EN                RCC_APB3ENR_LPTIM1EN_Msk                  /*!< LPTIM1 Enable */
#define RCC_APB3ENR_LPTIM3EN_Pos            (12UL)
#define RCC_APB3ENR_LPTIM3EN_Msk            (0x1UL << RCC_APB3ENR_LPTIM3EN_Pos)       /*!< 0x00001000 */
#define RCC_APB3ENR_LPTIM3EN                RCC_APB3ENR_LPTIM3EN_Msk                  /*!< LPTIM3 Enable */
#define RCC_APB3ENR_LPTIM4EN_Pos            (13UL)
#define RCC_APB3ENR_LPTIM4EN_Msk            (0x1UL << RCC_APB3ENR_LPTIM4EN_Pos)       /*!< 0x00002000 */
#define RCC_APB3ENR_LPTIM4EN                RCC_APB3ENR_LPTIM4EN_Msk                  /*!< LPTIM4 Enable */
#define RCC_APB3ENR_COMPEN_Pos              (15UL)
#define RCC_APB3ENR_COMPEN_Msk              (0x1UL << RCC_APB3ENR_COMPEN_Pos)         /*!< 0x00008000 */
#define RCC_APB3ENR_COMPEN                  RCC_APB3ENR_COMPEN_Msk                    /*!< COMP Enable */

/********************  Bit definition for RCC_AHB1SLPENR register  **************/
#define RCC_AHB1SLPENR1_GPDMA1SLPEN_Pos     (0UL)
#define RCC_AHB1SLPENR1_GPDMA1SLPEN_Msk     (0x1UL << RCC_AHB1SLPENR1_GPDMA1SLPEN_Pos)     /*!< 0x00000001 */
#define RCC_AHB1SLPENR1_GPDMA1SLPEN         RCC_AHB1SLPENR1_GPDMA1SLPEN_Msk                /*!< GPDMA1 Sleep Mode Enable */
#define RCC_AHB1SLPENR1_ADF1SLPEN_Pos       (3UL)
#define RCC_AHB1SLPENR1_ADF1SLPEN_Msk       (0x1UL << RCC_AHB1SLPENR1_ADF1SLPEN_Pos)       /*!< 0x00000008 */
#define RCC_AHB1SLPENR1_ADF1SLPEN           RCC_AHB1SLPENR1_ADF1SLPEN_Msk                  /*!< ADF1 Sleep Mode Enable */
#define RCC_AHB1SLPENR1_FLASHSLPEN_Pos      (8UL)
#define RCC_AHB1SLPENR1_FLASHSLPEN_Msk      (0x1UL << RCC_AHB1SLPENR1_FLASHSLPEN_Pos)      /*!< 0x00000100 */
#define RCC_AHB1SLPENR1_FLASHSLPEN          RCC_AHB1SLPENR1_FLASHSLPEN_Msk                 /*!< FLASH Sleep Mode Enable */
#define RCC_AHB1SLPENR1_CRCSLPEN_Pos        (12UL)
#define RCC_AHB1SLPENR1_CRCSLPEN_Msk        (0x1UL << RCC_AHB1SLPENR1_CRCSLPEN_Pos)        /*!< 0x00001000 */
#define RCC_AHB1SLPENR1_CRCSLPEN            RCC_AHB1SLPENR1_CRCSLPEN_Msk                   /*!< CRC Sleep Mode Enable */
#define RCC_AHB1SLPENR1_TSCSLPEN_Pos        (16UL)
#define RCC_AHB1SLPENR1_TSCSLPEN_Msk        (0x1UL << RCC_AHB1SLPENR1_TSCSLPEN_Pos)        /*!< 0x00010000 */
#define RCC_AHB1SLPENR1_TSCSLPEN            RCC_AHB1SLPENR1_TSCSLPEN_Msk                   /*!< Touch SSLPENsing Controller Sleep Mode Enable */
#define RCC_AHB1SLPENR1_RAMCFGSLPEN_Pos     (17UL)
#define RCC_AHB1SLPENR1_RAMCFGSLPEN_Msk     (0x1UL << RCC_AHB1SLPENR1_RAMCFGSLPEN_Pos)     /*!< 0x00020000 */
#define RCC_AHB1SLPENR1_RAMCFGSLPEN         RCC_AHB1SLPENR1_RAMCFGSLPEN_Msk                /*!< RAMCFG Sleep Mode Enable */
#define RCC_AHB1SLPENR1_GTZC1SLPEN_Pos      (24UL)
#define RCC_AHB1SLPENR1_GTZC1SLPEN_Msk      (0x1UL << RCC_AHB1SLPENR1_GTZC1SLPEN_Pos)      /*!< 0x00100000 */
#define RCC_AHB1SLPENR1_GTZC1SLPEN          RCC_AHB1SLPENR1_GTZC1SLPEN_Msk                 /*!< GTZC1 Sleep Mode Enable */
#define RCC_AHB1SLPENR1_ICACHESLPEN_Pos     (29UL)
#define RCC_AHB1SLPENR1_ICACHESLPEN_Msk     (0x1UL << RCC_AHB1SLPENR1_ICACHESLPEN_Pos)     /*!< 0x20000000 */
#define RCC_AHB1SLPENR1_ICACHESLPEN         RCC_AHB1SLPENR1_ICACHESLPEN_Msk                /*!< ICACHE Sleep Mode Enable */
#define RCC_AHB1SLPENR1_SRAM1SLPEN_Pos      (31UL)
#define RCC_AHB1SLPENR1_SRAM1SLPEN_Msk      (0x1UL << RCC_AHB1SLPENR1_SRAM1SLPEN_Pos)      /*!< 0x80000000 */
#define RCC_AHB1SLPENR1_SRAM1SLPEN          RCC_AHB1SLPENR1_SRAM1SLPEN_Msk                 /*!< SRAM1 Sleep Mode Enable */

/********************  Bit definition for RCC_AHB2SLPENR1 register  **************/
#define RCC_AHB2SLPENR1_GPIOASLPEN_Pos      (0UL)
#define RCC_AHB2SLPENR1_GPIOASLPEN_Msk      (0x1UL << RCC_AHB2SLPENR1_GPIOASLPEN_Pos)     /*!< 0x00000001 */
#define RCC_AHB2SLPENR1_GPIOASLPEN          RCC_AHB2SLPENR1_GPIOASLPEN_Msk                /*!< IO port A Sleep Mode Enable */
#define RCC_AHB2SLPENR1_GPIOBSLPEN_Pos      (1UL)
#define RCC_AHB2SLPENR1_GPIOBSLPEN_Msk      (0x1UL << RCC_AHB2SLPENR1_GPIOBSLPEN_Pos)     /*!< 0x00000002 */
#define RCC_AHB2SLPENR1_GPIOBSLPEN          RCC_AHB2SLPENR1_GPIOBSLPEN_Msk                /*!< IO port B Sleep Mode Enable */
#define RCC_AHB2SLPENR1_GPIOCSLPEN_Pos      (2UL)
#define RCC_AHB2SLPENR1_GPIOCSLPEN_Msk      (0x1UL << RCC_AHB2SLPENR1_GPIOCSLPEN_Pos)     /*!< 0x00000004 */
#define RCC_AHB2SLPENR1_GPIOCSLPEN          RCC_AHB2SLPENR1_GPIOCSLPEN_Msk                /*!< IO port C Sleep Mode Enable */
#define RCC_AHB2SLPENR1_GPIODSLPEN_Pos      (3UL)
#define RCC_AHB2SLPENR1_GPIODSLPEN_Msk      (0x1UL << RCC_AHB2SLPENR1_GPIODSLPEN_Pos)     /*!< 0x00000008 */
#define RCC_AHB2SLPENR1_GPIODSLPEN          RCC_AHB2SLPENR1_GPIODSLPEN_Msk                /*!< IO port D Sleep Mode Enable */
#define RCC_AHB2SLPENR1_GPIOESLPEN_Pos      (4UL)
#define RCC_AHB2SLPENR1_GPIOESLPEN_Msk      (0x1UL << RCC_AHB2SLPENR1_GPIOESLPEN_Pos)     /*!< 0x00000010 */
#define RCC_AHB2SLPENR1_GPIOESLPEN          RCC_AHB2SLPENR1_GPIOESLPEN_Msk                /*!< IO port E Sleep Mode Enable */
#define RCC_AHB2SLPENR1_GPIOGSLPEN_Pos      (6UL)
#define RCC_AHB2SLPENR1_GPIOGSLPEN_Msk      (0x1UL << RCC_AHB2SLPENR1_GPIOGSLPEN_Pos)     /*!< 0x00000040 */
#define RCC_AHB2SLPENR1_GPIOGSLPEN          RCC_AHB2SLPENR1_GPIOGSLPEN_Msk                /*!< IO port G Sleep Mode Enable */
#define RCC_AHB2SLPENR1_GPIOHSLPEN_Pos      (7UL)
#define RCC_AHB2SLPENR1_GPIOHSLPEN_Msk      (0x1UL << RCC_AHB2SLPENR1_GPIOHSLPEN_Pos)     /*!< 0x00000080 */
#define RCC_AHB2SLPENR1_GPIOHSLPEN          RCC_AHB2SLPENR1_GPIOHSLPEN_Msk                /*!< IO port H Sleep Mode Enable */
#define RCC_AHB2SLPENR1_ADC12SLPEN_Pos      (10UL)
#define RCC_AHB2SLPENR1_ADC12SLPEN_Msk      (0x1UL << RCC_AHB2SLPENR1_ADC12SLPEN_Pos)     /*!< 0x00000400 */
#define RCC_AHB2SLPENR1_ADC12SLPEN          RCC_AHB2SLPENR1_ADC12SLPEN_Msk                /*!< ADC12 Sleep Mode Enable */
#define RCC_AHB2SLPENR1_DAC1SLPEN_Pos       (11UL)
#define RCC_AHB2SLPENR1_DAC1SLPEN_Msk       (0x1UL << RCC_AHB2SLPENR1_DAC1SLPEN_Pos)      /*!< 0x00000800 */
#define RCC_AHB2SLPENR1_DAC1SLPEN           RCC_AHB2SLPENR1_DAC1SLPEN_Msk                 /*!< DAC1 Sleep Mode Enable */
#define RCC_AHB2SLPENR1_AESSLPEN_Pos        (16UL)
#define RCC_AHB2SLPENR1_AESSLPEN_Msk        (0x1UL << RCC_AHB2SLPENR1_AESSLPEN_Pos)       /*!< 0x00010000 */
#define RCC_AHB2SLPENR1_AESSLPEN            RCC_AHB2SLPENR1_AESSLPEN_Msk                  /*!< AES Sleep Mode Enable */
#define RCC_AHB2SLPENR1_HASHSLPEN_Pos       (17UL)
#define RCC_AHB2SLPENR1_HASHSLPEN_Msk       (0x1UL << RCC_AHB2SLPENR1_HASHSLPEN_Pos)      /*!< 0x00020000 */
#define RCC_AHB2SLPENR1_HASHSLPEN           RCC_AHB2SLPENR1_HASHSLPEN_Msk                 /*!< HASH Sleep Mode Enable */
#define RCC_AHB2SLPENR1_RNGSLPEN_Pos        (18UL)
#define RCC_AHB2SLPENR1_RNGSLPEN_Msk        (0x1UL << RCC_AHB2SLPENR1_RNGSLPEN_Pos)       /*!< 0x00040000 */
#define RCC_AHB2SLPENR1_RNGSLPEN            RCC_AHB2SLPENR1_RNGSLPEN_Msk                  /*!< RNG Sleep Mode Enable */
#define RCC_AHB2SLPENR1_PKASLPEN_Pos        (19UL)
#define RCC_AHB2SLPENR1_PKASLPEN_Msk        (0x1UL << RCC_AHB2SLPENR1_PKASLPEN_Pos)       /*!< 0x00080000 */
#define RCC_AHB2SLPENR1_PKASLPEN            RCC_AHB2SLPENR1_PKASLPEN_Msk                  /*!< PKA Sleep Mode Enable */
#define RCC_AHB2SLPENR1_SAESSLPEN_Pos       (20UL)
#define RCC_AHB2SLPENR1_SAESSLPEN_Msk       (0x1UL << RCC_AHB2SLPENR1_SAESSLPEN_Pos)      /*!< 0x00100000 */
#define RCC_AHB2SLPENR1_SAESSLPEN           RCC_AHB2SLPENR1_SAESSLPEN_Msk                 /*!< SAES Sleep Mode Enable */
#define RCC_AHB2SLPENR1_CCBSLPEN_Pos        (21UL)
#define RCC_AHB2SLPENR1_CCBSLPEN_Msk        (0x1UL << RCC_AHB2SLPENR1_CCBSLPEN_Pos)       /*!< 0x00200000 */
#define RCC_AHB2SLPENR1_CCBSLPEN            RCC_AHB2SLPENR1_CCBSLPEN_Msk                  /*!< CCB Sleep Mode Enable */
#define RCC_AHB2SLPENR1_SDMMC1SLPEN_Pos     (27UL)
#define RCC_AHB2SLPENR1_SDMMC1SLPEN_Msk     (0x1UL << RCC_AHB2SLPENR1_SDMMC1SLPEN_Pos)    /*!< 0x08000000 */
#define RCC_AHB2SLPENR1_SDMMC1SLPEN         RCC_AHB2SLPENR1_SDMMC1SLPEN_Msk               /*!< SDMMC1 Sleep Mode Enable */
#define RCC_AHB2SLPENR1_SRAM2SLPEN_Pos      (30UL)
#define RCC_AHB2SLPENR1_SRAM2SLPEN_Msk      (0x1UL << RCC_AHB2SLPENR1_SRAM2SLPEN_Pos)     /*!< 0x40000000 */
#define RCC_AHB2SLPENR1_SRAM2SLPEN          RCC_AHB2SLPENR1_SRAM2SLPEN_Msk                /*!< SRAM2 Sleep Mode Enable */

/********************  Bit definition for RCC_AHB2SLPENR2 register  **************/
#define RCC_AHB2SLPENR2_OCTOSPI1SLPEN_Pos   (4UL)
#define RCC_AHB2SLPENR2_OCTOSPI1SLPEN_Msk   (0x1UL << RCC_AHB2SLPENR2_OCTOSPI1SLPEN_Pos)  /*!< 0x00000010 */
#define RCC_AHB2SLPENR2_OCTOSPI1SLPEN       RCC_AHB2SLPENR2_OCTOSPI1SLPEN_Msk             /*!< OCTOSPI1 Sleep Mode Enable */

/********************  Bit definition for RCC_AHB1SLPENR2 register  **************/
#define RCC_AHB1SLPENR2_PWRSLPEN_Pos        (2UL)
#define RCC_AHB1SLPENR2_PWRSLPEN_Msk        (0x1UL << RCC_AHB1SLPENR2_PWRSLPEN_Pos)       /*!< 0x00000004 */
#define RCC_AHB1SLPENR2_PWRSLPEN            RCC_AHB1SLPENR2_PWRSLPEN_Msk                  /*!< PWR Sleep Mode Enable */

/********************  Bit definition for RCC_APB1SLPENR1 register  **************/
#define RCC_APB1SLPENR1_TIM2SLPEN_Pos       (0UL)
#define RCC_APB1SLPENR1_TIM2SLPEN_Msk       (0x1UL << RCC_APB1SLPENR1_TIM2SLPEN_Pos)      /*!< 0x00000001 */
#define RCC_APB1SLPENR1_TIM2SLPEN           RCC_APB1SLPENR1_TIM2SLPEN_Msk                 /*!< TIM2 Sleep Mode Enable */
#define RCC_APB1SLPENR1_TIM3SLPEN_Pos       (1UL)
#define RCC_APB1SLPENR1_TIM3SLPEN_Msk       (0x1UL << RCC_APB1SLPENR1_TIM3SLPEN_Pos)      /*!< 0x00000002 */
#define RCC_APB1SLPENR1_TIM3SLPEN           RCC_APB1SLPENR1_TIM3SLPEN_Msk                 /*!< TIM3 Sleep Mode Enable */
#define RCC_APB1SLPENR1_TIM4SLPEN_Pos       (2UL)
#define RCC_APB1SLPENR1_TIM4SLPEN_Msk       (0x1UL << RCC_APB1SLPENR1_TIM4SLPEN_Pos)      /*!< 0x00000004 */
#define RCC_APB1SLPENR1_TIM4SLPEN           RCC_APB1SLPENR1_TIM4SLPEN_Msk                 /*!< TIM4 Sleep Mode Enable */
#define RCC_APB1SLPENR1_TIM6SLPEN_Pos       (4UL)
#define RCC_APB1SLPENR1_TIM6SLPEN_Msk       (0x1UL << RCC_APB1SLPENR1_TIM6SLPEN_Pos)      /*!< 0x00000010 */
#define RCC_APB1SLPENR1_TIM6SLPEN           RCC_APB1SLPENR1_TIM6SLPEN_Msk                 /*!< TIM6 Sleep Mode Enable */
#define RCC_APB1SLPENR1_TIM7SLPEN_Pos       (5UL)
#define RCC_APB1SLPENR1_TIM7SLPEN_Msk       (0x1UL << RCC_APB1SLPENR1_TIM7SLPEN_Pos)      /*!< 0x00000020 */
#define RCC_APB1SLPENR1_TIM7SLPEN           RCC_APB1SLPENR1_TIM7SLPEN_Msk                 /*!< TIM7 Sleep Mode Enable */
#define RCC_APB1SLPENR1_SPI3SLPEN_Pos       (8UL)
#define RCC_APB1SLPENR1_SPI3SLPEN_Msk       (0x1UL << RCC_APB1SLPENR1_SPI3SLPEN_Pos)      /*!< 0x00000100 */
#define RCC_APB1SLPENR1_SPI3SLPEN           RCC_APB1SLPENR1_SPI3SLPEN_Msk                 /*!< SPI3 Sleep Mode Enable */
#define RCC_APB1SLPENR1_WWDGSLPEN_Pos       (11UL)
#define RCC_APB1SLPENR1_WWDGSLPEN_Msk       (0x1UL << RCC_APB1SLPENR1_WWDGSLPEN_Pos)      /*!< 0x00000800 */
#define RCC_APB1SLPENR1_WWDGSLPEN           RCC_APB1SLPENR1_WWDGSLPEN_Msk                 /*!< WWDG Sleep Mode Enable */
#define RCC_APB1SLPENR1_SPI2SLPEN_Pos       (14UL)
#define RCC_APB1SLPENR1_SPI2SLPEN_Msk       (0x1UL << RCC_APB1SLPENR1_SPI2SLPEN_Pos)      /*!< 0x00004000 */
#define RCC_APB1SLPENR1_SPI2SLPEN           RCC_APB1SLPENR1_SPI2SLPEN_Msk                 /*!< SPI2 Sleep Mode Enable */
#define RCC_APB1SLPENR1_USART3SLPEN_Pos     (18UL)
#define RCC_APB1SLPENR1_USART3SLPEN_Msk     (0x1UL << RCC_APB1SLPENR1_USART3SLPEN_Pos)    /*!< 0x00040000 */
#define RCC_APB1SLPENR1_USART3SLPEN         RCC_APB1SLPENR1_USART3SLPEN_Msk               /*!< USART3 Sleep Mode Enable */
#define RCC_APB1SLPENR1_UART4SLPEN_Pos      (19UL)
#define RCC_APB1SLPENR1_UART4SLPEN_Msk      (0x1UL << RCC_APB1SLPENR1_UART4SLPEN_Pos)     /*!< 0x00080000 */
#define RCC_APB1SLPENR1_UART4SLPEN          RCC_APB1SLPENR1_UART4SLPEN_Msk                /*!< UART4 Sleep Mode Enable */
#define RCC_APB1SLPENR1_UART5SLPEN_Pos      (20UL)
#define RCC_APB1SLPENR1_UART5SLPEN_Msk      (0x1UL << RCC_APB1SLPENR1_UART5SLPEN_Pos)     /*!< 0x00100000 */
#define RCC_APB1SLPENR1_UART5SLPEN          RCC_APB1SLPENR1_UART5SLPEN_Msk                /*!< UART5 Sleep Mode Enable */
#define RCC_APB1SLPENR1_I2C1SLPEN_Pos       (21UL)
#define RCC_APB1SLPENR1_I2C1SLPEN_Msk       (0x1UL << RCC_APB1SLPENR1_I2C1SLPEN_Pos)      /*!< 0x00200000 */
#define RCC_APB1SLPENR1_I2C1SLPEN           RCC_APB1SLPENR1_I2C1SLPEN_Msk                 /*!< I2C1 Sleep Mode Enable */
#define RCC_APB1SLPENR1_I2C2SLPEN_Pos       (22UL)
#define RCC_APB1SLPENR1_I2C2SLPEN_Msk       (0x1UL << RCC_APB1SLPENR1_I2C2SLPEN_Pos)      /*!< 0x00400000 */
#define RCC_APB1SLPENR1_I2C2SLPEN           RCC_APB1SLPENR1_I2C2SLPEN_Msk                 /*!< I2C2 Sleep Mode Enable */
#define RCC_APB1SLPENR1_I3C1SLPEN_Pos       (23UL)
#define RCC_APB1SLPENR1_I3C1SLPEN_Msk       (0x1UL << RCC_APB1SLPENR1_I3C1SLPEN_Pos)      /*!< 0x00800000 */
#define RCC_APB1SLPENR1_I3C1SLPEN           RCC_APB1SLPENR1_I3C1SLPEN_Msk                 /*!< I3C1 Sleep Mode Enable  */
#define RCC_APB1SLPENR1_CRSSLPEN_Pos        (24UL)
#define RCC_APB1SLPENR1_CRSSLPEN_Msk        (0x1UL << RCC_APB1SLPENR1_CRSSLPEN_Pos)       /*!< 0x01000000 */
#define RCC_APB1SLPENR1_CRSSLPEN            RCC_APB1SLPENR1_CRSSLPEN_Msk                  /*!< CRS Sleep Mode Enable */
#define RCC_APB1SLPENR1_OPAMPSLPEN_Pos      (28UL)
#define RCC_APB1SLPENR1_OPAMPSLPEN_Msk      (0x1UL << RCC_APB1SLPENR1_OPAMPSLPEN_Pos)     /*!< 0x100000000 */
#define RCC_APB1SLPENR1_OPAMPSLPEN          RCC_APB1SLPENR1_OPAMPSLPEN_Msk                /*!< OPAMP Sleep Mode Enable */
#define RCC_APB1SLPENR1_VREFSLPEN_Pos       (29UL)
#define RCC_APB1SLPENR1_VREFSLPEN_Msk       (0x1UL << RCC_APB1SLPENR1_VREFSLPEN_Pos)      /*!< 0x200000000 */
#define RCC_APB1SLPENR1_VREFSLPEN           RCC_APB1SLPENR1_VREFSLPEN_Msk                 /*!< VREFBUF Sleep Mode Enable */
#define RCC_APB1SLPENR1_RTCAPBSLPEN_Pos     (30UL)
#define RCC_APB1SLPENR1_RTCAPBSLPEN_Msk     (0x1UL << RCC_APB1SLPENR1_RTCAPBSLPEN_Pos)    /*!< 0x400000000 */
#define RCC_APB1SLPENR1_RTCAPBSLPEN         RCC_APB1SLPENR1_RTCAPBSLPEN_Msk               /*!< RTCAPB Sleep Mode Enable */

/********************  Bit definition for RCC_APB1SLPENR2 register  **************/
#define RCC_APB1SLPENR2_LPTIM2SLPEN_Pos     (5UL)
#define RCC_APB1SLPENR2_LPTIM2SLPEN_Msk     (0x1UL << RCC_APB1SLPENR2_LPTIM2SLPEN_Pos)    /*!< 0x00000020 */
#define RCC_APB1SLPENR2_LPTIM2SLPEN         RCC_APB1SLPENR2_LPTIM2SLPEN_Msk               /*!< LPTIM2 Sleep Mode Enable */
#define RCC_APB1SLPENR2_FDCANSLPEN_Pos      (9UL)
#define RCC_APB1SLPENR2_FDCANSLPEN_Msk      (0x1UL << RCC_APB1SLPENR2_FDCANSLPEN_Pos)    /*!< 0x00000200 */
#define RCC_APB1SLPENR2_FDCANSLPEN          RCC_APB1SLPENR2_FDCANSLPEN_Msk               /*!< FDCAN1 Sleep Mode Enable */
#define RCC_APB1SLPENR2_FDCAN1SLPEN_Pos     RCC_APB1SLPENR2_FDCANSLPEN_Pos
#define RCC_APB1SLPENR2_FDCAN1SLPEN_Msk     RCC_APB1SLPENR2_FDCANSLPEN_Msk
#define RCC_APB1SLPENR2_FDCAN1SLPEN         RCC_APB1SLPENR2_FDCANSLPEN

/********************  Bit definition for RCC_APB2SLPENR register  **************/
#define RCC_APB2SLPENR_TIM1SLPEN_Pos        (11UL)
#define RCC_APB2SLPENR_TIM1SLPEN_Msk        (0x1UL << RCC_APB2SLPENR_TIM1SLPEN_Pos)       /*!< 0x00000800 */
#define RCC_APB2SLPENR_TIM1SLPEN            RCC_APB2SLPENR_TIM1SLPEN_Msk                  /*!< TIM1 Sleep Mode Enable */
#define RCC_APB2SLPENR_SPI1SLPEN_Pos        (12UL)
#define RCC_APB2SLPENR_SPI1SLPEN_Msk        (0x1UL << RCC_APB2SLPENR_SPI1SLPEN_Pos)       /*!< 0x00001000 */
#define RCC_APB2SLPENR_SPI1SLPEN            RCC_APB2SLPENR_SPI1SLPEN_Msk                  /*!< SPI1 Sleep Mode Enable */
#define RCC_APB2SLPENR_USART1SLPEN_Pos      (14UL)
#define RCC_APB2SLPENR_USART1SLPEN_Msk      (0x1UL << RCC_APB2SLPENR_USART1SLPEN_Pos)     /*!< 0x00004000 */
#define RCC_APB2SLPENR_USART1SLPEN          RCC_APB2SLPENR_USART1SLPEN_Msk                /*!< USART1 Sleep Mode Enable */
#define RCC_APB2SLPENR_TIM15SLPEN_Pos       (16UL)
#define RCC_APB2SLPENR_TIM15SLPEN_Msk       (0x1UL << RCC_APB2SLPENR_TIM15SLPEN_Pos)      /*!< 0x00010000 */
#define RCC_APB2SLPENR_TIM15SLPEN           RCC_APB2SLPENR_TIM15SLPEN_Msk                 /*!< TIM15 Sleep Mode Enable */
#define RCC_APB2SLPENR_TIM16SLPEN_Pos       (17UL)
#define RCC_APB2SLPENR_TIM16SLPEN_Msk       (0x1UL << RCC_APB2SLPENR_TIM16SLPEN_Pos)      /*!< 0x00020000 */
#define RCC_APB2SLPENR_TIM16SLPEN           RCC_APB2SLPENR_TIM16SLPEN_Msk                 /*!< TIM16 Sleep Mode Enable */
#define RCC_APB2SLPENR_TIM17SLPEN_Pos       (18UL)
#define RCC_APB2SLPENR_TIM17SLPEN_Msk       (0x1UL << RCC_APB2SLPENR_TIM17SLPEN_Pos)      /*!< 0x00040000 */
#define RCC_APB2SLPENR_TIM17SLPEN           RCC_APB2SLPENR_TIM17SLPEN_Msk                 /*!< TIM17 Sleep Mode Enable */
#define RCC_APB2SLPENR_SAI1SLPEN_Pos        (21UL)
#define RCC_APB2SLPENR_SAI1SLPEN_Msk        (0x1UL << RCC_APB2SLPENR_SAI1SLPEN_Pos)       /*!< 0x00200000 */
#define RCC_APB2SLPENR_SAI1SLPEN            RCC_APB2SLPENR_SAI1SLPEN_Msk                  /*!< SAI1 Sleep Mode Enable */
#define RCC_APB2SLPENR_USB1SLPEN_Pos        (24UL)
#define RCC_APB2SLPENR_USB1SLPEN_Msk        (0x1UL << RCC_APB2SLPENR_USB1SLPEN_Pos)       /*!< 0x01000000 */
#define RCC_APB2SLPENR_USB1SLPEN            RCC_APB2SLPENR_USB1SLPEN_Msk                  /*!< USB1 Sleep Mode Enable */
#define RCC_APB2SLPENR_I3C2SLPEN_Pos        (27UL)
#define RCC_APB2SLPENR_I3C2SLPEN_Msk        (0x1UL << RCC_APB2SLPENR_I3C2SLPEN_Pos)       /*!< 0x08000000 */
#define RCC_APB2SLPENR_I3C2SLPEN            RCC_APB2SLPENR_I3C2SLPEN_Msk                  /*!< I3C2 Sleep Mode Enable */

/********************  Bit definition for RCC_APB3SLPENR register  **************/
#define RCC_APB3SLPENR_SYSCFGSLPEN_Pos      (1UL)
#define RCC_APB3SLPENR_SYSCFGSLPEN_Msk      (0x1UL << RCC_APB3SLPENR_SYSCFGSLPEN_Pos)     /*!< 0x00000002 */
#define RCC_APB3SLPENR_SYSCFGSLPEN          RCC_APB3SLPENR_SYSCFGSLPEN_Msk                /*!< SYSCFG Sleep Mode Enable */
#define RCC_APB3SLPENR_LPUART1SLPEN_Pos     (6UL)
#define RCC_APB3SLPENR_LPUART1SLPEN_Msk     (0x1UL << RCC_APB3SLPENR_LPUART1SLPEN_Pos)    /*!< 0x00000040 */
#define RCC_APB3SLPENR_LPUART1SLPEN         RCC_APB3SLPENR_LPUART1SLPEN_Msk               /*!< LPUART1 Sleep Mode Enable */
#define RCC_APB3SLPENR_I2C3SLPEN_Pos        (7UL)
#define RCC_APB3SLPENR_I2C3SLPEN_Msk        (0x1UL << RCC_APB3SLPENR_I2C3SLPEN_Pos)       /*!< 0x00000080 */
#define RCC_APB3SLPENR_I2C3SLPEN            RCC_APB3SLPENR_I2C3SLPEN_Msk                  /*!< I2C3 Sleep Mode Enable */
#define RCC_APB3SLPENR_LPTIM1SLPEN_Pos      (11UL)
#define RCC_APB3SLPENR_LPTIM1SLPEN_Msk      (0x1UL << RCC_APB3SLPENR_LPTIM1SLPEN_Pos)     /*!< 0x00000800 */
#define RCC_APB3SLPENR_LPTIM1SLPEN          RCC_APB3SLPENR_LPTIM1SLPEN_Msk                /*!< LPTIM1 Sleep Mode Enable */
#define RCC_APB3SLPENR_LPTIM3SLPEN_Pos      (12UL)
#define RCC_APB3SLPENR_LPTIM3SLPEN_Msk      (0x1UL << RCC_APB3SLPENR_LPTIM3SLPEN_Pos)     /*!< 0x00001000 */
#define RCC_APB3SLPENR_LPTIM3SLPEN          RCC_APB3SLPENR_LPTIM3SLPEN_Msk                /*!< LPTIM3 Sleep Mode Enable */
#define RCC_APB3SLPENR_LPTIM4SLPEN_Pos      (13UL)
#define RCC_APB3SLPENR_LPTIM4SLPEN_Msk      (0x1UL << RCC_APB3SLPENR_LPTIM4SLPEN_Pos)     /*!< 0x00002000 */
#define RCC_APB3SLPENR_LPTIM4SLPEN          RCC_APB3SLPENR_LPTIM4SLPEN_Msk                /*!< LPTIM4 Sleep Mode Enable */
#define RCC_APB3SLPENR_COMPSLPEN_Pos        (15UL)
#define RCC_APB3SLPENR_COMPSLPEN_Msk        (0x1UL << RCC_APB3SLPENR_COMPSLPEN_Pos)       /*!< 0x00008000 */
#define RCC_APB3SLPENR_COMPSLPEN            RCC_APB3SLPENR_COMPSLPEN_Msk                  /*!< COMP Sleep Mode Enable */

/********************  Bit definition for RCC_AHB1STPENR register  **************/
#define RCC_AHB1STPENR1_GPDMA1STPEN_Pos     (0UL)
#define RCC_AHB1STPENR1_GPDMA1STPEN_Msk     (0x1UL << RCC_AHB1STPENR1_GPDMA1STPEN_Pos)     /*!< 0x00000001 */
#define RCC_AHB1STPENR1_GPDMA1STPEN         RCC_AHB1STPENR1_GPDMA1STPEN_Msk                /*!< GPDMA1 Clock Enable in Stop Mode */
#define RCC_AHB1STPENR1_ADF1STPEN_Pos       (3UL)
#define RCC_AHB1STPENR1_ADF1STPEN_Msk       (0x1UL << RCC_AHB1STPENR1_ADF1STPEN_Pos)       /*!< 0x00000008 */
#define RCC_AHB1STPENR1_ADF1STPEN           RCC_AHB1STPENR1_ADF1STPEN_Msk                  /*!< ADF1 Clock Enable in Stop Mode */
#define RCC_AHB1STPENR1_FLASHSTPEN_Pos      (8UL)
#define RCC_AHB1STPENR1_FLASHSTPEN_Msk      (0x1UL << RCC_AHB1STPENR1_FLASHSTPEN_Pos)      /*!< 0x00000100 */
#define RCC_AHB1STPENR1_FLASHSTPEN          RCC_AHB1STPENR1_FLASHSTPEN_Msk                 /*!< FLASH Clock Enable in Stop Mode */
#define RCC_AHB1STPENR1_RAMCFGSTPEN_Pos     (17UL)
#define RCC_AHB1STPENR1_RAMCFGSTPEN_Msk     (0x1UL << RCC_AHB1STPENR1_RAMCFGSTPEN_Pos)     /*!< 0x00020000 */
#define RCC_AHB1STPENR1_RAMCFGSTPEN         RCC_AHB1STPENR1_RAMCFGSTPEN_Msk                /*!< RAMCFG Clock Enable in Stop Mode */
#define RCC_AHB1STPENR1_GTZC1STPEN_Pos      (24UL)
#define RCC_AHB1STPENR1_GTZC1STPEN_Msk      (0x1UL << RCC_AHB1STPENR1_GTZC1STPEN_Pos)      /*!< 0x00100000 */
#define RCC_AHB1STPENR1_GTZC1STPEN          RCC_AHB1STPENR1_GTZC1STPEN_Msk                 /*!< GTZC1 Clock Enable in Stop Mode */
#define RCC_AHB1STPENR1_SRAM1STPEN_Pos      (31UL)
#define RCC_AHB1STPENR1_SRAM1STPEN_Msk      (0x1UL << RCC_AHB1STPENR1_SRAM1STPEN_Pos)      /*!< 0x80000000 */
#define RCC_AHB1STPENR1_SRAM1STPEN          RCC_AHB1STPENR1_SRAM1STPEN_Msk                 /*!< SRAM1 Clock Enable in Stop Mode */

/********************  Bit definition for RCC_AHB2STPENR1 register  **************/
#define RCC_AHB2STPENR1_GPIOASTPEN_Pos      (0UL)
#define RCC_AHB2STPENR1_GPIOASTPEN_Msk      (0x1UL << RCC_AHB2STPENR1_GPIOASTPEN_Pos)     /*!< 0x00000001 */
#define RCC_AHB2STPENR1_GPIOASTPEN          RCC_AHB2STPENR1_GPIOASTPEN_Msk                /*!< IO port A Clock Enable in Stop Mode */
#define RCC_AHB2STPENR1_GPIOBSTPEN_Pos      (1UL)
#define RCC_AHB2STPENR1_GPIOBSTPEN_Msk      (0x1UL << RCC_AHB2STPENR1_GPIOBSTPEN_Pos)     /*!< 0x00000002 */
#define RCC_AHB2STPENR1_GPIOBSTPEN          RCC_AHB2STPENR1_GPIOBSTPEN_Msk                /*!< IO port B Clock Enable in Stop Mode */
#define RCC_AHB2STPENR1_GPIOCSTPEN_Pos      (2UL)
#define RCC_AHB2STPENR1_GPIOCSTPEN_Msk      (0x1UL << RCC_AHB2STPENR1_GPIOCSTPEN_Pos)     /*!< 0x00000004 */
#define RCC_AHB2STPENR1_GPIOCSTPEN          RCC_AHB2STPENR1_GPIOCSTPEN_Msk                /*!< IO port C Clock Enable in Stop Mode */
#define RCC_AHB2STPENR1_GPIODSTPEN_Pos      (3UL)
#define RCC_AHB2STPENR1_GPIODSTPEN_Msk      (0x1UL << RCC_AHB2STPENR1_GPIODSTPEN_Pos)     /*!< 0x00000008 */
#define RCC_AHB2STPENR1_GPIODSTPEN          RCC_AHB2STPENR1_GPIODSTPEN_Msk                /*!< IO port D Clock Enable in Stop Mode */
#define RCC_AHB2STPENR1_GPIOESTPEN_Pos      (4UL)
#define RCC_AHB2STPENR1_GPIOESTPEN_Msk      (0x1UL << RCC_AHB2STPENR1_GPIOESTPEN_Pos)     /*!< 0x00000010 */
#define RCC_AHB2STPENR1_GPIOESTPEN          RCC_AHB2STPENR1_GPIOESTPEN_Msk                /*!< IO port E Clock Enable in Stop Mode */
#define RCC_AHB2STPENR1_GPIOGSTPEN_Pos      (6UL)
#define RCC_AHB2STPENR1_GPIOGSTPEN_Msk      (0x1UL << RCC_AHB2STPENR1_GPIOGSTPEN_Pos)     /*!< 0x00000040 */
#define RCC_AHB2STPENR1_GPIOGSTPEN          RCC_AHB2STPENR1_GPIOGSTPEN_Msk                /*!< IO port G Clock Enable in Stop Mode */
#define RCC_AHB2STPENR1_GPIOHSTPEN_Pos      (7UL)
#define RCC_AHB2STPENR1_GPIOHSTPEN_Msk      (0x1UL << RCC_AHB2STPENR1_GPIOHSTPEN_Pos)     /*!< 0x00000080 */
#define RCC_AHB2STPENR1_GPIOHSTPEN          RCC_AHB2STPENR1_GPIOHSTPEN_Msk                /*!< IO port H Clock Enable in Stop Mode */
#define RCC_AHB2STPENR1_DAC1STPEN_Pos       (11UL)
#define RCC_AHB2STPENR1_DAC1STPEN_Msk       (0x1UL << RCC_AHB2STPENR1_DAC1STPEN_Pos)      /*!< 0x00000800 */
#define RCC_AHB2STPENR1_DAC1STPEN           RCC_AHB2STPENR1_DAC1STPEN_Msk                 /*!< DAC1 Clock Enable in Stop Mode */
#define RCC_AHB2STPENR1_SRAM2STPEN_Pos      (30UL)
#define RCC_AHB2STPENR1_SRAM2STPEN_Msk      (0x1UL << RCC_AHB2STPENR1_SRAM2STPEN_Pos)     /*!< 0x40000000 */
#define RCC_AHB2STPENR1_SRAM2STPEN          RCC_AHB2STPENR1_SRAM2STPEN_Msk                /*!< SRAM2 Clock Enable in Stop Mode */

/********************  Bit definition for RCC_APB1STPENR1 register  **************/
#define RCC_APB1STPENR1_SPI3STPEN_Pos       (8UL)
#define RCC_APB1STPENR1_SPI3STPEN_Msk       (0x1UL << RCC_APB1STPENR1_SPI3STPEN_Pos)      /*!< 0x00000100 */
#define RCC_APB1STPENR1_SPI3STPEN           RCC_APB1STPENR1_SPI3STPEN_Msk                 /*!< SPI3 Clock Enable in Stop Mode */
#define RCC_APB1STPENR1_SPI2STPEN_Pos       (14UL)
#define RCC_APB1STPENR1_SPI2STPEN_Msk       (0x1UL << RCC_APB1STPENR1_SPI2STPEN_Pos)      /*!< 0x00004000 */
#define RCC_APB1STPENR1_SPI2STPEN           RCC_APB1STPENR1_SPI2STPEN_Msk                 /*!< SPI2 Clock Enable in Stop Mode */
#define RCC_APB1STPENR1_USART3STPEN_Pos     (18UL)
#define RCC_APB1STPENR1_USART3STPEN_Msk     (0x1UL << RCC_APB1STPENR1_USART3STPEN_Pos)    /*!< 0x00040000 */
#define RCC_APB1STPENR1_USART3STPEN         RCC_APB1STPENR1_USART3STPEN_Msk               /*!< USART3 Clock Enable in Stop Mode */
#define RCC_APB1STPENR1_UART4STPEN_Pos      (19UL)
#define RCC_APB1STPENR1_UART4STPEN_Msk      (0x1UL << RCC_APB1STPENR1_UART4STPEN_Pos)     /*!< 0x00080000 */
#define RCC_APB1STPENR1_UART4STPEN          RCC_APB1STPENR1_UART4STPEN_Msk                /*!< UART4 Clock Enable in Stop Mode */
#define RCC_APB1STPENR1_UART5STPEN_Pos      (20UL)
#define RCC_APB1STPENR1_UART5STPEN_Msk      (0x1UL << RCC_APB1STPENR1_UART5STPEN_Pos)     /*!< 0x00100000 */
#define RCC_APB1STPENR1_UART5STPEN          RCC_APB1STPENR1_UART5STPEN_Msk                /*!< UART5 Clock Enable in Stop Mode */
#define RCC_APB1STPENR1_I2C1STPEN_Pos       (21UL)
#define RCC_APB1STPENR1_I2C1STPEN_Msk       (0x1UL << RCC_APB1STPENR1_I2C1STPEN_Pos)      /*!< 0x00200000 */
#define RCC_APB1STPENR1_I2C1STPEN           RCC_APB1STPENR1_I2C1STPEN_Msk                 /*!< I2C1 Clock Enable in Stop Mode */
#define RCC_APB1STPENR1_I2C2STPEN_Pos       (22UL)
#define RCC_APB1STPENR1_I2C2STPEN_Msk       (0x1UL << RCC_APB1STPENR1_I2C2STPEN_Pos)      /*!< 0x00400000 */
#define RCC_APB1STPENR1_I2C2STPEN           RCC_APB1STPENR1_I2C2STPEN_Msk                 /*!< I2C2 Clock Enable in Stop Mode */
#define RCC_APB1STPENR1_I3C1STPEN_Pos       (23UL)
#define RCC_APB1STPENR1_I3C1STPEN_Msk       (0x1UL << RCC_APB1STPENR1_I3C1STPEN_Pos)      /*!< 0x00800000 */
#define RCC_APB1STPENR1_I3C1STPEN           RCC_APB1STPENR1_I3C1STPEN_Msk                 /*!< I3C1 Clock Enable in Stop Mode  */
#define RCC_APB1STPENR1_OPAMPSTPEN_Pos      (28UL)
#define RCC_APB1STPENR1_OPAMPSTPEN_Msk      (0x1UL << RCC_APB1STPENR1_OPAMPSTPEN_Pos)     /*!< 0x100000000 */
#define RCC_APB1STPENR1_OPAMPSTPEN          RCC_APB1STPENR1_OPAMPSTPEN_Msk                /*!< OPAMP Clock Enable in Stop Mode */
#define RCC_APB1STPENR1_VREFSTPEN_Pos       (29UL)
#define RCC_APB1STPENR1_VREFSTPEN_Msk       (0x1UL << RCC_APB1STPENR1_VREFSTPEN_Pos)      /*!< 0x200000000 */
#define RCC_APB1STPENR1_VREFSTPEN           RCC_APB1STPENR1_VREFSTPEN_Msk                 /*!< VREFBUF Clock Enable in Stop Mode */
#define RCC_APB1STPENR1_RTCAPBSTPEN_Pos     (30UL)
#define RCC_APB1STPENR1_RTCAPBSTPEN_Msk     (0x1UL << RCC_APB1STPENR1_RTCAPBSTPEN_Pos)    /*!< 0x400000000 */
#define RCC_APB1STPENR1_RTCAPBSTPEN         RCC_APB1STPENR1_RTCAPBSTPEN_Msk               /*!< RTCAPB Clock Enable in Stop Mode */

/********************  Bit definition for RCC_APB1STPENR2 register  **************/
#define RCC_APB1STPENR2_LPTIM2STPEN_Pos     (5UL)
#define RCC_APB1STPENR2_LPTIM2STPEN_Msk     (0x1UL << RCC_APB1STPENR2_LPTIM2STPEN_Pos)    /*!< 0x00000020 */
#define RCC_APB1STPENR2_LPTIM2STPEN         RCC_APB1STPENR2_LPTIM2STPEN_Msk               /*!< LPTIM2 Clock Enable in Stop Mode */

/********************  Bit definition for RCC_APB2STPENR register  **************/
#define RCC_APB2STPENR_SPI1STPEN_Pos        (12UL)
#define RCC_APB2STPENR_SPI1STPEN_Msk        (0x1UL << RCC_APB2STPENR_SPI1STPEN_Pos)       /*!< 0x00001000 */
#define RCC_APB2STPENR_SPI1STPEN            RCC_APB2STPENR_SPI1STPEN_Msk                  /*!< SPI1 Clock Enable in Stop Mode */
#define RCC_APB2STPENR_USART1STPEN_Pos      (14UL)
#define RCC_APB2STPENR_USART1STPEN_Msk      (0x1UL << RCC_APB2STPENR_USART1STPEN_Pos)     /*!< 0x00004000 */
#define RCC_APB2STPENR_USART1STPEN          RCC_APB2STPENR_USART1STPEN_Msk                /*!< USART1 Clock Enable in Stop Mode */
#define RCC_APB2STPENR_USB1STPEN_Pos        (24UL)
#define RCC_APB2STPENR_USB1STPEN_Msk        (0x1UL << RCC_APB2STPENR_USB1STPEN_Pos)       /*!< 0x01000000 */
#define RCC_APB2STPENR_USB1STPEN            RCC_APB2STPENR_USB1STPEN_Msk                  /*!< USB1 Clock Enable in Stop Mode */
#define RCC_APB2STPENR_I3C2STPEN_Pos        (27UL)
#define RCC_APB2STPENR_I3C2STPEN_Msk        (0x1UL << RCC_APB2STPENR_I3C2STPEN_Pos)       /*!< 0x08000000 */
#define RCC_APB2STPENR_I3C2STPEN            RCC_APB2STPENR_I3C2STPEN_Msk                  /*!< I3C2 Clock Enable in Stop Mode */

/********************  Bit definition for RCC_APB3STPENR register  **************/
#define RCC_APB3STPENR_LPUART1STPEN_Pos     (6UL)
#define RCC_APB3STPENR_LPUART1STPEN_Msk     (0x1UL << RCC_APB3STPENR_LPUART1STPEN_Pos)   /*!< 0x00000040 */
#define RCC_APB3STPENR_LPUART1STPEN         RCC_APB3STPENR_LPUART1STPEN_Msk              /*!< LPUART1 Clock Enable in Stop Mode */
#define RCC_APB3STPENR_I2C3STPEN_Pos        (7UL)
#define RCC_APB3STPENR_I2C3STPEN_Msk        (0x1UL << RCC_APB3STPENR_I2C3STPEN_Pos)      /*!< 0x00000080 */
#define RCC_APB3STPENR_I2C3STPEN            RCC_APB3STPENR_I2C3STPEN_Msk                 /*!< I2C3 Clock Enable in Stop Mode */
#define RCC_APB3STPENR_LPTIM1STPEN_Pos      (11UL)
#define RCC_APB3STPENR_LPTIM1STPEN_Msk      (0x1UL << RCC_APB3STPENR_LPTIM1STPEN_Pos)    /*!< 0x00000800 */
#define RCC_APB3STPENR_LPTIM1STPEN          RCC_APB3STPENR_LPTIM1STPEN_Msk               /*!< LPTIM1 Clock Enable in Stop Mode */
#define RCC_APB3STPENR_LPTIM3STPEN_Pos      (12UL)
#define RCC_APB3STPENR_LPTIM3STPEN_Msk      (0x1UL << RCC_APB3STPENR_LPTIM3STPEN_Pos)    /*!< 0x00001000 */
#define RCC_APB3STPENR_LPTIM3STPEN          RCC_APB3STPENR_LPTIM3STPEN_Msk               /*!< LPTIM3 Clock Enable in Stop Mode */
#define RCC_APB3STPENR_LPTIM4STPEN_Pos      (13UL)
#define RCC_APB3STPENR_LPTIM4STPEN_Msk      (0x1UL << RCC_APB3STPENR_LPTIM4STPEN_Pos)    /*!< 0x00002000 */
#define RCC_APB3STPENR_LPTIM4STPEN          RCC_APB3STPENR_LPTIM4STPEN_Msk               /*!< LPTIM4 Clock Enable in Stop Mode */
#define RCC_APB3STPENR_COMPSTPEN_Pos        (15UL)
#define RCC_APB3STPENR_COMPSTPEN_Msk        (0x1UL << RCC_APB3STPENR_COMPSTPEN_Pos)      /*!< 0x00008000 */
#define RCC_APB3STPENR_COMPSTPEN            RCC_APB3STPENR_COMPSTPEN_Msk                 /*!< COMP Clock Enable in Stop Mode */

/********************  Bit definition for RCC_CCIPR1 register  ******************/
#define RCC_CCIPR1_USART1SEL_Pos            (0UL)
#define RCC_CCIPR1_USART1SEL_Msk            (0x1UL << RCC_CCIPR1_USART1SEL_Pos)     /*!< 0x00000001 */
#define RCC_CCIPR1_USART1SEL                RCC_CCIPR1_USART1SEL_Msk                /*!< USART1SEL: USART1 Kernel Clock Source Selection */
#define RCC_CCIPR1_USART3SEL_Pos            (2UL)
#define RCC_CCIPR1_USART3SEL_Msk            (0x1UL << RCC_CCIPR1_USART3SEL_Pos)     /*!< 0x00000004 */
#define RCC_CCIPR1_USART3SEL                RCC_CCIPR1_USART3SEL_Msk                /*!< USART3SEL: USART3 Kernel Clock Source Selection */
#define RCC_CCIPR1_UART4SEL_Pos             (4UL)
#define RCC_CCIPR1_UART4SEL_Msk             (0x1UL << RCC_CCIPR1_UART4SEL_Pos)      /*!< 0x00000010 */
#define RCC_CCIPR1_UART4SEL                 RCC_CCIPR1_UART4SEL_Msk                 /*!< UART4SEL: UART4 Kernel Clock Source Selection */
#define RCC_CCIPR1_UART5SEL_Pos             (6UL)
#define RCC_CCIPR1_UART5SEL_Msk             (0x1UL << RCC_CCIPR1_UART5SEL_Pos)      /*!< 0x00000040 */
#define RCC_CCIPR1_UART5SEL                 RCC_CCIPR1_UART5SEL_Msk                 /*!< UART5SEL: UART5 Kernel Clock Source Selection */
#define RCC_CCIPR1_I3C1SEL_Pos              (8UL)
#define RCC_CCIPR1_I3C1SEL_Msk              (0x1UL << RCC_CCIPR1_I3C1SEL_Pos)       /*!< 0x00000100 */
#define RCC_CCIPR1_I3C1SEL                  RCC_CCIPR1_I3C1SEL_Msk                  /*!< I3C1SEL: I3C1 Kernel Clock Source Selection */
#define RCC_CCIPR1_I2C1SEL_Pos              (10UL)
#define RCC_CCIPR1_I2C1SEL_Msk              (0x1UL << RCC_CCIPR1_I2C1SEL_Pos)       /*!< 0x00000400 */
#define RCC_CCIPR1_I2C1SEL                  RCC_CCIPR1_I2C1SEL_Msk                  /*!< I2C1SEL: I2C1 Kernel Clock Source Selection */
#define RCC_CCIPR1_I2C2SEL_Pos              (12UL)
#define RCC_CCIPR1_I2C2SEL_Msk              (0x1UL << RCC_CCIPR1_I2C2SEL_Pos)       /*!< 0x00001000 */
#define RCC_CCIPR1_I2C2SEL                  RCC_CCIPR1_I2C2SEL_Msk                  /*!< I2C2SEL: I2C2 Kernel Clock Source Selection */
#define RCC_CCIPR1_I3C2SEL_Pos              (14UL)
#define RCC_CCIPR1_I3C2SEL_Msk              (0x1UL << RCC_CCIPR1_I3C2SEL_Pos)       /*!< 0x00004000 */
#define RCC_CCIPR1_I3C2SEL                  RCC_CCIPR1_I3C2SEL_Msk                  /*!< I3C2SEL: I3C2 Kernel Clock Source Selection */
#define RCC_CCIPR1_SPI2SEL_Pos              (16UL)
#define RCC_CCIPR1_SPI2SEL_Msk              (0x1UL << RCC_CCIPR1_SPI2SEL_Pos)       /*!< 0x00010000 */
#define RCC_CCIPR1_SPI2SEL                  RCC_CCIPR1_SPI2SEL_Msk                  /*!< SPI2SEL: SPI2 Kernel Clock Source Selection */
#define RCC_CCIPR1_LPTIM2SEL_Pos            (18UL)
#define RCC_CCIPR1_LPTIM2SEL_Msk            (0x3UL << RCC_CCIPR1_LPTIM2SEL_Pos)     /*!< 0x000C0000 */
#define RCC_CCIPR1_LPTIM2SEL                RCC_CCIPR1_LPTIM2SEL_Msk                /*!< LPTIM2SEL[1:0]: LPTIM2 Kernel Clock Source Selection */
#define RCC_CCIPR1_LPTIM2SEL_0              (0x1UL << RCC_CCIPR1_LPTIM2SEL_Pos)     /*!< 0x00040000 */
#define RCC_CCIPR1_LPTIM2SEL_1              (0x2UL << RCC_CCIPR1_LPTIM2SEL_Pos)     /*!< 0x00080000 */
#define RCC_CCIPR1_SPI1SEL_Pos              (20UL)
#define RCC_CCIPR1_SPI1SEL_Msk              (0x1UL << RCC_CCIPR1_SPI1SEL_Pos)       /*!< 0x00100000 */
#define RCC_CCIPR1_SPI1SEL                  RCC_CCIPR1_SPI1SEL_Msk                  /*!< SPI1SEL:  SPI1 Kernel Clock Source Selection */
#define RCC_CCIPR1_SYSTICKSEL_Pos           (22UL)
#define RCC_CCIPR1_SYSTICKSEL_Msk           (0x3UL << RCC_CCIPR1_SYSTICKSEL_Pos)    /*!< 0x00C00000 */
#define RCC_CCIPR1_SYSTICKSEL               RCC_CCIPR1_SYSTICKSEL_Msk               /*!< SYSTICKSEL[1:0]: SYSTICK Clock Source Selection */
#define RCC_CCIPR1_SYSTICKSEL_0             (0x1UL << RCC_CCIPR1_SYSTICKSEL_Pos)    /*!< 0x00400000 */
#define RCC_CCIPR1_SYSTICKSEL_1             (0x2UL << RCC_CCIPR1_SYSTICKSEL_Pos)    /*!< 0x00800000 */
#define RCC_CCIPR1_FDCANSEL_Pos             (24UL)
#define RCC_CCIPR1_FDCANSEL_Msk             (0x1UL << RCC_CCIPR1_FDCANSEL_Pos)     /*!< 0x01000000 */
#define RCC_CCIPR1_FDCANSEL                 RCC_CCIPR1_FDCANSEL_Msk               /*!< FDCANSEL: FDCAN1 Kernel Clock Source Selection */
#define RCC_CCIPR1_FDCAN1SEL_Pos            RCC_CCIPR1_FDCANSEL_Pos
#define RCC_CCIPR1_FDCAN1SEL_Msk            RCC_CCIPR1_FDCANSEL_Msk
#define RCC_CCIPR1_FDCAN1SEL                RCC_CCIPR1_FDCANSEL
#define RCC_CCIPR1_ICLKSEL_Pos              (26UL)
#define RCC_CCIPR1_ICLKSEL_Msk              (0x3UL << RCC_CCIPR1_ICLKSEL_Pos)       /*!< 0x0C000000 */
#define RCC_CCIPR1_ICLKSEL                  RCC_CCIPR1_ICLKSEL_Msk                  /*!< ICLKSEL[1:0]: Intermediate Clock Source Selection */
#define RCC_CCIPR1_ICLKSEL_0                (0x1UL << RCC_CCIPR1_ICLKSEL_Pos)       /*!< 0x04000000 */
#define RCC_CCIPR1_ICLKSEL_1                (0x2UL << RCC_CCIPR1_ICLKSEL_Pos)       /*!< 0x08000000 */
#define RCC_CCIPR1_USB1SEL_Pos              (28UL)
#define RCC_CCIPR1_USB1SEL_Msk              (0x1UL << RCC_CCIPR1_USB1SEL_Pos)       /*!< 0x10000000 */
#define RCC_CCIPR1_USB1SEL                  RCC_CCIPR1_USB1SEL_Msk                  /*!< USB1SEL: USB1 Kernel Clock Source Selection */
#define RCC_CCIPR1_TIMICSEL_Pos             (29UL)
#define RCC_CCIPR1_TIMICSEL_Msk             (0x7UL << RCC_CCIPR1_TIMICSEL_Pos)      /*!< 0xE0000000 */
#define RCC_CCIPR1_TIMICSEL                 RCC_CCIPR1_TIMICSEL_Msk                 /*!< TIMICSEL[2:0]: TIM16, TIM17 and LPTIM2 Internal Input Capture Kernel Clock Source Selection */
#define RCC_CCIPR1_TIMICSEL_0               (0x1UL << RCC_CCIPR1_TIMICSEL_Pos)      /*!< 0x20000000 */
#define RCC_CCIPR1_TIMICSEL_1               (0x2UL << RCC_CCIPR1_TIMICSEL_Pos)      /*!< 0x40000000 */
#define RCC_CCIPR1_TIMICSEL_2               (0x4UL << RCC_CCIPR1_TIMICSEL_Pos)      /*!< 0x80000000 */

/********************  Bit definition for RCC_CCIPR2 register  ******************/
#define RCC_CCIPR2_ADF1SEL_Pos              (0UL)
#define RCC_CCIPR2_ADF1SEL_Msk              (0x3UL << RCC_CCIPR2_ADF1SEL_Pos)       /*!< 0x00000003 */
#define RCC_CCIPR2_ADF1SEL                  RCC_CCIPR2_ADF1SEL_Msk                  /*!< ADF1SEL[1:0]: ADF Kernel Clock Source Selection */
#define RCC_CCIPR2_ADF1SEL_0                (0x1UL << RCC_CCIPR2_ADF1SEL_Pos)       /*!< 0x00000001 */
#define RCC_CCIPR2_ADF1SEL_1                (0x2UL << RCC_CCIPR2_ADF1SEL_Pos)       /*!< 0x00000002 */
#define RCC_CCIPR2_SPI3SEL_Pos              (3UL)
#define RCC_CCIPR2_SPI3SEL_Msk              (0x1UL << RCC_CCIPR2_SPI3SEL_Pos)       /*!< 0x00000004 */
#define RCC_CCIPR2_SPI3SEL                  RCC_CCIPR2_SPI3SEL_Msk                  /*!< SPI3SEL: SPI3 Kernel Clock Source Selection */
#define RCC_CCIPR2_SAI1SEL_Pos              (5UL)
#define RCC_CCIPR2_SAI1SEL_Msk              (0x3UL << RCC_CCIPR2_SAI1SEL_Pos)       /*!< 0x00000060 */
#define RCC_CCIPR2_SAI1SEL                  RCC_CCIPR2_SAI1SEL_Msk                  /*!< SAI1SEL[1:0]: SAI1 Kernel Clock Source Selection */
#define RCC_CCIPR2_SAI1SEL_0                (0x1UL << RCC_CCIPR2_SAI1SEL_Pos)       /*!< 0x00000020 */
#define RCC_CCIPR2_SAI1SEL_1                (0x2UL << RCC_CCIPR2_SAI1SEL_Pos)       /*!< 0x00000040 */
#define RCC_CCIPR2_RNGSEL_Pos               (11UL)
#define RCC_CCIPR2_RNGSEL_Msk               (0x1UL << RCC_CCIPR2_RNGSEL_Pos)        /*!< 0x00000800 */
#define RCC_CCIPR2_RNGSEL                   RCC_CCIPR2_RNGSEL_Msk                   /*!< RNGSEL: RNG Kernel Clock Source Selection */
#define RCC_CCIPR2_ADCDACPRE_Pos            (12UL)
#define RCC_CCIPR2_ADCDACPRE_Msk            (0xFUL << RCC_CCIPR2_ADCDACPRE_Pos)     /*!< 0x0000F000 */
#define RCC_CCIPR2_ADCDACPRE                RCC_CCIPR2_ADCDACPRE_Msk                /*!< ADCDACPRE[3:0]: ADC/DAC prescaler */
#define RCC_CCIPR2_ADCDACPRE_0              (0x1UL << RCC_CCIPR2_ADCDACPRE_Pos)     /*!< 0x00001000 */
#define RCC_CCIPR2_ADCDACPRE_1              (0x2UL << RCC_CCIPR2_ADCDACPRE_Pos)     /*!< 0x00002000 */
#define RCC_CCIPR2_ADCDACPRE_2              (0x4UL << RCC_CCIPR2_ADCDACPRE_Pos)     /*!< 0x00004000 */
#define RCC_CCIPR2_ADCDACPRE_3              (0x8UL << RCC_CCIPR2_ADCDACPRE_Pos)     /*!< 0x00008000 */
#define RCC_CCIPR2_ADCDACSEL_Pos            (16UL)
#define RCC_CCIPR2_ADCDACSEL_Msk            (0x3UL << RCC_CCIPR2_ADCDACSEL_Pos)     /*!< 0x00030000 */
#define RCC_CCIPR2_ADCDACSEL                RCC_CCIPR2_ADCDACSEL_Msk                /*!< ADCDACSEL[2:0]: ADC1 and DAC1 Kernel Clock Source Selection */
#define RCC_CCIPR2_ADCDACSEL_0              (0x1UL << RCC_CCIPR2_ADCDACSEL_Pos)     /*!< 0x00010000 */
#define RCC_CCIPR2_ADCDACSEL_1              (0x2UL << RCC_CCIPR2_ADCDACSEL_Pos)     /*!< 0x00020000 */
#define RCC_CCIPR2_DAC1SHSEL_Pos            (19UL)
#define RCC_CCIPR2_DAC1SHSEL_Msk            (0x1UL << RCC_CCIPR2_DAC1SHSEL_Pos)     /*!< 0x00080000 */
#define RCC_CCIPR2_DAC1SHSEL                RCC_CCIPR2_DAC1SHSEL_Msk                /*!< DACSEL: DAC1 Sample and Hold Clock Source Selection */
#define RCC_CCIPR2_OCTOSPISEL_Pos           (20UL)
#define RCC_CCIPR2_OCTOSPISEL_Msk           (0x1UL << RCC_CCIPR2_OCTOSPISEL_Pos)    /*!< 0x00100000 */
#define RCC_CCIPR2_OCTOSPISEL               RCC_CCIPR2_OCTOSPISEL_Msk               /*!< OCTOSPISEL: OCTOSPI1 Kernel Clock Source Selection */

/********************  Bit definition for RCC_CCIPR3 register  ***************/
#define RCC_CCIPR3_LPUART1SEL_Pos           (0UL)
#define RCC_CCIPR3_LPUART1SEL_Msk           (0x3UL << RCC_CCIPR3_LPUART1SEL_Pos)    /*!< 0x00000003 */
#define RCC_CCIPR3_LPUART1SEL               RCC_CCIPR3_LPUART1SEL_Msk               /*!< LPUART1SEL[1:0]: LPUART1 Kernel Clock Source Selection */
#define RCC_CCIPR3_LPUART1SEL_0             (0x1UL << RCC_CCIPR3_LPUART1SEL_Pos)    /*!< 0x00000001 */
#define RCC_CCIPR3_LPUART1SEL_1             (0x2UL << RCC_CCIPR3_LPUART1SEL_Pos)    /*!< 0x00000002 */
#define RCC_CCIPR3_I2C3SEL_Pos              (6UL)
#define RCC_CCIPR3_I2C3SEL_Msk              (0x1UL << RCC_CCIPR3_I2C3SEL_Pos)       /*!< 0x00000040 */
#define RCC_CCIPR3_I2C3SEL                  RCC_CCIPR3_I2C3SEL_Msk                  /*!< I2C3SEL: I2C3 Kernel Clock Source Selection */
#define RCC_CCIPR3_LPTIM34SEL_Pos           (8UL)
#define RCC_CCIPR3_LPTIM34SEL_Msk           (0x3UL << RCC_CCIPR3_LPTIM34SEL_Pos)    /*!< 0x00000300 */
#define RCC_CCIPR3_LPTIM34SEL               RCC_CCIPR3_LPTIM34SEL_Msk               /*!< LPTIM34SEL[1:0]: LPTIM3 and LPTIM4 Kernel Clock Source Selection */
#define RCC_CCIPR3_LPTIM34SEL_0             (0x1UL << RCC_CCIPR3_LPTIM34SEL_Pos)    /*!< 0x00000100 */
#define RCC_CCIPR3_LPTIM34SEL_1             (0x2UL << RCC_CCIPR3_LPTIM34SEL_Pos)    /*!< 0x00000200 */
#define RCC_CCIPR3_LPTIM1SEL_Pos            (10UL)
#define RCC_CCIPR3_LPTIM1SEL_Msk            (0x3UL << RCC_CCIPR3_LPTIM1SEL_Pos)     /*!< 0x00000C00 */
#define RCC_CCIPR3_LPTIM1SEL                RCC_CCIPR3_LPTIM1SEL_Msk                /*!< LPTIM1SEL[1:0]: LPTIM1 Kernel Clock Source Selection */
#define RCC_CCIPR3_LPTIM1SEL_0              (0x1UL << RCC_CCIPR3_LPTIM1SEL_Pos)     /*!< 0x00000400 */
#define RCC_CCIPR3_LPTIM1SEL_1              (0x2UL << RCC_CCIPR3_LPTIM1SEL_Pos)     /*!< 0x00000800 */

/********************  Bit definition for RCC_BDCR register  ******************/
#define RCC_BDCR_LSEON_Pos                  (0UL)
#define RCC_BDCR_LSEON_Msk                  (0x1UL << RCC_BDCR_LSEON_Pos)           /*!< 0x00000001 */
#define RCC_BDCR_LSEON                      RCC_BDCR_LSEON_Msk                      /*!< LSE Oscillator Enable */
#define RCC_BDCR_LSERDY_Pos                 (1UL)
#define RCC_BDCR_LSERDY_Msk                 (0x1UL << RCC_BDCR_LSERDY_Pos)          /*!< 0x00000002 */
#define RCC_BDCR_LSERDY                     RCC_BDCR_LSERDY_Msk                     /*!< LSE Oscillator Ready */
#define RCC_BDCR_LSEBYP_Pos                 (2UL)
#define RCC_BDCR_LSEBYP_Msk                 (0x1UL << RCC_BDCR_LSEBYP_Pos)          /*!< 0x00000004 */
#define RCC_BDCR_LSEBYP                     RCC_BDCR_LSEBYP_Msk                     /*!< LSE Oscillator Bypass */
#define RCC_BDCR_LSEDRV_Pos                 (3UL)
#define RCC_BDCR_LSEDRV_Msk                 (0x3UL << RCC_BDCR_LSEDRV_Pos)          /*!< 0x00000018 */
#define RCC_BDCR_LSEDRV                     RCC_BDCR_LSEDRV_Msk                     /*!< LSEDRV[1:0]: LSE Oscillator Drive Capability */
#define RCC_BDCR_LSEDRV_0                   (0x1UL << RCC_BDCR_LSEDRV_Pos)          /*!< 0x00000008 */
#define RCC_BDCR_LSEDRV_1                   (0x2UL << RCC_BDCR_LSEDRV_Pos)          /*!< 0x00000010 */
#define RCC_BDCR_LSECSSON_Pos               (5UL)
#define RCC_BDCR_LSECSSON_Msk               (0x1UL << RCC_BDCR_LSECSSON_Pos)        /*!< 0x00000020 */
#define RCC_BDCR_LSECSSON                   RCC_BDCR_LSECSSON_Msk                   /*!< CSS on LSE Enable */
#define RCC_BDCR_LSECSSD_Pos                (6UL)
#define RCC_BDCR_LSECSSD_Msk                (0x1UL << RCC_BDCR_LSECSSD_Pos)         /*!< 0x00000040 */
#define RCC_BDCR_LSECSSD                    RCC_BDCR_LSECSSD_Msk                    /*!< CSS on LSE failure Detection */
#define RCC_BDCR_LSESYSEN_Pos               (7UL)
#define RCC_BDCR_LSESYSEN_Msk               (0x1UL << RCC_BDCR_LSESYSEN_Pos)        /*!< 0x00000080 */
#define RCC_BDCR_LSESYSEN                   RCC_BDCR_LSESYSEN_Msk                   /*!< LSE System Clock (LSESYS) Enable */
#define RCC_BDCR_RTCSEL_Pos                 (8UL)
#define RCC_BDCR_RTCSEL_Msk                 (0x3UL << RCC_BDCR_RTCSEL_Pos)          /*!< 0x00000300 */
#define RCC_BDCR_RTCSEL                     RCC_BDCR_RTCSEL_Msk                     /*!< RTCSEL[1:0]: RTC Clock Source Selection */
#define RCC_BDCR_RTCSEL_0                   (0x1UL << RCC_BDCR_RTCSEL_Pos)          /*!< 0x00000100 */
#define RCC_BDCR_RTCSEL_1                   (0x2UL << RCC_BDCR_RTCSEL_Pos)          /*!< 0x00000200 */
#define RCC_BDCR_LSESYSRDY_Pos              (11UL)
#define RCC_BDCR_LSESYSRDY_Msk              (0x1UL << RCC_BDCR_LSESYSRDY_Pos)       /*!< 0x00000800 */
#define RCC_BDCR_LSESYSRDY                  RCC_BDCR_LSESYSRDY_Msk                  /*!< LSE System Clock (LSESYS) Ready */
#define RCC_BDCR_LSEGFON_Pos                (12UL)
#define RCC_BDCR_LSEGFON_Msk                (0x1UL << RCC_BDCR_LSEGFON_Pos)         /*!< 0x00001000 */
#define RCC_BDCR_LSEGFON                    RCC_BDCR_LSEGFON_Msk                    /*!< LSE Clock Glitch Filter Enable */
#define RCC_BDCR_RTCEN_Pos                  (15UL)
#define RCC_BDCR_RTCEN_Msk                  (0x1UL << RCC_BDCR_RTCEN_Pos)           /*!< 0x00008000 */
#define RCC_BDCR_RTCEN                      RCC_BDCR_RTCEN_Msk                      /*!< RTC Clock Enable */
#define RCC_BDCR_BDRST_Pos                  (16UL)
#define RCC_BDCR_BDRST_Msk                  (0x1UL << RCC_BDCR_BDRST_Pos)           /*!< 0x00010000 */
#define RCC_BDCR_BDRST                      RCC_BDCR_BDRST_Msk                      /*!< BD reset */
#define RCC_BDCR_LSCOEN_Pos                 (24UL)
#define RCC_BDCR_LSCOEN_Msk                 (0x1UL << RCC_BDCR_LSCOEN_Pos)          /*!< 0x01000000 */
#define RCC_BDCR_LSCOEN                     RCC_BDCR_LSCOEN_Msk                     /*!< Low-speed Clock Output (LSCO) Enable */
#define RCC_BDCR_LSCOSEL_Pos                (25UL)
#define RCC_BDCR_LSCOSEL_Msk                (0x1UL << RCC_BDCR_LSCOSEL_Pos)         /*!< 0x02000000 */
#define RCC_BDCR_LSCOSEL                    RCC_BDCR_LSCOSEL_Msk                    /*!< Low-speed Clock Output Selection */

/********************  Bit definition for RCC_CSR register  *******************/
#define RCC_CSR_LSION_Pos                   (0UL)
#define RCC_CSR_LSION_Msk                   (0x1UL << RCC_CSR_LSION_Pos)            /*!< 0x00000001 */
#define RCC_CSR_LSION                       RCC_CSR_LSION_Msk                       /*!< LSI Oscillator Enable */
#define RCC_CSR_LSIRDY_Pos                  (1UL)
#define RCC_CSR_LSIRDY_Msk                  (0x1UL << RCC_CSR_LSIRDY_Pos)           /*!< 0x00000002 */
#define RCC_CSR_LSIRDY                      RCC_CSR_LSIRDY_Msk                      /*!< LSI Oscillator Ready */
#define RCC_CSR_LSIPREDIV_Pos               (2UL)
#define RCC_CSR_LSIPREDIV_Msk               (0x1UL << RCC_CSR_LSIPREDIV_Pos)        /*!< 0x00000004 */
#define RCC_CSR_LSIPREDIV                   RCC_CSR_LSIPREDIV_Msk                   /*!< LSI clock divider selection */
#define RCC_CSR_MSIKDIVS_Pos                (8UL)
#define RCC_CSR_MSIKDIVS_Msk                (0x3UL << RCC_CSR_MSIKDIVS_Pos)         /*!< 0x00000300 */
#define RCC_CSR_MSIKDIVS                    RCC_CSR_MSIKDIVS_Msk                    /*!< MSIKDIVS[1:0]: MSIK Range After Standby Mode */
#define RCC_CSR_MSIKDIVS_0                  (0x1UL << RCC_CSR_MSIKDIVS_Pos)         /*!< 0x00000100 */
#define RCC_CSR_MSIKDIVS_1                  (0x2UL << RCC_CSR_MSIKDIVS_Pos)         /*!< 0x00000200 */
#define RCC_CSR_MSISDIVS_Pos                (12UL)
#define RCC_CSR_MSISDIVS_Msk                (0x3UL << RCC_CSR_MSISDIVS_Pos)         /*!< 0x00003000 */
#define RCC_CSR_MSISDIVS                    RCC_CSR_MSISDIVS_Msk                    /*!< MSISDIVS[1:0]: MSIS Range After Standby Mode */
#define RCC_CSR_MSISDIVS_0                  (0x1UL << RCC_CSR_MSISDIVS_Pos)         /*!< 0x00001000 */
#define RCC_CSR_MSISDIVS_1                  (0x2UL << RCC_CSR_MSISDIVS_Pos)         /*!< 0x00002000 */
#define RCC_CSR_RMVF_Pos                    (23UL)
#define RCC_CSR_RMVF_Msk                    (0x1UL << RCC_CSR_RMVF_Pos)             /*!< 0x00800000 */
#define RCC_CSR_RMVF                        RCC_CSR_RMVF_Msk                        /*!< Remove Reset Flag */
#define RCC_CSR_OBLRSTF_Pos                 (25UL)
#define RCC_CSR_OBLRSTF_Msk                 (0x1UL << RCC_CSR_OBLRSTF_Pos)          /*!< 0x02000000 */
#define RCC_CSR_OBLRSTF                     RCC_CSR_OBLRSTF_Msk                     /*!< Option Byte Loader Reset Flag */
#define RCC_CSR_PINRSTF_Pos                 (26UL)
#define RCC_CSR_PINRSTF_Msk                 (0x1UL << RCC_CSR_PINRSTF_Pos)          /*!< 0x04000000 */
#define RCC_CSR_PINRSTF                     RCC_CSR_PINRSTF_Msk                     /*!< NRST Pin Reset Flag */
#define RCC_CSR_BORRSTF_Pos                 (27UL)
#define RCC_CSR_BORRSTF_Msk                 (0x1UL << RCC_CSR_BORRSTF_Pos)          /*!< 0x08000000 */
#define RCC_CSR_BORRSTF                     RCC_CSR_BORRSTF_Msk                     /*!< BOR Flag */
#define RCC_CSR_SFTRSTF_Pos                 (28UL)
#define RCC_CSR_SFTRSTF_Msk                 (0x1UL << RCC_CSR_SFTRSTF_Pos)          /*!< 0x10000000 */
#define RCC_CSR_SFTRSTF                     RCC_CSR_SFTRSTF_Msk                     /*!< Software Reset Flag */
#define RCC_CSR_IWDGRSTF_Pos                (29UL)
#define RCC_CSR_IWDGRSTF_Msk                (0x1UL << RCC_CSR_IWDGRSTF_Pos)         /*!< 0x20000000 */
#define RCC_CSR_IWDGRSTF                    RCC_CSR_IWDGRSTF_Msk                    /*!< Independent Watchdog Reset Flag */
#define RCC_CSR_WWDGRSTF_Pos                (30UL)
#define RCC_CSR_WWDGRSTF_Msk                (0x1UL << RCC_CSR_WWDGRSTF_Pos)         /*!< 0x40000000 */
#define RCC_CSR_WWDGRSTF                    RCC_CSR_WWDGRSTF_Msk                    /*!< Window Watchdog Reset Flag */
#define RCC_CSR_LPWRRSTF_Pos                (31UL)
#define RCC_CSR_LPWRRSTF_Msk                (0x1UL << RCC_CSR_LPWRRSTF_Pos)         /*!< 0x80000000 */
#define RCC_CSR_LPWRRSTF                    RCC_CSR_LPWRRSTF_Msk                    /*!< Low-power Reset Flag */

/********************  Bit definition for RCC_SECCFGR register  **************/
#define RCC_SECCFGR_HSISEC_Pos              (0UL)
#define RCC_SECCFGR_HSISEC_Msk              (0x1UL << RCC_SECCFGR_HSISEC_Pos)       /*!< 0x00000001 */
#define RCC_SECCFGR_HSISEC                  RCC_SECCFGR_HSISEC_Msk                  /*!< HSI Clock Configuration and Status Bits Security */
#define RCC_SECCFGR_HSESEC_Pos              (1UL)
#define RCC_SECCFGR_HSESEC_Msk              (0x1UL << RCC_SECCFGR_HSESEC_Pos)       /*!< 0x00000002 */
#define RCC_SECCFGR_HSESEC                  RCC_SECCFGR_HSESEC_Msk                  /*!< HSE Clock Configuration Bits, Status Bits and HSE_CSS Security */
#define RCC_SECCFGR_MSISEC_Pos              (2UL)
#define RCC_SECCFGR_MSISEC_Msk              (0x1UL << RCC_SECCFGR_MSISEC_Pos)       /*!< 0x00000004 */
#define RCC_SECCFGR_MSISEC                  RCC_SECCFGR_MSISEC_Msk                  /*!< MSI Clock Configuration and Status Bits Security */
#define RCC_SECCFGR_LSISEC_Pos              (3UL)
#define RCC_SECCFGR_LSISEC_Msk              (0x1UL << RCC_SECCFGR_LSISEC_Pos)       /*!< 0x00000008 */
#define RCC_SECCFGR_LSISEC                  RCC_SECCFGR_LSISEC_Msk                  /*!< LSI Clock Configuration and Status Bits Security */
#define RCC_SECCFGR_LSESEC_Pos              (4UL)
#define RCC_SECCFGR_LSESEC_Msk              (0x1UL << RCC_SECCFGR_LSESEC_Pos)       /*!< 0x00000010 */
#define RCC_SECCFGR_LSESEC                  RCC_SECCFGR_LSESEC_Msk                  /*!< LSE Clock Configuration and Status Bits Security */
#define RCC_SECCFGR_SYSCLKSEC_Pos           (5UL)
#define RCC_SECCFGR_SYSCLKSEC_Msk           (0x1UL << RCC_SECCFGR_SYSCLKSEC_Pos)    /*!< 0x00000020 */
#define RCC_SECCFGR_SYSCLKSEC               RCC_SECCFGR_SYSCLKSEC_Msk               /*!< SYSCLK Clock Selection, STOPWUCK bit, Clock Output on MCO Configuration Security */
#define RCC_SECCFGR_PRESCSEC_Pos            (6UL)
#define RCC_SECCFGR_PRESCSEC_Msk            (0x1UL << RCC_SECCFGR_PRESCSEC_Pos)     /*!< 0x00000040 */
#define RCC_SECCFGR_PRESCSEC                RCC_SECCFGR_PRESCSEC_Msk                /*!< AHBx/APBx Prescaler Configuration Bits Security */
#define RCC_SECCFGR_BOOSTSEC_Pos            (7UL)
#define RCC_SECCFGR_BOOSTSEC_Msk            (0x1UL << RCC_SECCFGR_BOOSTSEC_Pos)     /*!< 0x00000080 */
#define RCC_SECCFGR_BOOSTSEC                RCC_SECCFGR_BOOSTSEC_Msk                /*!< BOOST Configuration Bits Security */
#define RCC_SECCFGR_ICLKSEC_Pos             (10UL)
#define RCC_SECCFGR_ICLKSEC_Msk             (0x1UL << RCC_SECCFGR_ICLKSEC_Pos)      /*!< 0x00000400 */
#define RCC_SECCFGR_ICLKSEC                 RCC_SECCFGR_ICLKSEC_Msk                 /*!< 48 MHz Clock Source Selection Security */
#define RCC_SECCFGR_HSI48SEC_Pos            (11UL)
#define RCC_SECCFGR_HSI48SEC_Msk            (0x1UL << RCC_SECCFGR_HSI48SEC_Pos)     /*!< 0x00000800 */
#define RCC_SECCFGR_HSI48SEC                RCC_SECCFGR_HSI48SEC_Msk                /*!< HSI48 Clock Configuration and Status Bits Security */
#define RCC_SECCFGR_RMVFSEC_Pos             (12UL)
#define RCC_SECCFGR_RMVFSEC_Msk             (0x1UL << RCC_SECCFGR_RMVFSEC_Pos)      /*!< 0x00001000 */
#define RCC_SECCFGR_RMVFSEC                 RCC_SECCFGR_RMVFSEC_Msk                 /*!< Remove Reset Flag Security */

/********************  Bit definition for RCC_PRIVCFGR register  **************/
#define RCC_PRIVCFGR_SPRIV_Pos              (0UL)
#define RCC_PRIVCFGR_SPRIV_Msk              (0x1UL << RCC_PRIVCFGR_SPRIV_Pos)       /*!< 0x00000001 */
#define RCC_PRIVCFGR_SPRIV                  RCC_PRIVCFGR_SPRIV_Msk                  /*!< RCC Secure Functions Privilege Configuration */
#define RCC_PRIVCFGR_NSPRIV_Pos             (1UL)
#define RCC_PRIVCFGR_NSPRIV_Msk             (0x1UL << RCC_PRIVCFGR_NSPRIV_Pos)      /*!< 0x00000002 */
#define RCC_PRIVCFGR_NSPRIV                 RCC_PRIVCFGR_NSPRIV_Msk                 /*!< RCC Non-Secure Functions Privilege Configuration */

/******************************************************************************/
/*                                                                            */
/*                                    RNG                                     */
/*                                                                            */
/******************************************************************************/
/********************  Bits definition for RNG_CR register  *******************/
#define RNG_CR_RNGEN_Pos                    (2UL)
#define RNG_CR_RNGEN_Msk                    (0x1UL << RNG_CR_RNGEN_Pos)             /*!< 0x00000004 */
#define RNG_CR_RNGEN                        RNG_CR_RNGEN_Msk
#define RNG_CR_IE_Pos                       (3UL)
#define RNG_CR_IE_Msk                       (0x1UL << RNG_CR_IE_Pos)                /*!< 0x00000008 */
#define RNG_CR_IE                           RNG_CR_IE_Msk
#define RNG_CR_CED_Pos                      (5UL)
#define RNG_CR_CED_Msk                      (0x1UL << RNG_CR_CED_Pos)               /*!< 0x00000020 */
#define RNG_CR_CED                          RNG_CR_CED_Msk
#define RNG_CR_ARDIS_Pos                    (7UL)
#define RNG_CR_ARDIS_Msk                    (0x1UL << RNG_CR_ARDIS_Pos)
#define RNG_CR_ARDIS                        RNG_CR_ARDIS_Msk
#define RNG_CR_RNG_CONFIG3_Pos              (8UL)
#define RNG_CR_RNG_CONFIG3_Msk              (0xFUL << RNG_CR_RNG_CONFIG3_Pos)
#define RNG_CR_RNG_CONFIG3                  RNG_CR_RNG_CONFIG3_Msk
#define RNG_CR_NISTC_Pos                    (12UL)
#define RNG_CR_NISTC_Msk                    (0x1UL << RNG_CR_NISTC_Pos)
#define RNG_CR_NISTC                        RNG_CR_NISTC_Msk
#define RNG_CR_RNG_CONFIG2_Pos              (13UL)
#define RNG_CR_RNG_CONFIG2_Msk              (0x7UL << RNG_CR_RNG_CONFIG2_Pos)
#define RNG_CR_RNG_CONFIG2                  RNG_CR_RNG_CONFIG2_Msk
#define RNG_CR_CLKDIV_Pos                   (16UL)
#define RNG_CR_CLKDIV_Msk                   (0xFUL << RNG_CR_CLKDIV_Pos)
#define RNG_CR_CLKDIV                       RNG_CR_CLKDIV_Msk
#define RNG_CR_CLKDIV_0                     (0x1UL << RNG_CR_CLKDIV_Pos)            /*!< 0x00010000 */
#define RNG_CR_CLKDIV_1                     (0x2UL << RNG_CR_CLKDIV_Pos)            /*!< 0x00020000 */
#define RNG_CR_CLKDIV_2                     (0x4UL << RNG_CR_CLKDIV_Pos)            /*!< 0x00040000 */
#define RNG_CR_CLKDIV_3                     (0x8UL << RNG_CR_CLKDIV_Pos)            /*!< 0x00080000 */
#define RNG_CR_RNG_CONFIG1_Pos              (20UL)
#define RNG_CR_RNG_CONFIG1_Msk              (0x3FUL << RNG_CR_RNG_CONFIG1_Pos)
#define RNG_CR_RNG_CONFIG1                  RNG_CR_RNG_CONFIG1_Msk
#define RNG_CR_CONDRST_Pos                  (30UL)
#define RNG_CR_CONDRST_Msk                  (0x1UL << RNG_CR_CONDRST_Pos)
#define RNG_CR_CONDRST                      RNG_CR_CONDRST_Msk
#define RNG_CR_CONFIGLOCK_Pos               (31UL)
#define RNG_CR_CONFIGLOCK_Msk               (0x1UL << RNG_CR_CONFIGLOCK_Pos)
#define RNG_CR_CONFIGLOCK                   RNG_CR_CONFIGLOCK_Msk

/********************  Bits definition for RNG_SR register  *******************/
#define RNG_SR_DRDY_Pos                     (0UL)
#define RNG_SR_DRDY_Msk                     (0x1UL << RNG_SR_DRDY_Pos)              /*!< 0x00000001 */
#define RNG_SR_DRDY                         RNG_SR_DRDY_Msk
#define RNG_SR_CECS_Pos                     (1UL)
#define RNG_SR_CECS_Msk                     (0x1UL << RNG_SR_CECS_Pos)              /*!< 0x00000002 */
#define RNG_SR_CECS                         RNG_SR_CECS_Msk
#define RNG_SR_SECS_Pos                     (2UL)
#define RNG_SR_SECS_Msk                     (0x1UL << RNG_SR_SECS_Pos)              /*!< 0x00000004 */
#define RNG_SR_SECS                         RNG_SR_SECS_Msk
#define RNG_SR_BUSY_Pos                     (4UL)
#define RNG_SR_BUSY_Msk                     (0x1UL << RNG_SR_BUSY_Pos)              /*!< 0x00000010 */
#define RNG_SR_BUSY                         RNG_SR_BUSY_Msk
#define RNG_SR_CEIS_Pos                     (5UL)
#define RNG_SR_CEIS_Msk                     (0x1UL << RNG_SR_CEIS_Pos)              /*!< 0x00000020 */
#define RNG_SR_CEIS                         RNG_SR_CEIS_Msk
#define RNG_SR_SEIS_Pos                     (6UL)
#define RNG_SR_SEIS_Msk                     (0x1UL << RNG_SR_SEIS_Pos)              /*!< 0x00000040 */
#define RNG_SR_SEIS                         RNG_SR_SEIS_Msk

/********************  Bits definition for RNG_NSCR register  *******************/
#define RNG_NSCR_EN_OSC1_Pos                  (0UL)
#define RNG_NSCR_EN_OSC1_Msk                  (0x7UL << RNG_NSCR_EN_OSC1_Pos)      /*!< 0x00000007 */
#define RNG_NSCR_EN_OSC1                      RNG_NSCR_EN_OSC1_Msk
#define RNG_NSCR_EN_OSC2_Pos                  (3UL)
#define RNG_NSCR_EN_OSC2_Msk                  (0x7UL << RNG_NSCR_EN_OSC2_Pos)      /*!< 0x00000038 */
#define RNG_NSCR_EN_OSC2                      RNG_NSCR_EN_OSC2_Msk
#define RNG_NSCR_EN_OSC3_Pos                  (06UL)
#define RNG_NSCR_EN_OSC3_Msk                  (0x7UL << RNG_NSCR_EN_OSC3_Pos)      /*!< 0x000001C0 */
#define RNG_NSCR_EN_OSC3                      RNG_NSCR_EN_OSC3_Msk

/******************************************************************************/
/*                                                                            */
/*                           Real-Time Clock (RTC)                            */
/*                                                                            */
/******************************************************************************/
/*
* @brief RTC Specific device feature definitions
*/
#define RTC_BKP_NB                          32U
#define RTC_TAMP_NB                         5U

/********************  Bits definition for RTC_TR register  *******************/
#define RTC_TR_SU_Pos                       (0UL)
#define RTC_TR_SU_Msk                       (0xFUL << RTC_TR_SU_Pos)                /*!< 0x0000000F */
#define RTC_TR_SU                           RTC_TR_SU_Msk
#define RTC_TR_SU_0                         (0x1UL << RTC_TR_SU_Pos)                /*!< 0x00000001 */
#define RTC_TR_SU_1                         (0x2UL << RTC_TR_SU_Pos)                /*!< 0x00000002 */
#define RTC_TR_SU_2                         (0x4UL << RTC_TR_SU_Pos)                /*!< 0x00000004 */
#define RTC_TR_SU_3                         (0x8UL << RTC_TR_SU_Pos)                /*!< 0x00000008 */
#define RTC_TR_ST_Pos                       (4UL)
#define RTC_TR_ST_Msk                       (0x7UL << RTC_TR_ST_Pos)                /*!< 0x00000070 */
#define RTC_TR_ST                           RTC_TR_ST_Msk
#define RTC_TR_ST_0                         (0x1UL << RTC_TR_ST_Pos)                /*!< 0x00000010 */
#define RTC_TR_ST_1                         (0x2UL << RTC_TR_ST_Pos)                /*!< 0x00000020 */
#define RTC_TR_ST_2                         (0x4UL << RTC_TR_ST_Pos)                /*!< 0x00000040 */
#define RTC_TR_MNU_Pos                      (8UL)
#define RTC_TR_MNU_Msk                      (0xFUL << RTC_TR_MNU_Pos)               /*!< 0x00000F00 */
#define RTC_TR_MNU                          RTC_TR_MNU_Msk
#define RTC_TR_MNU_0                        (0x1UL << RTC_TR_MNU_Pos)               /*!< 0x00000100 */
#define RTC_TR_MNU_1                        (0x2UL << RTC_TR_MNU_Pos)               /*!< 0x00000200 */
#define RTC_TR_MNU_2                        (0x4UL << RTC_TR_MNU_Pos)               /*!< 0x00000400 */
#define RTC_TR_MNU_3                        (0x8UL << RTC_TR_MNU_Pos)               /*!< 0x00000800 */
#define RTC_TR_MNT_Pos                      (12UL)
#define RTC_TR_MNT_Msk                      (0x7UL << RTC_TR_MNT_Pos)               /*!< 0x00007000 */
#define RTC_TR_MNT                          RTC_TR_MNT_Msk
#define RTC_TR_MNT_0                        (0x1UL << RTC_TR_MNT_Pos)               /*!< 0x00001000 */
#define RTC_TR_MNT_1                        (0x2UL << RTC_TR_MNT_Pos)               /*!< 0x00002000 */
#define RTC_TR_MNT_2                        (0x4UL << RTC_TR_MNT_Pos)               /*!< 0x00004000 */
#define RTC_TR_HU_Pos                       (16UL)
#define RTC_TR_HU_Msk                       (0xFUL << RTC_TR_HU_Pos)                /*!< 0x000F0000 */
#define RTC_TR_HU                           RTC_TR_HU_Msk
#define RTC_TR_HU_0                         (0x1UL << RTC_TR_HU_Pos)                /*!< 0x00010000 */
#define RTC_TR_HU_1                         (0x2UL << RTC_TR_HU_Pos)                /*!< 0x00020000 */
#define RTC_TR_HU_2                         (0x4UL << RTC_TR_HU_Pos)                /*!< 0x00040000 */
#define RTC_TR_HU_3                         (0x8UL << RTC_TR_HU_Pos)                /*!< 0x00080000 */
#define RTC_TR_HT_Pos                       (20UL)
#define RTC_TR_HT_Msk                       (0x3UL << RTC_TR_HT_Pos)                /*!< 0x00300000 */
#define RTC_TR_HT                           RTC_TR_HT_Msk
#define RTC_TR_HT_0                         (0x1UL << RTC_TR_HT_Pos)                /*!< 0x00100000 */
#define RTC_TR_HT_1                         (0x2UL << RTC_TR_HT_Pos)                /*!< 0x00200000 */
#define RTC_TR_PM_Pos                       (22UL)
#define RTC_TR_PM_Msk                       (0x1UL << RTC_TR_PM_Pos)                /*!< 0x00400000 */
#define RTC_TR_PM                           RTC_TR_PM_Msk

/********************  Bits definition for RTC_DR register  *******************/
#define RTC_DR_DU_Pos                       (0UL)
#define RTC_DR_DU_Msk                       (0xFUL << RTC_DR_DU_Pos)                /*!< 0x0000000F */
#define RTC_DR_DU                           RTC_DR_DU_Msk
#define RTC_DR_DU_0                         (0x1UL << RTC_DR_DU_Pos)                /*!< 0x00000001 */
#define RTC_DR_DU_1                         (0x2UL << RTC_DR_DU_Pos)                /*!< 0x00000002 */
#define RTC_DR_DU_2                         (0x4UL << RTC_DR_DU_Pos)                /*!< 0x00000004 */
#define RTC_DR_DU_3                         (0x8UL << RTC_DR_DU_Pos)                /*!< 0x00000008 */
#define RTC_DR_DT_Pos                       (4UL)
#define RTC_DR_DT_Msk                       (0x3UL << RTC_DR_DT_Pos)                /*!< 0x00000030 */
#define RTC_DR_DT                           RTC_DR_DT_Msk
#define RTC_DR_DT_0                         (0x1UL << RTC_DR_DT_Pos)                /*!< 0x00000010 */
#define RTC_DR_DT_1                         (0x2UL << RTC_DR_DT_Pos)                /*!< 0x00000020 */
#define RTC_DR_MU_Pos                       (8UL)
#define RTC_DR_MU_Msk                       (0xFUL << RTC_DR_MU_Pos)                /*!< 0x00000F00 */
#define RTC_DR_MU                           RTC_DR_MU_Msk
#define RTC_DR_MU_0                         (0x1UL << RTC_DR_MU_Pos)                /*!< 0x00000100 */
#define RTC_DR_MU_1                         (0x2UL << RTC_DR_MU_Pos)                /*!< 0x00000200 */
#define RTC_DR_MU_2                         (0x4UL << RTC_DR_MU_Pos)                /*!< 0x00000400 */
#define RTC_DR_MU_3                         (0x8UL << RTC_DR_MU_Pos)                /*!< 0x00000800 */
#define RTC_DR_MT_Pos                       (12UL)
#define RTC_DR_MT_Msk                       (0x1UL << RTC_DR_MT_Pos)                /*!< 0x00001000 */
#define RTC_DR_MT                           RTC_DR_MT_Msk
#define RTC_DR_WDU_Pos                      (13UL)
#define RTC_DR_WDU_Msk                      (0x7UL << RTC_DR_WDU_Pos)               /*!< 0x0000E000 */
#define RTC_DR_WDU                          RTC_DR_WDU_Msk
#define RTC_DR_WDU_0                        (0x1UL << RTC_DR_WDU_Pos)               /*!< 0x00002000 */
#define RTC_DR_WDU_1                        (0x2UL << RTC_DR_WDU_Pos)               /*!< 0x00004000 */
#define RTC_DR_WDU_2                        (0x4UL << RTC_DR_WDU_Pos)               /*!< 0x00008000 */
#define RTC_DR_YU_Pos                       (16UL)
#define RTC_DR_YU_Msk                       (0xFUL << RTC_DR_YU_Pos)                /*!< 0x000F0000 */
#define RTC_DR_YU                           RTC_DR_YU_Msk
#define RTC_DR_YU_0                         (0x1UL << RTC_DR_YU_Pos)                /*!< 0x00010000 */
#define RTC_DR_YU_1                         (0x2UL << RTC_DR_YU_Pos)                /*!< 0x00020000 */
#define RTC_DR_YU_2                         (0x4UL << RTC_DR_YU_Pos)                /*!< 0x00040000 */
#define RTC_DR_YU_3                         (0x8UL << RTC_DR_YU_Pos)                /*!< 0x00080000 */
#define RTC_DR_YT_Pos                       (20UL)
#define RTC_DR_YT_Msk                       (0xFUL << RTC_DR_YT_Pos)                /*!< 0x00F00000 */
#define RTC_DR_YT                           RTC_DR_YT_Msk
#define RTC_DR_YT_0                         (0x1UL << RTC_DR_YT_Pos)                /*!< 0x00100000 */
#define RTC_DR_YT_1                         (0x2UL << RTC_DR_YT_Pos)                /*!< 0x00200000 */
#define RTC_DR_YT_2                         (0x4UL << RTC_DR_YT_Pos)                /*!< 0x00400000 */
#define RTC_DR_YT_3                         (0x8UL << RTC_DR_YT_Pos)                /*!< 0x00800000 */

/********************  Bits definition for RTC_SSR register  ******************/
#define RTC_SSR_SS_Pos                      (0UL)
#define RTC_SSR_SS_Msk                      (0xFFFFFFFFUL << RTC_SSR_SS_Pos)        /*!< 0xFFFFFFFF */
#define RTC_SSR_SS                          RTC_SSR_SS_Msk

/********************  Bits definition for RTC_ICSR register  ******************/
#define RTC_ICSR_WUTWF_Pos                  (2UL)
#define RTC_ICSR_WUTWF_Msk                  (0x1UL << RTC_ICSR_WUTWF_Pos)           /*!< 0x00000004 */
#define RTC_ICSR_WUTWF                      RTC_ICSR_WUTWF_Msk
#define RTC_ICSR_SHPF_Pos                   (3UL)
#define RTC_ICSR_SHPF_Msk                   (0x1UL << RTC_ICSR_SHPF_Pos)            /*!< 0x00000008 */
#define RTC_ICSR_SHPF                       RTC_ICSR_SHPF_Msk
#define RTC_ICSR_INITS_Pos                  (4UL)
#define RTC_ICSR_INITS_Msk                  (0x1UL << RTC_ICSR_INITS_Pos)           /*!< 0x00000010 */
#define RTC_ICSR_INITS                      RTC_ICSR_INITS_Msk
#define RTC_ICSR_RSF_Pos                    (5UL)
#define RTC_ICSR_RSF_Msk                    (0x1UL << RTC_ICSR_RSF_Pos)             /*!< 0x00000020 */
#define RTC_ICSR_RSF                        RTC_ICSR_RSF_Msk
#define RTC_ICSR_INITF_Pos                  (6UL)
#define RTC_ICSR_INITF_Msk                  (0x1UL << RTC_ICSR_INITF_Pos)           /*!< 0x00000040 */
#define RTC_ICSR_INITF                      RTC_ICSR_INITF_Msk
#define RTC_ICSR_INIT_Pos                   (7UL)
#define RTC_ICSR_INIT_Msk                   (0x1UL << RTC_ICSR_INIT_Pos)            /*!< 0x00000080 */
#define RTC_ICSR_INIT                       RTC_ICSR_INIT_Msk
#define RTC_ICSR_BIN_Pos                    (8UL)
#define RTC_ICSR_BIN_Msk                    (0x3UL << RTC_ICSR_BIN_Pos)             /*!< 0x00000300 */
#define RTC_ICSR_BIN                        RTC_ICSR_BIN_Msk
#define RTC_ICSR_BIN_0                      (0x1UL << RTC_ICSR_BIN_Pos)             /*!< 0x00000100 */
#define RTC_ICSR_BIN_1                      (0x2UL << RTC_ICSR_BIN_Pos)             /*!< 0x00000200 */
#define RTC_ICSR_BCDU_Pos                   (10UL)
#define RTC_ICSR_BCDU_Msk                   (0x7UL << RTC_ICSR_BCDU_Pos)            /*!< 0x00001C00 */
#define RTC_ICSR_BCDU                       RTC_ICSR_BCDU_Msk
#define RTC_ICSR_BCDU_0                     (0x1UL << RTC_ICSR_BCDU_Pos)            /*!< 0x00000400 */
#define RTC_ICSR_BCDU_1                     (0x2UL << RTC_ICSR_BCDU_Pos)            /*!< 0x00000800 */
#define RTC_ICSR_BCDU_2                     (0x4UL << RTC_ICSR_BCDU_Pos)            /*!< 0x00001000 */
#define RTC_ICSR_RECALPF_Pos                (16UL)
#define RTC_ICSR_RECALPF_Msk                (0x1UL << RTC_ICSR_RECALPF_Pos)         /*!< 0x00010000 */
#define RTC_ICSR_RECALPF                    RTC_ICSR_RECALPF_Msk

/********************  Bits definition for RTC_PRER register  *****************/
#define RTC_PRER_PREDIV_S_Pos               (0UL)
#define RTC_PRER_PREDIV_S_Msk               (0x7FFFUL << RTC_PRER_PREDIV_S_Pos)     /*!< 0x00007FFF */
#define RTC_PRER_PREDIV_S                   RTC_PRER_PREDIV_S_Msk
#define RTC_PRER_PREDIV_A_Pos               (16UL)
#define RTC_PRER_PREDIV_A_Msk               (0x7FUL << RTC_PRER_PREDIV_A_Pos)       /*!< 0x007F0000 */
#define RTC_PRER_PREDIV_A                   RTC_PRER_PREDIV_A_Msk

/********************  Bits definition for RTC_WUTR register  *****************/
#define RTC_WUTR_WUT_Pos                    (0UL)
#define RTC_WUTR_WUT_Msk                    (0xFFFFUL << RTC_WUTR_WUT_Pos)          /*!< 0x0000FFFF */
#define RTC_WUTR_WUT                        RTC_WUTR_WUT_Msk
#define RTC_WUTR_WUTOCLR_Pos                (16UL)
#define RTC_WUTR_WUTOCLR_Msk                (0xFFFFUL << RTC_WUTR_WUTOCLR_Pos)      /*!< 0x0000FFFF */
#define RTC_WUTR_WUTOCLR                    RTC_WUTR_WUTOCLR_Msk

/********************  Bits definition for RTC_CR register  *******************/
#define RTC_CR_WUCKSEL_Pos                  (0UL)
#define RTC_CR_WUCKSEL_Msk                  (0x7UL << RTC_CR_WUCKSEL_Pos)           /*!< 0x00000007 */
#define RTC_CR_WUCKSEL                      RTC_CR_WUCKSEL_Msk
#define RTC_CR_WUCKSEL_0                    (0x1UL << RTC_CR_WUCKSEL_Pos)           /*!< 0x00000001 */
#define RTC_CR_WUCKSEL_1                    (0x2UL << RTC_CR_WUCKSEL_Pos)           /*!< 0x00000002 */
#define RTC_CR_WUCKSEL_2                    (0x4UL << RTC_CR_WUCKSEL_Pos)           /*!< 0x00000004 */
#define RTC_CR_TSEDGE_Pos                   (3UL)
#define RTC_CR_TSEDGE_Msk                   (0x1UL << RTC_CR_TSEDGE_Pos)            /*!< 0x00000008 */
#define RTC_CR_TSEDGE                       RTC_CR_TSEDGE_Msk
#define RTC_CR_REFCKON_Pos                  (4UL)
#define RTC_CR_REFCKON_Msk                  (0x1UL << RTC_CR_REFCKON_Pos)           /*!< 0x00000010 */
#define RTC_CR_REFCKON                      RTC_CR_REFCKON_Msk
#define RTC_CR_BYPSHAD_Pos                  (5UL)
#define RTC_CR_BYPSHAD_Msk                  (0x1UL << RTC_CR_BYPSHAD_Pos)           /*!< 0x00000020 */
#define RTC_CR_BYPSHAD                      RTC_CR_BYPSHAD_Msk
#define RTC_CR_FMT_Pos                      (6UL)
#define RTC_CR_FMT_Msk                      (0x1UL << RTC_CR_FMT_Pos)               /*!< 0x00000040 */
#define RTC_CR_FMT                          RTC_CR_FMT_Msk
#define RTC_CR_SSRUIE_Pos                   (7UL)
#define RTC_CR_SSRUIE_Msk                   (0x1UL << RTC_CR_SSRUIE_Pos)            /*!< 0x00000080 */
#define RTC_CR_SSRUIE                       RTC_CR_SSRUIE_Msk
#define RTC_CR_ALRAE_Pos                    (8UL)
#define RTC_CR_ALRAE_Msk                    (0x1UL << RTC_CR_ALRAE_Pos)             /*!< 0x00000100 */
#define RTC_CR_ALRAE                        RTC_CR_ALRAE_Msk
#define RTC_CR_ALRBE_Pos                    (9UL)
#define RTC_CR_ALRBE_Msk                    (0x1UL << RTC_CR_ALRBE_Pos)             /*!< 0x00000200 */
#define RTC_CR_ALRBE                        RTC_CR_ALRBE_Msk
#define RTC_CR_WUTE_Pos                     (10UL)
#define RTC_CR_WUTE_Msk                     (0x1UL << RTC_CR_WUTE_Pos)              /*!< 0x00000400 */
#define RTC_CR_WUTE                         RTC_CR_WUTE_Msk
#define RTC_CR_TSE_Pos                      (11UL)
#define RTC_CR_TSE_Msk                      (0x1UL << RTC_CR_TSE_Pos)               /*!< 0x00000800 */
#define RTC_CR_TSE                          RTC_CR_TSE_Msk
#define RTC_CR_ALRAIE_Pos                   (12UL)
#define RTC_CR_ALRAIE_Msk                   (0x1UL << RTC_CR_ALRAIE_Pos)            /*!< 0x00001000 */
#define RTC_CR_ALRAIE                       RTC_CR_ALRAIE_Msk
#define RTC_CR_ALRBIE_Pos                   (13UL)
#define RTC_CR_ALRBIE_Msk                   (0x1UL << RTC_CR_ALRBIE_Pos)            /*!< 0x00002000 */
#define RTC_CR_ALRBIE                       RTC_CR_ALRBIE_Msk
#define RTC_CR_WUTIE_Pos                    (14UL)
#define RTC_CR_WUTIE_Msk                    (0x1UL << RTC_CR_WUTIE_Pos)             /*!< 0x00004000 */
#define RTC_CR_WUTIE                        RTC_CR_WUTIE_Msk
#define RTC_CR_TSIE_Pos                     (15UL)
#define RTC_CR_TSIE_Msk                     (0x1UL << RTC_CR_TSIE_Pos)              /*!< 0x00008000 */
#define RTC_CR_TSIE                         RTC_CR_TSIE_Msk
#define RTC_CR_ADD1H_Pos                    (16UL)
#define RTC_CR_ADD1H_Msk                    (0x1UL << RTC_CR_ADD1H_Pos)             /*!< 0x00010000 */
#define RTC_CR_ADD1H                        RTC_CR_ADD1H_Msk
#define RTC_CR_SUB1H_Pos                    (17UL)
#define RTC_CR_SUB1H_Msk                    (0x1UL << RTC_CR_SUB1H_Pos)             /*!< 0x00020000 */
#define RTC_CR_SUB1H                        RTC_CR_SUB1H_Msk
#define RTC_CR_BKP_Pos                      (18UL)
#define RTC_CR_BKP_Msk                      (0x1UL << RTC_CR_BKP_Pos)               /*!< 0x00040000 */
#define RTC_CR_BKP                          RTC_CR_BKP_Msk
#define RTC_CR_COSEL_Pos                    (19UL)
#define RTC_CR_COSEL_Msk                    (0x1UL << RTC_CR_COSEL_Pos)             /*!< 0x00080000 */
#define RTC_CR_COSEL                        RTC_CR_COSEL_Msk
#define RTC_CR_POL_Pos                      (20UL)
#define RTC_CR_POL_Msk                      (0x1UL << RTC_CR_POL_Pos)               /*!< 0x00100000 */
#define RTC_CR_POL                          RTC_CR_POL_Msk
#define RTC_CR_OSEL_Pos                     (21UL)
#define RTC_CR_OSEL_Msk                     (0x3UL << RTC_CR_OSEL_Pos)              /*!< 0x00600000 */
#define RTC_CR_OSEL                         RTC_CR_OSEL_Msk
#define RTC_CR_OSEL_0                       (0x1UL << RTC_CR_OSEL_Pos)              /*!< 0x00200000 */
#define RTC_CR_OSEL_1                       (0x2UL << RTC_CR_OSEL_Pos)              /*!< 0x00400000 */
#define RTC_CR_COE_Pos                      (23UL)
#define RTC_CR_COE_Msk                      (0x1UL << RTC_CR_COE_Pos)               /*!< 0x00800000 */
#define RTC_CR_COE                          RTC_CR_COE_Msk
#define RTC_CR_ITSE_Pos                     (24UL)
#define RTC_CR_ITSE_Msk                     (0x1UL << RTC_CR_ITSE_Pos)              /*!< 0x01000000 */
#define RTC_CR_ITSE                         RTC_CR_ITSE_Msk                         /*!<Timestamp on internal event enable  */
#define RTC_CR_TAMPTS_Pos                   (25UL)
#define RTC_CR_TAMPTS_Msk                   (0x1UL << RTC_CR_TAMPTS_Pos)            /*!< 0x02000000 */
#define RTC_CR_TAMPTS                       RTC_CR_TAMPTS_Msk                       /*!<Activate timestamp on tamper detection event  */
#define RTC_CR_TAMPOE_Pos                   (26UL)
#define RTC_CR_TAMPOE_Msk                   (0x1UL << RTC_CR_TAMPOE_Pos)            /*!< 0x04000000 */
#define RTC_CR_TAMPOE                       RTC_CR_TAMPOE_Msk                       /*!<Tamper detection output enable on TAMPALARM  */
#define RTC_CR_ALRAFCLR_Pos                 (27UL)
#define RTC_CR_ALRAFCLR_Msk                 (0x1UL << RTC_CR_ALRAFCLR_Pos)          /*!< 0x8000000 */
#define RTC_CR_ALRAFCLR                     RTC_CR_ALRAFCLR_Msk                     /*!<Alarm A mask */
#define RTC_CR_ALRBFCLR_Pos                 (28UL)
#define RTC_CR_ALRBFCLR_Msk                 (0x1UL << RTC_CR_ALRBFCLR_Pos)          /*!< 0x10000000 */
#define RTC_CR_ALRBFCLR                     RTC_CR_ALRBFCLR_Msk                     /*!<Alarm B mask */
#define RTC_CR_TAMPALRM_PU_Pos              (29UL)
#define RTC_CR_TAMPALRM_PU_Msk              (0x1UL << RTC_CR_TAMPALRM_PU_Pos)       /*!< 0x20000000 */
#define RTC_CR_TAMPALRM_PU                  RTC_CR_TAMPALRM_PU_Msk                  /*!<TAMPALARM output pull-up config */
#define RTC_CR_TAMPALRM_TYPE_Pos            (30UL)
#define RTC_CR_TAMPALRM_TYPE_Msk            (0x1UL << RTC_CR_TAMPALRM_TYPE_Pos)     /*!< 0x40000000 */
#define RTC_CR_TAMPALRM_TYPE                RTC_CR_TAMPALRM_TYPE_Msk                /*!<TAMPALARM output type  */
#define RTC_CR_OUT2EN_Pos                   (31UL)
#define RTC_CR_OUT2EN_Msk                   (0x1UL << RTC_CR_OUT2EN_Pos)            /*!< 0x80000000 */
#define RTC_CR_OUT2EN                       RTC_CR_OUT2EN_Msk                       /*!<RTC_OUT2 output enable */

/********************  Bits definition for RTC_PRIVCFGR register  *****************/
#define RTC_PRIVCFGR_ALRAPRIV_Pos           (0UL)
#define RTC_PRIVCFGR_ALRAPRIV_Msk           (0x1UL << RTC_PRIVCFGR_ALRAPRIV_Pos)    /*!< 0x00000001 */
#define RTC_PRIVCFGR_ALRAPRIV               RTC_PRIVCFGR_ALRAPRIV_Msk
#define RTC_PRIVCFGR_ALRBPRIV_Pos           (1UL)
#define RTC_PRIVCFGR_ALRBPRIV_Msk           (0x1UL << RTC_PRIVCFGR_ALRBPRIV_Pos)    /*!< 0x00000002 */
#define RTC_PRIVCFGR_ALRBPRIV               RTC_PRIVCFGR_ALRBPRIV_Msk
#define RTC_PRIVCFGR_WUTPRIV_Pos            (2UL)
#define RTC_PRIVCFGR_WUTPRIV_Msk            (0x1UL << RTC_PRIVCFGR_WUTPRIV_Pos)     /*!< 0x00000004 */
#define RTC_PRIVCFGR_WUTPRIV                RTC_PRIVCFGR_WUTPRIV_Msk
#define RTC_PRIVCFGR_TSPRIV_Pos             (3UL)
#define RTC_PRIVCFGR_TSPRIV_Msk             (0x1UL << RTC_PRIVCFGR_TSPRIV_Pos)      /*!< 0x00000008 */
#define RTC_PRIVCFGR_TSPRIV                 RTC_PRIVCFGR_TSPRIV_Msk
#define RTC_PRIVCFGR_CALPRIV_Pos            (13UL)
#define RTC_PRIVCFGR_CALPRIV_Msk            (0x1UL << RTC_PRIVCFGR_CALPRIV_Pos)     /*!< 0x00002000 */
#define RTC_PRIVCFGR_CALPRIV                RTC_PRIVCFGR_CALPRIV_Msk
#define RTC_PRIVCFGR_INITPRIV_Pos           (14UL)
#define RTC_PRIVCFGR_INITPRIV_Msk           (0x1UL << RTC_PRIVCFGR_INITPRIV_Pos)    /*!< 0x00004000 */
#define RTC_PRIVCFGR_INITPRIV               RTC_PRIVCFGR_INITPRIV_Msk
#define RTC_PRIVCFGR_PRIV_Pos               (15UL)
#define RTC_PRIVCFGR_PRIV_Msk               (0x1UL << RTC_PRIVCFGR_PRIV_Pos)        /*!< 0x00008000 */
#define RTC_PRIVCFGR_PRIV                   RTC_PRIVCFGR_PRIV_Msk

/********************  Bits definition for RTC_SECCFGR register  ******************/
#define RTC_SECCFGR_ALRASEC_Pos             (0UL)
#define RTC_SECCFGR_ALRASEC_Msk             (0x1UL << RTC_SECCFGR_ALRASEC_Pos)      /*!< 0x00000001 */
#define RTC_SECCFGR_ALRASEC                 RTC_SECCFGR_ALRASEC_Msk
#define RTC_SECCFGR_ALRBSEC_Pos             (1UL)
#define RTC_SECCFGR_ALRBSEC_Msk             (0x1UL << RTC_SECCFGR_ALRBSEC_Pos)      /*!< 0x00000002 */
#define RTC_SECCFGR_ALRBSEC                 RTC_SECCFGR_ALRBSEC_Msk
#define RTC_SECCFGR_WUTSEC_Pos              (2UL)
#define RTC_SECCFGR_WUTSEC_Msk              (0x1UL << RTC_SECCFGR_WUTSEC_Pos)       /*!< 0x00000004 */
#define RTC_SECCFGR_WUTSEC                  RTC_SECCFGR_WUTSEC_Msk
#define RTC_SECCFGR_TSSEC_Pos               (3UL)
#define RTC_SECCFGR_TSSEC_Msk               (0x1UL << RTC_SECCFGR_TSSEC_Pos)        /*!< 0x00000008 */
#define RTC_SECCFGR_TSSEC                   RTC_SECCFGR_TSSEC_Msk
#define RTC_SECCFGR_CALSEC_Pos              (13UL)
#define RTC_SECCFGR_CALSEC_Msk              (0x1UL << RTC_SECCFGR_CALSEC_Pos)       /*!< 0x00002000 */
#define RTC_SECCFGR_CALSEC                  RTC_SECCFGR_CALSEC_Msk
#define RTC_SECCFGR_INITSEC_Pos             (14UL)
#define RTC_SECCFGR_INITSEC_Msk             (0x1UL << RTC_SECCFGR_INITSEC_Pos)      /*!< 0x00004000 */
#define RTC_SECCFGR_INITSEC                 RTC_SECCFGR_INITSEC_Msk
#define RTC_SECCFGR_SEC_Pos                 (15UL)
#define RTC_SECCFGR_SEC_Msk                 (0x1UL << RTC_SECCFGR_SEC_Pos)          /*!< 0x00008000 */
#define RTC_SECCFGR_SEC                     RTC_SECCFGR_SEC_Msk

/********************  Bits definition for RTC_WPR register  ******************/
#define RTC_WPR_KEY_Pos                     (0UL)
#define RTC_WPR_KEY_Msk                     (0xFFUL << RTC_WPR_KEY_Pos)             /*!< 0x000000FF */
#define RTC_WPR_KEY                         RTC_WPR_KEY_Msk

/********************  Bits definition for RTC_CALR register  *****************/
#define RTC_CALR_CALM_Pos                   (0UL)
#define RTC_CALR_CALM_Msk                   (0x1FFUL << RTC_CALR_CALM_Pos)          /*!< 0x000001FF */
#define RTC_CALR_CALM                       RTC_CALR_CALM_Msk
#define RTC_CALR_CALM_0                     (0x001UL << RTC_CALR_CALM_Pos)          /*!< 0x00000001 */
#define RTC_CALR_CALM_1                     (0x002UL << RTC_CALR_CALM_Pos)          /*!< 0x00000002 */
#define RTC_CALR_CALM_2                     (0x004UL << RTC_CALR_CALM_Pos)          /*!< 0x00000004 */
#define RTC_CALR_CALM_3                     (0x008UL << RTC_CALR_CALM_Pos)          /*!< 0x00000008 */
#define RTC_CALR_CALM_4                     (0x010UL << RTC_CALR_CALM_Pos)          /*!< 0x00000010 */
#define RTC_CALR_CALM_5                     (0x020UL << RTC_CALR_CALM_Pos)          /*!< 0x00000020 */
#define RTC_CALR_CALM_6                     (0x040UL << RTC_CALR_CALM_Pos)          /*!< 0x00000040 */
#define RTC_CALR_CALM_7                     (0x080UL << RTC_CALR_CALM_Pos)          /*!< 0x00000080 */
#define RTC_CALR_CALM_8                     (0x100UL << RTC_CALR_CALM_Pos)          /*!< 0x00000100 */
#define RTC_CALR_LPCAL_Pos                  (12UL)
#define RTC_CALR_LPCAL_Msk                  (0x1UL << RTC_CALR_LPCAL_Pos)           /*!< 0x00001000 */
#define RTC_CALR_CALW16                     RTC_CALR_CALW16_Msk
#define RTC_CALR_CALW16_Pos                 (13UL)
#define RTC_CALR_CALW16_Msk                 (0x1UL << RTC_CALR_CALW16_Pos)          /*!< 0x00002000 */
#define RTC_CALR_LPCAL                      RTC_CALR_LPCAL_Msk
#define RTC_CALR_CALW8_Pos                  (14UL)
#define RTC_CALR_CALW8_Msk                  (0x1UL << RTC_CALR_CALW8_Pos)           /*!< 0x00004000 */
#define RTC_CALR_CALW8                      RTC_CALR_CALW8_Msk
#define RTC_CALR_CALP_Pos                   (15UL)
#define RTC_CALR_CALP_Msk                   (0x1UL << RTC_CALR_CALP_Pos)            /*!< 0x00008000 */
#define RTC_CALR_CALP                       RTC_CALR_CALP_Msk

/********************  Bits definition for RTC_SHIFTR register  ***************/
#define RTC_SHIFTR_SUBFS_Pos                (0UL)
#define RTC_SHIFTR_SUBFS_Msk                (0x7FFFUL << RTC_SHIFTR_SUBFS_Pos)      /*!< 0x00007FFF */
#define RTC_SHIFTR_SUBFS                    RTC_SHIFTR_SUBFS_Msk
#define RTC_SHIFTR_ADD1S_Pos                (31UL)
#define RTC_SHIFTR_ADD1S_Msk                (0x1UL << RTC_SHIFTR_ADD1S_Pos)         /*!< 0x80000000 */
#define RTC_SHIFTR_ADD1S                    RTC_SHIFTR_ADD1S_Msk

/********************  Bits definition for RTC_TSTR register  *****************/
#define RTC_TSTR_SU_Pos                     (0UL)
#define RTC_TSTR_SU_Msk                     (0xFUL << RTC_TSTR_SU_Pos)              /*!< 0x0000000F */
#define RTC_TSTR_SU                         RTC_TSTR_SU_Msk
#define RTC_TSTR_SU_0                       (0x1UL << RTC_TSTR_SU_Pos)              /*!< 0x00000001 */
#define RTC_TSTR_SU_1                       (0x2UL << RTC_TSTR_SU_Pos)              /*!< 0x00000002 */
#define RTC_TSTR_SU_2                       (0x4UL << RTC_TSTR_SU_Pos)              /*!< 0x00000004 */
#define RTC_TSTR_SU_3                       (0x8UL << RTC_TSTR_SU_Pos)              /*!< 0x00000008 */
#define RTC_TSTR_ST_Pos                     (4UL)
#define RTC_TSTR_ST_Msk                     (0x7UL << RTC_TSTR_ST_Pos)              /*!< 0x00000070 */
#define RTC_TSTR_ST                         RTC_TSTR_ST_Msk
#define RTC_TSTR_ST_0                       (0x1UL << RTC_TSTR_ST_Pos)              /*!< 0x00000010 */
#define RTC_TSTR_ST_1                       (0x2UL << RTC_TSTR_ST_Pos)              /*!< 0x00000020 */
#define RTC_TSTR_ST_2                       (0x4UL << RTC_TSTR_ST_Pos)              /*!< 0x00000040 */
#define RTC_TSTR_MNU_Pos                    (8UL)
#define RTC_TSTR_MNU_Msk                    (0xFUL << RTC_TSTR_MNU_Pos)             /*!< 0x00000F00 */
#define RTC_TSTR_MNU                        RTC_TSTR_MNU_Msk
#define RTC_TSTR_MNU_0                      (0x1UL << RTC_TSTR_MNU_Pos)             /*!< 0x00000100 */
#define RTC_TSTR_MNU_1                      (0x2UL << RTC_TSTR_MNU_Pos)             /*!< 0x00000200 */
#define RTC_TSTR_MNU_2                      (0x4UL << RTC_TSTR_MNU_Pos)             /*!< 0x00000400 */
#define RTC_TSTR_MNU_3                      (0x8UL << RTC_TSTR_MNU_Pos)             /*!< 0x00000800 */
#define RTC_TSTR_MNT_Pos                    (12UL)
#define RTC_TSTR_MNT_Msk                    (0x7UL << RTC_TSTR_MNT_Pos)             /*!< 0x00007000 */
#define RTC_TSTR_MNT                        RTC_TSTR_MNT_Msk
#define RTC_TSTR_MNT_0                      (0x1UL << RTC_TSTR_MNT_Pos)             /*!< 0x00001000 */
#define RTC_TSTR_MNT_1                      (0x2UL << RTC_TSTR_MNT_Pos)             /*!< 0x00002000 */
#define RTC_TSTR_MNT_2                      (0x4UL << RTC_TSTR_MNT_Pos)             /*!< 0x00004000 */
#define RTC_TSTR_HU_Pos                     (16UL)
#define RTC_TSTR_HU_Msk                     (0xFUL << RTC_TSTR_HU_Pos)              /*!< 0x000F0000 */
#define RTC_TSTR_HU                         RTC_TSTR_HU_Msk
#define RTC_TSTR_HU_0                       (0x1UL << RTC_TSTR_HU_Pos)              /*!< 0x00010000 */
#define RTC_TSTR_HU_1                       (0x2UL << RTC_TSTR_HU_Pos)              /*!< 0x00020000 */
#define RTC_TSTR_HU_2                       (0x4UL << RTC_TSTR_HU_Pos)              /*!< 0x00040000 */
#define RTC_TSTR_HU_3                       (0x8UL << RTC_TSTR_HU_Pos)              /*!< 0x00080000 */
#define RTC_TSTR_HT_Pos                     (20UL)
#define RTC_TSTR_HT_Msk                     (0x3UL << RTC_TSTR_HT_Pos)              /*!< 0x00300000 */
#define RTC_TSTR_HT                         RTC_TSTR_HT_Msk
#define RTC_TSTR_HT_0                       (0x1UL << RTC_TSTR_HT_Pos)              /*!< 0x00100000 */
#define RTC_TSTR_HT_1                       (0x2UL << RTC_TSTR_HT_Pos)              /*!< 0x00200000 */
#define RTC_TSTR_PM_Pos                     (22UL)
#define RTC_TSTR_PM_Msk                     (0x1UL << RTC_TSTR_PM_Pos)              /*!< 0x00400000 */
#define RTC_TSTR_PM                         RTC_TSTR_PM_Msk

/********************  Bits definition for RTC_TSDR register  *****************/
#define RTC_TSDR_DU_Pos                     (0UL)
#define RTC_TSDR_DU_Msk                     (0xFUL << RTC_TSDR_DU_Pos)              /*!< 0x0000000F */
#define RTC_TSDR_DU                         RTC_TSDR_DU_Msk
#define RTC_TSDR_DU_0                       (0x1UL << RTC_TSDR_DU_Pos)              /*!< 0x00000001 */
#define RTC_TSDR_DU_1                       (0x2UL << RTC_TSDR_DU_Pos)              /*!< 0x00000002 */
#define RTC_TSDR_DU_2                       (0x4UL << RTC_TSDR_DU_Pos)              /*!< 0x00000004 */
#define RTC_TSDR_DU_3                       (0x8UL << RTC_TSDR_DU_Pos)              /*!< 0x00000008 */
#define RTC_TSDR_DT_Pos                     (4UL)
#define RTC_TSDR_DT_Msk                     (0x3UL << RTC_TSDR_DT_Pos)              /*!< 0x00000030 */
#define RTC_TSDR_DT                         RTC_TSDR_DT_Msk
#define RTC_TSDR_DT_0                       (0x1UL << RTC_TSDR_DT_Pos)              /*!< 0x00000010 */
#define RTC_TSDR_DT_1                       (0x2UL << RTC_TSDR_DT_Pos)              /*!< 0x00000020 */
#define RTC_TSDR_MU_Pos                     (8UL)
#define RTC_TSDR_MU_Msk                     (0xFUL << RTC_TSDR_MU_Pos)              /*!< 0x00000F00 */
#define RTC_TSDR_MU                         RTC_TSDR_MU_Msk
#define RTC_TSDR_MU_0                       (0x1UL << RTC_TSDR_MU_Pos)              /*!< 0x00000100 */
#define RTC_TSDR_MU_1                       (0x2UL << RTC_TSDR_MU_Pos)              /*!< 0x00000200 */
#define RTC_TSDR_MU_2                       (0x4UL << RTC_TSDR_MU_Pos)              /*!< 0x00000400 */
#define RTC_TSDR_MU_3                       (0x8UL << RTC_TSDR_MU_Pos)              /*!< 0x00000800 */
#define RTC_TSDR_MT_Pos                     (12UL)
#define RTC_TSDR_MT_Msk                     (0x1UL << RTC_TSDR_MT_Pos)              /*!< 0x00001000 */
#define RTC_TSDR_MT                         RTC_TSDR_MT_Msk
#define RTC_TSDR_WDU_Pos                    (13UL)
#define RTC_TSDR_WDU_Msk                    (0x7UL << RTC_TSDR_WDU_Pos)             /*!< 0x0000E000 */
#define RTC_TSDR_WDU                        RTC_TSDR_WDU_Msk
#define RTC_TSDR_WDU_0                      (0x1UL << RTC_TSDR_WDU_Pos)             /*!< 0x00002000 */
#define RTC_TSDR_WDU_1                      (0x2UL << RTC_TSDR_WDU_Pos)             /*!< 0x00004000 */
#define RTC_TSDR_WDU_2                      (0x4UL << RTC_TSDR_WDU_Pos)             /*!< 0x00008000 */

/********************  Bits definition for RTC_TSSSR register  ****************/
#define RTC_TSSSR_SS_Pos                    (0UL)
#define RTC_TSSSR_SS_Msk                    (0xFFFFFFFFUL << RTC_TSSSR_SS_Pos)      /*!< 0xFFFFFFFF */
#define RTC_TSSSR_SS                        RTC_TSSSR_SS_Msk                        /*!< rtc timestamp sub second > */

/********************  Bits definition for RTC_ALRMAR register  ***************/
#define RTC_ALRMAR_SU_Pos                   (0UL)
#define RTC_ALRMAR_SU_Msk                   (0xFUL << RTC_ALRMAR_SU_Pos)            /*!< 0x0000000F */
#define RTC_ALRMAR_SU                       RTC_ALRMAR_SU_Msk
#define RTC_ALRMAR_SU_0                     (0x1UL << RTC_ALRMAR_SU_Pos)            /*!< 0x00000001 */
#define RTC_ALRMAR_SU_1                     (0x2UL << RTC_ALRMAR_SU_Pos)            /*!< 0x00000002 */
#define RTC_ALRMAR_SU_2                     (0x4UL << RTC_ALRMAR_SU_Pos)            /*!< 0x00000004 */
#define RTC_ALRMAR_SU_3                     (0x8UL << RTC_ALRMAR_SU_Pos)            /*!< 0x00000008 */
#define RTC_ALRMAR_ST_Pos                   (4UL)
#define RTC_ALRMAR_ST_Msk                   (0x7UL << RTC_ALRMAR_ST_Pos)            /*!< 0x00000070 */
#define RTC_ALRMAR_ST                       RTC_ALRMAR_ST_Msk
#define RTC_ALRMAR_ST_0                     (0x1UL << RTC_ALRMAR_ST_Pos)            /*!< 0x00000010 */
#define RTC_ALRMAR_ST_1                     (0x2UL << RTC_ALRMAR_ST_Pos)            /*!< 0x00000020 */
#define RTC_ALRMAR_ST_2                     (0x4UL << RTC_ALRMAR_ST_Pos)            /*!< 0x00000040 */
#define RTC_ALRMAR_MSK1_Pos                 (7UL)
#define RTC_ALRMAR_MSK1_Msk                 (0x1UL << RTC_ALRMAR_MSK1_Pos)          /*!< 0x00000080 */
#define RTC_ALRMAR_MSK1                     RTC_ALRMAR_MSK1_Msk
#define RTC_ALRMAR_MNU_Pos                  (8UL)
#define RTC_ALRMAR_MNU_Msk                  (0xFUL << RTC_ALRMAR_MNU_Pos)           /*!< 0x00000F00 */
#define RTC_ALRMAR_MNU                      RTC_ALRMAR_MNU_Msk
#define RTC_ALRMAR_MNU_0                    (0x1UL << RTC_ALRMAR_MNU_Pos)           /*!< 0x00000100 */
#define RTC_ALRMAR_MNU_1                    (0x2UL << RTC_ALRMAR_MNU_Pos)           /*!< 0x00000200 */
#define RTC_ALRMAR_MNU_2                    (0x4UL << RTC_ALRMAR_MNU_Pos)           /*!< 0x00000400 */
#define RTC_ALRMAR_MNU_3                    (0x8UL << RTC_ALRMAR_MNU_Pos)           /*!< 0x00000800 */
#define RTC_ALRMAR_MNT_Pos                  (12UL)
#define RTC_ALRMAR_MNT_Msk                  (0x7UL << RTC_ALRMAR_MNT_Pos)           /*!< 0x00007000 */
#define RTC_ALRMAR_MNT                      RTC_ALRMAR_MNT_Msk
#define RTC_ALRMAR_MNT_0                    (0x1UL << RTC_ALRMAR_MNT_Pos)           /*!< 0x00001000 */
#define RTC_ALRMAR_MNT_1                    (0x2UL << RTC_ALRMAR_MNT_Pos)           /*!< 0x00002000 */
#define RTC_ALRMAR_MNT_2                    (0x4UL << RTC_ALRMAR_MNT_Pos)           /*!< 0x00004000 */
#define RTC_ALRMAR_MSK2_Pos                 (15UL)
#define RTC_ALRMAR_MSK2_Msk                 (0x1UL << RTC_ALRMAR_MSK2_Pos)          /*!< 0x00008000 */
#define RTC_ALRMAR_MSK2                     RTC_ALRMAR_MSK2_Msk
#define RTC_ALRMAR_HU_Pos                   (16UL)
#define RTC_ALRMAR_HU_Msk                   (0xFUL << RTC_ALRMAR_HU_Pos)            /*!< 0x000F0000 */
#define RTC_ALRMAR_HU                       RTC_ALRMAR_HU_Msk
#define RTC_ALRMAR_HU_0                     (0x1UL << RTC_ALRMAR_HU_Pos)            /*!< 0x00010000 */
#define RTC_ALRMAR_HU_1                     (0x2UL << RTC_ALRMAR_HU_Pos)            /*!< 0x00020000 */
#define RTC_ALRMAR_HU_2                     (0x4UL << RTC_ALRMAR_HU_Pos)            /*!< 0x00040000 */
#define RTC_ALRMAR_HU_3                     (0x8UL << RTC_ALRMAR_HU_Pos)            /*!< 0x00080000 */
#define RTC_ALRMAR_HT_Pos                   (20UL)
#define RTC_ALRMAR_HT_Msk                   (0x3UL << RTC_ALRMAR_HT_Pos)            /*!< 0x00300000 */
#define RTC_ALRMAR_HT                       RTC_ALRMAR_HT_Msk
#define RTC_ALRMAR_HT_0                     (0x1UL << RTC_ALRMAR_HT_Pos)            /*!< 0x00100000 */
#define RTC_ALRMAR_HT_1                     (0x2UL << RTC_ALRMAR_HT_Pos)            /*!< 0x00200000 */
#define RTC_ALRMAR_PM_Pos                   (22UL)
#define RTC_ALRMAR_PM_Msk                   (0x1UL << RTC_ALRMAR_PM_Pos)            /*!< 0x00400000 */
#define RTC_ALRMAR_PM                       RTC_ALRMAR_PM_Msk
#define RTC_ALRMAR_MSK3_Pos                 (23UL)
#define RTC_ALRMAR_MSK3_Msk                 (0x1UL << RTC_ALRMAR_MSK3_Pos)          /*!< 0x00800000 */
#define RTC_ALRMAR_MSK3                     RTC_ALRMAR_MSK3_Msk
#define RTC_ALRMAR_DU_Pos                   (24UL)
#define RTC_ALRMAR_DU_Msk                   (0xFUL << RTC_ALRMAR_DU_Pos)            /*!< 0x0F000000 */
#define RTC_ALRMAR_DU                       RTC_ALRMAR_DU_Msk
#define RTC_ALRMAR_DU_0                     (0x1UL << RTC_ALRMAR_DU_Pos)            /*!< 0x01000000 */
#define RTC_ALRMAR_DU_1                     (0x2UL << RTC_ALRMAR_DU_Pos)            /*!< 0x02000000 */
#define RTC_ALRMAR_DU_2                     (0x4UL << RTC_ALRMAR_DU_Pos)            /*!< 0x04000000 */
#define RTC_ALRMAR_DU_3                     (0x8UL << RTC_ALRMAR_DU_Pos)            /*!< 0x08000000 */
#define RTC_ALRMAR_DT_Pos                   (28UL)
#define RTC_ALRMAR_DT_Msk                   (0x3UL << RTC_ALRMAR_DT_Pos)            /*!< 0x30000000 */
#define RTC_ALRMAR_DT                       RTC_ALRMAR_DT_Msk
#define RTC_ALRMAR_DT_0                     (0x1UL << RTC_ALRMAR_DT_Pos)            /*!< 0x10000000 */
#define RTC_ALRMAR_DT_1                     (0x2UL << RTC_ALRMAR_DT_Pos)            /*!< 0x20000000 */
#define RTC_ALRMAR_WDSEL_Pos                (30UL)
#define RTC_ALRMAR_WDSEL_Msk                (0x1UL << RTC_ALRMAR_WDSEL_Pos)         /*!< 0x40000000 */
#define RTC_ALRMAR_WDSEL                    RTC_ALRMAR_WDSEL_Msk
#define RTC_ALRMAR_MSK4_Pos                 (31UL)
#define RTC_ALRMAR_MSK4_Msk                 (0x1UL << RTC_ALRMAR_MSK4_Pos)          /*!< 0x80000000 */
#define RTC_ALRMAR_MSK4                     RTC_ALRMAR_MSK4_Msk

/********************  Bits definition for RTC_ALRMASSR register  *************/
#define RTC_ALRMASSR_SS_Pos                 (0UL)
#define RTC_ALRMASSR_SS_Msk                 (0x7FFFUL << RTC_ALRMASSR_SS_Pos)       /*!< 0x00007FFF */
#define RTC_ALRMASSR_SS                     RTC_ALRMASSR_SS_Msk
#define RTC_ALRMASSR_MASKSS_Pos             (24UL)
#define RTC_ALRMASSR_MASKSS_Msk             (0x3FUL << RTC_ALRMASSR_MASKSS_Pos)     /*!< 0x3F000000 */
#define RTC_ALRMASSR_MASKSS                 RTC_ALRMASSR_MASKSS_Msk
#define RTC_ALRMASSR_MASKSS_0               (0x1UL << RTC_ALRMASSR_MASKSS_Pos)      /*!< 0x01000000 */
#define RTC_ALRMASSR_MASKSS_1               (0x2UL << RTC_ALRMASSR_MASKSS_Pos)      /*!< 0x02000000 */
#define RTC_ALRMASSR_MASKSS_2               (0x4UL << RTC_ALRMASSR_MASKSS_Pos)      /*!< 0x04000000 */
#define RTC_ALRMASSR_MASKSS_3               (0x8UL << RTC_ALRMASSR_MASKSS_Pos)      /*!< 0x08000000 */
#define RTC_ALRMASSR_MASKSS_4               (0x10UL << RTC_ALRMASSR_MASKSS_Pos)     /*!< 0x10000000 */
#define RTC_ALRMASSR_MASKSS_5               (0x20UL << RTC_ALRMASSR_MASKSS_Pos)     /*!< 0x20000000 */
#define RTC_ALRMASSR_SSCLR_Pos              (31UL)
#define RTC_ALRMASSR_SSCLR_Msk              (0x1UL << RTC_ALRMASSR_SSCLR_Pos)       /*!< 0x80000000 */
#define RTC_ALRMASSR_SSCLR                  RTC_ALRMASSR_SSCLR_Msk

/********************  Bits definition for RTC_ALRMBR register  ***************/
#define RTC_ALRMBR_SU_Pos                   (0UL)
#define RTC_ALRMBR_SU_Msk                   (0xFUL << RTC_ALRMBR_SU_Pos)            /*!< 0x0000000F */
#define RTC_ALRMBR_SU                       RTC_ALRMBR_SU_Msk
#define RTC_ALRMBR_SU_0                     (0x1UL << RTC_ALRMBR_SU_Pos)            /*!< 0x00000001 */
#define RTC_ALRMBR_SU_1                     (0x2UL << RTC_ALRMBR_SU_Pos)            /*!< 0x00000002 */
#define RTC_ALRMBR_SU_2                     (0x4UL << RTC_ALRMBR_SU_Pos)            /*!< 0x00000004 */
#define RTC_ALRMBR_SU_3                     (0x8UL << RTC_ALRMBR_SU_Pos)            /*!< 0x00000008 */
#define RTC_ALRMBR_ST_Pos                   (4UL)
#define RTC_ALRMBR_ST_Msk                   (0x7UL << RTC_ALRMBR_ST_Pos)            /*!< 0x00000070 */
#define RTC_ALRMBR_ST                       RTC_ALRMBR_ST_Msk
#define RTC_ALRMBR_ST_0                     (0x1UL << RTC_ALRMBR_ST_Pos)            /*!< 0x00000010 */
#define RTC_ALRMBR_ST_1                     (0x2UL << RTC_ALRMBR_ST_Pos)            /*!< 0x00000020 */
#define RTC_ALRMBR_ST_2                     (0x4UL << RTC_ALRMBR_ST_Pos)            /*!< 0x00000040 */
#define RTC_ALRMBR_MSK1_Pos                 (7UL)
#define RTC_ALRMBR_MSK1_Msk                 (0x1UL << RTC_ALRMBR_MSK1_Pos)          /*!< 0x00000080 */
#define RTC_ALRMBR_MSK1                     RTC_ALRMBR_MSK1_Msk
#define RTC_ALRMBR_MNU_Pos                  (8UL)
#define RTC_ALRMBR_MNU_Msk                  (0xFUL << RTC_ALRMBR_MNU_Pos)           /*!< 0x00000F00 */
#define RTC_ALRMBR_MNU                      RTC_ALRMBR_MNU_Msk
#define RTC_ALRMBR_MNU_0                    (0x1UL << RTC_ALRMBR_MNU_Pos)           /*!< 0x00000100 */
#define RTC_ALRMBR_MNU_1                    (0x2UL << RTC_ALRMBR_MNU_Pos)           /*!< 0x00000200 */
#define RTC_ALRMBR_MNU_2                    (0x4UL << RTC_ALRMBR_MNU_Pos)           /*!< 0x00000400 */
#define RTC_ALRMBR_MNU_3                    (0x8UL << RTC_ALRMBR_MNU_Pos)           /*!< 0x00000800 */
#define RTC_ALRMBR_MNT_Pos                  (12UL)
#define RTC_ALRMBR_MNT_Msk                  (0x7UL << RTC_ALRMBR_MNT_Pos)           /*!< 0x00007000 */
#define RTC_ALRMBR_MNT                      RTC_ALRMBR_MNT_Msk
#define RTC_ALRMBR_MNT_0                    (0x1UL << RTC_ALRMBR_MNT_Pos)           /*!< 0x00001000 */
#define RTC_ALRMBR_MNT_1                    (0x2UL << RTC_ALRMBR_MNT_Pos)           /*!< 0x00002000 */
#define RTC_ALRMBR_MNT_2                    (0x4UL << RTC_ALRMBR_MNT_Pos)           /*!< 0x00004000 */
#define RTC_ALRMBR_MSK2_Pos                 (15UL)
#define RTC_ALRMBR_MSK2_Msk                 (0x1UL << RTC_ALRMBR_MSK2_Pos)          /*!< 0x00008000 */
#define RTC_ALRMBR_MSK2                     RTC_ALRMBR_MSK2_Msk
#define RTC_ALRMBR_HU_Pos                   (16UL)
#define RTC_ALRMBR_HU_Msk                   (0xFUL << RTC_ALRMBR_HU_Pos)            /*!< 0x000F0000 */
#define RTC_ALRMBR_HU                       RTC_ALRMBR_HU_Msk
#define RTC_ALRMBR_HU_0                     (0x1UL << RTC_ALRMBR_HU_Pos)            /*!< 0x00010000 */
#define RTC_ALRMBR_HU_1                     (0x2UL << RTC_ALRMBR_HU_Pos)            /*!< 0x00020000 */
#define RTC_ALRMBR_HU_2                     (0x4UL << RTC_ALRMBR_HU_Pos)            /*!< 0x00040000 */
#define RTC_ALRMBR_HU_3                     (0x8UL << RTC_ALRMBR_HU_Pos)            /*!< 0x00080000 */
#define RTC_ALRMBR_HT_Pos                   (20UL)
#define RTC_ALRMBR_HT_Msk                   (0x3UL << RTC_ALRMBR_HT_Pos)            /*!< 0x00300000 */
#define RTC_ALRMBR_HT                       RTC_ALRMBR_HT_Msk
#define RTC_ALRMBR_HT_0                     (0x1UL << RTC_ALRMBR_HT_Pos)            /*!< 0x00100000 */
#define RTC_ALRMBR_HT_1                     (0x2UL << RTC_ALRMBR_HT_Pos)            /*!< 0x00200000 */
#define RTC_ALRMBR_PM_Pos                   (22UL)
#define RTC_ALRMBR_PM_Msk                   (0x1UL << RTC_ALRMBR_PM_Pos)            /*!< 0x00400000 */
#define RTC_ALRMBR_PM                       RTC_ALRMBR_PM_Msk
#define RTC_ALRMBR_MSK3_Pos                 (23UL)
#define RTC_ALRMBR_MSK3_Msk                 (0x1UL << RTC_ALRMBR_MSK3_Pos)          /*!< 0x00800000 */
#define RTC_ALRMBR_MSK3                     RTC_ALRMBR_MSK3_Msk
#define RTC_ALRMBR_DU_Pos                   (24UL)
#define RTC_ALRMBR_DU_Msk                   (0xFUL << RTC_ALRMBR_DU_Pos)            /*!< 0x0F000000 */
#define RTC_ALRMBR_DU                       RTC_ALRMBR_DU_Msk
#define RTC_ALRMBR_DU_0                     (0x1UL << RTC_ALRMBR_DU_Pos)            /*!< 0x01000000 */
#define RTC_ALRMBR_DU_1                     (0x2UL << RTC_ALRMBR_DU_Pos)            /*!< 0x02000000 */
#define RTC_ALRMBR_DU_2                     (0x4UL << RTC_ALRMBR_DU_Pos)            /*!< 0x04000000 */
#define RTC_ALRMBR_DU_3                     (0x8UL << RTC_ALRMBR_DU_Pos)            /*!< 0x08000000 */
#define RTC_ALRMBR_DT_Pos                   (28UL)
#define RTC_ALRMBR_DT_Msk                   (0x3UL << RTC_ALRMBR_DT_Pos)            /*!< 0x30000000 */
#define RTC_ALRMBR_DT                       RTC_ALRMBR_DT_Msk
#define RTC_ALRMBR_DT_0                     (0x1UL << RTC_ALRMBR_DT_Pos)            /*!< 0x10000000 */
#define RTC_ALRMBR_DT_1                     (0x2UL << RTC_ALRMBR_DT_Pos)            /*!< 0x20000000 */
#define RTC_ALRMBR_WDSEL_Pos                (30UL)
#define RTC_ALRMBR_WDSEL_Msk                (0x1UL << RTC_ALRMBR_WDSEL_Pos)         /*!< 0x40000000 */
#define RTC_ALRMBR_WDSEL                    RTC_ALRMBR_WDSEL_Msk
#define RTC_ALRMBR_MSK4_Pos                 (31UL)
#define RTC_ALRMBR_MSK4_Msk                 (0x1UL << RTC_ALRMBR_MSK4_Pos)          /*!< 0x80000000 */
#define RTC_ALRMBR_MSK4                     RTC_ALRMBR_MSK4_Msk

/********************  Bits definition for RTC_ALRMBSSR register  *************/
#define RTC_ALRMBSSR_SS_Pos                 (0UL)
#define RTC_ALRMBSSR_SS_Msk                 (0x7FFFUL << RTC_ALRMBSSR_SS_Pos)       /*!< 0x00007FFF */
#define RTC_ALRMBSSR_SS                     RTC_ALRMBSSR_SS_Msk
#define RTC_ALRMBSSR_MASKSS_Pos             (24UL)
#define RTC_ALRMBSSR_MASKSS_Msk             (0x3FUL << RTC_ALRMBSSR_MASKSS_Pos)     /*!< 0x3F000000 */
#define RTC_ALRMBSSR_MASKSS                 RTC_ALRMBSSR_MASKSS_Msk
#define RTC_ALRMBSSR_MASKSS_0               (0x1UL << RTC_ALRMBSSR_MASKSS_Pos)      /*!< 0x01000000 */
#define RTC_ALRMBSSR_MASKSS_1               (0x2UL << RTC_ALRMBSSR_MASKSS_Pos)      /*!< 0x02000000 */
#define RTC_ALRMBSSR_MASKSS_2               (0x4UL << RTC_ALRMBSSR_MASKSS_Pos)      /*!< 0x04000000 */
#define RTC_ALRMBSSR_MASKSS_3               (0x8UL << RTC_ALRMBSSR_MASKSS_Pos)      /*!< 0x08000000 */
#define RTC_ALRMBSSR_MASKSS_4               (0x10UL << RTC_ALRMBSSR_MASKSS_Pos)     /*!< 0x10000000 */
#define RTC_ALRMBSSR_MASKSS_5               (0x20UL << RTC_ALRMBSSR_MASKSS_Pos)     /*!< 0x20000000 */
#define RTC_ALRMBSSR_SSCLR_Pos              (31UL)
#define RTC_ALRMBSSR_SSCLR_Msk              (0x1UL << RTC_ALRMBSSR_SSCLR_Pos)       /*!< 0x80000000 */
#define RTC_ALRMBSSR_SSCLR                  RTC_ALRMBSSR_SSCLR_Msk

/********************  Bits definition for RTC_SR register  *******************/
#define RTC_SR_ALRAF_Pos                    (0UL)
#define RTC_SR_ALRAF_Msk                    (0x1UL << RTC_SR_ALRAF_Pos)             /*!< 0x00000001 */
#define RTC_SR_ALRAF                        RTC_SR_ALRAF_Msk
#define RTC_SR_ALRBF_Pos                    (1UL)
#define RTC_SR_ALRBF_Msk                    (0x1UL << RTC_SR_ALRBF_Pos)             /*!< 0x00000002 */
#define RTC_SR_ALRBF                        RTC_SR_ALRBF_Msk
#define RTC_SR_WUTF_Pos                     (2UL)
#define RTC_SR_WUTF_Msk                     (0x1UL << RTC_SR_WUTF_Pos)              /*!< 0x00000004 */
#define RTC_SR_WUTF                         RTC_SR_WUTF_Msk
#define RTC_SR_TSF_Pos                      (3UL)
#define RTC_SR_TSF_Msk                      (0x1UL << RTC_SR_TSF_Pos)               /*!< 0x00000008 */
#define RTC_SR_TSF                          RTC_SR_TSF_Msk
#define RTC_SR_TSOVF_Pos                    (4UL)
#define RTC_SR_TSOVF_Msk                    (0x1UL << RTC_SR_TSOVF_Pos)             /*!< 0x00000010 */
#define RTC_SR_TSOVF                        RTC_SR_TSOVF_Msk
#define RTC_SR_ITSF_Pos                     (5UL)
#define RTC_SR_ITSF_Msk                     (0x1UL << RTC_SR_ITSF_Pos)              /*!< 0x00000020 */
#define RTC_SR_ITSF                         RTC_SR_ITSF_Msk
#define RTC_SR_SSRUF_Pos                    (6UL)
#define RTC_SR_SSRUF_Msk                    (0x1UL << RTC_SR_SSRUF_Pos)             /*!< 0x00000040 */
#define RTC_SR_SSRUF                        RTC_SR_SSRUF_Msk

/********************  Bits definition for RTC_MISR register  *****************/
#define RTC_MISR_ALRAMF_Pos                 (0UL)
#define RTC_MISR_ALRAMF_Msk                 (0x1UL << RTC_MISR_ALRAMF_Pos)          /*!< 0x00000001 */
#define RTC_MISR_ALRAMF                     RTC_MISR_ALRAMF_Msk
#define RTC_MISR_ALRBMF_Pos                 (1UL)
#define RTC_MISR_ALRBMF_Msk                 (0x1UL << RTC_MISR_ALRBMF_Pos)          /*!< 0x00000002 */
#define RTC_MISR_ALRBMF                     RTC_MISR_ALRBMF_Msk
#define RTC_MISR_WUTMF_Pos                  (2UL)
#define RTC_MISR_WUTMF_Msk                  (0x1UL << RTC_MISR_WUTMF_Pos)           /*!< 0x00000004 */
#define RTC_MISR_WUTMF                      RTC_MISR_WUTMF_Msk
#define RTC_MISR_TSMF_Pos                   (3UL)
#define RTC_MISR_TSMF_Msk                   (0x1UL << RTC_MISR_TSMF_Pos)            /*!< 0x00000008 */
#define RTC_MISR_TSMF                       RTC_MISR_TSMF_Msk
#define RTC_MISR_TSOVMF_Pos                 (4UL)
#define RTC_MISR_TSOVMF_Msk                 (0x1UL << RTC_MISR_TSOVMF_Pos)          /*!< 0x00000010 */
#define RTC_MISR_TSOVMF                     RTC_MISR_TSOVMF_Msk
#define RTC_MISR_ITSMF_Pos                  (5UL)
#define RTC_MISR_ITSMF_Msk                  (0x1UL << RTC_MISR_ITSMF_Pos)           /*!< 0x00000020 */
#define RTC_MISR_ITSMF                      RTC_MISR_ITSMF_Msk
#define RTC_MISR_SSRUMF_Pos                 (6UL)
#define RTC_MISR_SSRUMF_Msk                 (0x1UL << RTC_MISR_SSRUMF_Pos)          /*!< 0x00000040 */
#define RTC_MISR_SSRUMF                     RTC_MISR_SSRUMF_Msk

/********************  Bits definition for RTC_SMISR register  *****************/
#define RTC_SMISR_ALRAMF_Pos                (0UL)
#define RTC_SMISR_ALRAMF_Msk                (0x1UL << RTC_SMISR_ALRAMF_Pos)         /*!< 0x00000001 */
#define RTC_SMISR_ALRAMF                    RTC_SMISR_ALRAMF_Msk
#define RTC_SMISR_ALRBMF_Pos                (1UL)
#define RTC_SMISR_ALRBMF_Msk                (0x1UL << RTC_SMISR_ALRBMF_Pos)         /*!< 0x00000002 */
#define RTC_SMISR_ALRBMF                    RTC_SMISR_ALRBMF_Msk
#define RTC_SMISR_WUTMF_Pos                 (2UL)
#define RTC_SMISR_WUTMF_Msk                 (0x1UL << RTC_SMISR_WUTMF_Pos)          /*!< 0x00000004 */
#define RTC_SMISR_WUTMF                     RTC_SMISR_WUTMF_Msk
#define RTC_SMISR_TSMF_Pos                  (3UL)
#define RTC_SMISR_TSMF_Msk                  (0x1UL << RTC_SMISR_TSMF_Pos)           /*!< 0x00000008 */
#define RTC_SMISR_TSMF                      RTC_SMISR_TSMF_Msk
#define RTC_SMISR_TSOVMF_Pos                (4UL)
#define RTC_SMISR_TSOVMF_Msk                (0x1UL << RTC_SMISR_TSOVMF_Pos)         /*!< 0x00000010 */
#define RTC_SMISR_TSOVMF                    RTC_SMISR_TSOVMF_Msk
#define RTC_SMISR_ITSMF_Pos                 (5UL)
#define RTC_SMISR_ITSMF_Msk                 (0x1UL << RTC_SMISR_ITSMF_Pos)          /*!< 0x00000020 */
#define RTC_SMISR_ITSMF                     RTC_SMISR_ITSMF_Msk
#define RTC_SMISR_SSRUMF_Pos                (6UL)
#define RTC_SMISR_SSRUMF_Msk                (0x1UL << RTC_SMISR_SSRUMF_Pos)         /*!< 0x00000040 */
#define RTC_SMISR_SSRUMF                    RTC_SMISR_SSRUMF_Msk

/********************  Bits definition for RTC_SCR register  ******************/
#define RTC_SCR_CALRAF_Pos                  (0UL)
#define RTC_SCR_CALRAF_Msk                  (0x1UL << RTC_SCR_CALRAF_Pos)           /*!< 0x00000001 */
#define RTC_SCR_CALRAF                      RTC_SCR_CALRAF_Msk
#define RTC_SCR_CALRBF_Pos                  (1UL)
#define RTC_SCR_CALRBF_Msk                  (0x1UL << RTC_SCR_CALRBF_Pos)           /*!< 0x00000002 */
#define RTC_SCR_CALRBF                      RTC_SCR_CALRBF_Msk
#define RTC_SCR_CWUTF_Pos                   (2UL)
#define RTC_SCR_CWUTF_Msk                   (0x1UL << RTC_SCR_CWUTF_Pos)            /*!< 0x00000004 */
#define RTC_SCR_CWUTF                       RTC_SCR_CWUTF_Msk
#define RTC_SCR_CTSF_Pos                    (3UL)
#define RTC_SCR_CTSF_Msk                    (0x1UL << RTC_SCR_CTSF_Pos)             /*!< 0x00000008 */
#define RTC_SCR_CTSF                        RTC_SCR_CTSF_Msk
#define RTC_SCR_CTSOVF_Pos                  (4UL)
#define RTC_SCR_CTSOVF_Msk                  (0x1UL << RTC_SCR_CTSOVF_Pos)           /*!< 0x00000010 */
#define RTC_SCR_CTSOVF                      RTC_SCR_CTSOVF_Msk
#define RTC_SCR_CITSF_Pos                   (5UL)
#define RTC_SCR_CITSF_Msk                   (0x1UL << RTC_SCR_CITSF_Pos)            /*!< 0x00000020 */
#define RTC_SCR_CITSF                       RTC_SCR_CITSF_Msk
#define RTC_SCR_CSSRUF_Pos                  (6UL)
#define RTC_SCR_CSSRUF_Msk                  (0x1UL << RTC_SCR_CSSRUF_Pos)           /*!< 0x00000040 */
#define RTC_SCR_CSSRUF                      RTC_SCR_CSSRUF_Msk

/********************  Bits definition for RTC_TAMPTSCR register  ******************/
#define RTC_TAMPTSCR_TAMP1TS_Pos            (0UL)
#define RTC_TAMPTSCR_TAMP1TS_Msk            (0x1UL << RTC_TAMPTSCR_TAMP1TS_Pos)     /*!< 0x00000001 */
#define RTC_TAMPTSCR_TAMP1TS                RTC_TAMPTSCR_TAMP1TS_Msk
#define RTC_TAMPTSCR_TAMP2TS_Pos            (1UL)
#define RTC_TAMPTSCR_TAMP2TS_Msk            (0x1UL << RTC_TAMPTSCR_TAMP2TS_Pos)     /*!< 0x00000002 */
#define RTC_TAMPTSCR_TAMP2TS                RTC_TAMPTSCR_TAMP2TS_Msk
#define RTC_TAMPTSCR_TAMP3TS_Pos            (2UL)
#define RTC_TAMPTSCR_TAMP3TS_Msk            (0x1UL << RTC_TAMPTSCR_TAMP3TS_Pos)     /*!< 0x00000004 */
#define RTC_TAMPTSCR_TAMP3TS                RTC_TAMPTSCR_TAMP3TS_Msk
#define RTC_TAMPTSCR_TAMP4TS_Pos            (3UL)
#define RTC_TAMPTSCR_TAMP4TS_Msk            (0x1UL << RTC_TAMPTSCR_TAMP4TS_Pos)     /*!< 0x00000008 */
#define RTC_TAMPTSCR_TAMP4TS                RTC_TAMPTSCR_TAMP4TS_Msk
#define RTC_TAMPTSCR_TAMP5TS_Pos            (4UL)
#define RTC_TAMPTSCR_TAMP5TS_Msk            (0x1UL << RTC_TAMPTSCR_TAMP5TS_Pos)     /*!< 0x00000010 */
#define RTC_TAMPTSCR_TAMP5TS                RTC_TAMPTSCR_TAMP5TS_Msk
#define RTC_TAMPTSCR_ITAMPTS_Pos            (16UL)
#define RTC_TAMPTSCR_ITAMPTS_Msk            (0x1UL << RTC_TAMPTSCR_ITAMPTS_Pos)     /*!< 0x00010000 */
#define RTC_TAMPTSCR_ITAMPTS                RTC_TAMPTSCR_ITAMPTS_Msk

/********************  Bits definition for RTC_TSIDR register  ******************/
#define RTC_TSIDR_TSID_Pos                  (0UL)
#define RTC_TSIDR_TSID_Msk                  (0x3FUL << RTC_TSIDR_TSID_Pos)          /*!< 0x0000003F */
#define RTC_TSIDR_TSID                      RTC_TSIDR_TSID_Msk
#define RTC_TSIDR_TSID_0                    (0x1UL << RTC_TSIDR_TSID_Pos)           /*!< 0x00000001 */
#define RTC_TSIDR_TSID_1                    (0x2UL << RTC_TSIDR_TSID_Pos)           /*!< 0x00000002 */
#define RTC_TSIDR_TSID_2                    (0x4UL << RTC_TSIDR_TSID_Pos)           /*!< 0x00000004 */
#define RTC_TSIDR_TSID_3                    (0x8UL << RTC_TSIDR_TSID_Pos)           /*!< 0x00000008 */
#define RTC_TSIDR_TSID_4                    (0x10UL << RTC_TSIDR_TSID_Pos)          /*!< 0x00000010 */
#define RTC_TSIDR_TSID_5                    (0x20UL << RTC_TSIDR_TSID_Pos)          /*!< 0x00000020 */

/********************  Bits definition for RTC_ALRABINR register  ******************/
#define RTC_ALRABINR_SS_Pos                 (0UL)
#define RTC_ALRABINR_SS_Msk                 (0xFFFFFFFFUL << RTC_ALRABINR_SS_Pos)   /*!< 0xFFFFFFFF */
#define RTC_ALRABINR_SS                     RTC_ALRABINR_SS_Msk

/********************  Bits definition for RTC_ALRBBINR register  ******************/
#define RTC_ALRBBINR_SS_Pos                 (0UL)
#define RTC_ALRBBINR_SS_Msk                 (0xFFFFFFFFUL << RTC_ALRBBINR_SS_Pos)   /*!< 0xFFFFFFFF */
#define RTC_ALRBBINR_SS                     RTC_ALRBBINR_SS_Msk

/******************************************************************************/
/*                                                                            */
/*                          Serial Audio Interface                            */
/*                                                                            */
/******************************************************************************/
/*******************  Bit definition for SAI_xCR1 register  *******************/
#define SAI_xCR1_MODE_Pos                   (0UL)
#define SAI_xCR1_MODE_Msk                   (0x3UL << SAI_xCR1_MODE_Pos)            /*!< 0x00000003 */
#define SAI_xCR1_MODE                       SAI_xCR1_MODE_Msk                       /*!<MODE[1:0] bits (Audio Block Mode)           */
#define SAI_xCR1_MODE_0                     (0x1UL << SAI_xCR1_MODE_Pos)            /*!< 0x00000001 */
#define SAI_xCR1_MODE_1                     (0x2UL << SAI_xCR1_MODE_Pos)            /*!< 0x00000002 */
#define SAI_xCR1_PRTCFG_Pos                 (2UL)
#define SAI_xCR1_PRTCFG_Msk                 (0x3UL << SAI_xCR1_PRTCFG_Pos)          /*!< 0x0000000C */
#define SAI_xCR1_PRTCFG                     SAI_xCR1_PRTCFG_Msk                     /*!<PRTCFG[1:0] bits (Protocol Configuration)   */
#define SAI_xCR1_PRTCFG_0                   (0x1UL << SAI_xCR1_PRTCFG_Pos)          /*!< 0x00000004 */
#define SAI_xCR1_PRTCFG_1                   (0x2UL << SAI_xCR1_PRTCFG_Pos)          /*!< 0x00000008 */
#define SAI_xCR1_DS_Pos                     (5UL)
#define SAI_xCR1_DS_Msk                     (0x7UL << SAI_xCR1_DS_Pos)              /*!< 0x000000E0 */
#define SAI_xCR1_DS                         SAI_xCR1_DS_Msk                         /*!<DS[1:0] bits (Data Size) */
#define SAI_xCR1_DS_0                       (0x1UL << SAI_xCR1_DS_Pos)              /*!< 0x00000020 */
#define SAI_xCR1_DS_1                       (0x2UL << SAI_xCR1_DS_Pos)              /*!< 0x00000040 */
#define SAI_xCR1_DS_2                       (0x4UL << SAI_xCR1_DS_Pos)              /*!< 0x00000080 */
#define SAI_xCR1_LSBFIRST_Pos               (8UL)
#define SAI_xCR1_LSBFIRST_Msk               (0x1UL << SAI_xCR1_LSBFIRST_Pos)        /*!< 0x00000100 */
#define SAI_xCR1_LSBFIRST                   SAI_xCR1_LSBFIRST_Msk                   /*!<LSB First Configuration  */
#define SAI_xCR1_CKSTR_Pos                  (9UL)
#define SAI_xCR1_CKSTR_Msk                  (0x1UL << SAI_xCR1_CKSTR_Pos)           /*!< 0x00000200 */
#define SAI_xCR1_CKSTR                      SAI_xCR1_CKSTR_Msk                      /*!<ClocK STRobing edge      */
#define SAI_xCR1_SYNCEN_Pos                 (10UL)
#define SAI_xCR1_SYNCEN_Msk                 (0x3UL << SAI_xCR1_SYNCEN_Pos)          /*!< 0x00000C00 */
#define SAI_xCR1_SYNCEN                     SAI_xCR1_SYNCEN_Msk                     /*!<SYNCEN[1:0](SYNChronization ENable) */
#define SAI_xCR1_SYNCEN_0                   (0x1UL << SAI_xCR1_SYNCEN_Pos)          /*!< 0x00000400 */
#define SAI_xCR1_SYNCEN_1                   (0x2UL << SAI_xCR1_SYNCEN_Pos)          /*!< 0x00000800 */
#define SAI_xCR1_MONO_Pos                   (12UL)
#define SAI_xCR1_MONO_Msk                   (0x1UL << SAI_xCR1_MONO_Pos)            /*!< 0x00001000 */
#define SAI_xCR1_MONO                       SAI_xCR1_MONO_Msk                       /*!<Mono mode                  */
#define SAI_xCR1_OUTDRIV_Pos                (13UL)
#define SAI_xCR1_OUTDRIV_Msk                (0x1UL << SAI_xCR1_OUTDRIV_Pos)         /*!< 0x00002000 */
#define SAI_xCR1_OUTDRIV                    SAI_xCR1_OUTDRIV_Msk                    /*!<Output Drive               */
#define SAI_xCR1_SAIEN_Pos                  (16UL)
#define SAI_xCR1_SAIEN_Msk                  (0x1UL << SAI_xCR1_SAIEN_Pos)           /*!< 0x00010000 */
#define SAI_xCR1_SAIEN                      SAI_xCR1_SAIEN_Msk                      /*!<Audio Block enable         */
#define SAI_xCR1_DMAEN_Pos                  (17UL)
#define SAI_xCR1_DMAEN_Msk                  (0x1UL << SAI_xCR1_DMAEN_Pos)           /*!< 0x00020000 */
#define SAI_xCR1_DMAEN                      SAI_xCR1_DMAEN_Msk                      /*!<DMA enable                 */
#define SAI_xCR1_NODIV_Pos                  (19UL)
#define SAI_xCR1_NODIV_Msk                  (0x1UL << SAI_xCR1_NODIV_Pos)           /*!< 0x00080000 */
#define SAI_xCR1_NODIV                      SAI_xCR1_NODIV_Msk                      /*!<No Divider Configuration   */
#define SAI_xCR1_MCKDIV_Pos                 (20UL)
#define SAI_xCR1_MCKDIV_Msk                 (0x3FUL << SAI_xCR1_MCKDIV_Pos)         /*!< 0x03F00000 */
#define SAI_xCR1_MCKDIV                     SAI_xCR1_MCKDIV_Msk                     /*!<MCKDIV[5:0] (Master ClocK Divider)  */
#define SAI_xCR1_MCKDIV_0                   (0x00100000UL)                          /*!<Bit 0  */
#define SAI_xCR1_MCKDIV_1                   (0x00200000UL)                          /*!<Bit 1  */
#define SAI_xCR1_MCKDIV_2                   (0x00400000UL)                          /*!<Bit 2  */
#define SAI_xCR1_MCKDIV_3                   (0x00800000UL)                          /*!<Bit 3  */
#define SAI_xCR1_MCKDIV_4                   (0x01000000UL)                          /*!<Bit 4  */
#define SAI_xCR1_MCKDIV_5                   (0x02000000UL)                          /*!<Bit 5  */
#define SAI_xCR1_OSR_Pos                    (26UL)
#define SAI_xCR1_OSR_Msk                    (0x1UL << SAI_xCR1_OSR_Pos)             /*!< 0x04000000 */
#define SAI_xCR1_OSR                        SAI_xCR1_OSR_Msk                        /*!<Oversampling ratio for master clock */
#define SAI_xCR1_MCKEN_Pos                  (27UL)
#define SAI_xCR1_MCKEN_Msk                  (0x1UL << SAI_xCR1_MCKEN_Pos)           /*!< 0x08000000 */
#define SAI_xCR1_MCKEN                      SAI_xCR1_MCKEN_Msk                      /*!<Master clock generation enable */

/*******************  Bit definition for SAI_xCR2 register  *******************/
#define SAI_xCR2_FTH_Pos                    (0UL)
#define SAI_xCR2_FTH_Msk                    (0x7UL << SAI_xCR2_FTH_Pos)             /*!< 0x00000007 */
#define SAI_xCR2_FTH                        SAI_xCR2_FTH_Msk                        /*!<FTH[2:0](Fifo THreshold)  */
#define SAI_xCR2_FTH_0                      (0x1UL << SAI_xCR2_FTH_Pos)             /*!< 0x00000001 */
#define SAI_xCR2_FTH_1                      (0x2UL << SAI_xCR2_FTH_Pos)             /*!< 0x00000002 */
#define SAI_xCR2_FTH_2                      (0x4UL << SAI_xCR2_FTH_Pos)             /*!< 0x00000004 */
#define SAI_xCR2_FFLUSH_Pos                 (3UL)
#define SAI_xCR2_FFLUSH_Msk                 (0x1UL << SAI_xCR2_FFLUSH_Pos)          /*!< 0x00000008 */
#define SAI_xCR2_FFLUSH                     SAI_xCR2_FFLUSH_Msk                     /*!<Fifo FLUSH                       */
#define SAI_xCR2_TRIS_Pos                   (4UL)
#define SAI_xCR2_TRIS_Msk                   (0x1UL << SAI_xCR2_TRIS_Pos)            /*!< 0x00000010 */
#define SAI_xCR2_TRIS                       SAI_xCR2_TRIS_Msk                       /*!<TRIState Management on data line */
#define SAI_xCR2_MUTE_Pos                   (5UL)
#define SAI_xCR2_MUTE_Msk                   (0x1UL << SAI_xCR2_MUTE_Pos)            /*!< 0x00000020 */
#define SAI_xCR2_MUTE                       SAI_xCR2_MUTE_Msk                       /*!<Mute mode                        */
#define SAI_xCR2_MUTEVAL_Pos                (6UL)
#define SAI_xCR2_MUTEVAL_Msk                (0x1UL << SAI_xCR2_MUTEVAL_Pos)         /*!< 0x00000040 */
#define SAI_xCR2_MUTEVAL                    SAI_xCR2_MUTEVAL_Msk                    /*!<Muate value                      */
#define SAI_xCR2_MUTECNT_Pos                (7UL)
#define SAI_xCR2_MUTECNT_Msk                (0x3FUL << SAI_xCR2_MUTECNT_Pos)        /*!< 0x00001F80 */
#define SAI_xCR2_MUTECNT                    SAI_xCR2_MUTECNT_Msk                    /*!<MUTECNT[5:0] (MUTE counter) */
#define SAI_xCR2_MUTECNT_0                  (0x01UL << SAI_xCR2_MUTECNT_Pos)        /*!< 0x00000080 */
#define SAI_xCR2_MUTECNT_1                  (0x02UL << SAI_xCR2_MUTECNT_Pos)        /*!< 0x00000100 */
#define SAI_xCR2_MUTECNT_2                  (0x04UL << SAI_xCR2_MUTECNT_Pos)        /*!< 0x00000200 */
#define SAI_xCR2_MUTECNT_3                  (0x08UL << SAI_xCR2_MUTECNT_Pos)        /*!< 0x00000400 */
#define SAI_xCR2_MUTECNT_4                  (0x10UL << SAI_xCR2_MUTECNT_Pos)        /*!< 0x00000800 */
#define SAI_xCR2_MUTECNT_5                  (0x20UL << SAI_xCR2_MUTECNT_Pos)        /*!< 0x00001000 */
#define SAI_xCR2_CPL_Pos                    (13UL)
#define SAI_xCR2_CPL_Msk                    (0x1UL << SAI_xCR2_CPL_Pos)             /*!< 0x00002000 */
#define SAI_xCR2_CPL                        SAI_xCR2_CPL_Msk                        /*!<CPL mode                    */
#define SAI_xCR2_COMP_Pos                   (14UL)
#define SAI_xCR2_COMP_Msk                   (0x3UL << SAI_xCR2_COMP_Pos)            /*!< 0x0000C000 */
#define SAI_xCR2_COMP                       SAI_xCR2_COMP_Msk                       /*!<COMP[1:0] (Companding mode) */
#define SAI_xCR2_COMP_0                     (0x1UL << SAI_xCR2_COMP_Pos)            /*!< 0x00004000 */
#define SAI_xCR2_COMP_1                     (0x2UL << SAI_xCR2_COMP_Pos)            /*!< 0x00008000 */

/******************  Bit definition for SAI_xFRCR register  *******************/
#define SAI_xFRCR_FRL_Pos                   (0UL)
#define SAI_xFRCR_FRL_Msk                   (0xFFUL << SAI_xFRCR_FRL_Pos)           /*!< 0x000000FF */
#define SAI_xFRCR_FRL                       SAI_xFRCR_FRL_Msk                       /*!<FRL[7:0](Frame length)  */
#define SAI_xFRCR_FRL_0                     (0x01UL << SAI_xFRCR_FRL_Pos)           /*!< 0x00000001 */
#define SAI_xFRCR_FRL_1                     (0x02UL << SAI_xFRCR_FRL_Pos)           /*!< 0x00000002 */
#define SAI_xFRCR_FRL_2                     (0x04UL << SAI_xFRCR_FRL_Pos)           /*!< 0x00000004 */
#define SAI_xFRCR_FRL_3                     (0x08UL << SAI_xFRCR_FRL_Pos)           /*!< 0x00000008 */
#define SAI_xFRCR_FRL_4                     (0x10UL << SAI_xFRCR_FRL_Pos)           /*!< 0x00000010 */
#define SAI_xFRCR_FRL_5                     (0x20UL << SAI_xFRCR_FRL_Pos)           /*!< 0x00000020 */
#define SAI_xFRCR_FRL_6                     (0x40UL << SAI_xFRCR_FRL_Pos)           /*!< 0x00000040 */
#define SAI_xFRCR_FRL_7                     (0x80UL << SAI_xFRCR_FRL_Pos)           /*!< 0x00000080 */
#define SAI_xFRCR_FSALL_Pos                 (8UL)
#define SAI_xFRCR_FSALL_Msk                 (0x7FUL << SAI_xFRCR_FSALL_Pos)         /*!< 0x00007F00 */
#define SAI_xFRCR_FSALL                     SAI_xFRCR_FSALL_Msk                     /*!<FRL[6:0] (Frame synchronization active level length)  */
#define SAI_xFRCR_FSALL_0                   (0x01UL << SAI_xFRCR_FSALL_Pos)         /*!< 0x00000100 */
#define SAI_xFRCR_FSALL_1                   (0x02UL << SAI_xFRCR_FSALL_Pos)         /*!< 0x00000200 */
#define SAI_xFRCR_FSALL_2                   (0x04UL << SAI_xFRCR_FSALL_Pos)         /*!< 0x00000400 */
#define SAI_xFRCR_FSALL_3                   (0x08UL << SAI_xFRCR_FSALL_Pos)         /*!< 0x00000800 */
#define SAI_xFRCR_FSALL_4                   (0x10UL << SAI_xFRCR_FSALL_Pos)         /*!< 0x00001000 */
#define SAI_xFRCR_FSALL_5                   (0x20UL << SAI_xFRCR_FSALL_Pos)         /*!< 0x00002000 */
#define SAI_xFRCR_FSALL_6                   (0x40UL << SAI_xFRCR_FSALL_Pos)         /*!< 0x00004000 */
#define SAI_xFRCR_FSDEF_Pos                 (16UL)
#define SAI_xFRCR_FSDEF_Msk                 (0x1UL << SAI_xFRCR_FSDEF_Pos)          /*!< 0x00010000 */
#define SAI_xFRCR_FSDEF                     SAI_xFRCR_FSDEF_Msk                     /*!< Frame Synchronization Definition */
#define SAI_xFRCR_FSPOL_Pos                 (17UL)
#define SAI_xFRCR_FSPOL_Msk                 (0x1UL << SAI_xFRCR_FSPOL_Pos)          /*!< 0x00020000 */
#define SAI_xFRCR_FSPOL                     SAI_xFRCR_FSPOL_Msk                     /*!<Frame Synchronization POLarity    */
#define SAI_xFRCR_FSOFF_Pos                 (18UL)
#define SAI_xFRCR_FSOFF_Msk                 (0x1UL << SAI_xFRCR_FSOFF_Pos)          /*!< 0x00040000 */
#define SAI_xFRCR_FSOFF                     SAI_xFRCR_FSOFF_Msk                     /*!<Frame Synchronization OFFset      */

/******************  Bit definition for SAI_xSLOTR register  *******************/
#define SAI_xSLOTR_FBOFF_Pos                (0UL)
#define SAI_xSLOTR_FBOFF_Msk                (0x1FUL << SAI_xSLOTR_FBOFF_Pos)        /*!< 0x0000001F */
#define SAI_xSLOTR_FBOFF                    SAI_xSLOTR_FBOFF_Msk                    /*!<FRL[4:0](First Bit Offset)  */
#define SAI_xSLOTR_FBOFF_0                  (0x01UL << SAI_xSLOTR_FBOFF_Pos)        /*!< 0x00000001 */
#define SAI_xSLOTR_FBOFF_1                  (0x02UL << SAI_xSLOTR_FBOFF_Pos)        /*!< 0x00000002 */
#define SAI_xSLOTR_FBOFF_2                  (0x04UL << SAI_xSLOTR_FBOFF_Pos)        /*!< 0x00000004 */
#define SAI_xSLOTR_FBOFF_3                  (0x08UL << SAI_xSLOTR_FBOFF_Pos)        /*!< 0x00000008 */
#define SAI_xSLOTR_FBOFF_4                  (0x10UL << SAI_xSLOTR_FBOFF_Pos)        /*!< 0x00000010 */
#define SAI_xSLOTR_SLOTSZ_Pos               (6UL)
#define SAI_xSLOTR_SLOTSZ_Msk               (0x3UL << SAI_xSLOTR_SLOTSZ_Pos)        /*!< 0x000000C0 */
#define SAI_xSLOTR_SLOTSZ                   SAI_xSLOTR_SLOTSZ_Msk                   /*!<SLOTSZ[1:0] (Slot size)  */
#define SAI_xSLOTR_SLOTSZ_0                 (0x1UL << SAI_xSLOTR_SLOTSZ_Pos)        /*!< 0x00000040 */
#define SAI_xSLOTR_SLOTSZ_1                 (0x2UL << SAI_xSLOTR_SLOTSZ_Pos)        /*!< 0x00000080 */
#define SAI_xSLOTR_NBSLOT_Pos               (8UL)
#define SAI_xSLOTR_NBSLOT_Msk               (0xFUL << SAI_xSLOTR_NBSLOT_Pos)        /*!< 0x00000F00 */
#define SAI_xSLOTR_NBSLOT                   SAI_xSLOTR_NBSLOT_Msk                   /*!<NBSLOT[3:0] (Number of Slot in audio Frame)  */
#define SAI_xSLOTR_NBSLOT_0                 (0x1UL << SAI_xSLOTR_NBSLOT_Pos)        /*!< 0x00000100 */
#define SAI_xSLOTR_NBSLOT_1                 (0x2UL << SAI_xSLOTR_NBSLOT_Pos)        /*!< 0x00000200 */
#define SAI_xSLOTR_NBSLOT_2                 (0x4UL << SAI_xSLOTR_NBSLOT_Pos)        /*!< 0x00000400 */
#define SAI_xSLOTR_NBSLOT_3                 (0x8UL << SAI_xSLOTR_NBSLOT_Pos)        /*!< 0x00000800 */
#define SAI_xSLOTR_SLOTEN_Pos               (16UL)
#define SAI_xSLOTR_SLOTEN_Msk               (0xFFFFUL << SAI_xSLOTR_SLOTEN_Pos)     /*!< 0xFFFF0000 */
#define SAI_xSLOTR_SLOTEN                   SAI_xSLOTR_SLOTEN_Msk                   /*!<SLOTEN[15:0] (Slot Enable)  */

/*******************  Bit definition for SAI_xIMR register  *******************/
#define SAI_xIMR_OVRUDRIE_Pos               (0UL)
#define SAI_xIMR_OVRUDRIE_Msk               (0x1UL << SAI_xIMR_OVRUDRIE_Pos)        /*!< 0x00000001 */
#define SAI_xIMR_OVRUDRIE                   SAI_xIMR_OVRUDRIE_Msk                   /*!<Overrun underrun interrupt enable                              */
#define SAI_xIMR_MUTEDETIE_Pos              (1UL)
#define SAI_xIMR_MUTEDETIE_Msk              (0x1UL << SAI_xIMR_MUTEDETIE_Pos)       /*!< 0x00000002 */
#define SAI_xIMR_MUTEDETIE                  SAI_xIMR_MUTEDETIE_Msk                  /*!<Mute detection interrupt enable                                */
#define SAI_xIMR_WCKCFGIE_Pos               (2UL)
#define SAI_xIMR_WCKCFGIE_Msk               (0x1UL << SAI_xIMR_WCKCFGIE_Pos)        /*!< 0x00000004 */
#define SAI_xIMR_WCKCFGIE                   SAI_xIMR_WCKCFGIE_Msk                   /*!<Wrong Clock Configuration interrupt enable                     */
#define SAI_xIMR_FREQIE_Pos                 (3UL)
#define SAI_xIMR_FREQIE_Msk                 (0x1UL << SAI_xIMR_FREQIE_Pos)          /*!< 0x00000008 */
#define SAI_xIMR_FREQIE                     SAI_xIMR_FREQIE_Msk                     /*!<FIFO request interrupt enable                                  */
#define SAI_xIMR_CNRDYIE_Pos                (4UL)
#define SAI_xIMR_CNRDYIE_Msk                (0x1UL << SAI_xIMR_CNRDYIE_Pos)         /*!< 0x00000010 */
#define SAI_xIMR_CNRDYIE                    SAI_xIMR_CNRDYIE_Msk                    /*!<Codec not ready interrupt enable                               */
#define SAI_xIMR_AFSDETIE_Pos               (5UL)
#define SAI_xIMR_AFSDETIE_Msk               (0x1UL << SAI_xIMR_AFSDETIE_Pos)        /*!< 0x00000020 */
#define SAI_xIMR_AFSDETIE                   SAI_xIMR_AFSDETIE_Msk                   /*!<Anticipated frame synchronization detection interrupt enable   */
#define SAI_xIMR_LFSDETIE_Pos               (6UL)
#define SAI_xIMR_LFSDETIE_Msk               (0x1UL << SAI_xIMR_LFSDETIE_Pos)        /*!< 0x00000040 */
#define SAI_xIMR_LFSDETIE                   SAI_xIMR_LFSDETIE_Msk                   /*!<Late frame synchronization detection interrupt enable          */

/********************  Bit definition for SAI_xSR register  *******************/
#define SAI_xSR_OVRUDR_Pos                  (0UL)
#define SAI_xSR_OVRUDR_Msk                  (0x1UL << SAI_xSR_OVRUDR_Pos)           /*!< 0x00000001 */
#define SAI_xSR_OVRUDR                      SAI_xSR_OVRUDR_Msk                      /*!<Overrun underrun                               */
#define SAI_xSR_MUTEDET_Pos                 (1UL)
#define SAI_xSR_MUTEDET_Msk                 (0x1UL << SAI_xSR_MUTEDET_Pos)          /*!< 0x00000002 */
#define SAI_xSR_MUTEDET                     SAI_xSR_MUTEDET_Msk                     /*!<Mute detection                                 */
#define SAI_xSR_WCKCFG_Pos                  (2UL)
#define SAI_xSR_WCKCFG_Msk                  (0x1UL << SAI_xSR_WCKCFG_Pos)           /*!< 0x00000004 */
#define SAI_xSR_WCKCFG                      SAI_xSR_WCKCFG_Msk                      /*!<Wrong Clock Configuration                      */
#define SAI_xSR_FREQ_Pos                    (3UL)
#define SAI_xSR_FREQ_Msk                    (0x1UL << SAI_xSR_FREQ_Pos)             /*!< 0x00000008 */
#define SAI_xSR_FREQ                        SAI_xSR_FREQ_Msk                        /*!<FIFO request                                   */
#define SAI_xSR_CNRDY_Pos                   (4UL)
#define SAI_xSR_CNRDY_Msk                   (0x1UL << SAI_xSR_CNRDY_Pos)            /*!< 0x00000010 */
#define SAI_xSR_CNRDY                       SAI_xSR_CNRDY_Msk                       /*!<Codec not ready                                */
#define SAI_xSR_AFSDET_Pos                  (5UL)
#define SAI_xSR_AFSDET_Msk                  (0x1UL << SAI_xSR_AFSDET_Pos)           /*!< 0x00000020 */
#define SAI_xSR_AFSDET                      SAI_xSR_AFSDET_Msk                      /*!<Anticipated frame synchronization detection    */
#define SAI_xSR_LFSDET_Pos                  (6UL)
#define SAI_xSR_LFSDET_Msk                  (0x1UL << SAI_xSR_LFSDET_Pos)           /*!< 0x00000040 */
#define SAI_xSR_LFSDET                      SAI_xSR_LFSDET_Msk                      /*!<Late frame synchronization detection           */
#define SAI_xSR_FLVL_Pos                    (16UL)
#define SAI_xSR_FLVL_Msk                    (0x7UL << SAI_xSR_FLVL_Pos)             /*!< 0x00070000 */
#define SAI_xSR_FLVL                        SAI_xSR_FLVL_Msk                        /*!<FLVL[2:0] (FIFO Level Threshold)               */
#define SAI_xSR_FLVL_0                      (0x1UL << SAI_xSR_FLVL_Pos)             /*!< 0x00010000 */
#define SAI_xSR_FLVL_1                      (0x2UL << SAI_xSR_FLVL_Pos)             /*!< 0x00020000 */
#define SAI_xSR_FLVL_2                      (0x4UL << SAI_xSR_FLVL_Pos)             /*!< 0x00040000 */

/******************  Bit definition for SAI_xCLRFR register  ******************/
#define SAI_xCLRFR_COVRUDR_Pos              (0UL)
#define SAI_xCLRFR_COVRUDR_Msk              (0x1UL << SAI_xCLRFR_COVRUDR_Pos)       /*!< 0x00000001 */
#define SAI_xCLRFR_COVRUDR                  SAI_xCLRFR_COVRUDR_Msk                  /*!<Clear Overrun underrun                               */
#define SAI_xCLRFR_CMUTEDET_Pos             (1UL)
#define SAI_xCLRFR_CMUTEDET_Msk             (0x1UL << SAI_xCLRFR_CMUTEDET_Pos)      /*!< 0x00000002 */
#define SAI_xCLRFR_CMUTEDET                 SAI_xCLRFR_CMUTEDET_Msk                 /*!<Clear Mute detection                                 */
#define SAI_xCLRFR_CWCKCFG_Pos              (2UL)
#define SAI_xCLRFR_CWCKCFG_Msk              (0x1UL << SAI_xCLRFR_CWCKCFG_Pos)       /*!< 0x00000004 */
#define SAI_xCLRFR_CWCKCFG                  SAI_xCLRFR_CWCKCFG_Msk                  /*!<Clear Wrong Clock Configuration                      */
#define SAI_xCLRFR_CCNRDY_Pos               (4UL)
#define SAI_xCLRFR_CCNRDY_Msk               (0x1UL << SAI_xCLRFR_CCNRDY_Pos)        /*!< 0x00000010 */
#define SAI_xCLRFR_CCNRDY                   SAI_xCLRFR_CCNRDY_Msk                   /*!<Clear Codec not ready                                */
#define SAI_xCLRFR_CAFSDET_Pos              (5UL)
#define SAI_xCLRFR_CAFSDET_Msk              (0x1UL << SAI_xCLRFR_CAFSDET_Pos)       /*!< 0x00000020 */
#define SAI_xCLRFR_CAFSDET                  SAI_xCLRFR_CAFSDET_Msk                  /*!<Clear Anticipated frame synchronization detection    */
#define SAI_xCLRFR_CLFSDET_Pos              (6UL)
#define SAI_xCLRFR_CLFSDET_Msk              (0x1UL << SAI_xCLRFR_CLFSDET_Pos)       /*!< 0x00000040 */
#define SAI_xCLRFR_CLFSDET                  SAI_xCLRFR_CLFSDET_Msk                  /*!<Clear Late frame synchronization detection           */

/******************  Bit definition for SAI_xDR register  ******************/
#define SAI_xDR_DATA_Pos                    (0UL)
#define SAI_xDR_DATA_Msk                    (0xFFFFFFFFUL << SAI_xDR_DATA_Pos)      /*!< 0xFFFFFFFF */
#define SAI_xDR_DATA                        SAI_xDR_DATA_Msk

/******************  Bit definition for SAI_PDMCR register  *******************/
#define SAI_PDMCR_PDMEN_Pos                 (0UL)
#define SAI_PDMCR_PDMEN_Msk                 (0x1UL << SAI_PDMCR_PDMEN_Pos)          /*!< 0x00000001 */
#define SAI_PDMCR_PDMEN                     SAI_PDMCR_PDMEN_Msk                     /*!<PDM enable */
#define SAI_PDMCR_MICNBR_Pos                (4UL)
#define SAI_PDMCR_MICNBR_Msk                (0x3UL << SAI_PDMCR_MICNBR_Pos)         /*!< 0x00000030 */
#define SAI_PDMCR_MICNBR                    SAI_PDMCR_MICNBR_Msk                    /*!<MICNBR[1:0] (Number of microphones) */
#define SAI_PDMCR_MICNBR_0                  (0x1UL << SAI_PDMCR_MICNBR_Pos)         /*!< 0x00000010 */
#define SAI_PDMCR_MICNBR_1                  (0x2UL << SAI_PDMCR_MICNBR_Pos)         /*!< 0x00000020 */
#define SAI_PDMCR_CKEN1_Pos                 (8UL)
#define SAI_PDMCR_CKEN1_Msk                 (0x1UL << SAI_PDMCR_CKEN1_Pos)          /*!< 0x00000100 */
#define SAI_PDMCR_CKEN1                     SAI_PDMCR_CKEN1_Msk                     /*!<Clock 1 enable */
#define SAI_PDMCR_CKEN2_Pos                 (9UL)
#define SAI_PDMCR_CKEN2_Msk                 (0x1UL << SAI_PDMCR_CKEN2_Pos)          /*!< 0x00000200 */
#define SAI_PDMCR_CKEN2                     SAI_PDMCR_CKEN2_Msk                     /*!<Clock 2 enable */
#define SAI_PDMCR_CKEN3_Pos                 (10UL)
#define SAI_PDMCR_CKEN3_Msk                 (0x1UL << SAI_PDMCR_CKEN3_Pos)          /*!< 0x00000400 */
#define SAI_PDMCR_CKEN3                     SAI_PDMCR_CKEN3_Msk                     /*!<Clock 3 enable */
#define SAI_PDMCR_CKEN4_Pos                 (11UL)
#define SAI_PDMCR_CKEN4_Msk                 (0x1UL << SAI_PDMCR_CKEN4_Pos)          /*!< 0x00000800 */
#define SAI_PDMCR_CKEN4                     SAI_PDMCR_CKEN4_Msk                     /*!<Clock 4 enable */

/******************  Bit definition for SAI_PDMDLY register  ******************/
#define SAI_PDMDLY_DLYM1L_Pos               (0UL)
#define SAI_PDMDLY_DLYM1L_Msk               (0x7UL << SAI_PDMDLY_DLYM1L_Pos)        /*!< 0x00000007 */
#define SAI_PDMDLY_DLYM1L                   SAI_PDMDLY_DLYM1L_Msk                   /*!<DLYM1L[2:0] (Delay line adjust for left microphone of pair 1) */
#define SAI_PDMDLY_DLYM1L_0                 (0x1UL << SAI_PDMDLY_DLYM1L_Pos)        /*!< 0x00000001 */
#define SAI_PDMDLY_DLYM1L_1                 (0x2UL << SAI_PDMDLY_DLYM1L_Pos)        /*!< 0x00000002 */
#define SAI_PDMDLY_DLYM1L_2                 (0x4UL << SAI_PDMDLY_DLYM1L_Pos)        /*!< 0x00000004 */
#define SAI_PDMDLY_DLYM1R_Pos               (4UL)
#define SAI_PDMDLY_DLYM1R_Msk               (0x7UL << SAI_PDMDLY_DLYM1R_Pos)        /*!< 0x00000070 */
#define SAI_PDMDLY_DLYM1R                   SAI_PDMDLY_DLYM1R_Msk                   /*!<DLYM1R[2:0] (Delay line adjust for right microphone of pair 1) */
#define SAI_PDMDLY_DLYM1R_0                 (0x1UL << SAI_PDMDLY_DLYM1R_Pos)        /*!< 0x00000010 */
#define SAI_PDMDLY_DLYM1R_1                 (0x2UL << SAI_PDMDLY_DLYM1R_Pos)        /*!< 0x00000020 */
#define SAI_PDMDLY_DLYM1R_2                 (0x4UL << SAI_PDMDLY_DLYM1R_Pos)        /*!< 0x00000040 */
#define SAI_PDMDLY_DLYM2L_Pos               (8UL)
#define SAI_PDMDLY_DLYM2L_Msk               (0x7UL << SAI_PDMDLY_DLYM2L_Pos)        /*!< 0x00000700 */
#define SAI_PDMDLY_DLYM2L                   SAI_PDMDLY_DLYM2L_Msk                   /*!<DLYM2L[2:0] (Delay line adjust for left microphone of pair 2) */
#define SAI_PDMDLY_DLYM2L_0                 (0x1UL << SAI_PDMDLY_DLYM2L_Pos)        /*!< 0x00000100 */
#define SAI_PDMDLY_DLYM2L_1                 (0x2UL << SAI_PDMDLY_DLYM2L_Pos)        /*!< 0x00000200 */
#define SAI_PDMDLY_DLYM2L_2                 (0x4UL << SAI_PDMDLY_DLYM2L_Pos)        /*!< 0x00000400 */
#define SAI_PDMDLY_DLYM2R_Pos               (12UL)
#define SAI_PDMDLY_DLYM2R_Msk               (0x7UL << SAI_PDMDLY_DLYM2R_Pos)        /*!< 0x00007000 */
#define SAI_PDMDLY_DLYM2R                   SAI_PDMDLY_DLYM2R_Msk                   /*!<DLYM2R[2:0] (Delay line adjust for right microphone of pair 2) */
#define SAI_PDMDLY_DLYM2R_0                 (0x1UL << SAI_PDMDLY_DLYM2R_Pos)        /*!< 0x00001000 */
#define SAI_PDMDLY_DLYM2R_1                 (0x2UL << SAI_PDMDLY_DLYM2R_Pos)        /*!< 0x00002000 */
#define SAI_PDMDLY_DLYM2R_2                 (0x4UL << SAI_PDMDLY_DLYM2R_Pos)        /*!< 0x00004000 */
#define SAI_PDMDLY_DLYM3L_Pos               (16UL)
#define SAI_PDMDLY_DLYM3L_Msk               (0x7UL << SAI_PDMDLY_DLYM3L_Pos)        /*!< 0x00070000 */
#define SAI_PDMDLY_DLYM3L                   SAI_PDMDLY_DLYM3L_Msk                   /*!<DLYM3L[2:0] (Delay line adjust for left microphone of pair 3) */
#define SAI_PDMDLY_DLYM3L_0                 (0x1UL << SAI_PDMDLY_DLYM3L_Pos)        /*!< 0x00010000 */
#define SAI_PDMDLY_DLYM3L_1                 (0x2UL << SAI_PDMDLY_DLYM3L_Pos)        /*!< 0x00020000 */
#define SAI_PDMDLY_DLYM3L_2                 (0x4UL << SAI_PDMDLY_DLYM3L_Pos)        /*!< 0x00040000 */
#define SAI_PDMDLY_DLYM3R_Pos               (20UL)
#define SAI_PDMDLY_DLYM3R_Msk               (0x7UL << SAI_PDMDLY_DLYM3R_Pos)        /*!< 0x00700000 */
#define SAI_PDMDLY_DLYM3R                   SAI_PDMDLY_DLYM3R_Msk                   /*!<DLYM3R[2:0] (Delay line adjust for right microphone of pair 3) */
#define SAI_PDMDLY_DLYM3R_0                 (0x1UL << SAI_PDMDLY_DLYM3R_Pos)        /*!< 0x00100000 */
#define SAI_PDMDLY_DLYM3R_1                 (0x2UL << SAI_PDMDLY_DLYM3R_Pos)        /*!< 0x00200000 */
#define SAI_PDMDLY_DLYM3R_2                 (0x4UL << SAI_PDMDLY_DLYM3R_Pos)        /*!< 0x00400000 */
#define SAI_PDMDLY_DLYM4L_Pos               (24UL)
#define SAI_PDMDLY_DLYM4L_Msk               (0x7UL << SAI_PDMDLY_DLYM4L_Pos)        /*!< 0x07000000 */
#define SAI_PDMDLY_DLYM4L                   SAI_PDMDLY_DLYM4L_Msk                   /*!<DLYM4L[2:0] (Delay line adjust for left microphone of pair 4) */
#define SAI_PDMDLY_DLYM4L_0                 (0x1UL << SAI_PDMDLY_DLYM4L_Pos)        /*!< 0x01000000 */
#define SAI_PDMDLY_DLYM4L_1                 (0x2UL << SAI_PDMDLY_DLYM4L_Pos)        /*!< 0x02000000 */
#define SAI_PDMDLY_DLYM4L_2                 (0x4UL << SAI_PDMDLY_DLYM4L_Pos)        /*!< 0x04000000 */
#define SAI_PDMDLY_DLYM4R_Pos               (28UL)
#define SAI_PDMDLY_DLYM4R_Msk               (0x7UL << SAI_PDMDLY_DLYM4R_Pos)        /*!< 0x70000000 */
#define SAI_PDMDLY_DLYM4R                   SAI_PDMDLY_DLYM4R_Msk                   /*!<DLYM4R[2:0] (Delay line adjust for right microphone of pair 4) */
#define SAI_PDMDLY_DLYM4R_0                 (0x1UL << SAI_PDMDLY_DLYM4R_Pos)        /*!< 0x10000000 */
#define SAI_PDMDLY_DLYM4R_1                 (0x2UL << SAI_PDMDLY_DLYM4R_Pos)        /*!< 0x20000000 */
#define SAI_PDMDLY_DLYM4R_2                 (0x4UL << SAI_PDMDLY_DLYM4R_Pos)        /*!< 0x40000000 */

/******************************************************************************/
/*                                                                            */
/*                           SDMMC Interface                                  */
/*                                                                            */
/******************************************************************************/
/******************  Bit definition for SDMMC_POWER register  ******************/
#define SDMMC_POWER_PWRCTRL_Pos             (0UL)
#define SDMMC_POWER_PWRCTRL_Msk             (0x3UL << SDMMC_POWER_PWRCTRL_Pos)      /*!< 0x00000003 */
#define SDMMC_POWER_PWRCTRL                 SDMMC_POWER_PWRCTRL_Msk                 /*!<PWRCTRL[1:0] bits (Power supply control bits) */
#define SDMMC_POWER_PWRCTRL_0               (0x1UL << SDMMC_POWER_PWRCTRL_Pos)      /*!< 0x00000001 */
#define SDMMC_POWER_PWRCTRL_1               (0x2UL << SDMMC_POWER_PWRCTRL_Pos)      /*!< 0x00000002 */
#define SDMMC_POWER_VSWITCH_Pos             (2UL)
#define SDMMC_POWER_VSWITCH_Msk             (0x1UL << SDMMC_POWER_VSWITCH_Pos)      /*!< 0x00000004 */
#define SDMMC_POWER_VSWITCH                 SDMMC_POWER_VSWITCH_Msk                 /*!<Voltage switch sequence start */
#define SDMMC_POWER_VSWITCHEN_Pos           (3UL)
#define SDMMC_POWER_VSWITCHEN_Msk           (0x1UL << SDMMC_POWER_VSWITCHEN_Pos)    /*!< 0x00000008 */
#define SDMMC_POWER_VSWITCHEN               SDMMC_POWER_VSWITCHEN_Msk               /*!<Voltage switch procedure enable */
#define SDMMC_POWER_DIRPOL_Pos              (4UL)
#define SDMMC_POWER_DIRPOL_Msk              (0x1UL << SDMMC_POWER_DIRPOL_Pos)       /*!< 0x00000010 */
#define SDMMC_POWER_DIRPOL                  SDMMC_POWER_DIRPOL_Msk                  /*!<Data and Command direction signals polarity selection */

/******************  Bit definition for SDMMC_CLKCR register  ******************/
#define SDMMC_CLKCR_CLKDIV_Pos              (0UL)
#define SDMMC_CLKCR_CLKDIV_Msk              (0x3FFUL << SDMMC_CLKCR_CLKDIV_Pos)     /*!< 0x000003FF */
#define SDMMC_CLKCR_CLKDIV                  SDMMC_CLKCR_CLKDIV_Msk                  /*!<Clock divide factor             */
#define SDMMC_CLKCR_PWRSAV_Pos              (12UL)
#define SDMMC_CLKCR_PWRSAV_Msk              (0x1UL << SDMMC_CLKCR_PWRSAV_Pos)       /*!< 0x00001000 */
#define SDMMC_CLKCR_PWRSAV                  SDMMC_CLKCR_PWRSAV_Msk                  /*!<Power saving configuration bit  */
#define SDMMC_CLKCR_WIDBUS_Pos              (14UL)
#define SDMMC_CLKCR_WIDBUS_Msk              (0x3UL << SDMMC_CLKCR_WIDBUS_Pos)       /*!< 0x0000C000 */
#define SDMMC_CLKCR_WIDBUS                  SDMMC_CLKCR_WIDBUS_Msk                  /*!<WIDBUS[1:0] bits (Wide bus mode enable bit) */
#define SDMMC_CLKCR_WIDBUS_0                (0x1UL << SDMMC_CLKCR_WIDBUS_Pos)       /*!< 0x00004000 */
#define SDMMC_CLKCR_WIDBUS_1                (0x2UL << SDMMC_CLKCR_WIDBUS_Pos)       /*!< 0x00008000 */
#define SDMMC_CLKCR_NEGEDGE_Pos             (16UL)
#define SDMMC_CLKCR_NEGEDGE_Msk             (0x1UL << SDMMC_CLKCR_NEGEDGE_Pos)      /*!< 0x00010000 */
#define SDMMC_CLKCR_NEGEDGE                 SDMMC_CLKCR_NEGEDGE_Msk                 /*!<SDMMC_CK dephasing selection bit */
#define SDMMC_CLKCR_HWFC_EN_Pos             (17UL)
#define SDMMC_CLKCR_HWFC_EN_Msk             (0x1UL << SDMMC_CLKCR_HWFC_EN_Pos)      /*!< 0x00020000 */
#define SDMMC_CLKCR_HWFC_EN                 SDMMC_CLKCR_HWFC_EN_Msk                 /*!<HW Flow Control enable           */
#define SDMMC_CLKCR_DDR_Pos                 (18UL)
#define SDMMC_CLKCR_DDR_Msk                 (0x1UL << SDMMC_CLKCR_DDR_Pos)          /*!< 0x00040000 */
#define SDMMC_CLKCR_DDR                     SDMMC_CLKCR_DDR_Msk                     /*!<Data rate signaling selection    */
#define SDMMC_CLKCR_BUSSPEED_Pos            (19UL)
#define SDMMC_CLKCR_BUSSPEED_Msk            (0x1UL << SDMMC_CLKCR_BUSSPEED_Pos)     /*!< 0x00080000 */
#define SDMMC_CLKCR_BUSSPEED                SDMMC_CLKCR_BUSSPEED_Msk                /*!<Bus speed mode selection         */
#define SDMMC_CLKCR_SELCLKRX_Pos            (20UL)
#define SDMMC_CLKCR_SELCLKRX_Msk            (0x3UL << SDMMC_CLKCR_SELCLKRX_Pos)     /*!< 0x00300000 */
#define SDMMC_CLKCR_SELCLKRX                SDMMC_CLKCR_SELCLKRX_Msk                /*!<SELCLKRX[1:0] bits (Receive clock selection) */
#define SDMMC_CLKCR_SELCLKRX_0              (0x1UL << SDMMC_CLKCR_SELCLKRX_Pos)     /*!< 0x00100000 */
#define SDMMC_CLKCR_SELCLKRX_1              (0x2UL << SDMMC_CLKCR_SELCLKRX_Pos)     /*!< 0x00200000 */

/*******************  Bit definition for SDMMC_ARG register  *******************/
#define SDMMC_ARG_CMDARG_Pos                (0UL)
#define SDMMC_ARG_CMDARG_Msk                (0xFFFFFFFFUL << SDMMC_ARG_CMDARG_Pos)  /*!< 0xFFFFFFFF */
#define SDMMC_ARG_CMDARG                    SDMMC_ARG_CMDARG_Msk                    /*!<Command argument */

/*******************  Bit definition for SDMMC_CMD register  *******************/
#define SDMMC_CMD_CMDINDEX_Pos              (0UL)
#define SDMMC_CMD_CMDINDEX_Msk              (0x3FUL << SDMMC_CMD_CMDINDEX_Pos)      /*!< 0x0000003F */
#define SDMMC_CMD_CMDINDEX                  SDMMC_CMD_CMDINDEX_Msk                  /*!<Command Index                               */
#define SDMMC_CMD_CMDTRANS_Pos              (6UL)
#define SDMMC_CMD_CMDTRANS_Msk              (0x1UL << SDMMC_CMD_CMDTRANS_Pos)       /*!< 0x00000040 */
#define SDMMC_CMD_CMDTRANS                  SDMMC_CMD_CMDTRANS_Msk                  /*!<CPSM Treats command as a Data Transfer      */
#define SDMMC_CMD_CMDSTOP_Pos               (7UL)
#define SDMMC_CMD_CMDSTOP_Msk               (0x1UL << SDMMC_CMD_CMDSTOP_Pos)        /*!< 0x00000080 */
#define SDMMC_CMD_CMDSTOP                   SDMMC_CMD_CMDSTOP_Msk                   /*!<CPSM Treats command as a Stop               */
#define SDMMC_CMD_WAITRESP_Pos              (8UL)
#define SDMMC_CMD_WAITRESP_Msk              (0x3UL << SDMMC_CMD_WAITRESP_Pos)       /*!< 0x00000300 */
#define SDMMC_CMD_WAITRESP                  SDMMC_CMD_WAITRESP_Msk                  /*!<WAITRESP[1:0] bits (Wait for response bits) */
#define SDMMC_CMD_WAITRESP_0                (0x1UL << SDMMC_CMD_WAITRESP_Pos)       /*!< 0x00000100 */
#define SDMMC_CMD_WAITRESP_1                (0x2UL << SDMMC_CMD_WAITRESP_Pos)       /*!< 0x00000200 */
#define SDMMC_CMD_WAITINT_Pos               (10UL)
#define SDMMC_CMD_WAITINT_Msk               (0x1UL << SDMMC_CMD_WAITINT_Pos)        /*!< 0x00000400 */
#define SDMMC_CMD_WAITINT                   SDMMC_CMD_WAITINT_Msk                   /*!<CPSM Waits for Interrupt Request                               */
#define SDMMC_CMD_WAITPEND_Pos              (11UL)
#define SDMMC_CMD_WAITPEND_Msk              (0x1UL << SDMMC_CMD_WAITPEND_Pos)       /*!< 0x00000800 */
#define SDMMC_CMD_WAITPEND                  SDMMC_CMD_WAITPEND_Msk                  /*!<CPSM Waits for ends of data transfer (CmdPend internal signal) */
#define SDMMC_CMD_CPSMEN_Pos                (12UL)
#define SDMMC_CMD_CPSMEN_Msk                (0x1UL << SDMMC_CMD_CPSMEN_Pos)         /*!< 0x00001000 */
#define SDMMC_CMD_CPSMEN                    SDMMC_CMD_CPSMEN_Msk                    /*!<Command path state machine (CPSM) Enable bit                   */
#define SDMMC_CMD_DTHOLD_Pos                (13UL)
#define SDMMC_CMD_DTHOLD_Msk                (0x1UL << SDMMC_CMD_DTHOLD_Pos)         /*!< 0x00002000 */
#define SDMMC_CMD_DTHOLD                    SDMMC_CMD_DTHOLD_Msk                    /*!<Hold new data block transmission and reception in the DPSM     */
#define SDMMC_CMD_BOOTMODE_Pos              (14UL)
#define SDMMC_CMD_BOOTMODE_Msk              (0x1UL << SDMMC_CMD_BOOTMODE_Pos)       /*!< 0x00004000 */
#define SDMMC_CMD_BOOTMODE                  SDMMC_CMD_BOOTMODE_Msk                  /*!<Boot mode                                                      */
#define SDMMC_CMD_BOOTEN_Pos                (15UL)
#define SDMMC_CMD_BOOTEN_Msk                (0x1UL << SDMMC_CMD_BOOTEN_Pos)         /*!< 0x00008000 */
#define SDMMC_CMD_BOOTEN                    SDMMC_CMD_BOOTEN_Msk                    /*!<Enable Boot mode procedure                                     */
#define SDMMC_CMD_CMDSUSPEND_Pos            (16UL)
#define SDMMC_CMD_CMDSUSPEND_Msk            (0x1UL << SDMMC_CMD_CMDSUSPEND_Pos)     /*!< 0x00010000 */
#define SDMMC_CMD_CMDSUSPEND                SDMMC_CMD_CMDSUSPEND_Msk                /*!<CPSM Treats command as a Suspend or Resume command             */

/*****************  Bit definition for SDMMC_RESPCMD register  *****************/
#define SDMMC_RESPCMD_RESPCMD_Pos           (0UL)
#define SDMMC_RESPCMD_RESPCMD_Msk           (0x3FUL << SDMMC_RESPCMD_RESPCMD_Pos)   /*!< 0x0000003F */
#define SDMMC_RESPCMD_RESPCMD               SDMMC_RESPCMD_RESPCMD_Msk               /*!<Response command index */

/******************  Bit definition for SDMMC_RESP1 register  ******************/
#define SDMMC_RESP1_CARDSTATUS1_Pos         (0UL)
#define SDMMC_RESP1_CARDSTATUS1_Msk         (0xFFFFFFFFUL << SDMMC_RESP1_CARDSTATUS1_Pos) /*!< 0xFFFFFFFF */
#define SDMMC_RESP1_CARDSTATUS1             SDMMC_RESP1_CARDSTATUS1_Msk             /*!<Card Status */

/******************  Bit definition for SDMMC_RESP2 register  ******************/
#define SDMMC_RESP2_CARDSTATUS2_Pos         (0UL)
#define SDMMC_RESP2_CARDSTATUS2_Msk         (0xFFFFFFFFUL << SDMMC_RESP2_CARDSTATUS2_Pos) /*!< 0xFFFFFFFF */
#define SDMMC_RESP2_CARDSTATUS2             SDMMC_RESP2_CARDSTATUS2_Msk             /*!<Card Status */

/******************  Bit definition for SDMMC_RESP3 register  ******************/
#define SDMMC_RESP3_CARDSTATUS3_Pos         (0UL)
#define SDMMC_RESP3_CARDSTATUS3_Msk         (0xFFFFFFFFUL << SDMMC_RESP3_CARDSTATUS3_Pos) /*!< 0xFFFFFFFF */
#define SDMMC_RESP3_CARDSTATUS3             SDMMC_RESP3_CARDSTATUS3_Msk             /*!<Card Status */

/******************  Bit definition for SDMMC_RESP4 register  ******************/
#define SDMMC_RESP4_CARDSTATUS4_Pos         (0UL)
#define SDMMC_RESP4_CARDSTATUS4_Msk         (0xFFFFFFFFUL << SDMMC_RESP4_CARDSTATUS4_Pos) /*!< 0xFFFFFFFF */
#define SDMMC_RESP4_CARDSTATUS4             SDMMC_RESP4_CARDSTATUS4_Msk             /*!<Card Status */

/******************  Bit definition for SDMMC_DTIMER register  *****************/
#define SDMMC_DTIMER_DATATIME_Pos           (0UL)
#define SDMMC_DTIMER_DATATIME_Msk           (0xFFFFFFFFUL << SDMMC_DTIMER_DATATIME_Pos) /*!< 0xFFFFFFFF */
#define SDMMC_DTIMER_DATATIME               SDMMC_DTIMER_DATATIME_Msk               /*!<Data timeout period. */

/******************  Bit definition for SDMMC_DLEN register  *******************/
#define SDMMC_DLEN_DATALENGTH_Pos           (0UL)
#define SDMMC_DLEN_DATALENGTH_Msk           (0x1FFFFFFUL << SDMMC_DLEN_DATALENGTH_Pos) /*!< 0x01FFFFFF */
#define SDMMC_DLEN_DATALENGTH               SDMMC_DLEN_DATALENGTH_Msk               /*!<Data length value    */

/******************  Bit definition for SDMMC_DCTRL register  ******************/
#define SDMMC_DCTRL_DTEN_Pos                (0UL)
#define SDMMC_DCTRL_DTEN_Msk                (0x1UL << SDMMC_DCTRL_DTEN_Pos)         /*!< 0x00000001 */
#define SDMMC_DCTRL_DTEN                    SDMMC_DCTRL_DTEN_Msk                    /*!<Data transfer enabled bit                */
#define SDMMC_DCTRL_DTDIR_Pos               (1UL)
#define SDMMC_DCTRL_DTDIR_Msk               (0x1UL << SDMMC_DCTRL_DTDIR_Pos)        /*!< 0x00000002 */
#define SDMMC_DCTRL_DTDIR                   SDMMC_DCTRL_DTDIR_Msk                   /*!<Data transfer direction selection        */
#define SDMMC_DCTRL_DTMODE_Pos              (2UL)
#define SDMMC_DCTRL_DTMODE_Msk              (0x3UL << SDMMC_DCTRL_DTMODE_Pos)       /*!< 0x0000000C */
#define SDMMC_DCTRL_DTMODE                  SDMMC_DCTRL_DTMODE_Msk                  /*!<DTMODE[1:0] Data transfer mode selection */
#define SDMMC_DCTRL_DTMODE_0                (0x1UL << SDMMC_DCTRL_DTMODE_Pos)       /*!< 0x00000004 */
#define SDMMC_DCTRL_DTMODE_1                (0x2UL << SDMMC_DCTRL_DTMODE_Pos)       /*!< 0x00000008 */
#define SDMMC_DCTRL_DBLOCKSIZE_Pos          (4UL)
#define SDMMC_DCTRL_DBLOCKSIZE_Msk          (0xFUL << SDMMC_DCTRL_DBLOCKSIZE_Pos)   /*!< 0x000000F0 */
#define SDMMC_DCTRL_DBLOCKSIZE              SDMMC_DCTRL_DBLOCKSIZE_Msk              /*!<DBLOCKSIZE[3:0] bits (Data block size) */
#define SDMMC_DCTRL_DBLOCKSIZE_0            (0x1UL << SDMMC_DCTRL_DBLOCKSIZE_Pos)   /*!< 0x00000010 */
#define SDMMC_DCTRL_DBLOCKSIZE_1            (0x2UL << SDMMC_DCTRL_DBLOCKSIZE_Pos)   /*!< 0x00000020 */
#define SDMMC_DCTRL_DBLOCKSIZE_2            (0x4UL << SDMMC_DCTRL_DBLOCKSIZE_Pos)   /*!< 0x00000040 */
#define SDMMC_DCTRL_DBLOCKSIZE_3            (0x8UL << SDMMC_DCTRL_DBLOCKSIZE_Pos)   /*!< 0x00000080 */
#define SDMMC_DCTRL_RWSTART_Pos             (8UL)
#define SDMMC_DCTRL_RWSTART_Msk             (0x1UL << SDMMC_DCTRL_RWSTART_Pos)      /*!< 0x00000100 */
#define SDMMC_DCTRL_RWSTART                 SDMMC_DCTRL_RWSTART_Msk                 /*!<Read wait start                                 */
#define SDMMC_DCTRL_RWSTOP_Pos              (9UL)
#define SDMMC_DCTRL_RWSTOP_Msk              (0x1UL << SDMMC_DCTRL_RWSTOP_Pos)       /*!< 0x00000200 */
#define SDMMC_DCTRL_RWSTOP                  SDMMC_DCTRL_RWSTOP_Msk                  /*!<Read wait stop                                  */
#define SDMMC_DCTRL_RWMOD_Pos               (10UL)
#define SDMMC_DCTRL_RWMOD_Msk               (0x1UL << SDMMC_DCTRL_RWMOD_Pos)        /*!< 0x00000400 */
#define SDMMC_DCTRL_RWMOD                   SDMMC_DCTRL_RWMOD_Msk                   /*!<Read wait mode                                  */
#define SDMMC_DCTRL_SDIOEN_Pos              (11UL)
#define SDMMC_DCTRL_SDIOEN_Msk              (0x1UL << SDMMC_DCTRL_SDIOEN_Pos)       /*!< 0x00000800 */
#define SDMMC_DCTRL_SDIOEN                  SDMMC_DCTRL_SDIOEN_Msk                  /*!<SD I/O enable functions                         */
#define SDMMC_DCTRL_BOOTACKEN_Pos           (12UL)
#define SDMMC_DCTRL_BOOTACKEN_Msk           (0x1UL << SDMMC_DCTRL_BOOTACKEN_Pos)    /*!< 0x00001000 */
#define SDMMC_DCTRL_BOOTACKEN               SDMMC_DCTRL_BOOTACKEN_Msk               /*!<Enable the reception of the Boot Acknowledgment */
#define SDMMC_DCTRL_FIFORST_Pos             (13UL)
#define SDMMC_DCTRL_FIFORST_Msk             (0x1UL << SDMMC_DCTRL_FIFORST_Pos)      /*!< 0x00002000 */
#define SDMMC_DCTRL_FIFORST                 SDMMC_DCTRL_FIFORST_Msk                 /*!<FIFO reset                                      */

/******************  Bit definition for SDMMC_DCOUNT register  *****************/
#define SDMMC_DCOUNT_DATACOUNT_Pos          (0UL)
#define SDMMC_DCOUNT_DATACOUNT_Msk          (0x1FFFFFFUL << SDMMC_DCOUNT_DATACOUNT_Pos) /*!< 0x01FFFFFF */
#define SDMMC_DCOUNT_DATACOUNT              SDMMC_DCOUNT_DATACOUNT_Msk              /*!<Data count value */

/******************  Bit definition for SDMMC_STA register  ********************/
#define SDMMC_STA_CCRCFAIL_Pos              (0UL)
#define SDMMC_STA_CCRCFAIL_Msk              (0x1UL << SDMMC_STA_CCRCFAIL_Pos)       /*!< 0x00000001 */
#define SDMMC_STA_CCRCFAIL                  SDMMC_STA_CCRCFAIL_Msk                  /*!<Command response received (CRC check failed)  */
#define SDMMC_STA_DCRCFAIL_Pos              (1UL)
#define SDMMC_STA_DCRCFAIL_Msk              (0x1UL << SDMMC_STA_DCRCFAIL_Pos)       /*!< 0x00000002 */
#define SDMMC_STA_DCRCFAIL                  SDMMC_STA_DCRCFAIL_Msk                  /*!<Data block sent/received (CRC check failed)   */
#define SDMMC_STA_CTIMEOUT_Pos              (2UL)
#define SDMMC_STA_CTIMEOUT_Msk              (0x1UL << SDMMC_STA_CTIMEOUT_Pos)       /*!< 0x00000004 */
#define SDMMC_STA_CTIMEOUT                  SDMMC_STA_CTIMEOUT_Msk                  /*!<Command response timeout                      */
#define SDMMC_STA_DTIMEOUT_Pos              (3UL)
#define SDMMC_STA_DTIMEOUT_Msk              (0x1UL << SDMMC_STA_DTIMEOUT_Pos)       /*!< 0x00000008 */
#define SDMMC_STA_DTIMEOUT                  SDMMC_STA_DTIMEOUT_Msk                  /*!<Data timeout                                  */
#define SDMMC_STA_TXUNDERR_Pos              (4UL)
#define SDMMC_STA_TXUNDERR_Msk              (0x1UL << SDMMC_STA_TXUNDERR_Pos)       /*!< 0x00000010 */
#define SDMMC_STA_TXUNDERR                  SDMMC_STA_TXUNDERR_Msk                  /*!<Transmit FIFO underrun error                  */
#define SDMMC_STA_RXOVERR_Pos               (5UL)
#define SDMMC_STA_RXOVERR_Msk               (0x1UL << SDMMC_STA_RXOVERR_Pos)        /*!< 0x00000020 */
#define SDMMC_STA_RXOVERR                   SDMMC_STA_RXOVERR_Msk                   /*!<Received FIFO overrun error                   */
#define SDMMC_STA_CMDREND_Pos               (6UL)
#define SDMMC_STA_CMDREND_Msk               (0x1UL << SDMMC_STA_CMDREND_Pos)        /*!< 0x00000040 */
#define SDMMC_STA_CMDREND                   SDMMC_STA_CMDREND_Msk                   /*!<Command response received (CRC check passed)  */
#define SDMMC_STA_CMDSENT_Pos               (7UL)
#define SDMMC_STA_CMDSENT_Msk               (0x1UL << SDMMC_STA_CMDSENT_Pos)        /*!< 0x00000080 */
#define SDMMC_STA_CMDSENT                   SDMMC_STA_CMDSENT_Msk                   /*!<Command sent (no response required)           */
#define SDMMC_STA_DATAEND_Pos               (8UL)
#define SDMMC_STA_DATAEND_Msk               (0x1UL << SDMMC_STA_DATAEND_Pos)        /*!< 0x00000100 */
#define SDMMC_STA_DATAEND                   SDMMC_STA_DATAEND_Msk                   /*!<Data end (data counter, SDIDCOUNT, is zero)   */
#define SDMMC_STA_DHOLD_Pos                 (9UL)
#define SDMMC_STA_DHOLD_Msk                 (0x1UL << SDMMC_STA_DHOLD_Pos)          /*!< 0x00000200 */
#define SDMMC_STA_DHOLD                     SDMMC_STA_DHOLD_Msk                     /*!<Data transfer Hold                                                      */
#define SDMMC_STA_DBCKEND_Pos               (10UL)
#define SDMMC_STA_DBCKEND_Msk               (0x1UL << SDMMC_STA_DBCKEND_Pos)        /*!< 0x00000400 */
#define SDMMC_STA_DBCKEND                   SDMMC_STA_DBCKEND_Msk                   /*!<Data block sent/received (CRC check passed)   */
#define SDMMC_STA_DABORT_Pos                (11UL)
#define SDMMC_STA_DABORT_Msk                (0x1UL << SDMMC_STA_DABORT_Pos)         /*!< 0x00000800 */
#define SDMMC_STA_DABORT                    SDMMC_STA_DABORT_Msk                    /*!<Data transfer aborted by CMD12                                          */
#define SDMMC_STA_DPSMACT_Pos               (12UL)
#define SDMMC_STA_DPSMACT_Msk               (0x1UL << SDMMC_STA_DPSMACT_Pos)        /*!< 0x00001000 */
#define SDMMC_STA_DPSMACT                   SDMMC_STA_DPSMACT_Msk                   /*!<Data path state machine active                                       */
#define SDMMC_STA_CPSMACT_Pos               (13UL)
#define SDMMC_STA_CPSMACT_Msk               (0x1UL << SDMMC_STA_CPSMACT_Pos)        /*!< 0x00002000 */
#define SDMMC_STA_CPSMACT                   SDMMC_STA_CPSMACT_Msk                   /*!<Command path state machine active                                          */
#define SDMMC_STA_TXFIFOHE_Pos              (14UL)
#define SDMMC_STA_TXFIFOHE_Msk              (0x1UL << SDMMC_STA_TXFIFOHE_Pos)       /*!< 0x00004000 */
#define SDMMC_STA_TXFIFOHE                  SDMMC_STA_TXFIFOHE_Msk                  /*!<Transmit FIFO Half Empty: at least 8 words can be written into the FIFO */
#define SDMMC_STA_RXFIFOHF_Pos              (15UL)
#define SDMMC_STA_RXFIFOHF_Msk              (0x1UL << SDMMC_STA_RXFIFOHF_Pos)       /*!< 0x00008000 */
#define SDMMC_STA_RXFIFOHF                  SDMMC_STA_RXFIFOHF_Msk                  /*!<Receive FIFO Half Full: there are at least 8 words in the FIFO */
#define SDMMC_STA_TXFIFOF_Pos               (16UL)
#define SDMMC_STA_TXFIFOF_Msk               (0x1UL << SDMMC_STA_TXFIFOF_Pos)        /*!< 0x00010000 */
#define SDMMC_STA_TXFIFOF                   SDMMC_STA_TXFIFOF_Msk                   /*!<Transmit FIFO full                            */
#define SDMMC_STA_RXFIFOF_Pos               (17UL)
#define SDMMC_STA_RXFIFOF_Msk               (0x1UL << SDMMC_STA_RXFIFOF_Pos)        /*!< 0x00020000 */
#define SDMMC_STA_RXFIFOF                   SDMMC_STA_RXFIFOF_Msk                   /*!<Receive FIFO full                             */
#define SDMMC_STA_TXFIFOE_Pos               (18UL)
#define SDMMC_STA_TXFIFOE_Msk               (0x1UL << SDMMC_STA_TXFIFOE_Pos)        /*!< 0x00040000 */
#define SDMMC_STA_TXFIFOE                   SDMMC_STA_TXFIFOE_Msk                   /*!<Transmit FIFO empty                           */
#define SDMMC_STA_RXFIFOE_Pos               (19UL)
#define SDMMC_STA_RXFIFOE_Msk               (0x1UL << SDMMC_STA_RXFIFOE_Pos)        /*!< 0x00080000 */
#define SDMMC_STA_RXFIFOE                   SDMMC_STA_RXFIFOE_Msk                   /*!<Receive FIFO empty                            */
#define SDMMC_STA_BUSYD0_Pos                (20UL)
#define SDMMC_STA_BUSYD0_Msk                (0x1UL << SDMMC_STA_BUSYD0_Pos)         /*!< 0x00100000 */
#define SDMMC_STA_BUSYD0                    SDMMC_STA_BUSYD0_Msk                    /*!<Inverted value of SDMMC_D0 line (Busy)                                  */
#define SDMMC_STA_BUSYD0END_Pos             (21UL)
#define SDMMC_STA_BUSYD0END_Msk             (0x1UL << SDMMC_STA_BUSYD0END_Pos)      /*!< 0x00200000 */
#define SDMMC_STA_BUSYD0END                 SDMMC_STA_BUSYD0END_Msk                 /*!<End of SDMMC_D0 Busy following a CMD response detected                  */
#define SDMMC_STA_SDIOIT_Pos                (22UL)
#define SDMMC_STA_SDIOIT_Msk                (0x1UL << SDMMC_STA_SDIOIT_Pos)         /*!< 0x00400000 */
#define SDMMC_STA_SDIOIT                    SDMMC_STA_SDIOIT_Msk                    /*!<SDIO interrupt received                                                 */
#define SDMMC_STA_ACKFAIL_Pos               (23UL)
#define SDMMC_STA_ACKFAIL_Msk               (0x1UL << SDMMC_STA_ACKFAIL_Pos)        /*!< 0x00800000 */
#define SDMMC_STA_ACKFAIL                   SDMMC_STA_ACKFAIL_Msk                   /*!<Boot Acknowledgment received (BootAck check fail)                       */
#define SDMMC_STA_ACKTIMEOUT_Pos            (24UL)
#define SDMMC_STA_ACKTIMEOUT_Msk            (0x1UL << SDMMC_STA_ACKTIMEOUT_Pos)     /*!< 0x01000000 */
#define SDMMC_STA_ACKTIMEOUT                SDMMC_STA_ACKTIMEOUT_Msk                /*!<Boot Acknowledgment timeout                                             */
#define SDMMC_STA_VSWEND_Pos                (25UL)
#define SDMMC_STA_VSWEND_Msk                (0x1UL << SDMMC_STA_VSWEND_Pos)         /*!< 0x02000000 */
#define SDMMC_STA_VSWEND                    SDMMC_STA_VSWEND_Msk                    /*!<Voltage switch critical timing section completion                       */
#define SDMMC_STA_CKSTOP_Pos                (26UL)
#define SDMMC_STA_CKSTOP_Msk                (0x1UL << SDMMC_STA_CKSTOP_Pos)         /*!< 0x04000000 */
#define SDMMC_STA_CKSTOP                    SDMMC_STA_CKSTOP_Msk                    /*!<SDMMC_CK stopped in Voltage switch procedure                            */
#define SDMMC_STA_IDMATE_Pos                (27UL)
#define SDMMC_STA_IDMATE_Msk                (0x1UL << SDMMC_STA_IDMATE_Pos)         /*!< 0x08000000 */
#define SDMMC_STA_IDMATE                    SDMMC_STA_IDMATE_Msk                    /*!<IDMA transfer error                                                     */
#define SDMMC_STA_IDMABTC_Pos               (28UL)
#define SDMMC_STA_IDMABTC_Msk               (0x1UL << SDMMC_STA_IDMABTC_Pos)        /*!< 0x10000000 */
#define SDMMC_STA_IDMABTC                   SDMMC_STA_IDMABTC_Msk                   /*!<IDMA buffer transfer complete                                           */

/*******************  Bit definition for SDMMC_ICR register  *******************/
#define SDMMC_ICR_CCRCFAILC_Pos             (0UL)
#define SDMMC_ICR_CCRCFAILC_Msk             (0x1UL << SDMMC_ICR_CCRCFAILC_Pos)      /*!< 0x00000001 */
#define SDMMC_ICR_CCRCFAILC                 SDMMC_ICR_CCRCFAILC_Msk                 /*!<CCRCFAIL flag clear bit */
#define SDMMC_ICR_DCRCFAILC_Pos             (1UL)
#define SDMMC_ICR_DCRCFAILC_Msk             (0x1UL << SDMMC_ICR_DCRCFAILC_Pos)      /*!< 0x00000002 */
#define SDMMC_ICR_DCRCFAILC                 SDMMC_ICR_DCRCFAILC_Msk                 /*!<DCRCFAIL flag clear bit */
#define SDMMC_ICR_CTIMEOUTC_Pos             (2UL)
#define SDMMC_ICR_CTIMEOUTC_Msk             (0x1UL << SDMMC_ICR_CTIMEOUTC_Pos)      /*!< 0x00000004 */
#define SDMMC_ICR_CTIMEOUTC                 SDMMC_ICR_CTIMEOUTC_Msk                 /*!<CTIMEOUT flag clear bit */
#define SDMMC_ICR_DTIMEOUTC_Pos             (3UL)
#define SDMMC_ICR_DTIMEOUTC_Msk             (0x1UL << SDMMC_ICR_DTIMEOUTC_Pos)      /*!< 0x00000008 */
#define SDMMC_ICR_DTIMEOUTC                 SDMMC_ICR_DTIMEOUTC_Msk                 /*!<DTIMEOUT flag clear bit */
#define SDMMC_ICR_TXUNDERRC_Pos             (4UL)
#define SDMMC_ICR_TXUNDERRC_Msk             (0x1UL << SDMMC_ICR_TXUNDERRC_Pos)      /*!< 0x00000010 */
#define SDMMC_ICR_TXUNDERRC                 SDMMC_ICR_TXUNDERRC_Msk                 /*!<TXUNDERR flag clear bit */
#define SDMMC_ICR_RXOVERRC_Pos              (5UL)
#define SDMMC_ICR_RXOVERRC_Msk              (0x1UL << SDMMC_ICR_RXOVERRC_Pos)       /*!< 0x00000020 */
#define SDMMC_ICR_RXOVERRC                  SDMMC_ICR_RXOVERRC_Msk                  /*!<RXOVERR flag clear bit  */
#define SDMMC_ICR_CMDRENDC_Pos              (6UL)
#define SDMMC_ICR_CMDRENDC_Msk              (0x1UL << SDMMC_ICR_CMDRENDC_Pos)       /*!< 0x00000040 */
#define SDMMC_ICR_CMDRENDC                  SDMMC_ICR_CMDRENDC_Msk                  /*!<CMDREND flag clear bit  */
#define SDMMC_ICR_CMDSENTC_Pos              (7UL)
#define SDMMC_ICR_CMDSENTC_Msk              (0x1UL << SDMMC_ICR_CMDSENTC_Pos)       /*!< 0x00000080 */
#define SDMMC_ICR_CMDSENTC                  SDMMC_ICR_CMDSENTC_Msk                  /*!<CMDSENT flag clear bit  */
#define SDMMC_ICR_DATAENDC_Pos              (8UL)
#define SDMMC_ICR_DATAENDC_Msk              (0x1UL << SDMMC_ICR_DATAENDC_Pos)       /*!< 0x00000100 */
#define SDMMC_ICR_DATAENDC                  SDMMC_ICR_DATAENDC_Msk                  /*!<DATAEND flag clear bit  */
#define SDMMC_ICR_DHOLDC_Pos                (9UL)
#define SDMMC_ICR_DHOLDC_Msk                (0x1UL << SDMMC_ICR_DHOLDC_Pos)         /*!< 0x00000200 */
#define SDMMC_ICR_DHOLDC                    SDMMC_ICR_DHOLDC_Msk                    /*!<DHOLD flag clear bit       */
#define SDMMC_ICR_DBCKENDC_Pos              (10UL)
#define SDMMC_ICR_DBCKENDC_Msk              (0x1UL << SDMMC_ICR_DBCKENDC_Pos)       /*!< 0x00000400 */
#define SDMMC_ICR_DBCKENDC                  SDMMC_ICR_DBCKENDC_Msk                  /*!<DBCKEND flag clear bit  */
#define SDMMC_ICR_DABORTC_Pos               (11UL)
#define SDMMC_ICR_DABORTC_Msk               (0x1UL << SDMMC_ICR_DABORTC_Pos)        /*!< 0x00000800 */
#define SDMMC_ICR_DABORTC                   SDMMC_ICR_DABORTC_Msk                   /*!<DABORTC flag clear bit     */
#define SDMMC_ICR_BUSYD0ENDC_Pos            (21UL)
#define SDMMC_ICR_BUSYD0ENDC_Msk            (0x1UL << SDMMC_ICR_BUSYD0ENDC_Pos)     /*!< 0x00200000 */
#define SDMMC_ICR_BUSYD0ENDC                SDMMC_ICR_BUSYD0ENDC_Msk                /*!<BUSYD0ENDC flag clear bit  */
#define SDMMC_ICR_SDIOITC_Pos               (22UL)
#define SDMMC_ICR_SDIOITC_Msk               (0x1UL << SDMMC_ICR_SDIOITC_Pos)        /*!< 0x00400000 */
#define SDMMC_ICR_SDIOITC                   SDMMC_ICR_SDIOITC_Msk                   /*!<SDIOIT flag clear bit      */
#define SDMMC_ICR_ACKFAILC_Pos              (23UL)
#define SDMMC_ICR_ACKFAILC_Msk              (0x1UL << SDMMC_ICR_ACKFAILC_Pos)       /*!< 0x00800000 */
#define SDMMC_ICR_ACKFAILC                  SDMMC_ICR_ACKFAILC_Msk                  /*!<ACKFAILC flag clear bit    */
#define SDMMC_ICR_ACKTIMEOUTC_Pos           (24UL)
#define SDMMC_ICR_ACKTIMEOUTC_Msk           (0x1UL << SDMMC_ICR_ACKTIMEOUTC_Pos)    /*!< 0x01000000 */
#define SDMMC_ICR_ACKTIMEOUTC               SDMMC_ICR_ACKTIMEOUTC_Msk               /*!<ACKTIMEOUTC flag clear bit */
#define SDMMC_ICR_VSWENDC_Pos               (25UL)
#define SDMMC_ICR_VSWENDC_Msk               (0x1UL << SDMMC_ICR_VSWENDC_Pos)        /*!< 0x02000000 */
#define SDMMC_ICR_VSWENDC                   SDMMC_ICR_VSWENDC_Msk                   /*!<VSWENDC flag clear bit     */
#define SDMMC_ICR_CKSTOPC_Pos               (26UL)
#define SDMMC_ICR_CKSTOPC_Msk               (0x1UL << SDMMC_ICR_CKSTOPC_Pos)        /*!< 0x04000000 */
#define SDMMC_ICR_CKSTOPC                   SDMMC_ICR_CKSTOPC_Msk                   /*!<CKSTOPC flag clear bit     */
#define SDMMC_ICR_IDMATEC_Pos               (27UL)
#define SDMMC_ICR_IDMATEC_Msk               (0x1UL << SDMMC_ICR_IDMATEC_Pos)        /*!< 0x08000000 */
#define SDMMC_ICR_IDMATEC                   SDMMC_ICR_IDMATEC_Msk                   /*!<IDMATEC flag clear bit     */
#define SDMMC_ICR_IDMABTCC_Pos              (28UL)
#define SDMMC_ICR_IDMABTCC_Msk              (0x1UL << SDMMC_ICR_IDMABTCC_Pos)       /*!< 0x10000000 */
#define SDMMC_ICR_IDMABTCC                  SDMMC_ICR_IDMABTCC_Msk                  /*!<IDMABTCC flag clear bit    */

/******************  Bit definition for SDMMC_MASK register  *******************/
#define SDMMC_MASK_CCRCFAILIE_Pos           (0UL)
#define SDMMC_MASK_CCRCFAILIE_Msk           (0x1UL << SDMMC_MASK_CCRCFAILIE_Pos)    /*!< 0x00000001 */
#define SDMMC_MASK_CCRCFAILIE               SDMMC_MASK_CCRCFAILIE_Msk               /*!<Command CRC Fail Interrupt Enable          */
#define SDMMC_MASK_DCRCFAILIE_Pos           (1UL)
#define SDMMC_MASK_DCRCFAILIE_Msk           (0x1UL << SDMMC_MASK_DCRCFAILIE_Pos)    /*!< 0x00000002 */
#define SDMMC_MASK_DCRCFAILIE               SDMMC_MASK_DCRCFAILIE_Msk               /*!<Data CRC Fail Interrupt Enable             */
#define SDMMC_MASK_CTIMEOUTIE_Pos           (2UL)
#define SDMMC_MASK_CTIMEOUTIE_Msk           (0x1UL << SDMMC_MASK_CTIMEOUTIE_Pos)    /*!< 0x00000004 */
#define SDMMC_MASK_CTIMEOUTIE               SDMMC_MASK_CTIMEOUTIE_Msk               /*!<Command TimeOut Interrupt Enable           */
#define SDMMC_MASK_DTIMEOUTIE_Pos           (3UL)
#define SDMMC_MASK_DTIMEOUTIE_Msk           (0x1UL << SDMMC_MASK_DTIMEOUTIE_Pos)    /*!< 0x00000008 */
#define SDMMC_MASK_DTIMEOUTIE               SDMMC_MASK_DTIMEOUTIE_Msk               /*!<Data TimeOut Interrupt Enable              */
#define SDMMC_MASK_TXUNDERRIE_Pos           (4UL)
#define SDMMC_MASK_TXUNDERRIE_Msk           (0x1UL << SDMMC_MASK_TXUNDERRIE_Pos)    /*!< 0x00000010 */
#define SDMMC_MASK_TXUNDERRIE               SDMMC_MASK_TXUNDERRIE_Msk               /*!<Tx FIFO UnderRun Error Interrupt Enable    */
#define SDMMC_MASK_RXOVERRIE_Pos            (5UL)
#define SDMMC_MASK_RXOVERRIE_Msk            (0x1UL << SDMMC_MASK_RXOVERRIE_Pos)     /*!< 0x00000020 */
#define SDMMC_MASK_RXOVERRIE                SDMMC_MASK_RXOVERRIE_Msk                /*!<Rx FIFO OverRun Error Interrupt Enable     */
#define SDMMC_MASK_CMDRENDIE_Pos            (6UL)
#define SDMMC_MASK_CMDRENDIE_Msk            (0x1UL << SDMMC_MASK_CMDRENDIE_Pos)     /*!< 0x00000040 */
#define SDMMC_MASK_CMDRENDIE                SDMMC_MASK_CMDRENDIE_Msk                /*!<Command Response Received Interrupt Enable */
#define SDMMC_MASK_CMDSENTIE_Pos            (7UL)
#define SDMMC_MASK_CMDSENTIE_Msk            (0x1UL << SDMMC_MASK_CMDSENTIE_Pos)     /*!< 0x00000080 */
#define SDMMC_MASK_CMDSENTIE                SDMMC_MASK_CMDSENTIE_Msk                /*!<Command Sent Interrupt Enable              */
#define SDMMC_MASK_DATAENDIE_Pos            (8UL)
#define SDMMC_MASK_DATAENDIE_Msk            (0x1UL << SDMMC_MASK_DATAENDIE_Pos)     /*!< 0x00000100 */
#define SDMMC_MASK_DATAENDIE                SDMMC_MASK_DATAENDIE_Msk                /*!<Data End Interrupt Enable                  */
#define SDMMC_MASK_DHOLDIE_Pos              (9UL)
#define SDMMC_MASK_DHOLDIE_Msk              (0x1UL << SDMMC_MASK_DHOLDIE_Pos)       /*!< 0x00000200 */
#define SDMMC_MASK_DHOLDIE                  SDMMC_MASK_DHOLDIE_Msk                  /*!<Data Hold Interrupt Enable                 */
#define SDMMC_MASK_DBCKENDIE_Pos            (10UL)
#define SDMMC_MASK_DBCKENDIE_Msk            (0x1UL << SDMMC_MASK_DBCKENDIE_Pos)     /*!< 0x00000400 */
#define SDMMC_MASK_DBCKENDIE                SDMMC_MASK_DBCKENDIE_Msk                /*!<Data Block End Interrupt Enable            */
#define SDMMC_MASK_DABORTIE_Pos             (11UL)
#define SDMMC_MASK_DABORTIE_Msk             (0x1UL << SDMMC_MASK_DABORTIE_Pos)      /*!< 0x00000800 */
#define SDMMC_MASK_DABORTIE                 SDMMC_MASK_DABORTIE_Msk                 /*!<Data transfer aborted interrupt enable     */
#define SDMMC_MASK_TXFIFOHEIE_Pos           (14UL)
#define SDMMC_MASK_TXFIFOHEIE_Msk           (0x1UL << SDMMC_MASK_TXFIFOHEIE_Pos)    /*!< 0x00004000 */
#define SDMMC_MASK_TXFIFOHEIE               SDMMC_MASK_TXFIFOHEIE_Msk               /*!<Tx FIFO Half Empty interrupt Enable        */
#define SDMMC_MASK_RXFIFOHFIE_Pos           (15UL)
#define SDMMC_MASK_RXFIFOHFIE_Msk           (0x1UL << SDMMC_MASK_RXFIFOHFIE_Pos)    /*!< 0x00008000 */
#define SDMMC_MASK_RXFIFOHFIE               SDMMC_MASK_RXFIFOHFIE_Msk               /*!<Rx FIFO Half Full interrupt Enable         */
#define SDMMC_MASK_RXFIFOFIE_Pos            (17UL)
#define SDMMC_MASK_RXFIFOFIE_Msk            (0x1UL << SDMMC_MASK_RXFIFOFIE_Pos)     /*!< 0x00020000 */
#define SDMMC_MASK_RXFIFOFIE                SDMMC_MASK_RXFIFOFIE_Msk                /*!<Rx FIFO Full interrupt Enable              */
#define SDMMC_MASK_TXFIFOEIE_Pos            (18UL)
#define SDMMC_MASK_TXFIFOEIE_Msk            (0x1UL << SDMMC_MASK_TXFIFOEIE_Pos)     /*!< 0x00040000 */
#define SDMMC_MASK_TXFIFOEIE                SDMMC_MASK_TXFIFOEIE_Msk                /*!<Tx FIFO Empty interrupt Enable             */
#define SDMMC_MASK_BUSYD0ENDIE_Pos          (21UL)
#define SDMMC_MASK_BUSYD0ENDIE_Msk          (0x1UL << SDMMC_MASK_BUSYD0ENDIE_Pos)   /*!< 0x00200000 */
#define SDMMC_MASK_BUSYD0ENDIE              SDMMC_MASK_BUSYD0ENDIE_Msk              /*!<BUSYD0ENDIE interrupt Enable */
#define SDMMC_MASK_SDIOITIE_Pos             (22UL)
#define SDMMC_MASK_SDIOITIE_Msk             (0x1UL << SDMMC_MASK_SDIOITIE_Pos)      /*!< 0x00400000 */
#define SDMMC_MASK_SDIOITIE                 SDMMC_MASK_SDIOITIE_Msk                 /*!<SDMMC Mode Interrupt Received interrupt Enable */
#define SDMMC_MASK_ACKFAILIE_Pos            (23UL)
#define SDMMC_MASK_ACKFAILIE_Msk            (0x1UL << SDMMC_MASK_ACKFAILIE_Pos)     /*!< 0x00800000 */
#define SDMMC_MASK_ACKFAILIE                SDMMC_MASK_ACKFAILIE_Msk                /*!<Acknowledgment Fail Interrupt Enable */
#define SDMMC_MASK_ACKTIMEOUTIE_Pos         (24UL)
#define SDMMC_MASK_ACKTIMEOUTIE_Msk         (0x1UL << SDMMC_MASK_ACKTIMEOUTIE_Pos)  /*!< 0x01000000 */
#define SDMMC_MASK_ACKTIMEOUTIE             SDMMC_MASK_ACKTIMEOUTIE_Msk             /*!<Acknowledgment timeout Interrupt Enable */
#define SDMMC_MASK_VSWENDIE_Pos             (25UL)
#define SDMMC_MASK_VSWENDIE_Msk             (0x1UL << SDMMC_MASK_VSWENDIE_Pos)      /*!< 0x02000000 */
#define SDMMC_MASK_VSWENDIE                 SDMMC_MASK_VSWENDIE_Msk                 /*!<Voltage switch critical timing section completion Interrupt Enable */
#define SDMMC_MASK_CKSTOPIE_Pos             (26UL)
#define SDMMC_MASK_CKSTOPIE_Msk             (0x1UL << SDMMC_MASK_CKSTOPIE_Pos)      /*!< 0x04000000 */
#define SDMMC_MASK_CKSTOPIE                 SDMMC_MASK_CKSTOPIE_Msk                 /*!<Voltage Switch clock stopped Interrupt Enable */
#define SDMMC_MASK_IDMABTCIE_Pos            (28UL)
#define SDMMC_MASK_IDMABTCIE_Msk            (0x1UL << SDMMC_MASK_IDMABTCIE_Pos)     /*!< 0x10000000 */
#define SDMMC_MASK_IDMABTCIE                SDMMC_MASK_IDMABTCIE_Msk                /*!<IDMA buffer transfer complete Interrupt Enable */

/*****************  Bit definition for SDMMC_ACKTIME register  *****************/
#define SDMMC_ACKTIME_ACKTIME_Pos           (0UL)
#define SDMMC_ACKTIME_ACKTIME_Msk           (0x1FFFFFFUL << SDMMC_ACKTIME_ACKTIME_Pos) /*!< 0x01FFFFFF */
#define SDMMC_ACKTIME_ACKTIME               SDMMC_ACKTIME_ACKTIME_Msk               /*!<Boot acknowledgment timeout period */

/******************  Bit definition for SDMMC_FIFO register  *******************/
#define SDMMC_FIFO_FIFODATA_Pos             (0UL)
#define SDMMC_FIFO_FIFODATA_Msk             (0xFFFFFFFFUL << SDMMC_FIFO_FIFODATA_Pos) /*!< 0xFFFFFFFF */
#define SDMMC_FIFO_FIFODATA                 SDMMC_FIFO_FIFODATA_Msk                 /*!<Receive and transmit FIFO data */

/******************  Bit definition for SDMMC_IDMACTRL register ****************/
#define SDMMC_IDMA_IDMAEN_Pos               (0UL)
#define SDMMC_IDMA_IDMAEN_Msk               (0x1UL << SDMMC_IDMA_IDMAEN_Pos)        /*!< 0x00000001 */
#define SDMMC_IDMA_IDMAEN                   SDMMC_IDMA_IDMAEN_Msk                   /*!< Enable the internal DMA of the SDMMC peripheral */
#define SDMMC_IDMA_IDMABMODE_Pos            (1UL)
#define SDMMC_IDMA_IDMABMODE_Msk            (0x1UL << SDMMC_IDMA_IDMABMODE_Pos)     /*!< 0x00000002 */
#define SDMMC_IDMA_IDMABMODE                SDMMC_IDMA_IDMABMODE_Msk                /*!< Enable Linked List mode for IDMA */

/*****************  Bit definition for SDMMC_IDMABSIZE register  ***************/
#define SDMMC_IDMABSIZE_IDMABNDT_Pos        (5UL)
#define SDMMC_IDMABSIZE_IDMABNDT_Msk        (0xFFFUL << SDMMC_IDMABSIZE_IDMABNDT_Pos) /*!< 0x0000FFE0 */
#define SDMMC_IDMABSIZE_IDMABNDT            SDMMC_IDMABSIZE_IDMABNDT_Msk            /*!< Number of transfers per buffer */

/*****************  Bit definition for SDMMC_IDMABASER register  ***************/
#define SDMMC_IDMABASER_IDMABASER           ((uint32_t)0xFFFFFFFF)                  /*!< Memory base address register */

/*****************  Bit definition for SDMMC_IDMALAR) register  ***************/
#define SDMMC_IDMALAR_IDMALA_Pos            (0UL)
#define SDMMC_IDMALAR_IDMALA_Msk            (0x3FFFUL << SDMMC_IDMALAR_IDMALA_Pos)  /*!< 0x00003FFF */
#define SDMMC_IDMALAR_IDMALA                SDMMC_IDMALAR_IDMALA_Msk                /*!< Linked list item address offset */
#define SDMMC_IDMALAR_ABR_Pos               (29UL)
#define SDMMC_IDMALAR_ABR_Msk               (0x1UL << SDMMC_IDMALAR_ABR_Pos)        /*!< 0x20000000 */
#define SDMMC_IDMALAR_ABR                   SDMMC_IDMALAR_ABR_Msk                   /*!< Acknowledge linked list buffer ready */
#define SDMMC_IDMALAR_ULS_Pos               (30UL)
#define SDMMC_IDMALAR_ULS_Msk               (0x1UL << SDMMC_IDMALAR_ULS_Pos)        /*!< 0x40000000 */
#define SDMMC_IDMALAR_ULS                   SDMMC_IDMALAR_ULS_Msk                   /*!< Update Size from linked list */
#define SDMMC_IDMALAR_ULA_Pos               (31UL)
#define SDMMC_IDMALAR_ULA_Msk               (0x1UL << SDMMC_IDMALAR_ULA_Pos)        /*!< 0x80000000 */
#define SDMMC_IDMALAR_ULA                   SDMMC_IDMALAR_ULA_Msk                   /*!< Update Address from linked list */

/*****************  Bit definition for SDMMC_IDMABAR) register  ***************/
#define SDMMC_IDMABAR_IDMABAR               ((uint32_t)0xFFFFFFFF)                  /*!< linked list memory base register */

/******************************************************************************/
/*                                                                            */
/*                   Serial Peripheral Interface (SPI)                        */
/*                                                                            */
/******************************************************************************/
/*******************  Bit definition for SPI_CR1 register  ********************/
#define SPI_CR1_SPE_Pos                     (0UL)
#define SPI_CR1_SPE_Msk                     (0x1UL << SPI_CR1_SPE_Pos)              /*!< 0x00000001 */
#define SPI_CR1_SPE                         SPI_CR1_SPE_Msk                         /*!<Serial Peripheral Enable */
#define SPI_CR1_MASRX_Pos                   (8UL)
#define SPI_CR1_MASRX_Msk                   (0x1UL << SPI_CR1_MASRX_Pos)            /*!< 0x00000100 */
#define SPI_CR1_MASRX                       SPI_CR1_MASRX_Msk                       /*!<Master automatic SUSP in Receive mode */
#define SPI_CR1_CSTART_Pos                  (9UL)
#define SPI_CR1_CSTART_Msk                  (0x1UL << SPI_CR1_CSTART_Pos)           /*!< 0x00000200 */
#define SPI_CR1_CSTART                      SPI_CR1_CSTART_Msk                      /*!<Master transfer start  */
#define SPI_CR1_CSUSP_Pos                   (10UL)
#define SPI_CR1_CSUSP_Msk                   (0x1UL << SPI_CR1_CSUSP_Pos)            /*!< 0x00000400 */
#define SPI_CR1_CSUSP                       SPI_CR1_CSUSP_Msk                       /*!<Master SUSPend request */
#define SPI_CR1_HDDIR_Pos                   (11UL)
#define SPI_CR1_HDDIR_Msk                   (0x1UL << SPI_CR1_HDDIR_Pos)            /*!< 0x00000800 */
#define SPI_CR1_HDDIR                       SPI_CR1_HDDIR_Msk                       /*!<Rx/Tx direction at Half-duplex mode */
#define SPI_CR1_SSI_Pos                     (12UL)
#define SPI_CR1_SSI_Msk                     (0x1UL << SPI_CR1_SSI_Pos)              /*!< 0x00001000 */
#define SPI_CR1_SSI                         SPI_CR1_SSI_Msk                         /*!<Internal SS signal input level */
#define SPI_CR1_CRC33_17_Pos                (13UL)
#define SPI_CR1_CRC33_17_Msk                (0x1UL << SPI_CR1_CRC33_17_Pos)         /*!< 0x00002000 */
#define SPI_CR1_CRC33_17                    SPI_CR1_CRC33_17_Msk                    /*!<32-bit CRC polynomial configuration */
#define SPI_CR1_RCRCINI_Pos                 (14UL)
#define SPI_CR1_RCRCINI_Msk                 (0x1UL << SPI_CR1_RCRCINI_Pos)          /*!< 0x00004000 */
#define SPI_CR1_RCRCINI                     SPI_CR1_RCRCINI_Msk                     /*!<CRC init pattern control for receiver */
#define SPI_CR1_TCRCINI_Pos                 (15UL)
#define SPI_CR1_TCRCINI_Msk                 (0x1UL << SPI_CR1_TCRCINI_Pos)          /*!< 0x00008000 */
#define SPI_CR1_TCRCINI                     SPI_CR1_TCRCINI_Msk                     /*!<CRC init pattern control for transmitter */
#define SPI_CR1_IOLOCK_Pos                  (16UL)
#define SPI_CR1_IOLOCK_Msk                  (0x1UL << SPI_CR1_IOLOCK_Pos)           /*!< 0x00010000 */
#define SPI_CR1_IOLOCK                      SPI_CR1_IOLOCK_Msk                      /*!<Locking the AF configuration of associated IOs */

/*******************  Bit definition for SPI_CR2 register  ********************/
#define SPI_CR2_TSIZE_Pos                   (0UL)
#define SPI_CR2_TSIZE_Msk                   (0xFFFFUL << SPI_CR2_TSIZE_Pos)         /*!< 0x0000FFFF */
#define SPI_CR2_TSIZE                       SPI_CR2_TSIZE_Msk                       /*!<Number of data at current transfer */

/*******************  Bit definition for SPI_CFG1 register  ********************/
#define SPI_CFG1_DSIZE_Pos                  (0UL)
#define SPI_CFG1_DSIZE_Msk                  (0x1FUL << SPI_CFG1_DSIZE_Pos)          /*!< 0x0000001F */
#define SPI_CFG1_DSIZE                      SPI_CFG1_DSIZE_Msk                      /*!<DSIZE[4:0]: Bits number in single SPI data frame */
#define SPI_CFG1_DSIZE_0                    (0x01UL << SPI_CFG1_DSIZE_Pos)          /*!< 0x00000001 */
#define SPI_CFG1_DSIZE_1                    (0x02UL << SPI_CFG1_DSIZE_Pos)          /*!< 0x00000002 */
#define SPI_CFG1_DSIZE_2                    (0x04UL << SPI_CFG1_DSIZE_Pos)          /*!< 0x00000004 */
#define SPI_CFG1_DSIZE_3                    (0x08UL << SPI_CFG1_DSIZE_Pos)          /*!< 0x00000008 */
#define SPI_CFG1_DSIZE_4                    (0x10UL << SPI_CFG1_DSIZE_Pos)          /*!< 0x00000010 */
#define SPI_CFG1_FTHLV_Pos                  (5UL)
#define SPI_CFG1_FTHLV_Msk                  (0xFUL << SPI_CFG1_FTHLV_Pos)           /*!< 0x000001E0 */
#define SPI_CFG1_FTHLV                      SPI_CFG1_FTHLV_Msk                      /*!<FTHVL [3:0]: FIFO threshold level*/
#define SPI_CFG1_FTHLV_0                    (0x1UL << SPI_CFG1_FTHLV_Pos)           /*!< 0x00000020 */
#define SPI_CFG1_FTHLV_1                    (0x2UL << SPI_CFG1_FTHLV_Pos)           /*!< 0x00000040 */
#define SPI_CFG1_FTHLV_2                    (0x4UL << SPI_CFG1_FTHLV_Pos)           /*!< 0x00000080 */
#define SPI_CFG1_FTHLV_3                    (0x8UL << SPI_CFG1_FTHLV_Pos)           /*!< 0x00000100 */
#define SPI_CFG1_UDRCFG_Pos                 (9UL)
#define SPI_CFG1_UDRCFG_Msk                 (0x1UL << SPI_CFG1_UDRCFG_Pos)          /*!< 0x00000600 */
#define SPI_CFG1_UDRCFG                     SPI_CFG1_UDRCFG_Msk                     /*!<Behavior of Slave transmitter at underrun */
#define SPI_CFG1_RXDMAEN_Pos                (14UL)
#define SPI_CFG1_RXDMAEN_Msk                (0x1UL << SPI_CFG1_RXDMAEN_Pos)         /*!< 0x00004000 */
#define SPI_CFG1_RXDMAEN                    SPI_CFG1_RXDMAEN_Msk                    /*!<Rx DMA stream enable */
#define SPI_CFG1_TXDMAEN_Pos                (15UL)
#define SPI_CFG1_TXDMAEN_Msk                (0x1UL << SPI_CFG1_TXDMAEN_Pos)         /*!< 0x00008000 */
#define SPI_CFG1_TXDMAEN                    SPI_CFG1_TXDMAEN_Msk                    /*!<Tx DMA stream enable */
#define SPI_CFG1_CRCSIZE_Pos                (16UL)
#define SPI_CFG1_CRCSIZE_Msk                (0x1FUL << SPI_CFG1_CRCSIZE_Pos)        /*!< 0x001F0000 */
#define SPI_CFG1_CRCSIZE                    SPI_CFG1_CRCSIZE_Msk                    /*!<CRCSIZE [4:0]: Length of CRC frame */
#define SPI_CFG1_CRCSIZE_0                  (0x01UL << SPI_CFG1_CRCSIZE_Pos)        /*!< 0x00010000 */
#define SPI_CFG1_CRCSIZE_1                  (0x02UL << SPI_CFG1_CRCSIZE_Pos)        /*!< 0x00020000 */
#define SPI_CFG1_CRCSIZE_2                  (0x04UL << SPI_CFG1_CRCSIZE_Pos)        /*!< 0x00040000 */
#define SPI_CFG1_CRCSIZE_3                  (0x08UL << SPI_CFG1_CRCSIZE_Pos)        /*!< 0x00080000 */
#define SPI_CFG1_CRCSIZE_4                  (0x10UL << SPI_CFG1_CRCSIZE_Pos)        /*!< 0x00100000 */
#define SPI_CFG1_CRCEN_Pos                  (22UL)
#define SPI_CFG1_CRCEN_Msk                  (0x1UL << SPI_CFG1_CRCEN_Pos)           /*!< 0x00400000 */
#define SPI_CFG1_CRCEN                      SPI_CFG1_CRCEN_Msk                      /*!<Hardware CRC computation enable */
#define SPI_CFG1_MBR_Pos                    (28UL)
#define SPI_CFG1_MBR_Msk                    (0x7UL << SPI_CFG1_MBR_Pos)             /*!< 0x70000000 */
#define SPI_CFG1_MBR                        SPI_CFG1_MBR_Msk                        /*!<Master baud rate */
#define SPI_CFG1_MBR_0                      (0x1UL << SPI_CFG1_MBR_Pos)             /*!< 0x10000000 */
#define SPI_CFG1_MBR_1                      (0x2UL << SPI_CFG1_MBR_Pos)             /*!< 0x20000000 */
#define SPI_CFG1_MBR_2                      (0x4UL << SPI_CFG1_MBR_Pos)             /*!< 0x40000000 */
#define SPI_CFG1_BPASS_Pos                  (31UL)
#define SPI_CFG1_BPASS_Msk                  (0x1UL << SPI_CFG1_BPASS_Pos)           /*!< 0x80000000 */
#define SPI_CFG1_BPASS                      SPI_CFG1_BPASS_Msk                      /*!<Bypass of the prescaler */

/*******************  Bit definition for SPI_CFG2 register  ********************/
#define SPI_CFG2_MSSI_Pos                   (0UL)
#define SPI_CFG2_MSSI_Msk                   (0xFUL << SPI_CFG2_MSSI_Pos)            /*!< 0x0000000F */
#define SPI_CFG2_MSSI                       SPI_CFG2_MSSI_Msk                       /*!<Master SS Idleness */
#define SPI_CFG2_MSSI_0                     (0x1UL << SPI_CFG2_MSSI_Pos)            /*!< 0x00000001 */
#define SPI_CFG2_MSSI_1                     (0x2UL << SPI_CFG2_MSSI_Pos)            /*!< 0x00000002 */
#define SPI_CFG2_MSSI_2                     (0x4UL << SPI_CFG2_MSSI_Pos)            /*!< 0x00000004 */
#define SPI_CFG2_MSSI_3                     (0x8UL << SPI_CFG2_MSSI_Pos)            /*!< 0x00000008 */
#define SPI_CFG2_MIDI_Pos                   (4UL)
#define SPI_CFG2_MIDI_Msk                   (0xFUL << SPI_CFG2_MIDI_Pos)            /*!< 0x000000F0 */
#define SPI_CFG2_MIDI                       SPI_CFG2_MIDI_Msk                       /*!<Master Inter-Data Idleness */
#define SPI_CFG2_MIDI_0                     (0x1UL << SPI_CFG2_MIDI_Pos)            /*!< 0x00000010 */
#define SPI_CFG2_MIDI_1                     (0x2UL << SPI_CFG2_MIDI_Pos)            /*!< 0x00000020 */
#define SPI_CFG2_MIDI_2                     (0x4UL << SPI_CFG2_MIDI_Pos)            /*!< 0x00000040 */
#define SPI_CFG2_MIDI_3                     (0x8UL << SPI_CFG2_MIDI_Pos)            /*!< 0x00000080 */
#define SPI_CFG2_RDIOM_Pos                  (13UL)
#define SPI_CFG2_RDIOM_Msk                  (0x1UL << SPI_CFG2_RDIOM_Pos)           /*!< 0x00002000 */
#define SPI_CFG2_RDIOM                      SPI_CFG2_RDIOM_Msk                      /*!<RDY signal input/output master management */
#define SPI_CFG2_RDIOP_Pos                  (14UL)
#define SPI_CFG2_RDIOP_Msk                  (0x1UL << SPI_CFG2_RDIOP_Pos)           /*!< 0x00004000 */
#define SPI_CFG2_RDIOP                      SPI_CFG2_RDIOP_Msk                      /*!<RDY signal input/output polarity */
#define SPI_CFG2_IOSWP_Pos                  (15UL)
#define SPI_CFG2_IOSWP_Msk                  (0x1UL << SPI_CFG2_IOSWP_Pos)           /*!< 0x00008000 */
#define SPI_CFG2_IOSWP                      SPI_CFG2_IOSWP_Msk                      /*!<Swap functionality of MISO and MOSI pins */
#define SPI_CFG2_COMM_Pos                   (17UL)
#define SPI_CFG2_COMM_Msk                   (0x3UL << SPI_CFG2_COMM_Pos)            /*!< 0x00060000 */
#define SPI_CFG2_COMM                       SPI_CFG2_COMM_Msk                       /*!<COMM [1:0]: SPI Communication Mode*/
#define SPI_CFG2_COMM_0                     (0x1UL << SPI_CFG2_COMM_Pos)            /*!< 0x00020000 */
#define SPI_CFG2_COMM_1                     (0x2UL << SPI_CFG2_COMM_Pos)            /*!< 0x00040000 */
#define SPI_CFG2_SP_Pos                     (19UL)
#define SPI_CFG2_SP_Msk                     (0x7UL << SPI_CFG2_SP_Pos)              /*!< 0x00380000 */
#define SPI_CFG2_SP                         SPI_CFG2_SP_Msk                         /*!<SP[2:0]: Serial Protocol */
#define SPI_CFG2_SP_0                       (0x1UL << SPI_CFG2_SP_Pos)              /*!< 0x00080000 */
#define SPI_CFG2_SP_1                       (0x2UL << SPI_CFG2_SP_Pos)              /*!< 0x00100000 */
#define SPI_CFG2_SP_2                       (0x4UL << SPI_CFG2_SP_Pos)              /*!< 0x00200000 */
#define SPI_CFG2_MASTER_Pos                 (22UL)
#define SPI_CFG2_MASTER_Msk                 (0x1UL << SPI_CFG2_MASTER_Pos)          /*!< 0x00400000 */
#define SPI_CFG2_MASTER                     SPI_CFG2_MASTER_Msk                     /*!<SPI Master */
#define SPI_CFG2_LSBFRST_Pos                (23UL)
#define SPI_CFG2_LSBFRST_Msk                (0x1UL << SPI_CFG2_LSBFRST_Pos)         /*!< 0x00800000 */
#define SPI_CFG2_LSBFRST                    SPI_CFG2_LSBFRST_Msk                    /*!<Data frame format */
#define SPI_CFG2_CPHA_Pos                   (24UL)
#define SPI_CFG2_CPHA_Msk                   (0x1UL << SPI_CFG2_CPHA_Pos)            /*!< 0x01000000 */
#define SPI_CFG2_CPHA                       SPI_CFG2_CPHA_Msk                       /*!<Clock Phase */
#define SPI_CFG2_CPOL_Pos                   (25UL)
#define SPI_CFG2_CPOL_Msk                   (0x1UL << SPI_CFG2_CPOL_Pos)            /*!< 0x02000000 */
#define SPI_CFG2_CPOL                       SPI_CFG2_CPOL_Msk                       /*!<Clock Polarity */
#define SPI_CFG2_SSM_Pos                    (26UL)
#define SPI_CFG2_SSM_Msk                    (0x1UL << SPI_CFG2_SSM_Pos)             /*!< 0x04000000 */
#define SPI_CFG2_SSM                        SPI_CFG2_SSM_Msk                        /*!<Software slave management */
#define SPI_CFG2_SSIOP_Pos                  (28UL)
#define SPI_CFG2_SSIOP_Msk                  (0x1UL << SPI_CFG2_SSIOP_Pos)           /*!< 0x10000000 */
#define SPI_CFG2_SSIOP                      SPI_CFG2_SSIOP_Msk                      /*!<SS input/output polarity */
#define SPI_CFG2_SSOE_Pos                   (29UL)
#define SPI_CFG2_SSOE_Msk                   (0x1UL << SPI_CFG2_SSOE_Pos)            /*!< 0x20000000 */
#define SPI_CFG2_SSOE                       SPI_CFG2_SSOE_Msk                       /*!<SS output enable */
#define SPI_CFG2_SSOM_Pos                   (30UL)
#define SPI_CFG2_SSOM_Msk                   (0x1UL << SPI_CFG2_SSOM_Pos)            /*!< 0x40000000 */
#define SPI_CFG2_SSOM                       SPI_CFG2_SSOM_Msk                       /*!<SS output management in master mode */
#define SPI_CFG2_AFCNTR_Pos                 (31UL)
#define SPI_CFG2_AFCNTR_Msk                 (0x1UL << SPI_CFG2_AFCNTR_Pos)          /*!< 0x80000000 */
#define SPI_CFG2_AFCNTR                     SPI_CFG2_AFCNTR_Msk                     /*!<Alternate function GPIOs control */

/*******************  Bit definition for SPI_IER register  ********************/
#define SPI_IER_RXPIE_Pos                   (0UL)
#define SPI_IER_RXPIE_Msk                   (0x1UL << SPI_IER_RXPIE_Pos)            /*!< 0x00000001 */
#define SPI_IER_RXPIE                       SPI_IER_RXPIE_Msk                       /*!<RXP Interrupt Enable */
#define SPI_IER_TXPIE_Pos                   (1UL)
#define SPI_IER_TXPIE_Msk                   (0x1UL << SPI_IER_TXPIE_Pos)            /*!< 0x00000002 */
#define SPI_IER_TXPIE                       SPI_IER_TXPIE_Msk                       /*!<TXP interrupt enable */
#define SPI_IER_DXPIE_Pos                   (2UL)
#define SPI_IER_DXPIE_Msk                   (0x1UL << SPI_IER_DXPIE_Pos)            /*!< 0x00000004 */
#define SPI_IER_DXPIE                       SPI_IER_DXPIE_Msk                       /*!<DXP interrupt enable */
#define SPI_IER_EOTIE_Pos                   (3UL)
#define SPI_IER_EOTIE_Msk                   (0x1UL << SPI_IER_EOTIE_Pos)            /*!< 0x00000008 */
#define SPI_IER_EOTIE                       SPI_IER_EOTIE_Msk                       /*!<EOT/SUSP/TXC interrupt enable */
#define SPI_IER_TXTFIE_Pos                  (4UL)
#define SPI_IER_TXTFIE_Msk                  (0x1UL << SPI_IER_TXTFIE_Pos)           /*!< 0x00000010 */
#define SPI_IER_TXTFIE                      SPI_IER_TXTFIE_Msk                      /*!<TXTF interrupt enable */
#define SPI_IER_UDRIE_Pos                   (5UL)
#define SPI_IER_UDRIE_Msk                   (0x1UL << SPI_IER_UDRIE_Pos)            /*!< 0x00000020 */
#define SPI_IER_UDRIE                       SPI_IER_UDRIE_Msk                       /*!<UDR interrupt enable */
#define SPI_IER_OVRIE_Pos                   (6UL)
#define SPI_IER_OVRIE_Msk                   (0x1UL << SPI_IER_OVRIE_Pos)            /*!< 0x00000040 */
#define SPI_IER_OVRIE                       SPI_IER_OVRIE_Msk                       /*!<OVR interrupt enable */
#define SPI_IER_CRCEIE_Pos                  (7UL)
#define SPI_IER_CRCEIE_Msk                  (0x1UL << SPI_IER_CRCEIE_Pos)           /*!< 0x00000080 */
#define SPI_IER_CRCEIE                      SPI_IER_CRCEIE_Msk                      /*!<CRCE interrupt enable */
#define SPI_IER_TIFREIE_Pos                 (8UL)
#define SPI_IER_TIFREIE_Msk                 (0x1UL << SPI_IER_TIFREIE_Pos)          /*!< 0x00000100 */
#define SPI_IER_TIFREIE                     SPI_IER_TIFREIE_Msk                     /*!<TI Frame Error interrupt enable */
#define SPI_IER_MODFIE_Pos                  (9UL)
#define SPI_IER_MODFIE_Msk                  (0x1UL << SPI_IER_MODFIE_Pos)           /*!< 0x00000200 */
#define SPI_IER_MODFIE                      SPI_IER_MODFIE_Msk                      /*!<MODF interrupt enable */

/*******************  Bit definition for SPI_SR register  ********************/
#define SPI_SR_RXP_Pos                      (0UL)
#define SPI_SR_RXP_Msk                      (0x1UL << SPI_SR_RXP_Pos)               /*!< 0x00000001 */
#define SPI_SR_RXP                          SPI_SR_RXP_Msk                          /*!<Rx-Packet available */
#define SPI_SR_TXP_Pos                      (1UL)
#define SPI_SR_TXP_Msk                      (0x1UL << SPI_SR_TXP_Pos)               /*!< 0x00000002 */
#define SPI_SR_TXP                          SPI_SR_TXP_Msk                          /*!<Tx-Packet space available */
#define SPI_SR_DXP_Pos                      (2UL)
#define SPI_SR_DXP_Msk                      (0x1UL << SPI_SR_DXP_Pos)               /*!< 0x00000004 */
#define SPI_SR_DXP                          SPI_SR_DXP_Msk                          /*!<Duplex Packet available */
#define SPI_SR_EOT_Pos                      (3UL)
#define SPI_SR_EOT_Msk                      (0x1UL << SPI_SR_EOT_Pos)               /*!< 0x00000008 */
#define SPI_SR_EOT                          SPI_SR_EOT_Msk                          /*!<Duplex Packet available */
#define SPI_SR_TXTF_Pos                     (4UL)
#define SPI_SR_TXTF_Msk                     (0x1UL << SPI_SR_TXTF_Pos)              /*!< 0x00000010 */
#define SPI_SR_TXTF                         SPI_SR_TXTF_Msk                         /*!<Transmission Transfer Filled */
#define SPI_SR_UDR_Pos                      (5UL)
#define SPI_SR_UDR_Msk                      (0x1UL << SPI_SR_UDR_Pos)               /*!< 0x00000020 */
#define SPI_SR_UDR                          SPI_SR_UDR_Msk                          /*!<UDR at Slave transmission */
#define SPI_SR_OVR_Pos                      (6UL)
#define SPI_SR_OVR_Msk                      (0x1UL << SPI_SR_OVR_Pos)               /*!< 0x00000040 */
#define SPI_SR_OVR                          SPI_SR_OVR_Msk                          /*!<Rx-Packet available */
#define SPI_SR_CRCE_Pos                     (7UL)
#define SPI_SR_CRCE_Msk                     (0x1UL << SPI_SR_CRCE_Pos)              /*!< 0x00000080 */
#define SPI_SR_CRCE                         SPI_SR_CRCE_Msk                         /*!<CRC Error Detected */
#define SPI_SR_TIFRE_Pos                    (8UL)
#define SPI_SR_TIFRE_Msk                    (0x1UL << SPI_SR_TIFRE_Pos)             /*!< 0x00000100 */
#define SPI_SR_TIFRE                        SPI_SR_TIFRE_Msk                        /*!<TI frame format error Detected */
#define SPI_SR_MODF_Pos                     (9UL)
#define SPI_SR_MODF_Msk                     (0x1UL << SPI_SR_MODF_Pos)              /*!< 0x00000200 */
#define SPI_SR_MODF                         SPI_SR_MODF_Msk                         /*!<Mode Fault Detected */
#define SPI_SR_SUSP_Pos                     (11UL)
#define SPI_SR_SUSP_Msk                     (0x1UL << SPI_SR_SUSP_Pos)              /*!< 0x00000800 */
#define SPI_SR_SUSP                         SPI_SR_SUSP_Msk                         /*!<SUSP is set by hardware */
#define SPI_SR_TXC_Pos                      (12UL)
#define SPI_SR_TXC_Msk                      (0x1UL << SPI_SR_TXC_Pos)               /*!< 0x00001000 */
#define SPI_SR_TXC                          SPI_SR_TXC_Msk                          /*!<TxFIFO transmission complete */
#define SPI_SR_RXPLVL_Pos                   (13UL)
#define SPI_SR_RXPLVL_Msk                   (0x3UL << SPI_SR_RXPLVL_Pos)            /*!< 0x00006000 */
#define SPI_SR_RXPLVL                       SPI_SR_RXPLVL_Msk                       /*!<RxFIFO Packing Level */
#define SPI_SR_RXPLVL_0                     (0x1UL << SPI_SR_RXPLVL_Pos)            /*!< 0x00002000 */
#define SPI_SR_RXPLVL_1                     (0x2UL << SPI_SR_RXPLVL_Pos)            /*!< 0x00004000 */
#define SPI_SR_RXWNE_Pos                    (15UL)
#define SPI_SR_RXWNE_Msk                    (0x1UL << SPI_SR_RXWNE_Pos)             /*!< 0x00008000 */
#define SPI_SR_RXWNE                        SPI_SR_RXWNE_Msk                        /*!<Rx FIFO Word Not Empty */
#define SPI_SR_CTSIZE_Pos                   (16UL)
#define SPI_SR_CTSIZE_Msk                   (0xFFFFUL << SPI_SR_CTSIZE_Pos)         /*!< 0xFFFF0000 */
#define SPI_SR_CTSIZE                       SPI_SR_CTSIZE_Msk                       /*!<Number of data frames remaining in TSIZE */

/*******************  Bit definition for SPI_IFCR register  ********************/
#define SPI_IFCR_EOTC_Pos                   (3UL)
#define SPI_IFCR_EOTC_Msk                   (0x1UL << SPI_IFCR_EOTC_Pos)            /*!< 0x00000008 */
#define SPI_IFCR_EOTC                       SPI_IFCR_EOTC_Msk                       /*!<End Of Transfer flag clear */
#define SPI_IFCR_TXTFC_Pos                  (4UL)
#define SPI_IFCR_TXTFC_Msk                  (0x1UL << SPI_IFCR_TXTFC_Pos)           /*!< 0x00000010 */
#define SPI_IFCR_TXTFC                      SPI_IFCR_TXTFC_Msk                      /*!<Transmission Transfer Filled flag clear */
#define SPI_IFCR_UDRC_Pos                   (5UL)
#define SPI_IFCR_UDRC_Msk                   (0x1UL << SPI_IFCR_UDRC_Pos)            /*!< 0x00000020 */
#define SPI_IFCR_UDRC                       SPI_IFCR_UDRC_Msk                       /*!<Underrun flag clear */
#define SPI_IFCR_OVRC_Pos                   (6UL)
#define SPI_IFCR_OVRC_Msk                   (0x1UL << SPI_IFCR_OVRC_Pos)            /*!< 0x00000040 */
#define SPI_IFCR_OVRC                       SPI_IFCR_OVRC_Msk                       /*!<Overrun flag clear */
#define SPI_IFCR_CRCEC_Pos                  (7UL)
#define SPI_IFCR_CRCEC_Msk                  (0x1UL << SPI_IFCR_CRCEC_Pos)           /*!< 0x00000080 */
#define SPI_IFCR_CRCEC                      SPI_IFCR_CRCEC_Msk                      /*!<CRC Error flag clear */
#define SPI_IFCR_TIFREC_Pos                 (8UL)
#define SPI_IFCR_TIFREC_Msk                 (0x1UL << SPI_IFCR_TIFREC_Pos)          /*!< 0x00000100 */
#define SPI_IFCR_TIFREC                     SPI_IFCR_TIFREC_Msk                     /*!<TI frame format error flag clear */
#define SPI_IFCR_MODFC_Pos                  (9UL)
#define SPI_IFCR_MODFC_Msk                  (0x1UL << SPI_IFCR_MODFC_Pos)           /*!< 0x00000200 */
#define SPI_IFCR_MODFC                      SPI_IFCR_MODFC_Msk                      /*!<Mode Fault flag clear */
#define SPI_IFCR_SUSPC_Pos                  (11UL)
#define SPI_IFCR_SUSPC_Msk                  (0x1UL << SPI_IFCR_SUSPC_Pos)           /*!< 0x00000800 */
#define SPI_IFCR_SUSPC                      SPI_IFCR_SUSPC_Msk                      /*!<SUSPend flag clear */

/*******************  Bit definition for SPI_AUTOCR register  ********************/
#define SPI_AUTOCR_TRIGSEL_Pos              (16UL)
#define SPI_AUTOCR_TRIGSEL_Msk              (0xFUL << SPI_AUTOCR_TRIGSEL_Pos)       /*!< 0x000F0000 */
#define SPI_AUTOCR_TRIGSEL                  SPI_AUTOCR_TRIGSEL_Msk                  /*!<CTRIGSEL [3:0]: Trigger selection */
#define SPI_AUTOCR_TRIGSEL_0                (0x01UL << SPI_AUTOCR_TRIGSEL_Pos)      /*!< 0x00010000 */
#define SPI_AUTOCR_TRIGSEL_1                (0x02UL << SPI_AUTOCR_TRIGSEL_Pos)      /*!< 0x00020000 */
#define SPI_AUTOCR_TRIGSEL_2                (0x04UL << SPI_AUTOCR_TRIGSEL_Pos)      /*!< 0x00040000 */
#define SPI_AUTOCR_TRIGSEL_3                (0x08UL << SPI_AUTOCR_TRIGSEL_Pos)      /*!< 0x00080000 */
#define SPI_AUTOCR_TRIGPOL_Pos              (20UL)
#define SPI_AUTOCR_TRIGPOL_Msk              (0x1UL << SPI_AUTOCR_TRIGPOL_Pos)       /*!< 0x00100000 */
#define SPI_AUTOCR_TRIGPOL                  SPI_AUTOCR_TRIGPOL_Msk                  /*!<Trigger polarity */
#define SPI_AUTOCR_TRIGEN_Pos               (21UL)
#define SPI_AUTOCR_TRIGEN_Msk               (0x1UL << SPI_AUTOCR_TRIGEN_Pos)        /*!< 0x00200000 */
#define SPI_AUTOCR_TRIGEN                   SPI_AUTOCR_TRIGEN_Msk                   /*!<Trigger of CSTART control enable */

/*******************  Bit definition for SPI_TXDR register  ********************/
#define SPI_TXDR_TXDR_Pos                   (0UL)
#define SPI_TXDR_TXDR_Msk                   (0xFFFFFFFFUL << SPI_TXDR_TXDR_Pos)     /*!< 0xFFFFFFFF */
#define SPI_TXDR_TXDR                       SPI_TXDR_TXDR_Msk                       /* Transmit Data Register */

/*******************  Bit definition for SPI_RXDR register  ********************/
#define SPI_RXDR_RXDR_Pos                   (0UL)
#define SPI_RXDR_RXDR_Msk                   (0xFFFFFFFFUL << SPI_RXDR_RXDR_Pos)     /*!< 0xFFFFFFFF */
#define SPI_RXDR_RXDR                       SPI_RXDR_RXDR_Msk                       /* Receive Data Register */

/*******************  Bit definition for SPI_CRCPOLY register  ********************/
#define SPI_CRCPOLY_CRCPOLY_Pos             (0UL)
#define SPI_CRCPOLY_CRCPOLY_Msk             (0xFFFFFFFFUL << SPI_CRCPOLY_CRCPOLY_Pos) /*!< 0xFFFFFFFF */
#define SPI_CRCPOLY_CRCPOLY                 SPI_CRCPOLY_CRCPOLY_Msk                 /* CRC Polynomial register */

/*******************  Bit definition for SPI_TXCRC register  ********************/
#define SPI_TXCRC_TXCRC_Pos                 (0UL)
#define SPI_TXCRC_TXCRC_Msk                 (0xFFFFFFFFUL << SPI_TXCRC_TXCRC_Pos)   /*!< 0xFFFFFFFF */
#define SPI_TXCRC_TXCRC                     SPI_TXCRC_TXCRC_Msk                     /* CRCRegister for transmitter */

/*******************  Bit definition for SPI_RXCRC register  ********************/
#define SPI_RXCRC_RXCRC_Pos                 (0UL)
#define SPI_RXCRC_RXCRC_Msk                 (0xFFFFFFFFUL << SPI_RXCRC_RXCRC_Pos)   /*!< 0xFFFFFFFF */
#define SPI_RXCRC_RXCRC                     SPI_RXCRC_RXCRC_Msk                     /* CRCRegister for receiver */

/*******************  Bit definition for SPI_UDRDR register  ********************/
#define SPI_UDRDR_UDRDR_Pos                 (0UL)
#define SPI_UDRDR_UDRDR_Msk                 (0xFFFFFFFFUL << SPI_UDRDR_UDRDR_Pos)   /*!< 0xFFFFFFFF */
#define SPI_UDRDR_UDRDR                     SPI_UDRDR_UDRDR_Msk                     /* Data at slave underrun condition */

/******************************************************************************/
/*                                                                            */
/*                                 SYSCFG                                     */
/*                                                                            */
/******************************************************************************/
/******************  Bit definition for SYSCFG_SECRX register  ****************/
#define SYSCFG_SECCFGR_SYSCFGSEC_Pos        (0UL)
#define SYSCFG_SECCFGR_SYSCFGSEC_Msk        (0x1UL << SYSCFG_SECCFGR_SYSCFGSEC_Pos) /*!< 0x00000001 */
#define SYSCFG_SECCFGR_SYSCFGSEC            SYSCFG_SECCFGR_SYSCFGSEC_Msk            /*!< SYSCFG clock control security enable */
#define SYSCFG_SECCFGR_CLASSBSEC_Pos        (1UL)
#define SYSCFG_SECCFGR_CLASSBSEC_Msk        (0x1UL << SYSCFG_SECCFGR_CLASSBSEC_Pos) /*!< 0x00000002 */
#define SYSCFG_SECCFGR_CLASSBSEC            SYSCFG_SECCFGR_CLASSBSEC_Msk            /*!< ClassB SYSCFG security enable */
#define SYSCFG_SECCFGR_FPUSEC_Pos           (3UL)
#define SYSCFG_SECCFGR_FPUSEC_Msk           (0x1UL << SYSCFG_SECCFGR_FPUSEC_Pos)    /*!< 0x00000008 */
#define SYSCFG_SECCFGR_FPUSEC               SYSCFG_SECCFGR_FPUSEC_Msk               /*!< FPU SYSCFG security enable */

/******************  Bit definition for SYSCFG_CFGR1 register  ****************/
#define SYSCFG_CFGR1_IR_POL_Pos             (5UL)
#define SYSCFG_CFGR1_IR_POL_Msk             (0x1UL << SYSCFG_CFGR1_IR_POL_Pos)      /*!< 0x00000020 */
#define SYSCFG_CFGR1_IR_POL                 SYSCFG_CFGR1_IR_POL_Msk                 /*!< IR output polarity selection */
#define SYSCFG_CFGR1_IR_MOD_Pos             (6UL)
#define SYSCFG_CFGR1_IR_MOD_Msk             (0x3UL << SYSCFG_CFGR1_IR_MOD_Pos)      /*!< 0x000000C0 */
#define SYSCFG_CFGR1_IR_MOD                 SYSCFG_CFGR1_IR_MOD_Msk                 /*!< IR Modulation Envelope signal selection */
#define SYSCFG_CFGR1_IR_MOD_0               (0x1UL << SYSCFG_CFGR1_IR_MOD_Pos)      /*!< 0x00000040 */
#define SYSCFG_CFGR1_IR_MOD_1               (0x2UL << SYSCFG_CFGR1_IR_MOD_Pos)      /*!< 0x00000080 */
#define SYSCFG_CFGR1_BOOSTEN_Pos            (8UL)
#define SYSCFG_CFGR1_BOOSTEN_Msk            (0x1UL << SYSCFG_CFGR1_BOOSTEN_Pos)     /*!< 0x00000100 */
#define SYSCFG_CFGR1_BOOSTEN                SYSCFG_CFGR1_BOOSTEN_Msk                /*!< I/O analog switch voltage booster enable */
#define SYSCFG_CFGR1_ANASWVDD_Pos           (9UL)
#define SYSCFG_CFGR1_ANASWVDD_Msk           (0x1UL << SYSCFG_CFGR1_ANASWVDD_Pos)    /*!< 0x00000200 */
#define SYSCFG_CFGR1_ANASWVDD               SYSCFG_CFGR1_ANASWVDD_Msk               /*!< GPIO analog switch control voltage selection */
#define SYSCFG_CFGR1_PB6_FMP_Pos            (16UL)
#define SYSCFG_CFGR1_PB6_FMP_Msk            (0x1UL << SYSCFG_CFGR1_PB6_FMP_Pos)     /*!< 0x00010000 */
#define SYSCFG_CFGR1_PB6_FMP                SYSCFG_CFGR1_PB6_FMP_Msk                /*!< PB6 Fast mode plus */
#define SYSCFG_CFGR1_PB7_FMP_Pos            (17UL)
#define SYSCFG_CFGR1_PB7_FMP_Msk            (0x1UL << SYSCFG_CFGR1_PB7_FMP_Pos)     /*!< 0x00020000 */
#define SYSCFG_CFGR1_PB7_FMP                SYSCFG_CFGR1_PB7_FMP_Msk                /*!< PB7 Fast mode plus */
#define SYSCFG_CFGR1_PB8_FMP_Pos            (18UL)
#define SYSCFG_CFGR1_PB8_FMP_Msk            (0x1UL << SYSCFG_CFGR1_PB8_FMP_Pos)     /*!< 0x00040000 */
#define SYSCFG_CFGR1_PB8_FMP                SYSCFG_CFGR1_PB8_FMP_Msk                /*!< PB8 Fast mode plus */
#define SYSCFG_CFGR1_PB9_FMP_Pos            (19UL)
#define SYSCFG_CFGR1_PB9_FMP_Msk            (0x1UL << SYSCFG_CFGR1_PB9_FMP_Pos)     /*!< 0x00080000 */
#define SYSCFG_CFGR1_PB9_FMP                SYSCFG_CFGR1_PB9_FMP_Msk                /*!< PB9 Fast mode plus */

/*****************  Bit definition for SYSCFG_FPUIMR register  ***************/
#define SYSCFG_FPUIMR_FPU_IOIE_Pos          (0UL)
#define SYSCFG_FPUIMR_FPU_IOIE_Msk          (0x1UL << SYSCFG_FPUIMR_FPU_IOIE_Pos)   /*!< 0x00000001 */
#define SYSCFG_FPUIMR_FPU_IOIE              SYSCFG_FPUIMR_FPU_IOIE_Msk              /*!< Floating point unit interrupt enable bit - invalid operation */
#define SYSCFG_FPUIMR_FPU_DZIE_Pos          (1UL)
#define SYSCFG_FPUIMR_FPU_DZIE_Msk          (0x1UL << SYSCFG_FPUIMR_FPU_DZIE_Pos)   /*!< 0x00000002 */
#define SYSCFG_FPUIMR_FPU_DZIE              SYSCFG_FPUIMR_FPU_DZIE_Msk              /*!< Floating point unit interrupt enable bit - divide-by-zero */
#define SYSCFG_FPUIMR_FPU_UFIE_Pos          (2UL)
#define SYSCFG_FPUIMR_FPU_UFIE_Msk          (0x1UL << SYSCFG_FPUIMR_FPU_UFIE_Pos)   /*!< 0x00000004 */
#define SYSCFG_FPUIMR_FPU_UFIE              SYSCFG_FPUIMR_FPU_UFIE_Msk              /*!< Floating point unit interrupt enable bit - underflow */
#define SYSCFG_FPUIMR_FPU_OFIE_Pos          (3UL)
#define SYSCFG_FPUIMR_FPU_OFIE_Msk          (0x1UL << SYSCFG_FPUIMR_FPU_OFIE_Pos)   /*!< 0x00000008 */
#define SYSCFG_FPUIMR_FPU_OFIE              SYSCFG_FPUIMR_FPU_OFIE_Msk              /*!< Floating point unit interrupt enable bit - overflow */
#define SYSCFG_FPUIMR_FPU_IDIE_Pos          (4UL)
#define SYSCFG_FPUIMR_FPU_IDIE_Msk          (0x1UL << SYSCFG_FPUIMR_FPU_IDIE_Pos)   /*!< 0x00000010 */
#define SYSCFG_FPUIMR_FPU_IDIE              SYSCFG_FPUIMR_FPU_IDIE_Msk              /*!< Floating point unit interrupt enable bit - input denormal */
#define SYSCFG_FPUIMR_FPU_IXIE_Pos          (5UL)
#define SYSCFG_FPUIMR_FPU_IXIE_Msk          (0x1UL << SYSCFG_FPUIMR_FPU_IXIE_Pos)   /*!< 0x00000020 */
#define SYSCFG_FPUIMR_FPU_IXIE              SYSCFG_FPUIMR_FPU_IXIE_Msk              /*!< Floating point unit interrupt enable bit - inexact */

/******************  Bit definition for SYSCFG_CNSLCKR register  **************/
#define SYSCFG_CNSLCKR_LOCKNSVTOR_Pos       (0UL)
#define SYSCFG_CNSLCKR_LOCKNSVTOR_Msk       (0x1UL << SYSCFG_CNSLCKR_LOCKNSVTOR_Pos) /*!< 0x00000001 */
#define SYSCFG_CNSLCKR_LOCKNSVTOR           SYSCFG_CNSLCKR_LOCKNSVTOR_Msk           /*!< Disable VTOR_NS register writes by SW or debug agent */
#define SYSCFG_CNSLCKR_LOCKNSMPU_Pos        (1UL)
#define SYSCFG_CNSLCKR_LOCKNSMPU_Msk        (0x1UL << SYSCFG_CNSLCKR_LOCKNSMPU_Pos) /*!< 0x00000002 */
#define SYSCFG_CNSLCKR_LOCKNSMPU            SYSCFG_CNSLCKR_LOCKNSMPU_Msk            /*!< Disable Non-Secure MPU registers writes by SW or debug agent */

/******************  Bit definition for SYSCFG_CSLCKR register  ***************/
#define SYSCFG_CSLCKR_LOCKSVTAIRCR_Pos      (0UL)
#define SYSCFG_CSLCKR_LOCKSVTAIRCR_Msk      (0x1UL << SYSCFG_CSLCKR_LOCKSVTAIRCR_Pos) /*!< 0x00000001 */
#define SYSCFG_CSLCKR_LOCKSVTAIRCR          SYSCFG_CSLCKR_LOCKSVTAIRCR_Msk          /*!< Disable changes to the secure vector table address, handling of system faults */
#define SYSCFG_CSLCKR_LOCKSMPU_Pos          (1UL)
#define SYSCFG_CSLCKR_LOCKSMPU_Msk          (0x1UL << SYSCFG_CSLCKR_LOCKSMPU_Pos)   /*!< 0x00000002 */
#define SYSCFG_CSLCKR_LOCKSMPU              SYSCFG_CSLCKR_LOCKSMPU_Msk              /*!< Disable changes to the secure MPU registers writes by SW or debug agent */
#define SYSCFG_CSLCKR_LOCKSAU_Pos           (2UL)
#define SYSCFG_CSLCKR_LOCKSAU_Msk           (0x1UL << SYSCFG_CSLCKR_LOCKSAU_Pos)    /*!< 0x00000004 */
#define SYSCFG_CSLCKR_LOCKSAU               SYSCFG_CSLCKR_LOCKSAU_Msk               /*!< Disable changes to SAU registers */

/******************  Bit definition for SYSCFG_CFGR2 register  ****************/
#define SYSCFG_CFGR2_CLL_Pos                (0UL)
#define SYSCFG_CFGR2_CLL_Msk                (0x1UL << SYSCFG_CFGR2_CLL_Pos)         /*!< 0x00000001 */
#define SYSCFG_CFGR2_CLL                    SYSCFG_CFGR2_CLL_Msk                    /*!< Core Lockup Lock */
#define SYSCFG_CFGR2_SPL_Pos                (1UL)
#define SYSCFG_CFGR2_SPL_Msk                (0x1UL << SYSCFG_CFGR2_SPL_Pos)         /*!< 0x00000002 */
#define SYSCFG_CFGR2_SPL                    SYSCFG_CFGR2_SPL_Msk                    /*!< SRAM parity Lock */
#define SYSCFG_CFGR2_PVDL_Pos               (2UL)
#define SYSCFG_CFGR2_PVDL_Msk               (0x1UL << SYSCFG_CFGR2_PVDL_Pos)        /*!< 0x00000004 */
#define SYSCFG_CFGR2_PVDL                   SYSCFG_CFGR2_PVDL_Msk                   /*!< PVD Lock */
#define SYSCFG_CFGR2_ECCL_Pos               (3UL)
#define SYSCFG_CFGR2_ECCL_Msk               (0x1UL << SYSCFG_CFGR2_ECCL_Pos)        /*!< 0x00000008 */
#define SYSCFG_CFGR2_ECCL                   SYSCFG_CFGR2_ECCL_Msk                   /*!< ECC Lock*/

/******************  Bit definition for SYSCFG_CCCSR register  ****************/
#define SYSCFG_CCCSR_EN1_Pos                (0UL)
#define SYSCFG_CCCSR_EN1_Msk                (0x1UL << SYSCFG_CCCSR_EN1_Pos)         /*!< 0x00000001 */
#define SYSCFG_CCCSR_EN1                    SYSCFG_CCCSR_EN1_Msk                    /*!< Enable compensation cell for VDD power rail */
#define SYSCFG_CCCSR_CS1_Pos                (1UL)
#define SYSCFG_CCCSR_CS1_Msk                (0x1UL << SYSCFG_CCCSR_CS1_Pos)         /*!< 0x00000002 */
#define SYSCFG_CCCSR_CS1                    SYSCFG_CCCSR_CS1_Msk                    /*!< Code selection for VDD power rail */
#define SYSCFG_CCCSR_EN2_Pos                (2UL)
#define SYSCFG_CCCSR_EN2_Msk                (0x1UL << SYSCFG_CCCSR_EN2_Pos)         /*!< 0x00000004 */
#define SYSCFG_CCCSR_EN2                    SYSCFG_CCCSR_EN2_Msk                    /*!< Enable compensation cell for VDDIO power rail */
#define SYSCFG_CCCSR_CS2_Pos                (3UL)
#define SYSCFG_CCCSR_CS2_Msk                (0x1UL << SYSCFG_CCCSR_CS2_Pos)         /*!< 0x00000008 */
#define SYSCFG_CCCSR_CS2                    SYSCFG_CCCSR_CS2_Msk                    /*!< Code selection for VDDIO power rail */
#define SYSCFG_CCCSR_RDY1_Pos               (8UL)
#define SYSCFG_CCCSR_RDY1_Msk               (0x1UL << SYSCFG_CCCSR_RDY1_Pos)        /*!< 0x00000100 */
#define SYSCFG_CCCSR_RDY1                   SYSCFG_CCCSR_RDY1_Msk                   /*!< VDD compensation cell ready flag */
#define SYSCFG_CCCSR_RDY2_Pos               (9UL)
#define SYSCFG_CCCSR_RDY2_Msk               (0x1UL << SYSCFG_CCCSR_RDY2_Pos)        /*!< 0x00000200 */
#define SYSCFG_CCCSR_RDY2                   SYSCFG_CCCSR_RDY2_Msk                   /*!< VDDIO compensation cell ready flag */

/******************  Bit definition for SYSCFG_CCVR register  ****************/
#define SYSCFG_CCVR_NCV1_Pos                (0UL)
#define SYSCFG_CCVR_NCV1_Msk                (0xFUL << SYSCFG_CCVR_NCV1_Pos)         /*!< 0x0000000F */
#define SYSCFG_CCVR_NCV1                    SYSCFG_CCVR_NCV1_Msk                    /*!< NMOS compensation value for VDD Power Rail */
#define SYSCFG_CCVR_PCV1_Pos                (4UL)
#define SYSCFG_CCVR_PCV1_Msk                (0xFUL << SYSCFG_CCVR_PCV1_Pos)         /*!< 0x000000F0 */
#define SYSCFG_CCVR_PCV1                    SYSCFG_CCVR_PCV1_Msk                    /*!< PMOS compensation value for VDD Power Rail */
#define SYSCFG_CCVR_NCV2_Pos                (8UL)
#define SYSCFG_CCVR_NCV2_Msk                (0xFUL << SYSCFG_CCVR_NCV2_Pos)         /*!< 0x00000F00 */
#define SYSCFG_CCVR_NCV2                    SYSCFG_CCVR_NCV2_Msk                    /*!< NMOS compensation value for VDDIO Power Rail */
#define SYSCFG_CCVR_PCV2_Pos                (12UL)
#define SYSCFG_CCVR_PCV2_Msk                (0xFUL << SYSCFG_CCVR_PCV2_Pos)         /*!< 0x0000F000 */
#define SYSCFG_CCVR_PCV2                    SYSCFG_CCVR_PCV2_Msk                    /*!< PMOS compensation value for VDDIO Power Rail */

/******************  Bit definition for SYSCFG_CCCR register  ****************/
#define SYSCFG_CCCR_NCC1_Pos                (0UL)
#define SYSCFG_CCCR_NCC1_Msk                (0xFUL << SYSCFG_CCCR_NCC1_Pos)         /*!< 0x0000000F */
#define SYSCFG_CCCR_NCC1                    SYSCFG_CCCR_NCC1_Msk                    /*!< NMOS compensation code for VDD Power Rail */
#define SYSCFG_CCCR_PCC1_Pos                (4UL)
#define SYSCFG_CCCR_PCC1_Msk                (0xFUL << SYSCFG_CCCR_PCC1_Pos)         /*!< 0x000000F0 */
#define SYSCFG_CCCR_PCC1                    SYSCFG_CCCR_PCC1_Msk                    /*!< PMOS compensation code for VDD Power Rail */
#define SYSCFG_CCCR_NCC2_Pos                (8UL)
#define SYSCFG_CCCR_NCC2_Msk                (0xFUL << SYSCFG_CCCR_NCC2_Pos)         /*!< 0x00000F00 */
#define SYSCFG_CCCR_NCC2                    SYSCFG_CCCR_NCC2_Msk                    /*!< NMOS compensation code for VDDIO Power Rail */
#define SYSCFG_CCCR_PCC2_Pos                (12UL)
#define SYSCFG_CCCR_PCC2_Msk                (0xFUL << SYSCFG_CCCR_PCC2_Pos)         /*!< 0x0000F000 */
#define SYSCFG_CCCR_PCC2                    SYSCFG_CCCR_PCC2_Msk                    /*!< PMOS compensation code for VDDIO Power Rail */

/******************  Bit definition for SYSCFG_RSSCMDR register  *************/
#define SYSCFG_RSSCMDR_RSSCMD_Pos           (0UL)
#define SYSCFG_RSSCMDR_RSSCMD_Msk           (0xFFFFUL << SYSCFG_RSSCMDR_RSSCMD_Pos) /*!< 0x0000FFFF */
#define SYSCFG_RSSCMDR_RSSCMD               SYSCFG_RSSCMDR_RSSCMD_Msk               /*!< RSS commands */

/******************************************************************************/
/*                                                                            */
/*                     Tamper and backup register (TAMP)                      */
/*                                                                            */
/******************************************************************************/
/********************  Bits definition for TAMP_CR1 register  *****************/
#define TAMP_CR1_TAMP1E_Pos                 (0UL)
#define TAMP_CR1_TAMP1E_Msk                 (0x1UL << TAMP_CR1_TAMP1E_Pos)          /*!< 0x00000001 */
#define TAMP_CR1_TAMP1E                     TAMP_CR1_TAMP1E_Msk
#define TAMP_CR1_TAMP2E_Pos                 (1UL)
#define TAMP_CR1_TAMP2E_Msk                 (0x1UL << TAMP_CR1_TAMP2E_Pos)          /*!< 0x00000002 */
#define TAMP_CR1_TAMP2E                     TAMP_CR1_TAMP2E_Msk
#define TAMP_CR1_TAMP3E_Pos                 (2UL)
#define TAMP_CR1_TAMP3E_Msk                 (0x1UL << TAMP_CR1_TAMP3E_Pos)          /*!< 0x00000004 */
#define TAMP_CR1_TAMP3E                     TAMP_CR1_TAMP3E_Msk
#define TAMP_CR1_TAMP4E_Pos                 (3UL)
#define TAMP_CR1_TAMP4E_Msk                 (0x1UL << TAMP_CR1_TAMP4E_Pos)          /*!< 0x00000008 */
#define TAMP_CR1_TAMP4E                     TAMP_CR1_TAMP4E_Msk
#define TAMP_CR1_TAMP5E_Pos                 (4UL)
#define TAMP_CR1_TAMP5E_Msk                 (0x1UL << TAMP_CR1_TAMP5E_Pos)          /*!< 0x00000010 */
#define TAMP_CR1_TAMP5E                     TAMP_CR1_TAMP5E_Msk
#define TAMP_CR1_ITAMP3E_Pos                (18UL)
#define TAMP_CR1_ITAMP3E_Msk                (0x1UL << TAMP_CR1_ITAMP3E_Pos)         /*!< 0x00040000 */
#define TAMP_CR1_ITAMP3E                    TAMP_CR1_ITAMP3E_Msk
#define TAMP_CR1_ITAMP5E_Pos                (20UL)
#define TAMP_CR1_ITAMP5E_Msk                (0x1UL << TAMP_CR1_ITAMP5E_Pos)         /*!< 0x00100000 */
#define TAMP_CR1_ITAMP5E                    TAMP_CR1_ITAMP5E_Msk
#define TAMP_CR1_ITAMP6E_Pos                (21UL)
#define TAMP_CR1_ITAMP6E_Msk                (0x1UL << TAMP_CR1_ITAMP6E_Pos)         /*!< 0x00200000 */
#define TAMP_CR1_ITAMP6E                    TAMP_CR1_ITAMP6E_Msk
#define TAMP_CR1_ITAMP7E_Pos                (22UL)
#define TAMP_CR1_ITAMP7E_Msk                (0x1UL << TAMP_CR1_ITAMP7E_Pos)         /*!< 0x00400000 */
#define TAMP_CR1_ITAMP7E                    TAMP_CR1_ITAMP7E_Msk
#define TAMP_CR1_ITAMP8E_Pos                (23UL)
#define TAMP_CR1_ITAMP8E_Msk                (0x1UL << TAMP_CR1_ITAMP8E_Pos)         /*!< 0x00800000 */
#define TAMP_CR1_ITAMP8E                    TAMP_CR1_ITAMP8E_Msk
#define TAMP_CR1_ITAMP9E_Pos                (24UL)
#define TAMP_CR1_ITAMP9E_Msk                (0x1UL << TAMP_CR1_ITAMP9E_Pos)         /*!< 0x01000000 */
#define TAMP_CR1_ITAMP9E                    TAMP_CR1_ITAMP9E_Msk
#define TAMP_CR1_ITAMP11E_Pos               (26UL)
#define TAMP_CR1_ITAMP11E_Msk               (0x1UL << TAMP_CR1_ITAMP11E_Pos)        /*!< 0x04000000 */
#define TAMP_CR1_ITAMP11E                   TAMP_CR1_ITAMP11E_Msk
#define TAMP_CR1_ITAMP12E_Pos               (27UL)
#define TAMP_CR1_ITAMP12E_Msk               (0x1UL << TAMP_CR1_ITAMP12E_Pos)        /*!< 0x08000000 */
#define TAMP_CR1_ITAMP12E                   TAMP_CR1_ITAMP12E_Msk
#define TAMP_CR1_ITAMP13E_Pos               (28UL)
#define TAMP_CR1_ITAMP13E_Msk               (0x1UL << TAMP_CR1_ITAMP13E_Pos)        /*!< 0x10000000 */
#define TAMP_CR1_ITAMP13E                   TAMP_CR1_ITAMP13E_Msk

/********************  Bits definition for TAMP_CR2 register  *****************/
#define TAMP_CR2_TAMP1POM_Pos               (0UL)
#define TAMP_CR2_TAMP1POM_Msk               (0x1UL << TAMP_CR2_TAMP1POM_Pos)        /*!< 0x00000001 */
#define TAMP_CR2_TAMP1POM                   TAMP_CR2_TAMP1POM_Msk
#define TAMP_CR2_TAMP2POM_Pos               (1UL)
#define TAMP_CR2_TAMP2POM_Msk               (0x1UL << TAMP_CR2_TAMP2POM_Pos)        /*!< 0x00000002 */
#define TAMP_CR2_TAMP2POM                   TAMP_CR2_TAMP2POM_Msk
#define TAMP_CR2_TAMP3POM_Pos               (2UL)
#define TAMP_CR2_TAMP3POM_Msk               (0x1UL << TAMP_CR2_TAMP3POM_Pos)        /*!< 0x00000004 */
#define TAMP_CR2_TAMP3POM                   TAMP_CR2_TAMP3POM_Msk
#define TAMP_CR2_TAMP4POM_Pos               (3UL)
#define TAMP_CR2_TAMP4POM_Msk               (0x1UL << TAMP_CR2_TAMP4POM_Pos)        /*!< 0x00000008 */
#define TAMP_CR2_TAMP4POM                   TAMP_CR2_TAMP4POM_Msk
#define TAMP_CR2_TAMP5POM_Pos               (4UL)
#define TAMP_CR2_TAMP5POM_Msk               (0x1UL << TAMP_CR2_TAMP5POM_Pos)        /*!< 0x00000010 */
#define TAMP_CR2_TAMP5POM                   TAMP_CR2_TAMP5POM_Msk
#define TAMP_CR2_TAMP1MSK_Pos               (16UL)
#define TAMP_CR2_TAMP1MSK_Msk               (0x1UL << TAMP_CR2_TAMP1MSK_Pos)        /*!< 0x00010000 */
#define TAMP_CR2_TAMP1MSK                   TAMP_CR2_TAMP1MSK_Msk
#define TAMP_CR2_TAMP2MSK_Pos               (17UL)
#define TAMP_CR2_TAMP2MSK_Msk               (0x1UL << TAMP_CR2_TAMP2MSK_Pos)        /*!< 0x00020000 */
#define TAMP_CR2_TAMP2MSK                   TAMP_CR2_TAMP2MSK_Msk
#define TAMP_CR2_TAMP3MSK_Pos               (18UL)
#define TAMP_CR2_TAMP3MSK_Msk               (0x1UL << TAMP_CR2_TAMP3MSK_Pos)        /*!< 0x00040000 */
#define TAMP_CR2_TAMP3MSK                   TAMP_CR2_TAMP3MSK_Msk
#define TAMP_CR2_BKBLOCK_Pos                (22UL)
#define TAMP_CR2_BKBLOCK_Msk                (0x1UL << TAMP_CR2_BKBLOCK_Pos)         /*!< 0x00400000 */
#define TAMP_CR2_BKBLOCK                    TAMP_CR2_BKBLOCK_Msk
#define TAMP_CR2_BKERASE_Pos                (23UL)
#define TAMP_CR2_BKERASE_Msk                (0x1UL << TAMP_CR2_BKERASE_Pos)         /*!< 0x00800000 */
#define TAMP_CR2_BKERASE                    TAMP_CR2_BKERASE_Msk
#define TAMP_CR2_TAMP1TRG_Pos               (24UL)
#define TAMP_CR2_TAMP1TRG_Msk               (0x1UL << TAMP_CR2_TAMP1TRG_Pos)        /*!< 0x01000000 */
#define TAMP_CR2_TAMP1TRG                   TAMP_CR2_TAMP1TRG_Msk
#define TAMP_CR2_TAMP2TRG_Pos               (25UL)
#define TAMP_CR2_TAMP2TRG_Msk               (0x1UL << TAMP_CR2_TAMP2TRG_Pos)        /*!< 0x02000000 */
#define TAMP_CR2_TAMP2TRG                   TAMP_CR2_TAMP2TRG_Msk
#define TAMP_CR2_TAMP3TRG_Pos               (26UL)
#define TAMP_CR2_TAMP3TRG_Msk               (0x1UL << TAMP_CR2_TAMP3TRG_Pos)        /*!< 0x04000000 */
#define TAMP_CR2_TAMP3TRG                   TAMP_CR2_TAMP3TRG_Msk
#define TAMP_CR2_TAMP4TRG_Pos               (27UL)
#define TAMP_CR2_TAMP4TRG_Msk               (0x1UL << TAMP_CR2_TAMP4TRG_Pos)        /*!< 0x08000000 */
#define TAMP_CR2_TAMP4TRG                   TAMP_CR2_TAMP4TRG_Msk
#define TAMP_CR2_TAMP5TRG_Pos               (28UL)
#define TAMP_CR2_TAMP5TRG_Msk               (0x1UL << TAMP_CR2_TAMP5TRG_Pos)        /*!< 0x10000000 */
#define TAMP_CR2_TAMP5TRG                   TAMP_CR2_TAMP5TRG_Msk

/********************  Bits definition for TAMP_CR3 register  *****************/
#define TAMP_CR3_ITAMP3POM_Pos              (2UL)
#define TAMP_CR3_ITAMP3POM_Msk              (0x1UL << TAMP_CR3_ITAMP3POM_Pos)       /*!< 0x00000004 */
#define TAMP_CR3_ITAMP3POM                  TAMP_CR3_ITAMP3POM_Msk
#define TAMP_CR3_ITAMP5POM_Pos              (4UL)
#define TAMP_CR3_ITAMP5POM_Msk              (0x1UL << TAMP_CR3_ITAMP5POM_Pos)       /*!< 0x00000010 */
#define TAMP_CR3_ITAMP5POM                  TAMP_CR3_ITAMP5POM_Msk
#define TAMP_CR3_ITAMP6POM_Pos              (5UL)
#define TAMP_CR3_ITAMP6POM_Msk              (0x1UL << TAMP_CR3_ITAMP6POM_Pos)       /*!< 0x00000020 */
#define TAMP_CR3_ITAMP6POM                  TAMP_CR3_ITAMP6POM_Msk
#define TAMP_CR3_ITAMP7POM_Pos              (6UL)
#define TAMP_CR3_ITAMP7POM_Msk              (0x1UL << TAMP_CR3_ITAMP7POM_Pos)       /*!< 0x00000040 */
#define TAMP_CR3_ITAMP7POM                  TAMP_CR3_ITAMP7POM_Msk
#define TAMP_CR3_ITAMP8POM_Pos              (7UL)
#define TAMP_CR3_ITAMP8POM_Msk              (0x1UL << TAMP_CR3_ITAMP8POM_Pos)       /*!< 0x00000080 */
#define TAMP_CR3_ITAMP8POM                  TAMP_CR3_ITAMP8POM_Msk
#define TAMP_CR3_ITAMP9POM_Pos              (8UL)
#define TAMP_CR3_ITAMP9POM_Msk              (0x1UL << TAMP_CR3_ITAMP9POM_Pos)       /*!< 0x00000100 */
#define TAMP_CR3_ITAMP9POM                  TAMP_CR3_ITAMP9POM_Msk
#define TAMP_CR3_ITAMP11POM_Pos             (10UL)
#define TAMP_CR3_ITAMP11POM_Msk             (0x1UL << TAMP_CR3_ITAMP11POM_Pos)      /*!< 0x00000400 */
#define TAMP_CR3_ITAMP11POM                 TAMP_CR3_ITAMP11POM_Msk
#define TAMP_CR3_ITAMP12POM_Pos             (11UL)
#define TAMP_CR3_ITAMP12POM_Msk             (0x1UL << TAMP_CR3_ITAMP12POM_Pos)      /*!< 0x00000800 */
#define TAMP_CR3_ITAMP12POM                 TAMP_CR3_ITAMP12POM_Msk
#define TAMP_CR3_ITAMP13POM_Pos             (12UL)
#define TAMP_CR3_ITAMP13POM_Msk             (0x1UL << TAMP_CR3_ITAMP13POM_Pos)      /*!< 0x00001000 */
#define TAMP_CR3_ITAMP13POM                 TAMP_CR3_ITAMP13POM_Msk

/********************  Bits definition for TAMP_FLTCR register  ***************/
#define TAMP_FLTCR_TAMPFREQ_Pos             (0UL)
#define TAMP_FLTCR_TAMPFREQ_Msk             (0x7UL << TAMP_FLTCR_TAMPFREQ_Pos)      /*!< 0x00000007 */
#define TAMP_FLTCR_TAMPFREQ                 TAMP_FLTCR_TAMPFREQ_Msk
#define TAMP_FLTCR_TAMPFREQ_0               (0x1UL << TAMP_FLTCR_TAMPFREQ_Pos)      /*!< 0x00000001 */
#define TAMP_FLTCR_TAMPFREQ_1               (0x2UL << TAMP_FLTCR_TAMPFREQ_Pos)      /*!< 0x00000002 */
#define TAMP_FLTCR_TAMPFREQ_2               (0x4UL << TAMP_FLTCR_TAMPFREQ_Pos)      /*!< 0x00000004 */
#define TAMP_FLTCR_TAMPFLT_Pos              (3UL)
#define TAMP_FLTCR_TAMPFLT_Msk              (0x3UL << TAMP_FLTCR_TAMPFLT_Pos)       /*!< 0x00000018 */
#define TAMP_FLTCR_TAMPFLT                  TAMP_FLTCR_TAMPFLT_Msk
#define TAMP_FLTCR_TAMPFLT_0                (0x1UL << TAMP_FLTCR_TAMPFLT_Pos)       /*!< 0x00000008 */
#define TAMP_FLTCR_TAMPFLT_1                (0x2UL << TAMP_FLTCR_TAMPFLT_Pos)       /*!< 0x00000010 */
#define TAMP_FLTCR_TAMPPRCH_Pos             (5UL)
#define TAMP_FLTCR_TAMPPRCH_Msk             (0x3UL << TAMP_FLTCR_TAMPPRCH_Pos)      /*!< 0x00000060 */
#define TAMP_FLTCR_TAMPPRCH                 TAMP_FLTCR_TAMPPRCH_Msk
#define TAMP_FLTCR_TAMPPRCH_0               (0x1UL << TAMP_FLTCR_TAMPPRCH_Pos)      /*!< 0x00000020 */
#define TAMP_FLTCR_TAMPPRCH_1               (0x2UL << TAMP_FLTCR_TAMPPRCH_Pos)      /*!< 0x00000040 */
#define TAMP_FLTCR_TAMPPUDIS_Pos            (7UL)
#define TAMP_FLTCR_TAMPPUDIS_Msk            (0x1UL << TAMP_FLTCR_TAMPPUDIS_Pos)     /*!< 0x00000080 */
#define TAMP_FLTCR_TAMPPUDIS                TAMP_FLTCR_TAMPPUDIS_Msk

/********************  Bits definition for TAMP_SECCFGR register  *************/
#define TAMP_SECCFGR_BKPRWSEC_Pos           (0UL)
#define TAMP_SECCFGR_BKPRWSEC_Msk           (0xFFUL << TAMP_SECCFGR_BKPRWSEC_Pos)   /*!< 0x000000FF */
#define TAMP_SECCFGR_BKPRWSEC               TAMP_SECCFGR_BKPRWSEC_Msk
#define TAMP_SECCFGR_BKPRWSEC_0             (0x1UL << TAMP_SECCFGR_BKPRWSEC_Pos)    /*!< 0x00000001 */
#define TAMP_SECCFGR_BKPRWSEC_1             (0x2UL << TAMP_SECCFGR_BKPRWSEC_Pos)    /*!< 0x00000002 */
#define TAMP_SECCFGR_BKPRWSEC_2             (0x4UL << TAMP_SECCFGR_BKPRWSEC_Pos)    /*!< 0x00000004 */
#define TAMP_SECCFGR_BKPRWSEC_3             (0x8UL << TAMP_SECCFGR_BKPRWSEC_Pos)    /*!< 0x00000008 */
#define TAMP_SECCFGR_BKPRWSEC_4             (0x10UL << TAMP_SECCFGR_BKPRWSEC_Pos)   /*!< 0x00000010 */
#define TAMP_SECCFGR_BKPRWSEC_5             (0x20UL << TAMP_SECCFGR_BKPRWSEC_Pos)   /*!< 0x00000020 */
#define TAMP_SECCFGR_BKPRWSEC_6             (0x40UL << TAMP_SECCFGR_BKPRWSEC_Pos)   /*!< 0x00000040 */
#define TAMP_SECCFGR_BKPRWSEC_7             (0x80UL << TAMP_SECCFGR_BKPRWSEC_Pos)   /*!< 0x00000080 */
#define TAMP_SECCFGR_CNT1SEC_Pos            (15UL)
#define TAMP_SECCFGR_CNT1SEC_Msk            (0x1UL << TAMP_SECCFGR_CNT1SEC_Pos)     /*!< 0x00008000 */
#define TAMP_SECCFGR_CNT1SEC                TAMP_SECCFGR_CNT1SEC_Msk
#define TAMP_SECCFGR_BKPWSEC_Pos            (16UL)
#define TAMP_SECCFGR_BKPWSEC_Msk            (0xFFUL << TAMP_SECCFGR_BKPWSEC_Pos)    /*!< 0x00FF0000 */
#define TAMP_SECCFGR_BKPWSEC                TAMP_SECCFGR_BKPWSEC_Msk
#define TAMP_SECCFGR_BKPWSEC_0              (0x1UL << TAMP_SECCFGR_BKPWSEC_Pos)     /*!< 0x00010000 */
#define TAMP_SECCFGR_BKPWSEC_1              (0x2UL << TAMP_SECCFGR_BKPWSEC_Pos)     /*!< 0x00020000 */
#define TAMP_SECCFGR_BKPWSEC_2              (0x4UL << TAMP_SECCFGR_BKPWSEC_Pos)     /*!< 0x00040000 */
#define TAMP_SECCFGR_BKPWSEC_3              (0x8UL << TAMP_SECCFGR_BKPWSEC_Pos)     /*!< 0x00080000 */
#define TAMP_SECCFGR_BKPWSEC_4              (0x10UL << TAMP_SECCFGR_BKPWSEC_Pos)    /*!< 0x00100000 */
#define TAMP_SECCFGR_BKPWSEC_5              (0x20UL << TAMP_SECCFGR_BKPWSEC_Pos)    /*!< 0x00200000 */
#define TAMP_SECCFGR_BKPWSEC_6              (0x40UL << TAMP_SECCFGR_BKPWSEC_Pos)    /*!< 0x00400000 */
#define TAMP_SECCFGR_BKPWSEC_7              (0x80UL << TAMP_SECCFGR_BKPWSEC_Pos)    /*!< 0x00800000 */
#define TAMP_SECCFGR_BHKLOCK_Pos            (30UL)
#define TAMP_SECCFGR_BHKLOCK_Msk            (0x1UL << TAMP_SECCFGR_BHKLOCK_Pos)     /*!< 0x40000000 */
#define TAMP_SECCFGR_BHKLOCK                TAMP_SECCFGR_BHKLOCK_Msk
#define TAMP_SECCFGR_TAMPSEC_Pos            (31UL)
#define TAMP_SECCFGR_TAMPSEC_Msk            (0x1UL << TAMP_SECCFGR_TAMPSEC_Pos)     /*!< 0x80000000 */
#define TAMP_SECCFGR_TAMPSEC                TAMP_SECCFGR_TAMPSEC_Msk

/********************  Bits definition for TAMP_PRIVCFGR register  ************/
#define TAMP_PRIVCFGR_CNT1PRIV_Pos          (15UL)
#define TAMP_PRIVCFGR_CNT1PRIV_Msk          (0x1UL << TAMP_PRIVCFGR_CNT1PRIV_Pos)   /*!< 0x20000000 */
#define TAMP_PRIVCFGR_CNT1PRIV              TAMP_PRIVCFGR_CNT1PRIV_Msk
#define TAMP_PRIVCFGR_BKPRWPRIV_Pos         (29UL)
#define TAMP_PRIVCFGR_BKPRWPRIV_Msk         (0x1UL << TAMP_PRIVCFGR_BKPRWPRIV_Pos)  /*!< 0x20000000 */
#define TAMP_PRIVCFGR_BKPRWPRIV             TAMP_PRIVCFGR_BKPRWPRIV_Msk
#define TAMP_PRIVCFGR_BKPWPRIV_Pos          (30UL)
#define TAMP_PRIVCFGR_BKPWPRIV_Msk          (0x1UL << TAMP_PRIVCFGR_BKPWPRIV_Pos)   /*!< 0x40000000 */
#define TAMP_PRIVCFGR_BKPWPRIV              TAMP_PRIVCFGR_BKPWPRIV_Msk
#define TAMP_PRIVCFGR_TAMPPRIV_Pos          (31UL)
#define TAMP_PRIVCFGR_TAMPPRIV_Msk          (0x1UL << TAMP_PRIVCFGR_TAMPPRIV_Pos)   /*!< 0x80000000 */
#define TAMP_PRIVCFGR_TAMPPRIV              TAMP_PRIVCFGR_TAMPPRIV_Msk

/********************  Bits definition for TAMP_IER register  *****************/
#define TAMP_IER_TAMP1IE_Pos                (0UL)
#define TAMP_IER_TAMP1IE_Msk                (0x1UL << TAMP_IER_TAMP1IE_Pos)         /*!< 0x00000001 */
#define TAMP_IER_TAMP1IE                    TAMP_IER_TAMP1IE_Msk
#define TAMP_IER_TAMP2IE_Pos                (1UL)
#define TAMP_IER_TAMP2IE_Msk                (0x1UL << TAMP_IER_TAMP2IE_Pos)         /*!< 0x00000002 */
#define TAMP_IER_TAMP2IE                    TAMP_IER_TAMP2IE_Msk
#define TAMP_IER_TAMP3IE_Pos                (2UL)
#define TAMP_IER_TAMP3IE_Msk                (0x1UL << TAMP_IER_TAMP3IE_Pos)         /*!< 0x00000004 */
#define TAMP_IER_TAMP3IE                    TAMP_IER_TAMP3IE_Msk
#define TAMP_IER_TAMP4IE_Pos                (3UL)
#define TAMP_IER_TAMP4IE_Msk                (0x1UL << TAMP_IER_TAMP4IE_Pos)         /*!< 0x00000008 */
#define TAMP_IER_TAMP4IE                    TAMP_IER_TAMP4IE_Msk
#define TAMP_IER_TAMP5IE_Pos                (4UL)
#define TAMP_IER_TAMP5IE_Msk                (0x1UL << TAMP_IER_TAMP5IE_Pos)         /*!< 0x00000010 */
#define TAMP_IER_TAMP5IE                    TAMP_IER_TAMP5IE_Msk
#define TAMP_IER_ITAMP3IE_Pos               (18UL)
#define TAMP_IER_ITAMP3IE_Msk               (0x1UL << TAMP_IER_ITAMP3IE_Pos)        /*!< 0x00040000 */
#define TAMP_IER_ITAMP3IE                   TAMP_IER_ITAMP3IE_Msk
#define TAMP_IER_ITAMP5IE_Pos               (20UL)
#define TAMP_IER_ITAMP5IE_Msk               (0x1UL << TAMP_IER_ITAMP5IE_Pos)        /*!< 0x00100000 */
#define TAMP_IER_ITAMP5IE                   TAMP_IER_ITAMP5IE_Msk
#define TAMP_IER_ITAMP6IE_Pos               (21UL)
#define TAMP_IER_ITAMP6IE_Msk               (0x1UL << TAMP_IER_ITAMP6IE_Pos)        /*!< 0x00200000 */
#define TAMP_IER_ITAMP6IE                   TAMP_IER_ITAMP6IE_Msk
#define TAMP_IER_ITAMP7IE_Pos               (22UL)
#define TAMP_IER_ITAMP7IE_Msk               (0x1UL << TAMP_IER_ITAMP7IE_Pos)        /*!< 0x00400000 */
#define TAMP_IER_ITAMP7IE                   TAMP_IER_ITAMP7IE_Msk
#define TAMP_IER_ITAMP8IE_Pos               (23UL)
#define TAMP_IER_ITAMP8IE_Msk               (0x1UL << TAMP_IER_ITAMP8IE_Pos)        /*!< 0x00800000 */
#define TAMP_IER_ITAMP8IE                   TAMP_IER_ITAMP8IE_Msk
#define TAMP_IER_ITAMP9IE_Pos               (24UL)
#define TAMP_IER_ITAMP9IE_Msk               (0x1UL << TAMP_IER_ITAMP9IE_Pos)        /*!< 0x01000000 */
#define TAMP_IER_ITAMP9IE                   TAMP_IER_ITAMP9IE_Msk
#define TAMP_IER_ITAMP11IE_Pos              (26UL)
#define TAMP_IER_ITAMP11IE_Msk              (0x1UL << TAMP_IER_ITAMP11IE_Pos)       /*!< 0x04000000 */
#define TAMP_IER_ITAMP11IE                  TAMP_IER_ITAMP11IE_Msk
#define TAMP_IER_ITAMP12IE_Pos              (27UL)
#define TAMP_IER_ITAMP12IE_Msk              (0x1UL << TAMP_IER_ITAMP12IE_Pos)       /*!< 0x08000000 */
#define TAMP_IER_ITAMP12IE                  TAMP_IER_ITAMP12IE_Msk
#define TAMP_IER_ITAMP13IE_Pos              (28UL)
#define TAMP_IER_ITAMP13IE_Msk              (0x1UL << TAMP_IER_ITAMP13IE_Pos)       /*!< 0x10000000 */
#define TAMP_IER_ITAMP13IE                  TAMP_IER_ITAMP13IE_Msk

/********************  Bits definition for TAMP_SR register  *****************/
#define TAMP_SR_TAMP1F_Pos                  (0UL)
#define TAMP_SR_TAMP1F_Msk                  (0x1UL << TAMP_SR_TAMP1F_Pos)           /*!< 0x00000001 */
#define TAMP_SR_TAMP1F                      TAMP_SR_TAMP1F_Msk
#define TAMP_SR_TAMP2F_Pos                  (1UL)
#define TAMP_SR_TAMP2F_Msk                  (0x1UL << TAMP_SR_TAMP2F_Pos)           /*!< 0x00000002 */
#define TAMP_SR_TAMP2F                      TAMP_SR_TAMP2F_Msk
#define TAMP_SR_TAMP3F_Pos                  (2UL)
#define TAMP_SR_TAMP3F_Msk                  (0x1UL << TAMP_SR_TAMP3F_Pos)           /*!< 0x00000004 */
#define TAMP_SR_TAMP3F                      TAMP_SR_TAMP3F_Msk
#define TAMP_SR_TAMP4F_Pos                  (3UL)
#define TAMP_SR_TAMP4F_Msk                  (0x1UL << TAMP_SR_TAMP4F_Pos)           /*!< 0x00000008 */
#define TAMP_SR_TAMP4F                      TAMP_SR_TAMP4F_Msk
#define TAMP_SR_TAMP5F_Pos                  (4UL)
#define TAMP_SR_TAMP5F_Msk                  (0x1UL << TAMP_SR_TAMP5F_Pos)           /*!< 0x00000010 */
#define TAMP_SR_TAMP5F                      TAMP_SR_TAMP5F_Msk
#define TAMP_SR_ITAMP3F_Pos                 (18UL)
#define TAMP_SR_ITAMP3F_Msk                 (0x1UL << TAMP_SR_ITAMP3F_Pos)          /*!< 0x00040000 */
#define TAMP_SR_ITAMP3F                     TAMP_SR_ITAMP3F_Msk
#define TAMP_SR_ITAMP5F_Pos                 (20UL)
#define TAMP_SR_ITAMP5F_Msk                 (0x1UL << TAMP_SR_ITAMP5F_Pos)          /*!< 0x00100000 */
#define TAMP_SR_ITAMP5F                     TAMP_SR_ITAMP5F_Msk
#define TAMP_SR_ITAMP6F_Pos                 (21UL)
#define TAMP_SR_ITAMP6F_Msk                 (0x1UL << TAMP_SR_ITAMP6F_Pos)          /*!< 0x00200000 */
#define TAMP_SR_ITAMP6F                     TAMP_SR_ITAMP6F_Msk
#define TAMP_SR_ITAMP7F_Pos                 (22UL)
#define TAMP_SR_ITAMP7F_Msk                 (0x1UL << TAMP_SR_ITAMP7F_Pos)          /*!< 0x00400000 */
#define TAMP_SR_ITAMP7F                     TAMP_SR_ITAMP7F_Msk
#define TAMP_SR_ITAMP8F_Pos                 (23UL)
#define TAMP_SR_ITAMP8F_Msk                 (0x1UL << TAMP_SR_ITAMP8F_Pos)          /*!< 0x00800000 */
#define TAMP_SR_ITAMP8F                     TAMP_SR_ITAMP8F_Msk
#define TAMP_SR_ITAMP9F_Pos                 (24UL)
#define TAMP_SR_ITAMP9F_Msk                 (0x1UL << TAMP_SR_ITAMP9F_Pos)          /*!< 0x01000000 */
#define TAMP_SR_ITAMP9F                     TAMP_SR_ITAMP9F_Msk
#define TAMP_SR_ITAMP11F_Pos                (26UL)
#define TAMP_SR_ITAMP11F_Msk                (0x1UL << TAMP_SR_ITAMP11F_Pos)         /*!< 0x04000000 */
#define TAMP_SR_ITAMP11F                    TAMP_SR_ITAMP11F_Msk
#define TAMP_SR_ITAMP12F_Pos                (27UL)
#define TAMP_SR_ITAMP12F_Msk                (0x1UL << TAMP_SR_ITAMP12F_Pos)         /*!< 0x08000000 */
#define TAMP_SR_ITAMP12F                    TAMP_SR_ITAMP12F_Msk
#define TAMP_SR_ITAMP13F_Pos                (28UL)
#define TAMP_SR_ITAMP13F_Msk                (0x1UL << TAMP_SR_ITAMP13F_Pos)         /*!< 0x10000000 */
#define TAMP_SR_ITAMP13F                    TAMP_SR_ITAMP13F_Msk

/********************  Bits definition for TAMP_MISR register  ****************/
#define TAMP_MISR_TAMP1MF_Pos               (0UL)
#define TAMP_MISR_TAMP1MF_Msk               (0x1UL << TAMP_MISR_TAMP1MF_Pos)        /*!< 0x00000001 */
#define TAMP_MISR_TAMP1MF                   TAMP_MISR_TAMP1MF_Msk
#define TAMP_MISR_TAMP2MF_Pos               (1UL)
#define TAMP_MISR_TAMP2MF_Msk               (0x1UL << TAMP_MISR_TAMP2MF_Pos)        /*!< 0x00000002 */
#define TAMP_MISR_TAMP2MF                   TAMP_MISR_TAMP2MF_Msk
#define TAMP_MISR_TAMP3MF_Pos               (2UL)
#define TAMP_MISR_TAMP3MF_Msk               (0x1UL << TAMP_MISR_TAMP3MF_Pos)        /*!< 0x00000004 */
#define TAMP_MISR_TAMP3MF                   TAMP_MISR_TAMP3MF_Msk
#define TAMP_MISR_TAMP4MF_Pos               (3UL)
#define TAMP_MISR_TAMP4MF_Msk               (0x1UL << TAMP_MISR_TAMP4MF_Pos)        /*!< 0x00000008 */
#define TAMP_MISR_TAMP4MF                   TAMP_MISR_TAMP4MF_Msk
#define TAMP_MISR_TAMP5MF_Pos               (4UL)
#define TAMP_MISR_TAMP5MF_Msk               (0x1UL << TAMP_MISR_TAMP5MF_Pos)        /*!< 0x00000010 */
#define TAMP_MISR_TAMP5MF                   TAMP_MISR_TAMP5MF_Msk
#define TAMP_MISR_ITAMP3MF_Pos              (18UL)
#define TAMP_MISR_ITAMP3MF_Msk              (0x1UL << TAMP_MISR_ITAMP3MF_Pos)       /*!< 0x00040000 */
#define TAMP_MISR_ITAMP3MF                  TAMP_MISR_ITAMP3MF_Msk
#define TAMP_MISR_ITAMP5MF_Pos              (20UL)
#define TAMP_MISR_ITAMP5MF_Msk              (0x1UL << TAMP_MISR_ITAMP5MF_Pos)       /*!< 0x00100000 */
#define TAMP_MISR_ITAMP5MF                  TAMP_MISR_ITAMP5MF_Msk
#define TAMP_MISR_ITAMP6MF_Pos              (21UL)
#define TAMP_MISR_ITAMP6MF_Msk              (0x1UL << TAMP_MISR_ITAMP6MF_Pos)       /*!< 0x00200000 */
#define TAMP_MISR_ITAMP6MF                  TAMP_MISR_ITAMP6MF_Msk
#define TAMP_MISR_ITAMP7MF_Pos              (22UL)
#define TAMP_MISR_ITAMP7MF_Msk              (0x1UL << TAMP_MISR_ITAMP7MF_Pos)       /*!< 0x00400000 */
#define TAMP_MISR_ITAMP7MF                  TAMP_MISR_ITAMP7MF_Msk
#define TAMP_MISR_ITAMP8MF_Pos              (23UL)
#define TAMP_MISR_ITAMP8MF_Msk              (0x1UL << TAMP_MISR_ITAMP8MF_Pos)       /*!< 0x00800000 */
#define TAMP_MISR_ITAMP8MF                  TAMP_MISR_ITAMP8MF_Msk
#define TAMP_MISR_ITAMP9MF_Pos              (24UL)
#define TAMP_MISR_ITAMP9MF_Msk              (0x1UL << TAMP_MISR_ITAMP9MF_Pos)       /*!< 0x01000000 */
#define TAMP_MISR_ITAMP9MF                  TAMP_MISR_ITAMP9MF_Msk
#define TAMP_MISR_ITAMP11MF_Pos             (26UL)
#define TAMP_MISR_ITAMP11MF_Msk             (0x1UL << TAMP_MISR_ITAMP11MF_Pos)      /*!< 0x04000000 */
#define TAMP_MISR_ITAMP11MF                 TAMP_MISR_ITAMP11MF_Msk
#define TAMP_MISR_ITAMP12MF_Pos             (27UL)
#define TAMP_MISR_ITAMP12MF_Msk             (0x1UL << TAMP_MISR_ITAMP12MF_Pos)      /*!< 0x08000000 */
#define TAMP_MISR_ITAMP12MF                 TAMP_MISR_ITAMP12MF_Msk
#define TAMP_MISR_ITAMP13MF_Pos             (28UL)
#define TAMP_MISR_ITAMP13MF_Msk             (0x1UL << TAMP_MISR_ITAMP13MF_Pos)      /*!< 0x10000000 */
#define TAMP_MISR_ITAMP13MF                 TAMP_MISR_ITAMP13MF_Msk

/********************  Bits definition for TAMP_SMISR register  ************ *****/
#define TAMP_SMISR_TAMP1MF_Pos              (0UL)
#define TAMP_SMISR_TAMP1MF_Msk              (0x1UL << TAMP_SMISR_TAMP1MF_Pos)       /*!< 0x00000001 */
#define TAMP_SMISR_TAMP1MF                  TAMP_SMISR_TAMP1MF_Msk
#define TAMP_SMISR_TAMP2MF_Pos              (1UL)
#define TAMP_SMISR_TAMP2MF_Msk              (0x1UL << TAMP_SMISR_TAMP2MF_Pos)       /*!< 0x00000002 */
#define TAMP_SMISR_TAMP2MF                  TAMP_SMISR_TAMP2MF_Msk
#define TAMP_SMISR_TAMP3MF_Pos              (2UL)
#define TAMP_SMISR_TAMP3MF_Msk              (0x1UL << TAMP_SMISR_TAMP3MF_Pos)       /*!< 0x00000004 */
#define TAMP_SMISR_TAMP3MF                  TAMP_SMISR_TAMP3MF_Msk
#define TAMP_SMISR_TAMP4MF_Pos              (3UL)
#define TAMP_SMISR_TAMP4MF_Msk              (0x1UL << TAMP_SMISR_TAMP4MF_Pos)       /*!< 0x00000008 */
#define TAMP_SMISR_TAMP4MF                  TAMP_SMISR_TAMP4MF_Msk
#define TAMP_SMISR_TAMP5MF_Pos              (4UL)
#define TAMP_SMISR_TAMP5MF_Msk              (0x1UL << TAMP_SMISR_TAMP5MF_Pos)       /*!< 0x00000010 */
#define TAMP_SMISR_TAMP5MF                  TAMP_SMISR_TAMP5MF_Msk
#define TAMP_SMISR_ITAMP3MF_Pos             (18UL)
#define TAMP_SMISR_ITAMP3MF_Msk             (0x1UL << TAMP_SMISR_ITAMP3MF_Pos)      /*!< 0x00040000 */
#define TAMP_SMISR_ITAMP3MF                 TAMP_SMISR_ITAMP3MF_Msk
#define TAMP_SMISR_ITAMP5MF_Pos             (20UL)
#define TAMP_SMISR_ITAMP5MF_Msk             (0x1UL << TAMP_SMISR_ITAMP5MF_Pos)      /*!< 0x00100000 */
#define TAMP_SMISR_ITAMP5MF                 TAMP_SMISR_ITAMP5MF_Msk
#define TAMP_SMISR_ITAMP6MF_Pos             (21UL)
#define TAMP_SMISR_ITAMP6MF_Msk             (0x1UL << TAMP_SMISR_ITAMP6MF_Pos)      /*!< 0x00200000 */
#define TAMP_SMISR_ITAMP6MF                 TAMP_SMISR_ITAMP6MF_Msk
#define TAMP_SMISR_ITAMP7MF_Pos             (22UL)
#define TAMP_SMISR_ITAMP7MF_Msk             (0x1UL << TAMP_SMISR_ITAMP7MF_Pos)      /*!< 0x00400000 */
#define TAMP_SMISR_ITAMP7MF                 TAMP_SMISR_ITAMP7MF_Msk
#define TAMP_SMISR_ITAMP8MF_Pos             (23UL)
#define TAMP_SMISR_ITAMP8MF_Msk             (0x1UL << TAMP_SMISR_ITAMP8MF_Pos)      /*!< 0x00800000 */
#define TAMP_SMISR_ITAMP8MF                 TAMP_SMISR_ITAMP8MF_Msk
#define TAMP_SMISR_ITAMP9MF_Pos             (24UL)
#define TAMP_SMISR_ITAMP9MF_Msk             (0x1UL << TAMP_SMISR_ITAMP9MF_Pos)      /*!< 0x01000000 */
#define TAMP_SMISR_ITAMP9MF                 TAMP_SMISR_ITAMP9MF_Msk
#define TAMP_SMISR_ITAMP11MF_Pos            (26UL)
#define TAMP_SMISR_ITAMP11MF_Msk            (0x1UL << TAMP_SMISR_ITAMP11MF_Pos)     /*!< 0x04000000 */
#define TAMP_SMISR_ITAMP11MF                TAMP_SMISR_ITAMP11MF_Msk
#define TAMP_SMISR_ITAMP12MF_Pos            (27UL)
#define TAMP_SMISR_ITAMP12MF_Msk            (0x1UL << TAMP_SMISR_ITAMP12MF_Pos)     /*!< 0x08000000 */
#define TAMP_SMISR_ITAMP12MF                TAMP_SMISR_ITAMP12MF_Msk
#define TAMP_SMISR_ITAMP13MF_Pos            (28UL)
#define TAMP_SMISR_ITAMP13MF_Msk            (0x1UL << TAMP_SMISR_ITAMP13MF_Pos)     /*!< 0x10000000 */
#define TAMP_SMISR_ITAMP13MF                TAMP_SMISR_ITAMP13MF_Msk

/********************  Bits definition for TAMP_SCR register  *****************/
#define TAMP_SCR_CTAMP1F_Pos                (0UL)
#define TAMP_SCR_CTAMP1F_Msk                (0x1UL << TAMP_SCR_CTAMP1F_Pos)         /*!< 0x00000001 */
#define TAMP_SCR_CTAMP1F                    TAMP_SCR_CTAMP1F_Msk
#define TAMP_SCR_CTAMP2F_Pos                (1UL)
#define TAMP_SCR_CTAMP2F_Msk                (0x1UL << TAMP_SCR_CTAMP2F_Pos)         /*!< 0x00000002 */
#define TAMP_SCR_CTAMP2F                    TAMP_SCR_CTAMP2F_Msk
#define TAMP_SCR_CTAMP3F_Pos                (2UL)
#define TAMP_SCR_CTAMP3F_Msk                (0x1UL << TAMP_SCR_CTAMP3F_Pos)         /*!< 0x00000004 */
#define TAMP_SCR_CTAMP3F                    TAMP_SCR_CTAMP3F_Msk
#define TAMP_SCR_CTAMP4F_Pos                (3UL)
#define TAMP_SCR_CTAMP4F_Msk                (0x1UL << TAMP_SCR_CTAMP4F_Pos)         /*!< 0x00000008 */
#define TAMP_SCR_CTAMP4F                    TAMP_SCR_CTAMP4F_Msk
#define TAMP_SCR_CTAMP5F_Pos                (4UL)
#define TAMP_SCR_CTAMP5F_Msk                (0x1UL << TAMP_SCR_CTAMP5F_Pos)         /*!< 0x00000010 */
#define TAMP_SCR_CTAMP5F                    TAMP_SCR_CTAMP5F_Msk
#define TAMP_SCR_CITAMP3F_Pos               (18UL)
#define TAMP_SCR_CITAMP3F_Msk               (0x1UL << TAMP_SCR_CITAMP3F_Pos)        /*!< 0x00040000 */
#define TAMP_SCR_CITAMP3F                   TAMP_SCR_CITAMP3F_Msk
#define TAMP_SCR_CITAMP5F_Pos               (20UL)
#define TAMP_SCR_CITAMP5F_Msk               (0x1UL << TAMP_SCR_CITAMP5F_Pos)        /*!< 0x00100000 */
#define TAMP_SCR_CITAMP5F                   TAMP_SCR_CITAMP5F_Msk
#define TAMP_SCR_CITAMP6F_Pos               (21UL)
#define TAMP_SCR_CITAMP6F_Msk               (0x1UL << TAMP_SCR_CITAMP6F_Pos)        /*!< 0x00200000 */
#define TAMP_SCR_CITAMP6F                   TAMP_SCR_CITAMP6F_Msk
#define TAMP_SCR_CITAMP7F_Pos               (22UL)
#define TAMP_SCR_CITAMP7F_Msk               (0x1UL << TAMP_SCR_CITAMP7F_Pos)        /*!< 0x00400000 */
#define TAMP_SCR_CITAMP7F                   TAMP_SCR_CITAMP7F_Msk
#define TAMP_SCR_CITAMP8F_Pos               (23UL)
#define TAMP_SCR_CITAMP8F_Msk               (0x1UL << TAMP_SCR_CITAMP8F_Pos)        /*!< 0x00800000 */
#define TAMP_SCR_CITAMP8F                   TAMP_SCR_CITAMP8F_Msk
#define TAMP_SCR_CITAMP9F_Pos               (24UL)
#define TAMP_SCR_CITAMP9F_Msk               (0x1UL << TAMP_SCR_CITAMP9F_Pos)        /*!< 0x01000000 */
#define TAMP_SCR_CITAMP9F                   TAMP_SCR_CITAMP9F_Msk
#define TAMP_SCR_CITAMP11F_Pos              (26UL)
#define TAMP_SCR_CITAMP11F_Msk              (0x1UL << TAMP_SCR_CITAMP11F_Pos)       /*!< 0x04000000 */
#define TAMP_SCR_CITAMP11F                  TAMP_SCR_CITAMP11F_Msk
#define TAMP_SCR_CITAMP12F_Pos              (27UL)
#define TAMP_SCR_CITAMP12F_Msk              (0x1UL << TAMP_SCR_CITAMP12F_Pos)       /*!< 0x08000000 */
#define TAMP_SCR_CITAMP12F                  TAMP_SCR_CITAMP12F_Msk
#define TAMP_SCR_CITAMP13F_Pos              (28UL)
#define TAMP_SCR_CITAMP13F_Msk              (0x1UL << TAMP_SCR_CITAMP13F_Pos)       /*!< 0x10000000 */
#define TAMP_SCR_CITAMP13F                  TAMP_SCR_CITAMP13F_Msk

/********************  Bits definition for TAMP_COUNT1R register  ***************/
#define TAMP_COUNT1R_COUNT_Pos              (0UL)
#define TAMP_COUNT1R_COUNT_Msk              (0xFFFFFFFFUL << TAMP_COUNT1R_COUNT_Pos)/*!< 0xFFFFFFFF */
#define TAMP_COUNT1R_COUNT                  TAMP_COUNT1R_COUNT_Msk

/********************  Bits definition for TAMP_RPCFGR register  ***************/
#define TAMP_RPCFGR_RPCFG0_Pos             (0UL)
#define TAMP_RPCFGR_RPCFG0_Msk             (0x1UL << TAMP_RPCFGR_RPCFG0_Pos)        /*!< 0x00000001 */
#define TAMP_RPCFGR_RPCFG0                 TAMP_RPCFGR_RPCFG0_Msk
#define TAMP_RPCFGR_RPCFG1_Pos             (1UL)
#define TAMP_RPCFGR_RPCFG1_Msk             (0x1UL << TAMP_RPCFGR_RPCFG1_Pos)        /*!< 0x00000002 */
#define TAMP_RPCFGR_RPCFG1                 TAMP_RPCFGR_RPCFG1_Msk
#define TAMP_RPCFGR_RPCFG2_Pos             (2UL)
#define TAMP_RPCFGR_RPCFG2_Msk             (0x1UL << TAMP_RPCFGR_RPCFG2_Pos)        /*!< 0x00000004 */
#define TAMP_RPCFGR_RPCFG2                 TAMP_RPCFGR_RPCFG2_Msk
#define TAMP_RPCFGR_RPCFG3_Pos             (3UL)
#define TAMP_RPCFGR_RPCFG3_Msk             (0x1UL << TAMP_RPCFGR_RPCFG3_Pos)        /*!< 0x00000008 */
#define TAMP_RPCFGR_RPCFG3                 TAMP_RPCFGR_RPCFG3_Msk
#define TAMP_RPCFGR_RPCFG4_Pos             (4UL)
#define TAMP_RPCFGR_RPCFG4_Msk             (0x1UL << TAMP_RPCFGR_RPCFG4_Pos)        /*!< 0x00000010 */
#define TAMP_RPCFGR_RPCFG4                 TAMP_RPCFGR_RPCFG4_Msk
#define TAMP_RPCFGR_RPCFG5_Pos             (5UL)
#define TAMP_RPCFGR_RPCFG5_Msk             (0x1UL << TAMP_RPCFGR_RPCFG5_Pos)        /*!< 0x00000020 */
#define TAMP_RPCFGR_RPCFG5                 TAMP_RPCFGR_RPCFG5_Msk
#define TAMP_RPCFGR_RPCFG31_Pos            (31UL)
#define TAMP_RPCFGR_RPCFG31_Msk            (0x1UL << TAMP_RPCFGR_RPCFG31_Pos)       /*!< 0x80000000 */
#define TAMP_RPCFGR_RPCFG31                TAMP_RPCFGR_RPCFG31_Msk

/********************  Bits definition for TAMP_BKP0R register  ***************/
#define TAMP_BKP0R_Pos                      (0UL)
#define TAMP_BKP0R_Msk                      (0xFFFFFFFFUL << TAMP_BKP0R_Pos)        /*!< 0xFFFFFFFF */
#define TAMP_BKP0R                          TAMP_BKP0R_Msk

/********************  Bits definition for TAMP_BKP1R register  ****************/
#define TAMP_BKP1R_Pos                      (0UL)
#define TAMP_BKP1R_Msk                      (0xFFFFFFFFUL << TAMP_BKP1R_Pos)        /*!< 0xFFFFFFFF */
#define TAMP_BKP1R                          TAMP_BKP1R_Msk

/********************  Bits definition for TAMP_BKP2R register  ****************/
#define TAMP_BKP2R_Pos                      (0UL)
#define TAMP_BKP2R_Msk                      (0xFFFFFFFFUL << TAMP_BKP2R_Pos)        /*!< 0xFFFFFFFF */
#define TAMP_BKP2R                          TAMP_BKP2R_Msk

/********************  Bits definition for TAMP_BKP3R register  ****************/
#define TAMP_BKP3R_Pos                      (0UL)
#define TAMP_BKP3R_Msk                      (0xFFFFFFFFUL << TAMP_BKP3R_Pos)        /*!< 0xFFFFFFFF */
#define TAMP_BKP3R                          TAMP_BKP3R_Msk

/********************  Bits definition for TAMP_BKP4R register  ****************/
#define TAMP_BKP4R_Pos                      (0UL)
#define TAMP_BKP4R_Msk                      (0xFFFFFFFFUL << TAMP_BKP4R_Pos)        /*!< 0xFFFFFFFF */
#define TAMP_BKP4R                          TAMP_BKP4R_Msk

/********************  Bits definition for TAMP_BKP5R register  ****************/
#define TAMP_BKP5R_Pos                      (0UL)
#define TAMP_BKP5R_Msk                      (0xFFFFFFFFUL << TAMP_BKP5R_Pos)        /*!< 0xFFFFFFFF */
#define TAMP_BKP5R                          TAMP_BKP5R_Msk

/********************  Bits definition for TAMP_BKP6R register  ****************/
#define TAMP_BKP6R_Pos                      (0UL)
#define TAMP_BKP6R_Msk                      (0xFFFFFFFFUL << TAMP_BKP6R_Pos)        /*!< 0xFFFFFFFF */
#define TAMP_BKP6R                          TAMP_BKP6R_Msk

/********************  Bits definition for TAMP_BKP7R register  ****************/
#define TAMP_BKP7R_Pos                      (0UL)
#define TAMP_BKP7R_Msk                      (0xFFFFFFFFUL << TAMP_BKP7R_Pos)        /*!< 0xFFFFFFFF */
#define TAMP_BKP7R                          TAMP_BKP7R_Msk

/********************  Bits definition for TAMP_BKP8R register  ****************/
#define TAMP_BKP8R_Pos                      (0UL)
#define TAMP_BKP8R_Msk                      (0xFFFFFFFFUL << TAMP_BKP8R_Pos)        /*!< 0xFFFFFFFF */
#define TAMP_BKP8R                          TAMP_BKP8R_Msk

/********************  Bits definition for TAMP_BKP9R register  ****************/
#define TAMP_BKP9R_Pos                      (0UL)
#define TAMP_BKP9R_Msk                      (0xFFFFFFFFUL << TAMP_BKP9R_Pos)        /*!< 0xFFFFFFFF */
#define TAMP_BKP9R                          TAMP_BKP9R_Msk

/********************  Bits definition for TAMP_BKP10R register  ***************/
#define TAMP_BKP10R_Pos                     (0UL)
#define TAMP_BKP10R_Msk                     (0xFFFFFFFFUL << TAMP_BKP10R_Pos)       /*!< 0xFFFFFFFF */
#define TAMP_BKP10R                         TAMP_BKP10R_Msk

/********************  Bits definition for TAMP_BKP11R register  ***************/
#define TAMP_BKP11R_Pos                     (0UL)
#define TAMP_BKP11R_Msk                     (0xFFFFFFFFUL << TAMP_BKP11R_Pos)       /*!< 0xFFFFFFFF */
#define TAMP_BKP11R                         TAMP_BKP11R_Msk

/********************  Bits definition for TAMP_BKP12R register  ***************/
#define TAMP_BKP12R_Pos                     (0UL)
#define TAMP_BKP12R_Msk                     (0xFFFFFFFFUL << TAMP_BKP12R_Pos)       /*!< 0xFFFFFFFF */
#define TAMP_BKP12R                         TAMP_BKP12R_Msk

/********************  Bits definition for TAMP_BKP13R register  ***************/
#define TAMP_BKP13R_Pos                     (0UL)
#define TAMP_BKP13R_Msk                     (0xFFFFFFFFUL << TAMP_BKP13R_Pos)       /*!< 0xFFFFFFFF */
#define TAMP_BKP13R                         TAMP_BKP13R_Msk

/********************  Bits definition for TAMP_BKP14R register  ***************/
#define TAMP_BKP14R_Pos                     (0UL)
#define TAMP_BKP14R_Msk                     (0xFFFFFFFFUL << TAMP_BKP14R_Pos)       /*!< 0xFFFFFFFF */
#define TAMP_BKP14R                         TAMP_BKP14R_Msk

/********************  Bits definition for TAMP_BKP15R register  ***************/
#define TAMP_BKP15R_Pos                     (0UL)
#define TAMP_BKP15R_Msk                     (0xFFFFFFFFUL << TAMP_BKP15R_Pos)       /*!< 0xFFFFFFFF */
#define TAMP_BKP15R                         TAMP_BKP15R_Msk

/********************  Bits definition for TAMP_BKP16R register  ***************/
#define TAMP_BKP16R_Pos                     (0UL)
#define TAMP_BKP16R_Msk                     (0xFFFFFFFFUL << TAMP_BKP16R_Pos)       /*!< 0xFFFFFFFF */
#define TAMP_BKP16R                         TAMP_BKP16R_Msk

/********************  Bits definition for TAMP_BKP17R register  ***************/
#define TAMP_BKP17R_Pos                     (0UL)
#define TAMP_BKP17R_Msk                     (0xFFFFFFFFUL << TAMP_BKP17R_Pos)       /*!< 0xFFFFFFFF */
#define TAMP_BKP17R                         TAMP_BKP17R_Msk

/********************  Bits definition for TAMP_BKP18R register  ***************/
#define TAMP_BKP18R_Pos                     (0UL)
#define TAMP_BKP18R_Msk                     (0xFFFFFFFFUL << TAMP_BKP18R_Pos)       /*!< 0xFFFFFFFF */
#define TAMP_BKP18R                         TAMP_BKP18R_Msk

/********************  Bits definition for TAMP_BKP19R register  ***************/
#define TAMP_BKP19R_Pos                     (0UL)
#define TAMP_BKP19R_Msk                     (0xFFFFFFFFUL << TAMP_BKP19R_Pos)       /*!< 0xFFFFFFFF */
#define TAMP_BKP19R                         TAMP_BKP19R_Msk

/********************  Bits definition for TAMP_BKP20R register  ***************/
#define TAMP_BKP20R_Pos                     (0UL)
#define TAMP_BKP20R_Msk                     (0xFFFFFFFFUL << TAMP_BKP20R_Pos)       /*!< 0xFFFFFFFF */
#define TAMP_BKP20R                         TAMP_BKP20R_Msk

/********************  Bits definition for TAMP_BKP21R register  ***************/
#define TAMP_BKP21R_Pos                     (0UL)
#define TAMP_BKP21R_Msk                     (0xFFFFFFFFUL << TAMP_BKP21R_Pos)       /*!< 0xFFFFFFFF */
#define TAMP_BKP21R                         TAMP_BKP21R_Msk

/********************  Bits definition for TAMP_BKP22R register  ***************/
#define TAMP_BKP22R_Pos                     (0UL)
#define TAMP_BKP22R_Msk                     (0xFFFFFFFFUL << TAMP_BKP22R_Pos)       /*!< 0xFFFFFFFF */
#define TAMP_BKP22R                         TAMP_BKP22R_Msk

/********************  Bits definition for TAMP_BKP23R register  ***************/
#define TAMP_BKP23R_Pos                     (0UL)
#define TAMP_BKP23R_Msk                     (0xFFFFFFFFUL << TAMP_BKP23R_Pos)       /*!< 0xFFFFFFFF */
#define TAMP_BKP23R                         TAMP_BKP23R_Msk

/********************  Bits definition for TAMP_BKP24R register  ***************/
#define TAMP_BKP24R_Pos                     (0UL)
#define TAMP_BKP24R_Msk                     (0xFFFFFFFFUL << TAMP_BKP24R_Pos)       /*!< 0xFFFFFFFF */
#define TAMP_BKP24R                         TAMP_BKP24R_Msk

/********************  Bits definition for TAMP_BKP25R register  ***************/
#define TAMP_BKP25R_Pos                     (0UL)
#define TAMP_BKP25R_Msk                     (0xFFFFFFFFUL << TAMP_BKP25R_Pos)       /*!< 0xFFFFFFFF */
#define TAMP_BKP25R                         TAMP_BKP25R_Msk

/********************  Bits definition for TAMP_BKP26R register  ***************/
#define TAMP_BKP26R_Pos                     (0UL)
#define TAMP_BKP26R_Msk                     (0xFFFFFFFFUL << TAMP_BKP26R_Pos)       /*!< 0xFFFFFFFF */
#define TAMP_BKP26R                         TAMP_BKP26R_Msk

/********************  Bits definition for TAMP_BKP27R register  ***************/
#define TAMP_BKP27R_Pos                     (0UL)
#define TAMP_BKP27R_Msk                     (0xFFFFFFFFUL << TAMP_BKP27R_Pos)       /*!< 0xFFFFFFFF */
#define TAMP_BKP27R                         TAMP_BKP27R_Msk

/********************  Bits definition for TAMP_BKP28R register  ***************/
#define TAMP_BKP28R_Pos                     (0UL)
#define TAMP_BKP28R_Msk                     (0xFFFFFFFFUL << TAMP_BKP28R_Pos)       /*!< 0xFFFFFFFF */
#define TAMP_BKP28R                         TAMP_BKP28R_Msk

/********************  Bits definition for TAMP_BKP29R register  ***************/
#define TAMP_BKP29R_Pos                     (0UL)
#define TAMP_BKP29R_Msk                     (0xFFFFFFFFUL << TAMP_BKP29R_Pos)       /*!< 0xFFFFFFFF */
#define TAMP_BKP29R                         TAMP_BKP29R_Msk

/********************  Bits definition for TAMP_BKP30R register  ***************/
#define TAMP_BKP30R_Pos                     (0UL)
#define TAMP_BKP30R_Msk                     (0xFFFFFFFFUL << TAMP_BKP30R_Pos)       /*!< 0xFFFFFFFF */
#define TAMP_BKP30R                         TAMP_BKP30R_Msk

/********************  Bits definition for TAMP_BKP31R register  ***************/
#define TAMP_BKP31R_Pos                     (0UL)
#define TAMP_BKP31R_Msk                     (0xFFFFFFFFUL << TAMP_BKP31R_Pos)       /*!< 0xFFFFFFFF */
#define TAMP_BKP31R                         TAMP_BKP31R_Msk

/******************************************************************************/
/*                                                                            */
/*                                    TIM                                     */
/*                                                                            */
/******************************************************************************/
/*******************  Bit definition for TIM_CR1 register  ********************/
#define TIM_CR1_CEN_Pos                     (0UL)
#define TIM_CR1_CEN_Msk                     (0x1UL << TIM_CR1_CEN_Pos)              /*!< 0x00000001 */
#define TIM_CR1_CEN                         TIM_CR1_CEN_Msk                         /*!<Counter enable */
#define TIM_CR1_UDIS_Pos                    (1UL)
#define TIM_CR1_UDIS_Msk                    (0x1UL << TIM_CR1_UDIS_Pos)             /*!< 0x00000002 */
#define TIM_CR1_UDIS                        TIM_CR1_UDIS_Msk                        /*!<Update disable */
#define TIM_CR1_URS_Pos                     (2UL)
#define TIM_CR1_URS_Msk                     (0x1UL << TIM_CR1_URS_Pos)              /*!< 0x00000004 */
#define TIM_CR1_URS                         TIM_CR1_URS_Msk                         /*!<Update request source */
#define TIM_CR1_OPM_Pos                     (3UL)
#define TIM_CR1_OPM_Msk                     (0x1UL << TIM_CR1_OPM_Pos)              /*!< 0x00000008 */
#define TIM_CR1_OPM                         TIM_CR1_OPM_Msk                         /*!<One pulse mode */
#define TIM_CR1_DIR_Pos                     (4UL)
#define TIM_CR1_DIR_Msk                     (0x1UL << TIM_CR1_DIR_Pos)              /*!< 0x00000010 */
#define TIM_CR1_DIR                         TIM_CR1_DIR_Msk                         /*!<Direction */
#define TIM_CR1_CMS_Pos                     (5UL)
#define TIM_CR1_CMS_Msk                     (0x3UL << TIM_CR1_CMS_Pos)              /*!< 0x00000060 */
#define TIM_CR1_CMS                         TIM_CR1_CMS_Msk                         /*!<CMS[1:0] bits (Center-aligned mode selection) */
#define TIM_CR1_CMS_0                       (0x1UL << TIM_CR1_CMS_Pos)              /*!< 0x00000020 */
#define TIM_CR1_CMS_1                       (0x2UL << TIM_CR1_CMS_Pos)              /*!< 0x00000040 */
#define TIM_CR1_ARPE_Pos                    (7UL)
#define TIM_CR1_ARPE_Msk                    (0x1UL << TIM_CR1_ARPE_Pos)             /*!< 0x00000080 */
#define TIM_CR1_ARPE                        TIM_CR1_ARPE_Msk                        /*!<Auto-reload preload enable */
#define TIM_CR1_CKD_Pos                     (8UL)
#define TIM_CR1_CKD_Msk                     (0x3UL << TIM_CR1_CKD_Pos)              /*!< 0x00000300 */
#define TIM_CR1_CKD                         TIM_CR1_CKD_Msk                         /*!<CKD[1:0] bits (clock division) */
#define TIM_CR1_CKD_0                       (0x1UL << TIM_CR1_CKD_Pos)              /*!< 0x00000100 */
#define TIM_CR1_CKD_1                       (0x2UL << TIM_CR1_CKD_Pos)              /*!< 0x00000200 */
#define TIM_CR1_UIFREMAP_Pos                (11UL)
#define TIM_CR1_UIFREMAP_Msk                (0x1UL << TIM_CR1_UIFREMAP_Pos)         /*!< 0x00000800 */
#define TIM_CR1_UIFREMAP                    TIM_CR1_UIFREMAP_Msk                    /*!<Update interrupt flag remap */
#define TIM_CR1_DITHEN_Pos                  (12UL)
#define TIM_CR1_DITHEN_Msk                  (0x1UL << TIM_CR1_DITHEN_Pos)           /*!< 0x00001000 */
#define TIM_CR1_DITHEN                      TIM_CR1_DITHEN_Msk                      /*!<Dithering enable */

/*******************  Bit definition for TIM_CR2 register  ********************/
#define TIM_CR2_CCPC_Pos                    (0UL)
#define TIM_CR2_CCPC_Msk                    (0x1UL << TIM_CR2_CCPC_Pos)             /*!< 0x00000001 */
#define TIM_CR2_CCPC                        TIM_CR2_CCPC_Msk                        /*!<Capture/Compare Preloaded Control */
#define TIM_CR2_CCUS_Pos                    (2UL)
#define TIM_CR2_CCUS_Msk                    (0x1UL << TIM_CR2_CCUS_Pos)             /*!< 0x00000004 */
#define TIM_CR2_CCUS                        TIM_CR2_CCUS_Msk                        /*!<Capture/Compare Control Update Selection */
#define TIM_CR2_CCDS_Pos                    (3UL)
#define TIM_CR2_CCDS_Msk                    (0x1UL << TIM_CR2_CCDS_Pos)             /*!< 0x00000008 */
#define TIM_CR2_CCDS                        TIM_CR2_CCDS_Msk                        /*!<Capture/Compare DMA Selection */
#define TIM_CR2_MMS_Pos                     (4UL)
#define TIM_CR2_MMS_Msk                     (0x200007UL << TIM_CR2_MMS_Pos)         /*!< 0x02000070 */
#define TIM_CR2_MMS                         TIM_CR2_MMS_Msk                         /*!<MMS[3:0] bits (Master Mode Selection) */
#define TIM_CR2_MMS_0                       (0x000001UL << TIM_CR2_MMS_Pos)         /*!< 0x00000010 */
#define TIM_CR2_MMS_1                       (0x000002UL << TIM_CR2_MMS_Pos)         /*!< 0x00000020 */
#define TIM_CR2_MMS_2                       (0x000004UL << TIM_CR2_MMS_Pos)         /*!< 0x00000040 */
#define TIM_CR2_MMS_3                       (0x200000UL << TIM_CR2_MMS_Pos)         /*!< 0x02000000 */
#define TIM_CR2_TI1S_Pos                    (7UL)
#define TIM_CR2_TI1S_Msk                    (0x1UL << TIM_CR2_TI1S_Pos)             /*!< 0x00000080 */
#define TIM_CR2_TI1S                        TIM_CR2_TI1S_Msk                        /*!<TI1 Selection */
#define TIM_CR2_OIS1_Pos                    (8UL)
#define TIM_CR2_OIS1_Msk                    (0x1UL << TIM_CR2_OIS1_Pos)             /*!< 0x00000100 */
#define TIM_CR2_OIS1                        TIM_CR2_OIS1_Msk                        /*!<Output Idle state 1 (OC1 output) */
#define TIM_CR2_OIS1N_Pos                   (9UL)
#define TIM_CR2_OIS1N_Msk                   (0x1UL << TIM_CR2_OIS1N_Pos)            /*!< 0x00000200 */
#define TIM_CR2_OIS1N                       TIM_CR2_OIS1N_Msk                       /*!<Output Idle state 1 (OC1N output) */
#define TIM_CR2_OIS2_Pos                    (10UL)
#define TIM_CR2_OIS2_Msk                    (0x1UL << TIM_CR2_OIS2_Pos)             /*!< 0x00000400 */
#define TIM_CR2_OIS2                        TIM_CR2_OIS2_Msk                        /*!<Output Idle state 2 (OC2 output) */
#define TIM_CR2_OIS2N_Pos                   (11UL)
#define TIM_CR2_OIS2N_Msk                   (0x1UL << TIM_CR2_OIS2N_Pos)            /*!< 0x00000800 */
#define TIM_CR2_OIS2N                       TIM_CR2_OIS2N_Msk                       /*!<Output Idle state 2 (OC2N output) */
#define TIM_CR2_OIS3_Pos                    (12UL)
#define TIM_CR2_OIS3_Msk                    (0x1UL << TIM_CR2_OIS3_Pos)             /*!< 0x00001000 */
#define TIM_CR2_OIS3                        TIM_CR2_OIS3_Msk                        /*!<Output Idle state 3 (OC3 output) */
#define TIM_CR2_OIS3N_Pos                   (13UL)
#define TIM_CR2_OIS3N_Msk                   (0x1UL << TIM_CR2_OIS3N_Pos)            /*!< 0x00002000 */
#define TIM_CR2_OIS3N                       TIM_CR2_OIS3N_Msk                       /*!<Output Idle state 3 (OC3N output) */
#define TIM_CR2_OIS4_Pos                    (14UL)
#define TIM_CR2_OIS4_Msk                    (0x1UL << TIM_CR2_OIS4_Pos)             /*!< 0x00004000 */
#define TIM_CR2_OIS4                        TIM_CR2_OIS4_Msk                        /*!<Output Idle state 4 (OC4 output) */
#define TIM_CR2_OIS4N_Pos                   (15UL)
#define TIM_CR2_OIS4N_Msk                   (0x1UL << TIM_CR2_OIS4N_Pos)            /*!< 0x00008000 */
#define TIM_CR2_OIS4N                       TIM_CR2_OIS4N_Msk                       /*!<Output Idle state 4 (OC4N output) */
#define TIM_CR2_OIS5_Pos                    (16UL)
#define TIM_CR2_OIS5_Msk                    (0x1UL << TIM_CR2_OIS5_Pos)             /*!< 0x00010000 */
#define TIM_CR2_OIS5                        TIM_CR2_OIS5_Msk                        /*!<Output Idle state 5 (OC5 output) */
#define TIM_CR2_OIS6_Pos                    (18UL)
#define TIM_CR2_OIS6_Msk                    (0x1UL << TIM_CR2_OIS6_Pos)             /*!< 0x00040000 */
#define TIM_CR2_OIS6                        TIM_CR2_OIS6_Msk                        /*!<Output Idle state 6 (OC6 output) */
#define TIM_CR2_MMS2_Pos                    (20UL)
#define TIM_CR2_MMS2_Msk                    (0xFUL << TIM_CR2_MMS2_Pos)             /*!< 0x00F00000 */
#define TIM_CR2_MMS2                        TIM_CR2_MMS2_Msk                        /*!<MMS[2:0] bits (Master Mode Selection) */
#define TIM_CR2_MMS2_0                      (0x1UL << TIM_CR2_MMS2_Pos)             /*!< 0x00100000 */
#define TIM_CR2_MMS2_1                      (0x2UL << TIM_CR2_MMS2_Pos)             /*!< 0x00200000 */
#define TIM_CR2_MMS2_2                      (0x4UL << TIM_CR2_MMS2_Pos)             /*!< 0x00400000 */
#define TIM_CR2_MMS2_3                      (0x8UL << TIM_CR2_MMS2_Pos)             /*!< 0x00800000 */
#define TIM_CR2_ADSYNC_Pos                  (28UL)
#define TIM_CR2_ADSYNC_Msk                  (0x1UL << TIM_CR2_ADSYNC_Pos)             /*!< 0x10000000 */
#define TIM_CR2_ADSYNC                      TIM_CR2_ADSYNC_Msk                        /*!<ADC synchronization */

/*******************  Bit definition for TIM_SMCR register  *******************/
#define TIM_SMCR_SMS_Pos                    (0UL)
#define TIM_SMCR_SMS_Msk                    (0x10007UL << TIM_SMCR_SMS_Pos)         /*!< 0x00010007 */
#define TIM_SMCR_SMS                        TIM_SMCR_SMS_Msk                        /*!<SMS[2:0] bits (Slave mode selection) */
#define TIM_SMCR_SMS_0                      (0x00001UL << TIM_SMCR_SMS_Pos)         /*!< 0x00000001 */
#define TIM_SMCR_SMS_1                      (0x00002UL << TIM_SMCR_SMS_Pos)         /*!< 0x00000002 */
#define TIM_SMCR_SMS_2                      (0x00004UL << TIM_SMCR_SMS_Pos)         /*!< 0x00000004 */
#define TIM_SMCR_SMS_3                      (0x10000UL << TIM_SMCR_SMS_Pos)         /*!< 0x00010000 */
#define TIM_SMCR_OCCS_Pos                   (3UL)
#define TIM_SMCR_OCCS_Msk                   (0x1UL << TIM_SMCR_OCCS_Pos)            /*!< 0x00000008 */
#define TIM_SMCR_OCCS                       TIM_SMCR_OCCS_Msk                       /*!< OCREF clear selection */
#define TIM_SMCR_TS_Pos                     (4UL)
#define TIM_SMCR_TS_Msk                     (0x30007UL << TIM_SMCR_TS_Pos)          /*!< 0x00300070 */
#define TIM_SMCR_TS                         TIM_SMCR_TS_Msk                         /*!<TS[2:0] bits (Trigger selection) */
#define TIM_SMCR_TS_0                       (0x00001UL << TIM_SMCR_TS_Pos)          /*!< 0x00000010 */
#define TIM_SMCR_TS_1                       (0x00002UL << TIM_SMCR_TS_Pos)          /*!< 0x00000020 */
#define TIM_SMCR_TS_2                       (0x00004UL << TIM_SMCR_TS_Pos)          /*!< 0x00000040 */
#define TIM_SMCR_TS_3                       (0x10000UL << TIM_SMCR_TS_Pos)          /*!< 0x00100000 */
#define TIM_SMCR_TS_4                       (0x20000UL << TIM_SMCR_TS_Pos)          /*!< 0x00200000 */
#define TIM_SMCR_MSM_Pos                    (7UL)
#define TIM_SMCR_MSM_Msk                    (0x1UL << TIM_SMCR_MSM_Pos)             /*!< 0x00000080 */
#define TIM_SMCR_MSM                        TIM_SMCR_MSM_Msk                        /*!<Master/slave mode */
#define TIM_SMCR_ETF_Pos                    (8UL)
#define TIM_SMCR_ETF_Msk                    (0xFUL << TIM_SMCR_ETF_Pos)             /*!< 0x00000F00 */
#define TIM_SMCR_ETF                        TIM_SMCR_ETF_Msk                        /*!<ETF[3:0] bits (External trigger filter) */
#define TIM_SMCR_ETF_0                      (0x1UL << TIM_SMCR_ETF_Pos)             /*!< 0x00000100 */
#define TIM_SMCR_ETF_1                      (0x2UL << TIM_SMCR_ETF_Pos)             /*!< 0x00000200 */
#define TIM_SMCR_ETF_2                      (0x4UL << TIM_SMCR_ETF_Pos)             /*!< 0x00000400 */
#define TIM_SMCR_ETF_3                      (0x8UL << TIM_SMCR_ETF_Pos)             /*!< 0x00000800 */
#define TIM_SMCR_ETPS_Pos                   (12UL)
#define TIM_SMCR_ETPS_Msk                   (0x3UL << TIM_SMCR_ETPS_Pos)            /*!< 0x00003000 */
#define TIM_SMCR_ETPS                       TIM_SMCR_ETPS_Msk                       /*!<ETPS[1:0] bits (External trigger prescaler) */
#define TIM_SMCR_ETPS_0                     (0x1UL << TIM_SMCR_ETPS_Pos)            /*!< 0x00001000 */
#define TIM_SMCR_ETPS_1                     (0x2UL << TIM_SMCR_ETPS_Pos)            /*!< 0x00002000 */
#define TIM_SMCR_ECE_Pos                    (14UL)
#define TIM_SMCR_ECE_Msk                    (0x1UL << TIM_SMCR_ECE_Pos)             /*!< 0x00004000 */
#define TIM_SMCR_ECE                        TIM_SMCR_ECE_Msk                        /*!<External clock enable */
#define TIM_SMCR_ETP_Pos                    (15UL)
#define TIM_SMCR_ETP_Msk                    (0x1UL << TIM_SMCR_ETP_Pos)             /*!< 0x00008000 */
#define TIM_SMCR_ETP                        TIM_SMCR_ETP_Msk                        /*!<External trigger polarity */
#define TIM_SMCR_SMSPE_Pos                  (24UL)
#define TIM_SMCR_SMSPE_Msk                  (0x1UL << TIM_SMCR_SMSPE_Pos)           /*!< 0x02000000 */
#define TIM_SMCR_SMSPE                      TIM_SMCR_SMSPE_Msk                      /*!<SMS preload enable */
#define TIM_SMCR_SMSPS_Pos                  (25UL)
#define TIM_SMCR_SMSPS_Msk                  (0x1UL << TIM_SMCR_SMSPS_Pos)           /*!< 0x04000000 */
#define TIM_SMCR_SMSPS                      TIM_SMCR_SMSPS_Msk                      /*!<SMS preload source */

/*******************  Bit definition for TIM_DIER register  *******************/
#define TIM_DIER_UIE_Pos                    (0UL)
#define TIM_DIER_UIE_Msk                    (0x1UL << TIM_DIER_UIE_Pos)             /*!< 0x00000001 */
#define TIM_DIER_UIE                        TIM_DIER_UIE_Msk                        /*!<Update interrupt enable */
#define TIM_DIER_CC1IE_Pos                  (1UL)
#define TIM_DIER_CC1IE_Msk                  (0x1UL << TIM_DIER_CC1IE_Pos)           /*!< 0x00000002 */
#define TIM_DIER_CC1IE                      TIM_DIER_CC1IE_Msk                      /*!<Capture/Compare 1 interrupt enable */
#define TIM_DIER_CC2IE_Pos                  (2UL)
#define TIM_DIER_CC2IE_Msk                  (0x1UL << TIM_DIER_CC2IE_Pos)           /*!< 0x00000004 */
#define TIM_DIER_CC2IE                      TIM_DIER_CC2IE_Msk                      /*!<Capture/Compare 2 interrupt enable */
#define TIM_DIER_CC3IE_Pos                  (3UL)
#define TIM_DIER_CC3IE_Msk                  (0x1UL << TIM_DIER_CC3IE_Pos)           /*!< 0x00000008 */
#define TIM_DIER_CC3IE                      TIM_DIER_CC3IE_Msk                      /*!<Capture/Compare 3 interrupt enable */
#define TIM_DIER_CC4IE_Pos                  (4UL)
#define TIM_DIER_CC4IE_Msk                  (0x1UL << TIM_DIER_CC4IE_Pos)           /*!< 0x00000010 */
#define TIM_DIER_CC4IE                      TIM_DIER_CC4IE_Msk                      /*!<Capture/Compare 4 interrupt enable */
#define TIM_DIER_COMIE_Pos                  (5UL)
#define TIM_DIER_COMIE_Msk                  (0x1UL << TIM_DIER_COMIE_Pos)           /*!< 0x00000020 */
#define TIM_DIER_COMIE                      TIM_DIER_COMIE_Msk                      /*!<COM interrupt enable */
#define TIM_DIER_TIE_Pos                    (6UL)
#define TIM_DIER_TIE_Msk                    (0x1UL << TIM_DIER_TIE_Pos)             /*!< 0x00000040 */
#define TIM_DIER_TIE                        TIM_DIER_TIE_Msk                        /*!<Trigger interrupt enable */
#define TIM_DIER_BIE_Pos                    (7UL)
#define TIM_DIER_BIE_Msk                    (0x1UL << TIM_DIER_BIE_Pos)             /*!< 0x00000080 */
#define TIM_DIER_BIE                        TIM_DIER_BIE_Msk                        /*!<Break interrupt enable */
#define TIM_DIER_UDE_Pos                    (8UL)
#define TIM_DIER_UDE_Msk                    (0x1UL << TIM_DIER_UDE_Pos)             /*!< 0x00000100 */
#define TIM_DIER_UDE                        TIM_DIER_UDE_Msk                        /*!<Update DMA request enable */
#define TIM_DIER_CC1DE_Pos                  (9UL)
#define TIM_DIER_CC1DE_Msk                  (0x1UL << TIM_DIER_CC1DE_Pos)           /*!< 0x00000200 */
#define TIM_DIER_CC1DE                      TIM_DIER_CC1DE_Msk                      /*!<Capture/Compare 1 DMA request enable */
#define TIM_DIER_CC2DE_Pos                  (10UL)
#define TIM_DIER_CC2DE_Msk                  (0x1UL << TIM_DIER_CC2DE_Pos)           /*!< 0x00000400 */
#define TIM_DIER_CC2DE                      TIM_DIER_CC2DE_Msk                      /*!<Capture/Compare 2 DMA request enable */
#define TIM_DIER_CC3DE_Pos                  (11UL)
#define TIM_DIER_CC3DE_Msk                  (0x1UL << TIM_DIER_CC3DE_Pos)           /*!< 0x00000800 */
#define TIM_DIER_CC3DE                      TIM_DIER_CC3DE_Msk                      /*!<Capture/Compare 3 DMA request enable */
#define TIM_DIER_CC4DE_Pos                  (12UL)
#define TIM_DIER_CC4DE_Msk                  (0x1UL << TIM_DIER_CC4DE_Pos)           /*!< 0x00001000 */
#define TIM_DIER_CC4DE                      TIM_DIER_CC4DE_Msk                      /*!<Capture/Compare 4 DMA request enable */
#define TIM_DIER_COMDE_Pos                  (13UL)
#define TIM_DIER_COMDE_Msk                  (0x1UL << TIM_DIER_COMDE_Pos)           /*!< 0x00002000 */
#define TIM_DIER_COMDE                      TIM_DIER_COMDE_Msk                      /*!<COM DMA request enable */
#define TIM_DIER_TDE_Pos                    (14UL)
#define TIM_DIER_TDE_Msk                    (0x1UL << TIM_DIER_TDE_Pos)             /*!< 0x00004000 */
#define TIM_DIER_TDE                        TIM_DIER_TDE_Msk                        /*!<Trigger DMA request enable */
#define TIM_DIER_IDXIE_Pos                  (20UL)
#define TIM_DIER_IDXIE_Msk                  (0x1UL << TIM_DIER_IDXIE_Pos)           /*!< 0x00100000 */
#define TIM_DIER_IDXIE                      TIM_DIER_IDXIE_Msk                      /*!<Encoder index interrupt enable */
#define TIM_DIER_DIRIE_Pos                  (21UL)
#define TIM_DIER_DIRIE_Msk                  (0x1UL << TIM_DIER_DIRIE_Pos)           /*!< 0x00200000 */
#define TIM_DIER_DIRIE                      TIM_DIER_DIRIE_Msk                      /*!<Encoder direction change interrupt enable */
#define TIM_DIER_IERRIE_Pos                 (22UL)
#define TIM_DIER_IERRIE_Msk                 (0x1UL << TIM_DIER_IERRIE_Pos)          /*!< 0x00400000 */
#define TIM_DIER_IERRIE                     TIM_DIER_IERRIE_Msk                     /*!<Encoder index error enable */
#define TIM_DIER_TERRIE_Pos                 (23UL)
#define TIM_DIER_TERRIE_Msk                 (0x1UL << TIM_DIER_TERRIE_Pos)          /*!< 0x00800000 */
#define TIM_DIER_TERRIE                     TIM_DIER_TERRIE_Msk                     /*!<Encoder transition error enable */

/********************  Bit definition for TIM_SR register  ********************/
#define TIM_SR_UIF_Pos                      (0UL)
#define TIM_SR_UIF_Msk                      (0x1UL << TIM_SR_UIF_Pos)               /*!< 0x00000001 */
#define TIM_SR_UIF                          TIM_SR_UIF_Msk                          /*!<Update interrupt Flag */
#define TIM_SR_CC1IF_Pos                    (1UL)
#define TIM_SR_CC1IF_Msk                    (0x1UL << TIM_SR_CC1IF_Pos)             /*!< 0x00000002 */
#define TIM_SR_CC1IF                        TIM_SR_CC1IF_Msk                        /*!<Capture/Compare 1 interrupt Flag */
#define TIM_SR_CC2IF_Pos                    (2UL)
#define TIM_SR_CC2IF_Msk                    (0x1UL << TIM_SR_CC2IF_Pos)             /*!< 0x00000004 */
#define TIM_SR_CC2IF                        TIM_SR_CC2IF_Msk                        /*!<Capture/Compare 2 interrupt Flag */
#define TIM_SR_CC3IF_Pos                    (3UL)
#define TIM_SR_CC3IF_Msk                    (0x1UL << TIM_SR_CC3IF_Pos)             /*!< 0x00000008 */
#define TIM_SR_CC3IF                        TIM_SR_CC3IF_Msk                        /*!<Capture/Compare 3 interrupt Flag */
#define TIM_SR_CC4IF_Pos                    (4UL)
#define TIM_SR_CC4IF_Msk                    (0x1UL << TIM_SR_CC4IF_Pos)             /*!< 0x00000010 */
#define TIM_SR_CC4IF                        TIM_SR_CC4IF_Msk                        /*!<Capture/Compare 4 interrupt Flag */
#define TIM_SR_COMIF_Pos                    (5UL)
#define TIM_SR_COMIF_Msk                    (0x1UL << TIM_SR_COMIF_Pos)             /*!< 0x00000020 */
#define TIM_SR_COMIF                        TIM_SR_COMIF_Msk                        /*!<COM interrupt Flag */
#define TIM_SR_TIF_Pos                      (6UL)
#define TIM_SR_TIF_Msk                      (0x1UL << TIM_SR_TIF_Pos)               /*!< 0x00000040 */
#define TIM_SR_TIF                          TIM_SR_TIF_Msk                          /*!<Trigger interrupt Flag */
#define TIM_SR_BIF_Pos                      (7UL)
#define TIM_SR_BIF_Msk                      (0x1UL << TIM_SR_BIF_Pos)               /*!< 0x00000080 */
#define TIM_SR_BIF                          TIM_SR_BIF_Msk                          /*!<Break interrupt Flag */
#define TIM_SR_B2IF_Pos                     (8UL)
#define TIM_SR_B2IF_Msk                     (0x1UL << TIM_SR_B2IF_Pos)              /*!< 0x00000100 */
#define TIM_SR_B2IF                         TIM_SR_B2IF_Msk                         /*!<Break 2 interrupt Flag */
#define TIM_SR_CC1OF_Pos                    (9UL)
#define TIM_SR_CC1OF_Msk                    (0x1UL << TIM_SR_CC1OF_Pos)             /*!< 0x00000200 */
#define TIM_SR_CC1OF                        TIM_SR_CC1OF_Msk                        /*!<Capture/Compare 1 Overcapture Flag */
#define TIM_SR_CC2OF_Pos                    (10UL)
#define TIM_SR_CC2OF_Msk                    (0x1UL << TIM_SR_CC2OF_Pos)             /*!< 0x00000400 */
#define TIM_SR_CC2OF                        TIM_SR_CC2OF_Msk                        /*!<Capture/Compare 2 Overcapture Flag */
#define TIM_SR_CC3OF_Pos                    (11UL)
#define TIM_SR_CC3OF_Msk                    (0x1UL << TIM_SR_CC3OF_Pos)             /*!< 0x00000800 */
#define TIM_SR_CC3OF                        TIM_SR_CC3OF_Msk                        /*!<Capture/Compare 3 Overcapture Flag */
#define TIM_SR_CC4OF_Pos                    (12UL)
#define TIM_SR_CC4OF_Msk                    (0x1UL << TIM_SR_CC4OF_Pos)             /*!< 0x00001000 */
#define TIM_SR_CC4OF                        TIM_SR_CC4OF_Msk                        /*!<Capture/Compare 4 Overcapture Flag */
#define TIM_SR_SBIF_Pos                     (13UL)
#define TIM_SR_SBIF_Msk                     (0x1UL << TIM_SR_SBIF_Pos)              /*!< 0x00002000 */
#define TIM_SR_SBIF                         TIM_SR_SBIF_Msk                         /*!<System Break interrupt Flag */
#define TIM_SR_CC5IF_Pos                    (16UL)
#define TIM_SR_CC5IF_Msk                    (0x1UL << TIM_SR_CC5IF_Pos)             /*!< 0x00010000 */
#define TIM_SR_CC5IF                        TIM_SR_CC5IF_Msk                        /*!<Capture/Compare 5 interrupt Flag */
#define TIM_SR_CC6IF_Pos                    (17UL)
#define TIM_SR_CC6IF_Msk                    (0x1UL << TIM_SR_CC6IF_Pos)             /*!< 0x00020000 */
#define TIM_SR_CC6IF                        TIM_SR_CC6IF_Msk                        /*!<Capture/Compare 6 interrupt Flag */
#define TIM_SR_IDXF_Pos                     (20UL)
#define TIM_SR_IDXF_Msk                     (0x1UL << TIM_SR_IDXF_Pos)              /*!< 0x00100000 */
#define TIM_SR_IDXF                         TIM_SR_IDXF_Msk                         /*!<Encoder index interrupt flag */
#define TIM_SR_DIRF_Pos                     (21UL)
#define TIM_SR_DIRF_Msk                     (0x1UL << TIM_SR_DIRF_Pos)              /*!< 0x00200000 */
#define TIM_SR_DIRF                         TIM_SR_DIRF_Msk                         /*!<Encoder direction change interrupt flag */
#define TIM_SR_IERRF_Pos                    (22UL)
#define TIM_SR_IERRF_Msk                    (0x1UL << TIM_SR_IERRF_Pos)             /*!< 0x00400000 */
#define TIM_SR_IERRF                        TIM_SR_IERRF_Msk                        /*!<Encoder index error flag */
#define TIM_SR_TERRF_Pos                    (23UL)
#define TIM_SR_TERRF_Msk                    (0x1UL << TIM_SR_TERRF_Pos)             /*!< 0x00800000 */
#define TIM_SR_TERRF                        TIM_SR_TERRF_Msk                        /*!<Encoder transition error flag */

/*******************  Bit definition for TIM_EGR register  ********************/
#define TIM_EGR_UG_Pos                      (0UL)
#define TIM_EGR_UG_Msk                      (0x1UL << TIM_EGR_UG_Pos)               /*!< 0x00000001 */
#define TIM_EGR_UG                          TIM_EGR_UG_Msk                          /*!<Update Generation */
#define TIM_EGR_CC1G_Pos                    (1UL)
#define TIM_EGR_CC1G_Msk                    (0x1UL << TIM_EGR_CC1G_Pos)             /*!< 0x00000002 */
#define TIM_EGR_CC1G                        TIM_EGR_CC1G_Msk                        /*!<Capture/Compare 1 Generation */
#define TIM_EGR_CC2G_Pos                    (2UL)
#define TIM_EGR_CC2G_Msk                    (0x1UL << TIM_EGR_CC2G_Pos)             /*!< 0x00000004 */
#define TIM_EGR_CC2G                        TIM_EGR_CC2G_Msk                        /*!<Capture/Compare 2 Generation */
#define TIM_EGR_CC3G_Pos                    (3UL)
#define TIM_EGR_CC3G_Msk                    (0x1UL << TIM_EGR_CC3G_Pos)             /*!< 0x00000008 */
#define TIM_EGR_CC3G                        TIM_EGR_CC3G_Msk                        /*!<Capture/Compare 3 Generation */
#define TIM_EGR_CC4G_Pos                    (4UL)
#define TIM_EGR_CC4G_Msk                    (0x1UL << TIM_EGR_CC4G_Pos)             /*!< 0x00000010 */
#define TIM_EGR_CC4G                        TIM_EGR_CC4G_Msk                        /*!<Capture/Compare 4 Generation */
#define TIM_EGR_COMG_Pos                    (5UL)
#define TIM_EGR_COMG_Msk                    (0x1UL << TIM_EGR_COMG_Pos)             /*!< 0x00000020 */
#define TIM_EGR_COMG                        TIM_EGR_COMG_Msk                        /*!<Capture/Compare Control Update Generation */
#define TIM_EGR_TG_Pos                      (6UL)
#define TIM_EGR_TG_Msk                      (0x1UL << TIM_EGR_TG_Pos)               /*!< 0x00000040 */
#define TIM_EGR_TG                          TIM_EGR_TG_Msk                          /*!<Trigger Generation */
#define TIM_EGR_BG_Pos                      (7UL)
#define TIM_EGR_BG_Msk                      (0x1UL << TIM_EGR_BG_Pos)               /*!< 0x00000080 */
#define TIM_EGR_BG                          TIM_EGR_BG_Msk                          /*!<Break Generation */
#define TIM_EGR_B2G_Pos                     (8UL)
#define TIM_EGR_B2G_Msk                     (0x1UL << TIM_EGR_B2G_Pos)              /*!< 0x00000100 */
#define TIM_EGR_B2G                         TIM_EGR_B2G_Msk                         /*!<Break 2 Generation */

/******************  Bit definition for TIM_CCMR1 register  *******************/
#define TIM_CCMR1_CC1S_Pos                  (0UL)
#define TIM_CCMR1_CC1S_Msk                  (0x3UL << TIM_CCMR1_CC1S_Pos)           /*!< 0x00000003 */
#define TIM_CCMR1_CC1S                      TIM_CCMR1_CC1S_Msk                      /*!<CC1S[1:0] bits (Capture/Compare 1 Selection) */
#define TIM_CCMR1_CC1S_0                    (0x1UL << TIM_CCMR1_CC1S_Pos)           /*!< 0x00000001 */
#define TIM_CCMR1_CC1S_1                    (0x2UL << TIM_CCMR1_CC1S_Pos)           /*!< 0x00000002 */
#define TIM_CCMR1_OC1FE_Pos                 (2UL)
#define TIM_CCMR1_OC1FE_Msk                 (0x1UL << TIM_CCMR1_OC1FE_Pos)          /*!< 0x00000004 */
#define TIM_CCMR1_OC1FE                     TIM_CCMR1_OC1FE_Msk                     /*!<Output Compare 1 Fast enable */
#define TIM_CCMR1_OC1PE_Pos                 (3UL)
#define TIM_CCMR1_OC1PE_Msk                 (0x1UL << TIM_CCMR1_OC1PE_Pos)          /*!< 0x00000008 */
#define TIM_CCMR1_OC1PE                     TIM_CCMR1_OC1PE_Msk                     /*!<Output Compare 1 Preload enable */
#define TIM_CCMR1_OC1M_Pos                  (4UL)
#define TIM_CCMR1_OC1M_Msk                  (0x1007UL << TIM_CCMR1_OC1M_Pos)        /*!< 0x00010070 */
#define TIM_CCMR1_OC1M                      TIM_CCMR1_OC1M_Msk                      /*!<OC1M[2:0] bits (Output Compare 1 Mode) */
#define TIM_CCMR1_OC1M_0                    (0x0001UL << TIM_CCMR1_OC1M_Pos)        /*!< 0x00000010 */
#define TIM_CCMR1_OC1M_1                    (0x0002UL << TIM_CCMR1_OC1M_Pos)        /*!< 0x00000020 */
#define TIM_CCMR1_OC1M_2                    (0x0004UL << TIM_CCMR1_OC1M_Pos)        /*!< 0x00000040 */
#define TIM_CCMR1_OC1M_3                    (0x1000UL << TIM_CCMR1_OC1M_Pos)        /*!< 0x00010000 */
#define TIM_CCMR1_OC1CE_Pos                 (7UL)
#define TIM_CCMR1_OC1CE_Msk                 (0x1UL << TIM_CCMR1_OC1CE_Pos)          /*!< 0x00000080 */
#define TIM_CCMR1_OC1CE                     TIM_CCMR1_OC1CE_Msk                     /*!<Output Compare 1 Clear Enable */
#define TIM_CCMR1_CC2S_Pos                  (8UL)
#define TIM_CCMR1_CC2S_Msk                  (0x3UL << TIM_CCMR1_CC2S_Pos)           /*!< 0x00000300 */
#define TIM_CCMR1_CC2S                      TIM_CCMR1_CC2S_Msk                      /*!<CC2S[1:0] bits (Capture/Compare 2 Selection) */
#define TIM_CCMR1_CC2S_0                    (0x1UL << TIM_CCMR1_CC2S_Pos)           /*!< 0x00000100 */
#define TIM_CCMR1_CC2S_1                    (0x2UL << TIM_CCMR1_CC2S_Pos)           /*!< 0x00000200 */
#define TIM_CCMR1_OC2FE_Pos                 (10UL)
#define TIM_CCMR1_OC2FE_Msk                 (0x1UL << TIM_CCMR1_OC2FE_Pos)          /*!< 0x00000400 */
#define TIM_CCMR1_OC2FE                     TIM_CCMR1_OC2FE_Msk                     /*!<Output Compare 2 Fast enable */
#define TIM_CCMR1_OC2PE_Pos                 (11UL)
#define TIM_CCMR1_OC2PE_Msk                 (0x1UL << TIM_CCMR1_OC2PE_Pos)          /*!< 0x00000800 */
#define TIM_CCMR1_OC2PE                     TIM_CCMR1_OC2PE_Msk                     /*!<Output Compare 2 Preload enable */
#define TIM_CCMR1_OC2M_Pos                  (12UL)
#define TIM_CCMR1_OC2M_Msk                  (0x1007UL << TIM_CCMR1_OC2M_Pos)        /*!< 0x01007000 */
#define TIM_CCMR1_OC2M                      TIM_CCMR1_OC2M_Msk                      /*!<OC2M[2:0] bits (Output Compare 2 Mode) */
#define TIM_CCMR1_OC2M_0                    (0x0001UL << TIM_CCMR1_OC2M_Pos)        /*!< 0x00001000 */
#define TIM_CCMR1_OC2M_1                    (0x0002UL << TIM_CCMR1_OC2M_Pos)        /*!< 0x00002000 */
#define TIM_CCMR1_OC2M_2                    (0x0004UL << TIM_CCMR1_OC2M_Pos)        /*!< 0x00004000 */
#define TIM_CCMR1_OC2M_3                    (0x1000UL << TIM_CCMR1_OC2M_Pos)        /*!< 0x01000000 */
#define TIM_CCMR1_OC2CE_Pos                 (15UL)
#define TIM_CCMR1_OC2CE_Msk                 (0x1UL << TIM_CCMR1_OC2CE_Pos)          /*!< 0x00008000 */
#define TIM_CCMR1_OC2CE                     TIM_CCMR1_OC2CE_Msk                     /*!<Output Compare 2 Clear Enable */

/*----------------------------------------------------------------------------*/
#define TIM_CCMR1_IC1PSC_Pos                (2UL)
#define TIM_CCMR1_IC1PSC_Msk                (0x3UL << TIM_CCMR1_IC1PSC_Pos)         /*!< 0x0000000C */
#define TIM_CCMR1_IC1PSC                    TIM_CCMR1_IC1PSC_Msk                    /*!<IC1PSC[1:0] bits (Input Capture 1 Prescaler) */
#define TIM_CCMR1_IC1PSC_0                  (0x1UL << TIM_CCMR1_IC1PSC_Pos)         /*!< 0x00000004 */
#define TIM_CCMR1_IC1PSC_1                  (0x2UL << TIM_CCMR1_IC1PSC_Pos)         /*!< 0x00000008 */
#define TIM_CCMR1_IC1F_Pos                  (4UL)
#define TIM_CCMR1_IC1F_Msk                  (0xFUL << TIM_CCMR1_IC1F_Pos)           /*!< 0x000000F0 */
#define TIM_CCMR1_IC1F                      TIM_CCMR1_IC1F_Msk                      /*!<IC1F[3:0] bits (Input Capture 1 Filter) */
#define TIM_CCMR1_IC1F_0                    (0x1UL << TIM_CCMR1_IC1F_Pos)           /*!< 0x00000010 */
#define TIM_CCMR1_IC1F_1                    (0x2UL << TIM_CCMR1_IC1F_Pos)           /*!< 0x00000020 */
#define TIM_CCMR1_IC1F_2                    (0x4UL << TIM_CCMR1_IC1F_Pos)           /*!< 0x00000040 */
#define TIM_CCMR1_IC1F_3                    (0x8UL << TIM_CCMR1_IC1F_Pos)           /*!< 0x00000080 */
#define TIM_CCMR1_IC2PSC_Pos                (10UL)
#define TIM_CCMR1_IC2PSC_Msk                (0x3UL << TIM_CCMR1_IC2PSC_Pos)         /*!< 0x00000C00 */
#define TIM_CCMR1_IC2PSC                    TIM_CCMR1_IC2PSC_Msk                    /*!<IC2PSC[1:0] bits (Input Capture 2 Prescaler) */
#define TIM_CCMR1_IC2PSC_0                  (0x1UL << TIM_CCMR1_IC2PSC_Pos)         /*!< 0x00000400 */
#define TIM_CCMR1_IC2PSC_1                  (0x2UL << TIM_CCMR1_IC2PSC_Pos)         /*!< 0x00000800 */
#define TIM_CCMR1_IC2F_Pos                  (12UL)
#define TIM_CCMR1_IC2F_Msk                  (0xFUL << TIM_CCMR1_IC2F_Pos)           /*!< 0x0000F000 */
#define TIM_CCMR1_IC2F                      TIM_CCMR1_IC2F_Msk                      /*!<IC2F[3:0] bits (Input Capture 2 Filter) */
#define TIM_CCMR1_IC2F_0                    (0x1UL << TIM_CCMR1_IC2F_Pos)           /*!< 0x00001000 */
#define TIM_CCMR1_IC2F_1                    (0x2UL << TIM_CCMR1_IC2F_Pos)           /*!< 0x00002000 */
#define TIM_CCMR1_IC2F_2                    (0x4UL << TIM_CCMR1_IC2F_Pos)           /*!< 0x00004000 */
#define TIM_CCMR1_IC2F_3                    (0x8UL << TIM_CCMR1_IC2F_Pos)           /*!< 0x00008000 */

/******************  Bit definition for TIM_CCMR2 register  *******************/
#define TIM_CCMR2_CC3S_Pos                  (0UL)
#define TIM_CCMR2_CC3S_Msk                  (0x3UL << TIM_CCMR2_CC3S_Pos)           /*!< 0x00000003 */
#define TIM_CCMR2_CC3S                      TIM_CCMR2_CC3S_Msk                      /*!<CC3S[1:0] bits (Capture/Compare 3 Selection) */
#define TIM_CCMR2_CC3S_0                    (0x1UL << TIM_CCMR2_CC3S_Pos)           /*!< 0x00000001 */
#define TIM_CCMR2_CC3S_1                    (0x2UL << TIM_CCMR2_CC3S_Pos)           /*!< 0x00000002 */
#define TIM_CCMR2_OC3FE_Pos                 (2UL)
#define TIM_CCMR2_OC3FE_Msk                 (0x1UL << TIM_CCMR2_OC3FE_Pos)          /*!< 0x00000004 */
#define TIM_CCMR2_OC3FE                     TIM_CCMR2_OC3FE_Msk                     /*!<Output Compare 3 Fast enable */
#define TIM_CCMR2_OC3PE_Pos                 (3UL)
#define TIM_CCMR2_OC3PE_Msk                 (0x1UL << TIM_CCMR2_OC3PE_Pos)          /*!< 0x00000008 */
#define TIM_CCMR2_OC3PE                     TIM_CCMR2_OC3PE_Msk                     /*!<Output Compare 3 Preload enable */
#define TIM_CCMR2_OC3M_Pos                  (4UL)
#define TIM_CCMR2_OC3M_Msk                  (0x1007UL << TIM_CCMR2_OC3M_Pos)        /*!< 0x00010070 */
#define TIM_CCMR2_OC3M                      TIM_CCMR2_OC3M_Msk                      /*!<OC3M[2:0] bits (Output Compare 3 Mode) */
#define TIM_CCMR2_OC3M_0                    (0x0001UL << TIM_CCMR2_OC3M_Pos)        /*!< 0x00000010 */
#define TIM_CCMR2_OC3M_1                    (0x0002UL << TIM_CCMR2_OC3M_Pos)        /*!< 0x00000020 */
#define TIM_CCMR2_OC3M_2                    (0x0004UL << TIM_CCMR2_OC3M_Pos)        /*!< 0x00000040 */
#define TIM_CCMR2_OC3M_3                    (0x1000UL << TIM_CCMR2_OC3M_Pos)        /*!< 0x00010000 */
#define TIM_CCMR2_OC3CE_Pos                 (7UL)
#define TIM_CCMR2_OC3CE_Msk                 (0x1UL << TIM_CCMR2_OC3CE_Pos)          /*!< 0x00000080 */
#define TIM_CCMR2_OC3CE                     TIM_CCMR2_OC3CE_Msk                     /*!<Output Compare 3 Clear Enable */
#define TIM_CCMR2_CC4S_Pos                  (8UL)
#define TIM_CCMR2_CC4S_Msk                  (0x3UL << TIM_CCMR2_CC4S_Pos)           /*!< 0x00000300 */
#define TIM_CCMR2_CC4S                      TIM_CCMR2_CC4S_Msk                      /*!<CC4S[1:0] bits (Capture/Compare 4 Selection) */
#define TIM_CCMR2_CC4S_0                    (0x1UL << TIM_CCMR2_CC4S_Pos)           /*!< 0x00000100 */
#define TIM_CCMR2_CC4S_1                    (0x2UL << TIM_CCMR2_CC4S_Pos)           /*!< 0x00000200 */
#define TIM_CCMR2_OC4FE_Pos                 (10UL)
#define TIM_CCMR2_OC4FE_Msk                 (0x1UL << TIM_CCMR2_OC4FE_Pos)          /*!< 0x00000400 */
#define TIM_CCMR2_OC4FE                     TIM_CCMR2_OC4FE_Msk                     /*!<Output Compare 4 Fast enable */
#define TIM_CCMR2_OC4PE_Pos                 (11UL)
#define TIM_CCMR2_OC4PE_Msk                 (0x1UL << TIM_CCMR2_OC4PE_Pos)          /*!< 0x00000800 */
#define TIM_CCMR2_OC4PE                     TIM_CCMR2_OC4PE_Msk                     /*!<Output Compare 4 Preload enable */
#define TIM_CCMR2_OC4M_Pos                  (12UL)
#define TIM_CCMR2_OC4M_Msk                  (0x1007UL << TIM_CCMR2_OC4M_Pos)        /*!< 0x01007000 */
#define TIM_CCMR2_OC4M                      TIM_CCMR2_OC4M_Msk                      /*!<OC4M[2:0] bits (Output Compare 4 Mode) */
#define TIM_CCMR2_OC4M_0                    (0x0001UL << TIM_CCMR2_OC4M_Pos)        /*!< 0x00001000 */
#define TIM_CCMR2_OC4M_1                    (0x0002UL << TIM_CCMR2_OC4M_Pos)        /*!< 0x00002000 */
#define TIM_CCMR2_OC4M_2                    (0x0004UL << TIM_CCMR2_OC4M_Pos)        /*!< 0x00004000 */
#define TIM_CCMR2_OC4M_3                    (0x1000UL << TIM_CCMR2_OC4M_Pos)        /*!< 0x01000000 */
#define TIM_CCMR2_OC4CE_Pos                 (15UL)
#define TIM_CCMR2_OC4CE_Msk                 (0x1UL << TIM_CCMR2_OC4CE_Pos)          /*!< 0x00008000 */
#define TIM_CCMR2_OC4CE                     TIM_CCMR2_OC4CE_Msk                     /*!<Output Compare 4 Clear Enable */

/*----------------------------------------------------------------------------*/
#define TIM_CCMR2_IC3PSC_Pos                (2UL)
#define TIM_CCMR2_IC3PSC_Msk                (0x3UL << TIM_CCMR2_IC3PSC_Pos)         /*!< 0x0000000C */
#define TIM_CCMR2_IC3PSC                    TIM_CCMR2_IC3PSC_Msk                    /*!<IC3PSC[1:0] bits (Input Capture 3 Prescaler) */
#define TIM_CCMR2_IC3PSC_0                  (0x1UL << TIM_CCMR2_IC3PSC_Pos)         /*!< 0x00000004 */
#define TIM_CCMR2_IC3PSC_1                  (0x2UL << TIM_CCMR2_IC3PSC_Pos)         /*!< 0x00000008 */
#define TIM_CCMR2_IC3F_Pos                  (4UL)
#define TIM_CCMR2_IC3F_Msk                  (0xFUL << TIM_CCMR2_IC3F_Pos)           /*!< 0x000000F0 */
#define TIM_CCMR2_IC3F                      TIM_CCMR2_IC3F_Msk                      /*!<IC3F[3:0] bits (Input Capture 3 Filter) */
#define TIM_CCMR2_IC3F_0                    (0x1UL << TIM_CCMR2_IC3F_Pos)           /*!< 0x00000010 */
#define TIM_CCMR2_IC3F_1                    (0x2UL << TIM_CCMR2_IC3F_Pos)           /*!< 0x00000020 */
#define TIM_CCMR2_IC3F_2                    (0x4UL << TIM_CCMR2_IC3F_Pos)           /*!< 0x00000040 */
#define TIM_CCMR2_IC3F_3                    (0x8UL << TIM_CCMR2_IC3F_Pos)           /*!< 0x00000080 */
#define TIM_CCMR2_IC4PSC_Pos                (10UL)
#define TIM_CCMR2_IC4PSC_Msk                (0x3UL << TIM_CCMR2_IC4PSC_Pos)         /*!< 0x00000C00 */
#define TIM_CCMR2_IC4PSC                    TIM_CCMR2_IC4PSC_Msk                    /*!<IC4PSC[1:0] bits (Input Capture 4 Prescaler) */
#define TIM_CCMR2_IC4PSC_0                  (0x1UL << TIM_CCMR2_IC4PSC_Pos)         /*!< 0x00000400 */
#define TIM_CCMR2_IC4PSC_1                  (0x2UL << TIM_CCMR2_IC4PSC_Pos)         /*!< 0x00000800 */
#define TIM_CCMR2_IC4F_Pos                  (12UL)
#define TIM_CCMR2_IC4F_Msk                  (0xFUL << TIM_CCMR2_IC4F_Pos)           /*!< 0x0000F000 */
#define TIM_CCMR2_IC4F                      TIM_CCMR2_IC4F_Msk                      /*!<IC4F[3:0] bits (Input Capture 4 Filter) */
#define TIM_CCMR2_IC4F_0                    (0x1UL << TIM_CCMR2_IC4F_Pos)           /*!< 0x00001000 */
#define TIM_CCMR2_IC4F_1                    (0x2UL << TIM_CCMR2_IC4F_Pos)           /*!< 0x00002000 */
#define TIM_CCMR2_IC4F_2                    (0x4UL << TIM_CCMR2_IC4F_Pos)           /*!< 0x00004000 */
#define TIM_CCMR2_IC4F_3                    (0x8UL << TIM_CCMR2_IC4F_Pos)           /*!< 0x00008000 */

/******************  Bit definition for TIM_CCMR3 register  *******************/
#define TIM_CCMR3_OC5FE_Pos                 (2UL)
#define TIM_CCMR3_OC5FE_Msk                 (0x1UL << TIM_CCMR3_OC5FE_Pos)          /*!< 0x00000004 */
#define TIM_CCMR3_OC5FE                     TIM_CCMR3_OC5FE_Msk                     /*!<Output Compare 5 Fast enable */
#define TIM_CCMR3_OC5PE_Pos                 (3UL)
#define TIM_CCMR3_OC5PE_Msk                 (0x1UL << TIM_CCMR3_OC5PE_Pos)          /*!< 0x00000008 */
#define TIM_CCMR3_OC5PE                     TIM_CCMR3_OC5PE_Msk                     /*!<Output Compare 5 Preload enable */
#define TIM_CCMR3_OC5M_Pos                  (4UL)
#define TIM_CCMR3_OC5M_Msk                  (0x1007UL << TIM_CCMR3_OC5M_Pos)        /*!< 0x00010070 */
#define TIM_CCMR3_OC5M                      TIM_CCMR3_OC5M_Msk                      /*!<OC5M[3:0] bits (Output Compare 5 Mode) */
#define TIM_CCMR3_OC5M_0                    (0x0001UL << TIM_CCMR3_OC5M_Pos)        /*!< 0x00000010 */
#define TIM_CCMR3_OC5M_1                    (0x0002UL << TIM_CCMR3_OC5M_Pos)        /*!< 0x00000020 */
#define TIM_CCMR3_OC5M_2                    (0x0004UL << TIM_CCMR3_OC5M_Pos)        /*!< 0x00000040 */
#define TIM_CCMR3_OC5M_3                    (0x1000UL << TIM_CCMR3_OC5M_Pos)        /*!< 0x00010000 */
#define TIM_CCMR3_OC5CE_Pos                 (7UL)
#define TIM_CCMR3_OC5CE_Msk                 (0x1UL << TIM_CCMR3_OC5CE_Pos)          /*!< 0x00000080 */
#define TIM_CCMR3_OC5CE                     TIM_CCMR3_OC5CE_Msk                     /*!<Output Compare 5 Clear Enable */
#define TIM_CCMR3_OC6FE_Pos                 (10UL)
#define TIM_CCMR3_OC6FE_Msk                 (0x1UL << TIM_CCMR3_OC6FE_Pos)          /*!< 0x00000400 */
#define TIM_CCMR3_OC6FE                     TIM_CCMR3_OC6FE_Msk                     /*!<Output Compare 6 Fast enable */
#define TIM_CCMR3_OC6PE_Pos                 (11UL)
#define TIM_CCMR3_OC6PE_Msk                 (0x1UL << TIM_CCMR3_OC6PE_Pos)          /*!< 0x00000800 */
#define TIM_CCMR3_OC6PE                     TIM_CCMR3_OC6PE_Msk                     /*!<Output Compare 6 Preload enable */
#define TIM_CCMR3_OC6M_Pos                  (12UL)
#define TIM_CCMR3_OC6M_Msk                  (0x1007UL << TIM_CCMR3_OC6M_Pos)        /*!< 0x01007000 */
#define TIM_CCMR3_OC6M                      TIM_CCMR3_OC6M_Msk                      /*!<OC6M[3:0] bits (Output Compare 6 Mode) */
#define TIM_CCMR3_OC6M_0                    (0x0001UL << TIM_CCMR3_OC6M_Pos)        /*!< 0x00001000 */
#define TIM_CCMR3_OC6M_1                    (0x0002UL << TIM_CCMR3_OC6M_Pos)        /*!< 0x00002000 */
#define TIM_CCMR3_OC6M_2                    (0x0004UL << TIM_CCMR3_OC6M_Pos)        /*!< 0x00004000 */
#define TIM_CCMR3_OC6M_3                    (0x1000UL << TIM_CCMR3_OC6M_Pos)        /*!< 0x01000000 */
#define TIM_CCMR3_OC6CE_Pos                 (15UL)
#define TIM_CCMR3_OC6CE_Msk                 (0x1UL << TIM_CCMR3_OC6CE_Pos)          /*!< 0x00008000 */
#define TIM_CCMR3_OC6CE                     TIM_CCMR3_OC6CE_Msk                     /*!<Output Compare 6 Clear Enable */

/*******************  Bit definition for TIM_CCER register  *******************/
#define TIM_CCER_CC1E_Pos                   (0UL)
#define TIM_CCER_CC1E_Msk                   (0x1UL << TIM_CCER_CC1E_Pos)            /*!< 0x00000001 */
#define TIM_CCER_CC1E                       TIM_CCER_CC1E_Msk                       /*!<Capture/Compare 1 output enable */
#define TIM_CCER_CC1P_Pos                   (1UL)
#define TIM_CCER_CC1P_Msk                   (0x1UL << TIM_CCER_CC1P_Pos)            /*!< 0x00000002 */
#define TIM_CCER_CC1P                       TIM_CCER_CC1P_Msk                       /*!<Capture/Compare 1 output Polarity */
#define TIM_CCER_CC1NE_Pos                  (2UL)
#define TIM_CCER_CC1NE_Msk                  (0x1UL << TIM_CCER_CC1NE_Pos)           /*!< 0x00000004 */
#define TIM_CCER_CC1NE                      TIM_CCER_CC1NE_Msk                      /*!<Capture/Compare 1 Complementary output enable */
#define TIM_CCER_CC1NP_Pos                  (3UL)
#define TIM_CCER_CC1NP_Msk                  (0x1UL << TIM_CCER_CC1NP_Pos)           /*!< 0x00000008 */
#define TIM_CCER_CC1NP                      TIM_CCER_CC1NP_Msk                      /*!<Capture/Compare 1 Complementary output Polarity */
#define TIM_CCER_CC2E_Pos                   (4UL)
#define TIM_CCER_CC2E_Msk                   (0x1UL << TIM_CCER_CC2E_Pos)            /*!< 0x00000010 */
#define TIM_CCER_CC2E                       TIM_CCER_CC2E_Msk                       /*!<Capture/Compare 2 output enable */
#define TIM_CCER_CC2P_Pos                   (5UL)
#define TIM_CCER_CC2P_Msk                   (0x1UL << TIM_CCER_CC2P_Pos)            /*!< 0x00000020 */
#define TIM_CCER_CC2P                       TIM_CCER_CC2P_Msk                       /*!<Capture/Compare 2 output Polarity */
#define TIM_CCER_CC2NE_Pos                  (6UL)
#define TIM_CCER_CC2NE_Msk                  (0x1UL << TIM_CCER_CC2NE_Pos)           /*!< 0x00000040 */
#define TIM_CCER_CC2NE                      TIM_CCER_CC2NE_Msk                      /*!<Capture/Compare 2 Complementary output enable */
#define TIM_CCER_CC2NP_Pos                  (7UL)
#define TIM_CCER_CC2NP_Msk                  (0x1UL << TIM_CCER_CC2NP_Pos)           /*!< 0x00000080 */
#define TIM_CCER_CC2NP                      TIM_CCER_CC2NP_Msk                      /*!<Capture/Compare 2 Complementary output Polarity */
#define TIM_CCER_CC3E_Pos                   (8UL)
#define TIM_CCER_CC3E_Msk                   (0x1UL << TIM_CCER_CC3E_Pos)            /*!< 0x00000100 */
#define TIM_CCER_CC3E                       TIM_CCER_CC3E_Msk                       /*!<Capture/Compare 3 output enable */
#define TIM_CCER_CC3P_Pos                   (9UL)
#define TIM_CCER_CC3P_Msk                   (0x1UL << TIM_CCER_CC3P_Pos)            /*!< 0x00000200 */
#define TIM_CCER_CC3P                       TIM_CCER_CC3P_Msk                       /*!<Capture/Compare 3 output Polarity */
#define TIM_CCER_CC3NE_Pos                  (10UL)
#define TIM_CCER_CC3NE_Msk                  (0x1UL << TIM_CCER_CC3NE_Pos)           /*!< 0x00000400 */
#define TIM_CCER_CC3NE                      TIM_CCER_CC3NE_Msk                      /*!<Capture/Compare 3 Complementary output enable */
#define TIM_CCER_CC3NP_Pos                  (11UL)
#define TIM_CCER_CC3NP_Msk                  (0x1UL << TIM_CCER_CC3NP_Pos)           /*!< 0x00000800 */
#define TIM_CCER_CC3NP                      TIM_CCER_CC3NP_Msk                      /*!<Capture/Compare 3 Complementary output Polarity */
#define TIM_CCER_CC4E_Pos                   (12UL)
#define TIM_CCER_CC4E_Msk                   (0x1UL << TIM_CCER_CC4E_Pos)            /*!< 0x00001000 */
#define TIM_CCER_CC4E                       TIM_CCER_CC4E_Msk                       /*!<Capture/Compare 4 output enable */
#define TIM_CCER_CC4P_Pos                   (13UL)
#define TIM_CCER_CC4P_Msk                   (0x1UL << TIM_CCER_CC4P_Pos)            /*!< 0x00002000 */
#define TIM_CCER_CC4P                       TIM_CCER_CC4P_Msk                       /*!<Capture/Compare 4 output Polarity */
#define TIM_CCER_CC4NE_Pos                  (14UL)
#define TIM_CCER_CC4NE_Msk                  (0x1UL << TIM_CCER_CC4NE_Pos)           /*!< 0x00004000 */
#define TIM_CCER_CC4NE                      TIM_CCER_CC4NE_Msk                      /*!<Capture/Compare 4 Complementary output enable */
#define TIM_CCER_CC4NP_Pos                  (15UL)
#define TIM_CCER_CC4NP_Msk                  (0x1UL << TIM_CCER_CC4NP_Pos)           /*!< 0x00008000 */
#define TIM_CCER_CC4NP                      TIM_CCER_CC4NP_Msk                      /*!<Capture/Compare 4 Complementary output Polarity */
#define TIM_CCER_CC5E_Pos                   (16UL)
#define TIM_CCER_CC5E_Msk                   (0x1UL << TIM_CCER_CC5E_Pos)            /*!< 0x00010000 */
#define TIM_CCER_CC5E                       TIM_CCER_CC5E_Msk                       /*!<Capture/Compare 5 output enable */
#define TIM_CCER_CC5P_Pos                   (17UL)
#define TIM_CCER_CC5P_Msk                   (0x1UL << TIM_CCER_CC5P_Pos)            /*!< 0x00020000 */
#define TIM_CCER_CC5P                       TIM_CCER_CC5P_Msk                       /*!<Capture/Compare 5 output Polarity */
#define TIM_CCER_CC6E_Pos                   (20UL)
#define TIM_CCER_CC6E_Msk                   (0x1UL << TIM_CCER_CC6E_Pos)            /*!< 0x00100000 */
#define TIM_CCER_CC6E                       TIM_CCER_CC6E_Msk                       /*!<Capture/Compare 6 output enable */
#define TIM_CCER_CC6P_Pos                   (21UL)
#define TIM_CCER_CC6P_Msk                   (0x1UL << TIM_CCER_CC6P_Pos)            /*!< 0x00200000 */
#define TIM_CCER_CC6P                       TIM_CCER_CC6P_Msk                       /*!<Capture/Compare 6 output Polarity */

/*******************  Bit definition for TIM_CNT register  ********************/
#define TIM_CNT_CNT_Pos                     (0UL)
#define TIM_CNT_CNT_Msk                     (0xFFFFFFFFUL << TIM_CNT_CNT_Pos)       /*!< 0xFFFFFFFF */
#define TIM_CNT_CNT                         TIM_CNT_CNT_Msk                         /*!<Counter Value */
#define TIM_CNT_UIFCPY_Pos                  (31UL)
#define TIM_CNT_UIFCPY_Msk                  (0x1UL << TIM_CNT_UIFCPY_Pos)           /*!< 0x80000000 */
#define TIM_CNT_UIFCPY                      TIM_CNT_UIFCPY_Msk                      /*!<Update interrupt flag copy (if UIFREMAP=1) */

/*******************  Bit definition for TIM_PSC register  ********************/
#define TIM_PSC_PSC_Pos                     (0UL)
#define TIM_PSC_PSC_Msk                     (0xFFFFUL << TIM_PSC_PSC_Pos)           /*!< 0x0000FFFF */
#define TIM_PSC_PSC                         TIM_PSC_PSC_Msk                         /*!<Prescaler Value */

/*******************  Bit definition for TIM_ARR register  ********************/
#define TIM_ARR_ARR_Pos                     (0UL)
#define TIM_ARR_ARR_Msk                     (0xFFFFFFFFUL << TIM_ARR_ARR_Pos)       /*!< 0xFFFFFFFF */
#define TIM_ARR_ARR                         TIM_ARR_ARR_Msk                         /*!<Actual auto-reload Value */

/*******************  Bit definition for TIM_RCR register  ********************/
#define TIM_RCR_REP_Pos                     (0UL)
#define TIM_RCR_REP_Msk                     (0xFFFFUL << TIM_RCR_REP_Pos)           /*!< 0x0000FFFF */
#define TIM_RCR_REP                         TIM_RCR_REP_Msk                         /*!<Repetition Counter Value */

/*******************  Bit definition for TIM_CCR1 register  *******************/
#define TIM_CCR1_CCR1_Pos                   (0UL)
#define TIM_CCR1_CCR1_Msk                   (0xFFFFUL << TIM_CCR1_CCR1_Pos)         /*!< 0x0000FFFF */
#define TIM_CCR1_CCR1                       TIM_CCR1_CCR1_Msk                       /*!<Capture/Compare 1 Value */

/*******************  Bit definition for TIM_CCR2 register  *******************/
#define TIM_CCR2_CCR2_Pos                   (0UL)
#define TIM_CCR2_CCR2_Msk                   (0xFFFFUL << TIM_CCR2_CCR2_Pos)         /*!< 0x0000FFFF */
#define TIM_CCR2_CCR2                       TIM_CCR2_CCR2_Msk                       /*!<Capture/Compare 2 Value */

/*******************  Bit definition for TIM_CCR3 register  *******************/
#define TIM_CCR3_CCR3_Pos                   (0UL)
#define TIM_CCR3_CCR3_Msk                   (0xFFFFUL << TIM_CCR3_CCR3_Pos)         /*!< 0x0000FFFF */
#define TIM_CCR3_CCR3                       TIM_CCR3_CCR3_Msk                       /*!<Capture/Compare 3 Value */

/*******************  Bit definition for TIM_CCR4 register  *******************/
#define TIM_CCR4_CCR4_Pos                   (0UL)
#define TIM_CCR4_CCR4_Msk                   (0xFFFFUL << TIM_CCR4_CCR4_Pos)         /*!< 0x0000FFFF */
#define TIM_CCR4_CCR4                       TIM_CCR4_CCR4_Msk                       /*!<Capture/Compare 4 Value */

/*******************  Bit definition for TIM_CCR5 register  *******************/
#define TIM_CCR5_CCR5_Pos                   (0UL)
#define TIM_CCR5_CCR5_Msk                   (0xFFFFUL << TIM_CCR5_CCR5_Pos)         /*!< 0xFFFF */
#define TIM_CCR5_CCR5                       TIM_CCR5_CCR5_Msk                       /*!<Capture/Compare 5 Value */
#define TIM_CCR5_GC5C1_Pos                  (29UL)
#define TIM_CCR5_GC5C1_Msk                  (0x1UL << TIM_CCR5_GC5C1_Pos)           /*!< 0x20000000 */
#define TIM_CCR5_GC5C1                      TIM_CCR5_GC5C1_Msk                      /*!<Group Channel 5 and Channel 1 */
#define TIM_CCR5_GC5C2_Pos                  (30UL)
#define TIM_CCR5_GC5C2_Msk                  (0x1UL << TIM_CCR5_GC5C2_Pos)           /*!< 0x40000000 */
#define TIM_CCR5_GC5C2                      TIM_CCR5_GC5C2_Msk                      /*!<Group Channel 5 and Channel 2 */
#define TIM_CCR5_GC5C3_Pos                  (31UL)
#define TIM_CCR5_GC5C3_Msk                  (0x1UL << TIM_CCR5_GC5C3_Pos)           /*!< 0x80000000 */
#define TIM_CCR5_GC5C3                      TIM_CCR5_GC5C3_Msk                      /*!<Group Channel 5 and Channel 3 */

/*******************  Bit definition for TIM_CCR6 register  *******************/
#define TIM_CCR6_CCR6_Pos                   (0UL)
#define TIM_CCR6_CCR6_Msk                   (0xFFFFUL << TIM_CCR6_CCR6_Pos)         /*!< 0x0000FFFF */
#define TIM_CCR6_CCR6                       TIM_CCR6_CCR6_Msk                       /*!<Capture/Compare 6 Value */

/*******************  Bit definition for TIM_BDTR register  *******************/
#define TIM_BDTR_DTG_Pos                    (0UL)
#define TIM_BDTR_DTG_Msk                    (0xFFUL << TIM_BDTR_DTG_Pos)            /*!< 0x000000FF */
#define TIM_BDTR_DTG                        TIM_BDTR_DTG_Msk                        /*!<DTG[0:7] bits (Dead-Time Generator set-up) */
#define TIM_BDTR_DTG_0                      (0x01UL << TIM_BDTR_DTG_Pos)            /*!< 0x00000001 */
#define TIM_BDTR_DTG_1                      (0x02UL << TIM_BDTR_DTG_Pos)            /*!< 0x00000002 */
#define TIM_BDTR_DTG_2                      (0x04UL << TIM_BDTR_DTG_Pos)            /*!< 0x00000004 */
#define TIM_BDTR_DTG_3                      (0x08UL << TIM_BDTR_DTG_Pos)            /*!< 0x00000008 */
#define TIM_BDTR_DTG_4                      (0x10UL << TIM_BDTR_DTG_Pos)            /*!< 0x00000010 */
#define TIM_BDTR_DTG_5                      (0x20UL << TIM_BDTR_DTG_Pos)            /*!< 0x00000020 */
#define TIM_BDTR_DTG_6                      (0x40UL << TIM_BDTR_DTG_Pos)            /*!< 0x00000040 */
#define TIM_BDTR_DTG_7                      (0x80UL << TIM_BDTR_DTG_Pos)            /*!< 0x00000080 */
#define TIM_BDTR_LOCK_Pos                   (8UL)
#define TIM_BDTR_LOCK_Msk                   (0x3UL << TIM_BDTR_LOCK_Pos)            /*!< 0x00000300 */
#define TIM_BDTR_LOCK                       TIM_BDTR_LOCK_Msk                       /*!<LOCK[1:0] bits (Lock Configuration) */
#define TIM_BDTR_LOCK_0                     (0x1UL << TIM_BDTR_LOCK_Pos)            /*!< 0x00000100 */
#define TIM_BDTR_LOCK_1                     (0x2UL << TIM_BDTR_LOCK_Pos)            /*!< 0x00000200 */
#define TIM_BDTR_OSSI_Pos                   (10UL)
#define TIM_BDTR_OSSI_Msk                   (0x1UL << TIM_BDTR_OSSI_Pos)            /*!< 0x00000400 */
#define TIM_BDTR_OSSI                       TIM_BDTR_OSSI_Msk                       /*!<Off-State Selection for Idle mode */
#define TIM_BDTR_OSSR_Pos                   (11UL)
#define TIM_BDTR_OSSR_Msk                   (0x1UL << TIM_BDTR_OSSR_Pos)            /*!< 0x00000800 */
#define TIM_BDTR_OSSR                       TIM_BDTR_OSSR_Msk                       /*!<Off-State Selection for Run mode */
#define TIM_BDTR_BKE_Pos                    (12UL)
#define TIM_BDTR_BKE_Msk                    (0x1UL << TIM_BDTR_BKE_Pos)             /*!< 0x00001000 */
#define TIM_BDTR_BKE                        TIM_BDTR_BKE_Msk                        /*!<Break enable for Break 1 */
#define TIM_BDTR_BKP_Pos                    (13UL)
#define TIM_BDTR_BKP_Msk                    (0x1UL << TIM_BDTR_BKP_Pos)             /*!< 0x00002000 */
#define TIM_BDTR_BKP                        TIM_BDTR_BKP_Msk                        /*!<Break Polarity for Break 1 */
#define TIM_BDTR_AOE_Pos                    (14UL)
#define TIM_BDTR_AOE_Msk                    (0x1UL << TIM_BDTR_AOE_Pos)             /*!< 0x00004000 */
#define TIM_BDTR_AOE                        TIM_BDTR_AOE_Msk                        /*!<Automatic Output enable */
#define TIM_BDTR_MOE_Pos                    (15UL)
#define TIM_BDTR_MOE_Msk                    (0x1UL << TIM_BDTR_MOE_Pos)             /*!< 0x00008000 */
#define TIM_BDTR_MOE                        TIM_BDTR_MOE_Msk                        /*!<Main Output enable */
#define TIM_BDTR_BKF_Pos                    (16UL)
#define TIM_BDTR_BKF_Msk                    (0xFUL << TIM_BDTR_BKF_Pos)             /*!< 0x000F0000 */
#define TIM_BDTR_BKF                        TIM_BDTR_BKF_Msk                        /*!<Break Filter for Break 1 */
#define TIM_BDTR_BK2F_Pos                   (20UL)
#define TIM_BDTR_BK2F_Msk                   (0xFUL << TIM_BDTR_BK2F_Pos)            /*!< 0x00F00000 */
#define TIM_BDTR_BK2F                       TIM_BDTR_BK2F_Msk                       /*!<Break Filter for Break 2 */
#define TIM_BDTR_BK2E_Pos                   (24UL)
#define TIM_BDTR_BK2E_Msk                   (0x1UL << TIM_BDTR_BK2E_Pos)            /*!< 0x01000000 */
#define TIM_BDTR_BK2E                       TIM_BDTR_BK2E_Msk                       /*!<Break enable for Break 2 */
#define TIM_BDTR_BK2P_Pos                   (25UL)
#define TIM_BDTR_BK2P_Msk                   (0x1UL << TIM_BDTR_BK2P_Pos)            /*!< 0x02000000 */
#define TIM_BDTR_BK2P                       TIM_BDTR_BK2P_Msk                       /*!<Break Polarity for Break 2 */
#define TIM_BDTR_BKDSRM_Pos                 (26UL)
#define TIM_BDTR_BKDSRM_Msk                 (0x1UL << TIM_BDTR_BKDSRM_Pos)          /*!< 0x04000000 */
#define TIM_BDTR_BKDSRM                     TIM_BDTR_BKDSRM_Msk                     /*!<Break disarming/re-arming */
#define TIM_BDTR_BK2DSRM_Pos                (27UL)
#define TIM_BDTR_BK2DSRM_Msk                (0x1UL << TIM_BDTR_BK2DSRM_Pos)         /*!< 0x08000000 */
#define TIM_BDTR_BK2DSRM                    TIM_BDTR_BK2DSRM_Msk                    /*!<Break2 disarming/re-arming */
#define TIM_BDTR_BKBID_Pos                  (28UL)
#define TIM_BDTR_BKBID_Msk                  (0x1UL << TIM_BDTR_BKBID_Pos)           /*!< 0x10000000 */
#define TIM_BDTR_BKBID                      TIM_BDTR_BKBID_Msk                      /*!<Break BIDirectional */
#define TIM_BDTR_BK2BID_Pos                 (29UL)
#define TIM_BDTR_BK2BID_Msk                 (0x1UL << TIM_BDTR_BK2BID_Pos)          /*!< 0x20000000 */
#define TIM_BDTR_BK2BID                     TIM_BDTR_BK2BID_Msk                     /*!<Break2 BIDirectional */

/*******************  Bit definition for TIM_DCR register  ********************/
#define TIM_DCR_DBA_Pos                     (0UL)
#define TIM_DCR_DBA_Msk                     (0x1FUL << TIM_DCR_DBA_Pos)             /*!< 0x0000001F */
#define TIM_DCR_DBA                         TIM_DCR_DBA_Msk                         /*!<DBA[4:0] bits (DMA Base Address) */
#define TIM_DCR_DBA_0                       (0x01UL << TIM_DCR_DBA_Pos)             /*!< 0x00000001 */
#define TIM_DCR_DBA_1                       (0x02UL << TIM_DCR_DBA_Pos)             /*!< 0x00000002 */
#define TIM_DCR_DBA_2                       (0x04UL << TIM_DCR_DBA_Pos)             /*!< 0x00000004 */
#define TIM_DCR_DBA_3                       (0x08UL << TIM_DCR_DBA_Pos)             /*!< 0x00000008 */
#define TIM_DCR_DBA_4                       (0x10UL << TIM_DCR_DBA_Pos)             /*!< 0x00000010 */
#define TIM_DCR_DBL_Pos                     (8UL)
#define TIM_DCR_DBL_Msk                     (0x1FUL << TIM_DCR_DBL_Pos)             /*!< 0x00001F00 */
#define TIM_DCR_DBL                         TIM_DCR_DBL_Msk                         /*!<DBL[4:0] bits (DMA Burst Length) */
#define TIM_DCR_DBL_0                       (0x01UL << TIM_DCR_DBL_Pos)             /*!< 0x00000100 */
#define TIM_DCR_DBL_1                       (0x02UL << TIM_DCR_DBL_Pos)             /*!< 0x00000200 */
#define TIM_DCR_DBL_2                       (0x04UL << TIM_DCR_DBL_Pos)             /*!< 0x00000400 */
#define TIM_DCR_DBL_3                       (0x08UL << TIM_DCR_DBL_Pos)             /*!< 0x00000800 */
#define TIM_DCR_DBL_4                       (0x10UL << TIM_DCR_DBL_Pos)             /*!< 0x00001000 */
#define TIM_DCR_DBSS_Pos                    (16UL)
#define TIM_DCR_DBSS_Msk                    (0xFUL << TIM_DCR_DBSS_Pos)             /*!< 0x00000F00 */
#define TIM_DCR_DBSS                        TIM_DCR_DBSS_Msk                        /*!<DBSS[19:16] bits (DMA Burst Source Selection) */
#define TIM_DCR_DBSS_0                      (0x01UL << TIM_DCR_DBSS_Pos)            /*!< 0x00010000 */
#define TIM_DCR_DBSS_1                      (0x02UL << TIM_DCR_DBSS_Pos)            /*!< 0x00020000 */
#define TIM_DCR_DBSS_2                      (0x04UL << TIM_DCR_DBSS_Pos)            /*!< 0x00040000 */
#define TIM_DCR_DBSS_3                      (0x08UL << TIM_DCR_DBSS_Pos)            /*!< 0x00080000 */

/*******************  Bit definition for TIM_AF1 register  *******************/
#define TIM_AF1_BKINE_Pos                  (0UL)
#define TIM_AF1_BKINE_Msk                  (0x1UL << TIM_AF1_BKINE_Pos)              /*!< 0x00000001 */
#define TIM_AF1_BKINE                      TIM_AF1_BKINE_Msk                         /*!<BRK BKIN input enable */
#define TIM_AF1_BKCMP1E_Pos                (1UL)
#define TIM_AF1_BKCMP1E_Msk                (0x1UL << TIM_AF1_BKCMP1E_Pos)            /*!< 0x00000002 */
#define TIM_AF1_BKCMP1E                    TIM_AF1_BKCMP1E_Msk                       /*!<BRK CMP1 enable */
#define TIM_AF1_BKCMP2E_Pos                (2UL)
#define TIM_AF1_BKCMP2E_Msk                (0x1UL << TIM_AF1_BKCMP2E_Pos)            /*!< 0x00000004 */
#define TIM_AF1_BKCMP2E                    TIM_AF1_BKCMP2E_Msk                       /*!<BRK CMP2 enable */
#define TIM_AF1_BKINP_Pos                  (9UL)
#define TIM_AF1_BKINP_Msk                  (0x1UL << TIM_AF1_BKINP_Pos)              /*!< 0x00000200 */
#define TIM_AF1_BKINP                      TIM_AF1_BKINP_Msk                         /*!<BRK BKIN input polarity */
#define TIM_AF1_BKCMP1P_Pos                (10UL)
#define TIM_AF1_BKCMP1P_Msk                (0x1UL << TIM_AF1_BKCMP1P_Pos)            /*!< 0x00000400 */
#define TIM_AF1_BKCMP1P                    TIM_AF1_BKCMP1P_Msk                       /*!<BRK CMP1 input polarity */
#define TIM_AF1_BKCMP2P_Pos                (11UL)
#define TIM_AF1_BKCMP2P_Msk                (0x1UL << TIM_AF1_BKCMP2P_Pos)            /*!< 0x00000800 */
#define TIM_AF1_BKCMP2P                    TIM_AF1_BKCMP2P_Msk                       /*!<BRK CMP2 input polarity */
#define TIM_AF1_ETRSEL_Pos                 (14UL)
#define TIM_AF1_ETRSEL_Msk                 (0xFUL << TIM_AF1_ETRSEL_Pos)             /*!< 0x0003C000 */
#define TIM_AF1_ETRSEL                     TIM_AF1_ETRSEL_Msk                        /*!<ETRSEL[3:0] bits (TIM1 ETR source selection) */
#define TIM_AF1_ETRSEL_0                   (0x1UL << TIM_AF1_ETRSEL_Pos)             /*!< 0x00004000 */
#define TIM_AF1_ETRSEL_1                   (0x2UL << TIM_AF1_ETRSEL_Pos)             /*!< 0x00008000 */
#define TIM_AF1_ETRSEL_2                   (0x4UL << TIM_AF1_ETRSEL_Pos)             /*!< 0x00010000 */
#define TIM_AF1_ETRSEL_3                   (0x8UL << TIM_AF1_ETRSEL_Pos)             /*!< 0x00020000 */

/*******************  Bit definition for TIM_AF2 register  *********************/
#define TIM_AF2_BK2INE_Pos                 (0UL)
#define TIM_AF2_BK2INE_Msk                 (0x1UL << TIM_AF2_BK2INE_Pos)             /*!< 0x00000001 */
#define TIM_AF2_BK2INE                     TIM_AF2_BK2INE_Msk                        /*!<BRK2 BKIN input enable */
#define TIM_AF2_BK2CMP1E_Pos               (1UL)
#define TIM_AF2_BK2CMP1E_Msk               (0x1UL << TIM_AF2_BK2CMP1E_Pos)           /*!< 0x00000002 */
#define TIM_AF2_BK2CMP1E                   TIM_AF2_BK2CMP1E_Msk                      /*!<BRK2 CMP1 enable */
#define TIM_AF2_BK2CMP2E_Pos               (2UL)
#define TIM_AF2_BK2CMP2E_Msk               (0x1UL << TIM_AF2_BK2CMP2E_Pos)           /*!< 0x00000004 */
#define TIM_AF2_BK2CMP2E                   TIM_AF2_BK2CMP2E_Msk                      /*!<BRK2 CMP2 enable */
#define TIM_AF2_BK2INP_Pos                 (9UL)
#define TIM_AF2_BK2INP_Msk                 (0x1UL << TIM_AF2_BK2INP_Pos)             /*!< 0x00000200 */
#define TIM_AF2_BK2INP                     TIM_AF2_BK2INP_Msk                        /*!<BRK2 BKIN input polarity */
#define TIM_AF2_BK2CMP1P_Pos               (10UL)
#define TIM_AF2_BK2CMP1P_Msk               (0x1UL << TIM_AF2_BK2CMP1P_Pos)           /*!< 0x00000400 */
#define TIM_AF2_BK2CMP1P                   TIM_AF2_BK2CMP1P_Msk                      /*!<BRK2 CMP1 input polarity */
#define TIM_AF2_BK2CMP2P_Pos               (11UL)
#define TIM_AF2_BK2CMP2P_Msk               (0x1UL << TIM_AF2_BK2CMP2P_Pos)           /*!< 0x00000800 */
#define TIM_AF2_BK2CMP2P                   TIM_AF2_BK2CMP2P_Msk                      /*!<BRK2 CMP2 input polarity */
#define TIM_AF2_OCRSEL_Pos                 (16UL)
#define TIM_AF2_OCRSEL_Msk                 (0x1UL << TIM_AF2_OCRSEL_Pos)             /*!< 0x00010000 */
#define TIM_AF2_OCRSEL                     TIM_AF2_OCRSEL_Msk                        /*!<OCREF_CLR source selection */
#define TIM_AF2_OCRSEL_0                   (0x1UL << TIM_AF2_OCRSEL_Pos)             /*!< 0x00010000 */

/*******************  Bit definition for TIM_OR register  *********************/
#define TIM_OR1_HSE32EN_Pos                 (1UL)
#define TIM_OR1_HSE32EN_Msk                 (0x1UL << TIM_OR1_HSE32EN_Pos)           /*!< 0x00000002 */
#define TIM_OR1_HSE32EN                     TIM_OR1_HSE32EN_Msk                      /*!< HSE/32 clock enable */

/*******************  Bit definition for TIM_TISEL register  *********************/
#define TIM_TISEL_TI1SEL_Pos                (0UL)
#define TIM_TISEL_TI1SEL_Msk                (0xFUL << TIM_TISEL_TI1SEL_Pos)         /*!< 0x0000000F */
#define TIM_TISEL_TI1SEL                    TIM_TISEL_TI1SEL_Msk                    /*!<TI1SEL[3:0] bits (TIM1 TI1 SEL)*/
#define TIM_TISEL_TI1SEL_0                  (0x1UL << TIM_TISEL_TI1SEL_Pos)         /*!< 0x00000001 */
#define TIM_TISEL_TI1SEL_1                  (0x2UL << TIM_TISEL_TI1SEL_Pos)         /*!< 0x00000002 */
#define TIM_TISEL_TI1SEL_2                  (0x4UL << TIM_TISEL_TI1SEL_Pos)         /*!< 0x00000004 */
#define TIM_TISEL_TI1SEL_3                  (0x8UL << TIM_TISEL_TI1SEL_Pos)         /*!< 0x00000008 */
#define TIM_TISEL_TI2SEL_Pos                (8UL)
#define TIM_TISEL_TI2SEL_Msk                (0xFUL << TIM_TISEL_TI2SEL_Pos)         /*!< 0x00000F00 */
#define TIM_TISEL_TI2SEL                    TIM_TISEL_TI2SEL_Msk                    /*!<TI2SEL[3:0] bits (TIM1 TI2 SEL)*/
#define TIM_TISEL_TI2SEL_0                  (0x1UL << TIM_TISEL_TI2SEL_Pos)         /*!< 0x00000100 */
#define TIM_TISEL_TI2SEL_1                  (0x2UL << TIM_TISEL_TI2SEL_Pos)         /*!< 0x00000200 */
#define TIM_TISEL_TI2SEL_2                  (0x4UL << TIM_TISEL_TI2SEL_Pos)         /*!< 0x00000400 */
#define TIM_TISEL_TI2SEL_3                  (0x8UL << TIM_TISEL_TI2SEL_Pos)         /*!< 0x00000800 */
#define TIM_TISEL_TI3SEL_Pos                (16UL)
#define TIM_TISEL_TI3SEL_Msk                (0xFUL << TIM_TISEL_TI3SEL_Pos)         /*!< 0x000F0000 */
#define TIM_TISEL_TI3SEL                    TIM_TISEL_TI3SEL_Msk                    /*!<TI3SEL[3:0] bits (TIM1 TI3 SEL)*/
#define TIM_TISEL_TI3SEL_0                  (0x1UL << TIM_TISEL_TI3SEL_Pos)         /*!< 0x00010000 */
#define TIM_TISEL_TI3SEL_1                  (0x2UL << TIM_TISEL_TI3SEL_Pos)         /*!< 0x00020000 */
#define TIM_TISEL_TI3SEL_2                  (0x4UL << TIM_TISEL_TI3SEL_Pos)         /*!< 0x00040000 */
#define TIM_TISEL_TI3SEL_3                  (0x8UL << TIM_TISEL_TI3SEL_Pos)         /*!< 0x00080000 */
#define TIM_TISEL_TI4SEL_Pos                (24UL)
#define TIM_TISEL_TI4SEL_Msk                (0xFUL << TIM_TISEL_TI4SEL_Pos)         /*!< 0x0F000000 */
#define TIM_TISEL_TI4SEL                    TIM_TISEL_TI4SEL_Msk                    /*!<TI4SEL[3:0] bits (TIM1 TI4 SEL)*/
#define TIM_TISEL_TI4SEL_0                  (0x1UL << TIM_TISEL_TI4SEL_Pos)         /*!< 0x01000000 */
#define TIM_TISEL_TI4SEL_1                  (0x2UL << TIM_TISEL_TI4SEL_Pos)         /*!< 0x02000000 */
#define TIM_TISEL_TI4SEL_2                  (0x4UL << TIM_TISEL_TI4SEL_Pos)         /*!< 0x04000000 */
#define TIM_TISEL_TI4SEL_3                  (0x8UL << TIM_TISEL_TI4SEL_Pos)         /*!< 0x08000000 */

/*******************  Bit definition for TIM_DTR2 register  *********************/
#define TIM_DTR2_DTGF_Pos                   (0UL)
#define TIM_DTR2_DTGF_Msk                   (0xFFUL << TIM_DTR2_DTGF_Pos)           /*!< 0x0000000F */
#define TIM_DTR2_DTGF                       TIM_DTR2_DTGF_Msk                       /*!<DTGF[7:0] bits (Deadtime falling edge generator setup)*/
#define TIM_DTR2_DTGF_0                     (0x01UL << TIM_DTR2_DTGF_Pos)           /*!< 0x00000001 */
#define TIM_DTR2_DTGF_1                     (0x02UL << TIM_DTR2_DTGF_Pos)           /*!< 0x00000002 */
#define TIM_DTR2_DTGF_2                     (0x04UL << TIM_DTR2_DTGF_Pos)           /*!< 0x00000004 */
#define TIM_DTR2_DTGF_3                     (0x08UL << TIM_DTR2_DTGF_Pos)           /*!< 0x00000008 */
#define TIM_DTR2_DTGF_4                     (0x10UL << TIM_DTR2_DTGF_Pos)           /*!< 0x00000010 */
#define TIM_DTR2_DTGF_5                     (0x20UL << TIM_DTR2_DTGF_Pos)           /*!< 0x00000020 */
#define TIM_DTR2_DTGF_6                     (0x40UL << TIM_DTR2_DTGF_Pos)           /*!< 0x00000040 */
#define TIM_DTR2_DTGF_7                     (0x80UL << TIM_DTR2_DTGF_Pos)           /*!< 0x00000080 */
#define TIM_DTR2_DTAE_Pos                   (16UL)
#define TIM_DTR2_DTAE_Msk                   (0x1UL << TIM_DTR2_DTAE_Pos)            /*!< 0x00004000 */
#define TIM_DTR2_DTAE                       TIM_DTR2_DTAE_Msk                       /*!<Deadtime asymmetric enable */
#define TIM_DTR2_DTPE_Pos                   (17UL)
#define TIM_DTR2_DTPE_Msk                   (0x1UL << TIM_DTR2_DTPE_Pos)            /*!< 0x00008000 */
#define TIM_DTR2_DTPE                       TIM_DTR2_DTPE_Msk                       /*!<Deadtime prelaod enable */

/*******************  Bit definition for TIM_ECR register  *********************/
#define TIM_ECR_IE_Pos                      (0UL)
#define TIM_ECR_IE_Msk                      (0x1UL << TIM_ECR_IE_Pos)               /*!< 0x00000001 */
#define TIM_ECR_IE                          TIM_ECR_IE_Msk                          /*!<Index enable */
#define TIM_ECR_IDIR_Pos                    (1UL)
#define TIM_ECR_IDIR_Msk                    (0x3UL << TIM_ECR_IDIR_Pos)             /*!< 0x00000006 */
#define TIM_ECR_IDIR                        TIM_ECR_IDIR_Msk                        /*!<IDIR[1:0] bits (Index direction)*/
#define TIM_ECR_IDIR_0                      (0x01UL << TIM_ECR_IDIR_Pos)            /*!< 0x00000001 */
#define TIM_ECR_IDIR_1                      (0x02UL << TIM_ECR_IDIR_Pos)            /*!< 0x00000002 */
#define TIM_ECR_IBLK_Pos                    (3UL)
#define TIM_ECR_IBLK_Msk                    (0x3UL << TIM_ECR_IBLK_Pos)             /*!< 0x00000018 */
#define TIM_ECR_IBLK                        TIM_ECR_IBLK_Msk                        /*!<IBLK[1:0] bits (Index blanking)*/
#define TIM_ECR_IBLK_0                      (0x01UL << TIM_ECR_IBLK_Pos)            /*!< 0x00000008 */
#define TIM_ECR_IBLK_1                      (0x02UL << TIM_ECR_IBLK_Pos)            /*!< 0x00000010 */
#define TIM_ECR_FIDX_Pos                    (5UL)
#define TIM_ECR_FIDX_Msk                    (0x1UL << TIM_ECR_FIDX_Pos)             /*!< 0x00000020 */
#define TIM_ECR_FIDX                        TIM_ECR_FIDX_Msk                        /*!<First index enable */
#define TIM_ECR_IPOS_Pos                    (6UL)
#define TIM_ECR_IPOS_Msk                    (0x3UL << TIM_ECR_IPOS_Pos)             /*!< 0x000000C0 */
#define TIM_ECR_IPOS                        TIM_ECR_IPOS_Msk                        /*!<IPOS[1:0] bits (Index positioning)*/
#define TIM_ECR_IPOS_0                      (0x01UL << TIM_ECR_IPOS_Pos)            /*!< 0x00000040 */
#define TIM_ECR_IPOS_1                      (0x02UL << TIM_ECR_IPOS_Pos)            /*!< 0x00000080 */
#define TIM_ECR_PW_Pos                      (16UL)
#define TIM_ECR_PW_Msk                      (0xFFUL << TIM_ECR_PW_Pos)              /*!< 0x00FF0000 */
#define TIM_ECR_PW                          TIM_ECR_PW_Msk                          /*!<PW[7:0] bits (Pulse width)*/
#define TIM_ECR_PW_0                        (0x01UL << TIM_ECR_PW_Pos)              /*!< 0x00010000 */
#define TIM_ECR_PW_1                        (0x02UL << TIM_ECR_PW_Pos)              /*!< 0x00020000 */
#define TIM_ECR_PW_2                        (0x04UL << TIM_ECR_PW_Pos)              /*!< 0x00040000 */
#define TIM_ECR_PW_3                        (0x08UL << TIM_ECR_PW_Pos)              /*!< 0x00080000 */
#define TIM_ECR_PW_4                        (0x10UL << TIM_ECR_PW_Pos)              /*!< 0x00100000 */
#define TIM_ECR_PW_5                        (0x20UL << TIM_ECR_PW_Pos)              /*!< 0x00200000 */
#define TIM_ECR_PW_6                        (0x40UL << TIM_ECR_PW_Pos)              /*!< 0x00400000 */
#define TIM_ECR_PW_7                        (0x80UL << TIM_ECR_PW_Pos)              /*!< 0x00800000 */
#define TIM_ECR_PWPRSC_Pos                  (24UL)
#define TIM_ECR_PWPRSC_Msk                  (0x7UL << TIM_ECR_PWPRSC_Pos)           /*!< 0x07000000 */
#define TIM_ECR_PWPRSC                      TIM_ECR_PWPRSC_Msk                      /*!<PWPRSC[2:0] bits (Pulse width prescaler)*/
#define TIM_ECR_PWPRSC_0                    (0x01UL << TIM_ECR_PWPRSC_Pos)          /*!< 0x01000000 */
#define TIM_ECR_PWPRSC_1                    (0x02UL << TIM_ECR_PWPRSC_Pos)          /*!< 0x02000000 */
#define TIM_ECR_PWPRSC_2                    (0x04UL << TIM_ECR_PWPRSC_Pos)          /*!< 0x04000000 */

/*******************  Bit definition for TIM_DMAR register  *******************/
#define TIM_DMAR_DMAB_Pos                   (0UL)
#define TIM_DMAR_DMAB_Msk                   (0xFFFFFFFFUL << TIM_DMAR_DMAB_Pos)     /*!< 0xFFFFFFFF */
#define TIM_DMAR_DMAB                       TIM_DMAR_DMAB_Msk                       /*!<DMA register for burst accesses */


/******************************************************************************/
/*                                                                            */
/*                          Touch Sensing Controller (TSC)                    */
/*                                                                            */
/******************************************************************************/
/*******************  Bit definition for TSC_CR register  *********************/
#define TSC_CR_TSCE_Pos          (0UL)
#define TSC_CR_TSCE_Msk          (0x1UL << TSC_CR_TSCE_Pos)                    /*!< 0x00000001 */
#define TSC_CR_TSCE              TSC_CR_TSCE_Msk                               /*!<Touch sensing controller enable */
#define TSC_CR_START_Pos         (1UL)
#define TSC_CR_START_Msk         (0x1UL << TSC_CR_START_Pos)                   /*!< 0x00000002 */
#define TSC_CR_START             TSC_CR_START_Msk                              /*!<Start acquisition */
#define TSC_CR_AM_Pos            (2UL)
#define TSC_CR_AM_Msk            (0x1UL << TSC_CR_AM_Pos)                      /*!< 0x00000004 */
#define TSC_CR_AM                TSC_CR_AM_Msk                                 /*!<Acquisition mode */
#define TSC_CR_SYNCPOL_Pos       (3UL)
#define TSC_CR_SYNCPOL_Msk       (0x1UL << TSC_CR_SYNCPOL_Pos)                 /*!< 0x00000008 */
#define TSC_CR_SYNCPOL           TSC_CR_SYNCPOL_Msk                            /*!<Synchronization pin polarity */
#define TSC_CR_IODEF_Pos         (4UL)
#define TSC_CR_IODEF_Msk         (0x1UL << TSC_CR_IODEF_Pos)                   /*!< 0x00000010 */
#define TSC_CR_IODEF             TSC_CR_IODEF_Msk                              /*!<IO default mode */

#define TSC_CR_MCV_Pos           (5UL)
#define TSC_CR_MCV_Msk           (0x7UL << TSC_CR_MCV_Pos)                     /*!< 0x000000E0 */
#define TSC_CR_MCV               TSC_CR_MCV_Msk                                /*!<MCV[2:0] bits (Max Count Value) */
#define TSC_CR_MCV_0             (0x1UL << TSC_CR_MCV_Pos)                     /*!< 0x00000020 */
#define TSC_CR_MCV_1             (0x2UL << TSC_CR_MCV_Pos)                     /*!< 0x00000040 */
#define TSC_CR_MCV_2             (0x4UL << TSC_CR_MCV_Pos)                     /*!< 0x00000080 */

#define TSC_CR_PGPSC_Pos         (12UL)
#define TSC_CR_PGPSC_Msk         (0x7UL << TSC_CR_PGPSC_Pos)                   /*!< 0x00007000 */
#define TSC_CR_PGPSC             TSC_CR_PGPSC_Msk                              /*!<PGPSC[2:0] bits (Pulse Generator Prescaler) */
#define TSC_CR_PGPSC_0           (0x1UL << TSC_CR_PGPSC_Pos)                   /*!< 0x00001000 */
#define TSC_CR_PGPSC_1           (0x2UL << TSC_CR_PGPSC_Pos)                   /*!< 0x00002000 */
#define TSC_CR_PGPSC_2           (0x4UL << TSC_CR_PGPSC_Pos)                   /*!< 0x00004000 */

#define TSC_CR_SSPSC_Pos         (15UL)
#define TSC_CR_SSPSC_Msk         (0x1UL << TSC_CR_SSPSC_Pos)                   /*!< 0x00008000 */
#define TSC_CR_SSPSC             TSC_CR_SSPSC_Msk                              /*!<Spread Spectrum Prescaler */
#define TSC_CR_SSE_Pos           (16UL)
#define TSC_CR_SSE_Msk           (0x1UL << TSC_CR_SSE_Pos)                     /*!< 0x00010000 */
#define TSC_CR_SSE               TSC_CR_SSE_Msk                                /*!<Spread Spectrum Enable */

#define TSC_CR_SSD_Pos           (17UL)
#define TSC_CR_SSD_Msk           (0x7FUL << TSC_CR_SSD_Pos)                    /*!< 0x00FE0000 */
#define TSC_CR_SSD               TSC_CR_SSD_Msk                                /*!<SSD[6:0] bits (Spread Spectrum Deviation) */
#define TSC_CR_SSD_0             (0x01UL << TSC_CR_SSD_Pos)                    /*!< 0x00020000 */
#define TSC_CR_SSD_1             (0x02UL << TSC_CR_SSD_Pos)                    /*!< 0x00040000 */
#define TSC_CR_SSD_2             (0x04UL << TSC_CR_SSD_Pos)                    /*!< 0x00080000 */
#define TSC_CR_SSD_3             (0x08UL << TSC_CR_SSD_Pos)                    /*!< 0x00100000 */
#define TSC_CR_SSD_4             (0x10UL << TSC_CR_SSD_Pos)                    /*!< 0x00200000 */
#define TSC_CR_SSD_5             (0x20UL << TSC_CR_SSD_Pos)                    /*!< 0x00400000 */
#define TSC_CR_SSD_6             (0x40UL << TSC_CR_SSD_Pos)                    /*!< 0x00800000 */

#define TSC_CR_CTPL_Pos          (24UL)
#define TSC_CR_CTPL_Msk          (0xFUL << TSC_CR_CTPL_Pos)                    /*!< 0x0F000000 */
#define TSC_CR_CTPL              TSC_CR_CTPL_Msk                               /*!<CTPL[3:0] bits (Charge Transfer pulse low) */
#define TSC_CR_CTPL_0            (0x1UL << TSC_CR_CTPL_Pos)                    /*!< 0x01000000 */
#define TSC_CR_CTPL_1            (0x2UL << TSC_CR_CTPL_Pos)                    /*!< 0x02000000 */
#define TSC_CR_CTPL_2            (0x4UL << TSC_CR_CTPL_Pos)                    /*!< 0x04000000 */
#define TSC_CR_CTPL_3            (0x8UL << TSC_CR_CTPL_Pos)                    /*!< 0x08000000 */

#define TSC_CR_CTPH_Pos          (28UL)
#define TSC_CR_CTPH_Msk          (0xFUL << TSC_CR_CTPH_Pos)                    /*!< 0xF0000000 */
#define TSC_CR_CTPH              TSC_CR_CTPH_Msk                               /*!<CTPH[3:0] bits (Charge Transfer pulse high) */
#define TSC_CR_CTPH_0            (0x1UL << TSC_CR_CTPH_Pos)                    /*!< 0x10000000 */
#define TSC_CR_CTPH_1            (0x2UL << TSC_CR_CTPH_Pos)                    /*!< 0x20000000 */
#define TSC_CR_CTPH_2            (0x4UL << TSC_CR_CTPH_Pos)                    /*!< 0x40000000 */
#define TSC_CR_CTPH_3            (0x8UL << TSC_CR_CTPH_Pos)                    /*!< 0x80000000 */

/*******************  Bit definition for TSC_IER register  ********************/
#define TSC_IER_EOAIE_Pos        (0UL)
#define TSC_IER_EOAIE_Msk        (0x1UL << TSC_IER_EOAIE_Pos)                  /*!< 0x00000001 */
#define TSC_IER_EOAIE            TSC_IER_EOAIE_Msk                             /*!<End of acquisition interrupt enable */
#define TSC_IER_MCEIE_Pos        (1UL)
#define TSC_IER_MCEIE_Msk        (0x1UL << TSC_IER_MCEIE_Pos)                  /*!< 0x00000002 */
#define TSC_IER_MCEIE            TSC_IER_MCEIE_Msk                             /*!<Max count error interrupt enable */

/*******************  Bit definition for TSC_ICR register  ********************/
#define TSC_ICR_EOAIC_Pos        (0UL)
#define TSC_ICR_EOAIC_Msk        (0x1UL << TSC_ICR_EOAIC_Pos)                  /*!< 0x00000001 */
#define TSC_ICR_EOAIC            TSC_ICR_EOAIC_Msk                             /*!<End of acquisition interrupt clear */
#define TSC_ICR_MCEIC_Pos        (1UL)
#define TSC_ICR_MCEIC_Msk        (0x1UL << TSC_ICR_MCEIC_Pos)                  /*!< 0x00000002 */
#define TSC_ICR_MCEIC            TSC_ICR_MCEIC_Msk                             /*!<Max count error interrupt clear */

/*******************  Bit definition for TSC_ISR register  ********************/
#define TSC_ISR_EOAF_Pos         (0UL)
#define TSC_ISR_EOAF_Msk         (0x1UL << TSC_ISR_EOAF_Pos)                   /*!< 0x00000001 */
#define TSC_ISR_EOAF             TSC_ISR_EOAF_Msk                              /*!<End of acquisition flag */
#define TSC_ISR_MCEF_Pos         (1UL)
#define TSC_ISR_MCEF_Msk         (0x1UL << TSC_ISR_MCEF_Pos)                   /*!< 0x00000002 */
#define TSC_ISR_MCEF             TSC_ISR_MCEF_Msk                              /*!<Max count error flag */

/*******************  Bit definition for TSC_IOHCR register  ******************/
#define TSC_IOHCR_G1_IO1_Pos     (0UL)
#define TSC_IOHCR_G1_IO1_Msk     (0x1UL << TSC_IOHCR_G1_IO1_Pos)               /*!< 0x00000001 */
#define TSC_IOHCR_G1_IO1         TSC_IOHCR_G1_IO1_Msk                          /*!<GROUP1_IO1 schmitt trigger hysteresis mode */
#define TSC_IOHCR_G1_IO2_Pos     (1UL)
#define TSC_IOHCR_G1_IO2_Msk     (0x1UL << TSC_IOHCR_G1_IO2_Pos)               /*!< 0x00000002 */
#define TSC_IOHCR_G1_IO2         TSC_IOHCR_G1_IO2_Msk                          /*!<GROUP1_IO2 schmitt trigger hysteresis mode */
#define TSC_IOHCR_G1_IO3_Pos     (2UL)
#define TSC_IOHCR_G1_IO3_Msk     (0x1UL << TSC_IOHCR_G1_IO3_Pos)               /*!< 0x00000004 */
#define TSC_IOHCR_G1_IO3         TSC_IOHCR_G1_IO3_Msk                          /*!<GROUP1_IO3 schmitt trigger hysteresis mode */
#define TSC_IOHCR_G1_IO4_Pos     (3UL)
#define TSC_IOHCR_G1_IO4_Msk     (0x1UL << TSC_IOHCR_G1_IO4_Pos)               /*!< 0x00000008 */
#define TSC_IOHCR_G1_IO4         TSC_IOHCR_G1_IO4_Msk                          /*!<GROUP1_IO4 schmitt trigger hysteresis mode */
#define TSC_IOHCR_G2_IO1_Pos     (4UL)
#define TSC_IOHCR_G2_IO1_Msk     (0x1UL << TSC_IOHCR_G2_IO1_Pos)               /*!< 0x00000010 */
#define TSC_IOHCR_G2_IO1         TSC_IOHCR_G2_IO1_Msk                          /*!<GROUP2_IO1 schmitt trigger hysteresis mode */
#define TSC_IOHCR_G2_IO2_Pos     (5UL)
#define TSC_IOHCR_G2_IO2_Msk     (0x1UL << TSC_IOHCR_G2_IO2_Pos)               /*!< 0x00000020 */
#define TSC_IOHCR_G2_IO2         TSC_IOHCR_G2_IO2_Msk                          /*!<GROUP2_IO2 schmitt trigger hysteresis mode */
#define TSC_IOHCR_G2_IO3_Pos     (6UL)
#define TSC_IOHCR_G2_IO3_Msk     (0x1UL << TSC_IOHCR_G2_IO3_Pos)               /*!< 0x00000040 */
#define TSC_IOHCR_G2_IO3         TSC_IOHCR_G2_IO3_Msk                          /*!<GROUP2_IO3 schmitt trigger hysteresis mode */
#define TSC_IOHCR_G2_IO4_Pos     (7UL)
#define TSC_IOHCR_G2_IO4_Msk     (0x1UL << TSC_IOHCR_G2_IO4_Pos)               /*!< 0x00000080 */
#define TSC_IOHCR_G2_IO4         TSC_IOHCR_G2_IO4_Msk                          /*!<GROUP2_IO4 schmitt trigger hysteresis mode */
#define TSC_IOHCR_G3_IO1_Pos     (8UL)
#define TSC_IOHCR_G3_IO1_Msk     (0x1UL << TSC_IOHCR_G3_IO1_Pos)               /*!< 0x00000100 */
#define TSC_IOHCR_G3_IO1         TSC_IOHCR_G3_IO1_Msk                          /*!<GROUP3_IO1 schmitt trigger hysteresis mode */
#define TSC_IOHCR_G3_IO2_Pos     (9UL)
#define TSC_IOHCR_G3_IO2_Msk     (0x1UL << TSC_IOHCR_G3_IO2_Pos)               /*!< 0x00000200 */
#define TSC_IOHCR_G3_IO2         TSC_IOHCR_G3_IO2_Msk                          /*!<GROUP3_IO2 schmitt trigger hysteresis mode */
#define TSC_IOHCR_G3_IO3_Pos     (10UL)
#define TSC_IOHCR_G3_IO3_Msk     (0x1UL << TSC_IOHCR_G3_IO3_Pos)               /*!< 0x00000400 */
#define TSC_IOHCR_G3_IO3         TSC_IOHCR_G3_IO3_Msk                          /*!<GROUP3_IO3 schmitt trigger hysteresis mode */
#define TSC_IOHCR_G3_IO4_Pos     (11UL)
#define TSC_IOHCR_G3_IO4_Msk     (0x1UL << TSC_IOHCR_G3_IO4_Pos)               /*!< 0x00000800 */
#define TSC_IOHCR_G3_IO4         TSC_IOHCR_G3_IO4_Msk                          /*!<GROUP3_IO4 schmitt trigger hysteresis mode */
#define TSC_IOHCR_G4_IO1_Pos     (12UL)
#define TSC_IOHCR_G4_IO1_Msk     (0x1UL << TSC_IOHCR_G4_IO1_Pos)               /*!< 0x00001000 */
#define TSC_IOHCR_G4_IO1         TSC_IOHCR_G4_IO1_Msk                          /*!<GROUP4_IO1 schmitt trigger hysteresis mode */
#define TSC_IOHCR_G4_IO2_Pos     (13UL)
#define TSC_IOHCR_G4_IO2_Msk     (0x1UL << TSC_IOHCR_G4_IO2_Pos)               /*!< 0x00002000 */
#define TSC_IOHCR_G4_IO2         TSC_IOHCR_G4_IO2_Msk                          /*!<GROUP4_IO2 schmitt trigger hysteresis mode */
#define TSC_IOHCR_G4_IO3_Pos     (14UL)
#define TSC_IOHCR_G4_IO3_Msk     (0x1UL << TSC_IOHCR_G4_IO3_Pos)               /*!< 0x00004000 */
#define TSC_IOHCR_G4_IO3         TSC_IOHCR_G4_IO3_Msk                          /*!<GROUP4_IO3 schmitt trigger hysteresis mode */
#define TSC_IOHCR_G4_IO4_Pos     (15UL)
#define TSC_IOHCR_G4_IO4_Msk     (0x1UL << TSC_IOHCR_G4_IO4_Pos)               /*!< 0x00008000 */
#define TSC_IOHCR_G4_IO4         TSC_IOHCR_G4_IO4_Msk                          /*!<GROUP4_IO4 schmitt trigger hysteresis mode */
#define TSC_IOHCR_G5_IO1_Pos     (16UL)
#define TSC_IOHCR_G5_IO1_Msk     (0x1UL << TSC_IOHCR_G5_IO1_Pos)               /*!< 0x00010000 */
#define TSC_IOHCR_G5_IO1         TSC_IOHCR_G5_IO1_Msk                          /*!<GROUP5_IO1 schmitt trigger hysteresis mode */
#define TSC_IOHCR_G5_IO2_Pos     (17UL)
#define TSC_IOHCR_G5_IO2_Msk     (0x1UL << TSC_IOHCR_G5_IO2_Pos)               /*!< 0x00020000 */
#define TSC_IOHCR_G5_IO2         TSC_IOHCR_G5_IO2_Msk                          /*!<GROUP5_IO2 schmitt trigger hysteresis mode */
#define TSC_IOHCR_G5_IO3_Pos     (18UL)
#define TSC_IOHCR_G5_IO3_Msk     (0x1UL << TSC_IOHCR_G5_IO3_Pos)               /*!< 0x00040000 */
#define TSC_IOHCR_G5_IO3         TSC_IOHCR_G5_IO3_Msk                          /*!<GROUP5_IO3 schmitt trigger hysteresis mode */
#define TSC_IOHCR_G5_IO4_Pos     (19UL)
#define TSC_IOHCR_G5_IO4_Msk     (0x1UL << TSC_IOHCR_G5_IO4_Pos)               /*!< 0x00080000 */
#define TSC_IOHCR_G5_IO4         TSC_IOHCR_G5_IO4_Msk                          /*!<GROUP5_IO4 schmitt trigger hysteresis mode */
#define TSC_IOHCR_G6_IO1_Pos     (20UL)
#define TSC_IOHCR_G6_IO1_Msk     (0x1UL << TSC_IOHCR_G6_IO1_Pos)               /*!< 0x00100000 */
#define TSC_IOHCR_G6_IO1         TSC_IOHCR_G6_IO1_Msk                          /*!<GROUP6_IO1 schmitt trigger hysteresis mode */
#define TSC_IOHCR_G6_IO2_Pos     (21UL)
#define TSC_IOHCR_G6_IO2_Msk     (0x1UL << TSC_IOHCR_G6_IO2_Pos)               /*!< 0x00200000 */
#define TSC_IOHCR_G6_IO2         TSC_IOHCR_G6_IO2_Msk                          /*!<GROUP6_IO2 schmitt trigger hysteresis mode */
#define TSC_IOHCR_G6_IO3_Pos     (22UL)
#define TSC_IOHCR_G6_IO3_Msk     (0x1UL << TSC_IOHCR_G6_IO3_Pos)               /*!< 0x00400000 */
#define TSC_IOHCR_G6_IO3         TSC_IOHCR_G6_IO3_Msk                          /*!<GROUP6_IO3 schmitt trigger hysteresis mode */
#define TSC_IOHCR_G6_IO4_Pos     (23UL)
#define TSC_IOHCR_G6_IO4_Msk     (0x1UL << TSC_IOHCR_G6_IO4_Pos)               /*!< 0x00800000 */
#define TSC_IOHCR_G6_IO4         TSC_IOHCR_G6_IO4_Msk                          /*!<GROUP6_IO4 schmitt trigger hysteresis mode */
#define TSC_IOHCR_G7_IO1_Pos     (24UL)
#define TSC_IOHCR_G7_IO1_Msk     (0x1UL << TSC_IOHCR_G7_IO1_Pos)               /*!< 0x01000000 */
#define TSC_IOHCR_G7_IO1         TSC_IOHCR_G7_IO1_Msk                          /*!<GROUP7_IO1 schmitt trigger hysteresis mode */
#define TSC_IOHCR_G7_IO2_Pos     (25UL)
#define TSC_IOHCR_G7_IO2_Msk     (0x1UL << TSC_IOHCR_G7_IO2_Pos)               /*!< 0x02000000 */
#define TSC_IOHCR_G7_IO2         TSC_IOHCR_G7_IO2_Msk                          /*!<GROUP7_IO2 schmitt trigger hysteresis mode */
#define TSC_IOHCR_G7_IO3_Pos     (26UL)
#define TSC_IOHCR_G7_IO3_Msk     (0x1UL << TSC_IOHCR_G7_IO3_Pos)               /*!< 0x04000000 */
#define TSC_IOHCR_G7_IO3         TSC_IOHCR_G7_IO3_Msk                          /*!<GROUP7_IO3 schmitt trigger hysteresis mode */
#define TSC_IOHCR_G7_IO4_Pos     (27UL)
#define TSC_IOHCR_G7_IO4_Msk     (0x1UL << TSC_IOHCR_G7_IO4_Pos)               /*!< 0x08000000 */
#define TSC_IOHCR_G7_IO4         TSC_IOHCR_G7_IO4_Msk                          /*!<GROUP7_IO4 schmitt trigger hysteresis mode */

/*******************  Bit definition for TSC_IOASCR register  *****************/
#define TSC_IOASCR_G1_IO1_Pos    (0UL)
#define TSC_IOASCR_G1_IO1_Msk    (0x1UL << TSC_IOASCR_G1_IO1_Pos)              /*!< 0x00000001 */
#define TSC_IOASCR_G1_IO1        TSC_IOASCR_G1_IO1_Msk                         /*!<GROUP1_IO1 analog switch enable */
#define TSC_IOASCR_G1_IO2_Pos    (1UL)
#define TSC_IOASCR_G1_IO2_Msk    (0x1UL << TSC_IOASCR_G1_IO2_Pos)              /*!< 0x00000002 */
#define TSC_IOASCR_G1_IO2        TSC_IOASCR_G1_IO2_Msk                         /*!<GROUP1_IO2 analog switch enable */
#define TSC_IOASCR_G1_IO3_Pos    (2UL)
#define TSC_IOASCR_G1_IO3_Msk    (0x1UL << TSC_IOASCR_G1_IO3_Pos)              /*!< 0x00000004 */
#define TSC_IOASCR_G1_IO3        TSC_IOASCR_G1_IO3_Msk                         /*!<GROUP1_IO3 analog switch enable */
#define TSC_IOASCR_G1_IO4_Pos    (3UL)
#define TSC_IOASCR_G1_IO4_Msk    (0x1UL << TSC_IOASCR_G1_IO4_Pos)              /*!< 0x00000008 */
#define TSC_IOASCR_G1_IO4        TSC_IOASCR_G1_IO4_Msk                         /*!<GROUP1_IO4 analog switch enable */
#define TSC_IOASCR_G2_IO1_Pos    (4UL)
#define TSC_IOASCR_G2_IO1_Msk    (0x1UL << TSC_IOASCR_G2_IO1_Pos)              /*!< 0x00000010 */
#define TSC_IOASCR_G2_IO1        TSC_IOASCR_G2_IO1_Msk                         /*!<GROUP2_IO1 analog switch enable */
#define TSC_IOASCR_G2_IO2_Pos    (5UL)
#define TSC_IOASCR_G2_IO2_Msk    (0x1UL << TSC_IOASCR_G2_IO2_Pos)              /*!< 0x00000020 */
#define TSC_IOASCR_G2_IO2        TSC_IOASCR_G2_IO2_Msk                         /*!<GROUP2_IO2 analog switch enable */
#define TSC_IOASCR_G2_IO3_Pos    (6UL)
#define TSC_IOASCR_G2_IO3_Msk    (0x1UL << TSC_IOASCR_G2_IO3_Pos)              /*!< 0x00000040 */
#define TSC_IOASCR_G2_IO3        TSC_IOASCR_G2_IO3_Msk                         /*!<GROUP2_IO3 analog switch enable */
#define TSC_IOASCR_G2_IO4_Pos    (7UL)
#define TSC_IOASCR_G2_IO4_Msk    (0x1UL << TSC_IOASCR_G2_IO4_Pos)              /*!< 0x00000080 */
#define TSC_IOASCR_G2_IO4        TSC_IOASCR_G2_IO4_Msk                         /*!<GROUP2_IO4 analog switch enable */
#define TSC_IOASCR_G3_IO1_Pos    (8UL)
#define TSC_IOASCR_G3_IO1_Msk    (0x1UL << TSC_IOASCR_G3_IO1_Pos)              /*!< 0x00000100 */
#define TSC_IOASCR_G3_IO1        TSC_IOASCR_G3_IO1_Msk                         /*!<GROUP3_IO1 analog switch enable */
#define TSC_IOASCR_G3_IO2_Pos    (9UL)
#define TSC_IOASCR_G3_IO2_Msk    (0x1UL << TSC_IOASCR_G3_IO2_Pos)              /*!< 0x00000200 */
#define TSC_IOASCR_G3_IO2        TSC_IOASCR_G3_IO2_Msk                         /*!<GROUP3_IO2 analog switch enable */
#define TSC_IOASCR_G3_IO3_Pos    (10UL)
#define TSC_IOASCR_G3_IO3_Msk    (0x1UL << TSC_IOASCR_G3_IO3_Pos)              /*!< 0x00000400 */
#define TSC_IOASCR_G3_IO3        TSC_IOASCR_G3_IO3_Msk                         /*!<GROUP3_IO3 analog switch enable */
#define TSC_IOASCR_G3_IO4_Pos    (11UL)
#define TSC_IOASCR_G3_IO4_Msk    (0x1UL << TSC_IOASCR_G3_IO4_Pos)              /*!< 0x00000800 */
#define TSC_IOASCR_G3_IO4        TSC_IOASCR_G3_IO4_Msk                         /*!<GROUP3_IO4 analog switch enable */
#define TSC_IOASCR_G4_IO1_Pos    (12UL)
#define TSC_IOASCR_G4_IO1_Msk    (0x1UL << TSC_IOASCR_G4_IO1_Pos)              /*!< 0x00001000 */
#define TSC_IOASCR_G4_IO1        TSC_IOASCR_G4_IO1_Msk                         /*!<GROUP4_IO1 analog switch enable */
#define TSC_IOASCR_G4_IO2_Pos    (13UL)
#define TSC_IOASCR_G4_IO2_Msk    (0x1UL << TSC_IOASCR_G4_IO2_Pos)              /*!< 0x00002000 */
#define TSC_IOASCR_G4_IO2        TSC_IOASCR_G4_IO2_Msk                         /*!<GROUP4_IO2 analog switch enable */
#define TSC_IOASCR_G4_IO3_Pos    (14UL)
#define TSC_IOASCR_G4_IO3_Msk    (0x1UL << TSC_IOASCR_G4_IO3_Pos)              /*!< 0x00004000 */
#define TSC_IOASCR_G4_IO3        TSC_IOASCR_G4_IO3_Msk                         /*!<GROUP4_IO3 analog switch enable */
#define TSC_IOASCR_G4_IO4_Pos    (15UL)
#define TSC_IOASCR_G4_IO4_Msk    (0x1UL << TSC_IOASCR_G4_IO4_Pos)              /*!< 0x00008000 */
#define TSC_IOASCR_G4_IO4        TSC_IOASCR_G4_IO4_Msk                         /*!<GROUP4_IO4 analog switch enable */
#define TSC_IOASCR_G5_IO1_Pos    (16UL)
#define TSC_IOASCR_G5_IO1_Msk    (0x1UL << TSC_IOASCR_G5_IO1_Pos)              /*!< 0x00010000 */
#define TSC_IOASCR_G5_IO1        TSC_IOASCR_G5_IO1_Msk                         /*!<GROUP5_IO1 analog switch enable */
#define TSC_IOASCR_G5_IO2_Pos    (17UL)
#define TSC_IOASCR_G5_IO2_Msk    (0x1UL << TSC_IOASCR_G5_IO2_Pos)              /*!< 0x00020000 */
#define TSC_IOASCR_G5_IO2        TSC_IOASCR_G5_IO2_Msk                         /*!<GROUP5_IO2 analog switch enable */
#define TSC_IOASCR_G5_IO3_Pos    (18UL)
#define TSC_IOASCR_G5_IO3_Msk    (0x1UL << TSC_IOASCR_G5_IO3_Pos)              /*!< 0x00040000 */
#define TSC_IOASCR_G5_IO3        TSC_IOASCR_G5_IO3_Msk                         /*!<GROUP5_IO3 analog switch enable */
#define TSC_IOASCR_G5_IO4_Pos    (19UL)
#define TSC_IOASCR_G5_IO4_Msk    (0x1UL << TSC_IOASCR_G5_IO4_Pos)              /*!< 0x00080000 */
#define TSC_IOASCR_G5_IO4        TSC_IOASCR_G5_IO4_Msk                         /*!<GROUP5_IO4 analog switch enable */
#define TSC_IOASCR_G6_IO1_Pos    (20UL)
#define TSC_IOASCR_G6_IO1_Msk    (0x1UL << TSC_IOASCR_G6_IO1_Pos)              /*!< 0x00100000 */
#define TSC_IOASCR_G6_IO1        TSC_IOASCR_G6_IO1_Msk                         /*!<GROUP6_IO1 analog switch enable */
#define TSC_IOASCR_G6_IO2_Pos    (21UL)
#define TSC_IOASCR_G6_IO2_Msk    (0x1UL << TSC_IOASCR_G6_IO2_Pos)              /*!< 0x00200000 */
#define TSC_IOASCR_G6_IO2        TSC_IOASCR_G6_IO2_Msk                         /*!<GROUP6_IO2 analog switch enable */
#define TSC_IOASCR_G6_IO3_Pos    (22UL)
#define TSC_IOASCR_G6_IO3_Msk    (0x1UL << TSC_IOASCR_G6_IO3_Pos)              /*!< 0x00400000 */
#define TSC_IOASCR_G6_IO3        TSC_IOASCR_G6_IO3_Msk                         /*!<GROUP6_IO3 analog switch enable */
#define TSC_IOASCR_G6_IO4_Pos    (23UL)
#define TSC_IOASCR_G6_IO4_Msk    (0x1UL << TSC_IOASCR_G6_IO4_Pos)              /*!< 0x00800000 */
#define TSC_IOASCR_G6_IO4        TSC_IOASCR_G6_IO4_Msk                         /*!<GROUP6_IO4 analog switch enable */
#define TSC_IOASCR_G7_IO1_Pos    (24UL)
#define TSC_IOASCR_G7_IO1_Msk    (0x1UL << TSC_IOASCR_G7_IO1_Pos)              /*!< 0x01000000 */
#define TSC_IOASCR_G7_IO1        TSC_IOASCR_G7_IO1_Msk                         /*!<GROUP7_IO1 analog switch enable */
#define TSC_IOASCR_G7_IO2_Pos    (25UL)
#define TSC_IOASCR_G7_IO2_Msk    (0x1UL << TSC_IOASCR_G7_IO2_Pos)              /*!< 0x02000000 */
#define TSC_IOASCR_G7_IO2        TSC_IOASCR_G7_IO2_Msk                         /*!<GROUP7_IO2 analog switch enable */
#define TSC_IOASCR_G7_IO3_Pos    (26UL)
#define TSC_IOASCR_G7_IO3_Msk    (0x1UL << TSC_IOASCR_G7_IO3_Pos)              /*!< 0x04000000 */
#define TSC_IOASCR_G7_IO3        TSC_IOASCR_G7_IO3_Msk                         /*!<GROUP7_IO3 analog switch enable */
#define TSC_IOASCR_G7_IO4_Pos    (27UL)
#define TSC_IOASCR_G7_IO4_Msk    (0x1UL << TSC_IOASCR_G7_IO4_Pos)              /*!< 0x08000000 */
#define TSC_IOASCR_G7_IO4        TSC_IOASCR_G7_IO4_Msk                         /*!<GROUP7_IO4 analog switch enable */

/*******************  Bit definition for TSC_IOSCR register  ******************/
#define TSC_IOSCR_G1_IO1_Pos     (0UL)
#define TSC_IOSCR_G1_IO1_Msk     (0x1UL << TSC_IOSCR_G1_IO1_Pos)               /*!< 0x00000001 */
#define TSC_IOSCR_G1_IO1         TSC_IOSCR_G1_IO1_Msk                          /*!<GROUP1_IO1 sampling mode */
#define TSC_IOSCR_G1_IO2_Pos     (1UL)
#define TSC_IOSCR_G1_IO2_Msk     (0x1UL << TSC_IOSCR_G1_IO2_Pos)               /*!< 0x00000002 */
#define TSC_IOSCR_G1_IO2         TSC_IOSCR_G1_IO2_Msk                          /*!<GROUP1_IO2 sampling mode */
#define TSC_IOSCR_G1_IO3_Pos     (2UL)
#define TSC_IOSCR_G1_IO3_Msk     (0x1UL << TSC_IOSCR_G1_IO3_Pos)               /*!< 0x00000004 */
#define TSC_IOSCR_G1_IO3         TSC_IOSCR_G1_IO3_Msk                          /*!<GROUP1_IO3 sampling mode */
#define TSC_IOSCR_G1_IO4_Pos     (3UL)
#define TSC_IOSCR_G1_IO4_Msk     (0x1UL << TSC_IOSCR_G1_IO4_Pos)               /*!< 0x00000008 */
#define TSC_IOSCR_G1_IO4         TSC_IOSCR_G1_IO4_Msk                          /*!<GROUP1_IO4 sampling mode */
#define TSC_IOSCR_G2_IO1_Pos     (4UL)
#define TSC_IOSCR_G2_IO1_Msk     (0x1UL << TSC_IOSCR_G2_IO1_Pos)               /*!< 0x00000010 */
#define TSC_IOSCR_G2_IO1         TSC_IOSCR_G2_IO1_Msk                          /*!<GROUP2_IO1 sampling mode */
#define TSC_IOSCR_G2_IO2_Pos     (5UL)
#define TSC_IOSCR_G2_IO2_Msk     (0x1UL << TSC_IOSCR_G2_IO2_Pos)               /*!< 0x00000020 */
#define TSC_IOSCR_G2_IO2         TSC_IOSCR_G2_IO2_Msk                          /*!<GROUP2_IO2 sampling mode */
#define TSC_IOSCR_G2_IO3_Pos     (6UL)
#define TSC_IOSCR_G2_IO3_Msk     (0x1UL << TSC_IOSCR_G2_IO3_Pos)               /*!< 0x00000040 */
#define TSC_IOSCR_G2_IO3         TSC_IOSCR_G2_IO3_Msk                          /*!<GROUP2_IO3 sampling mode */
#define TSC_IOSCR_G2_IO4_Pos     (7UL)
#define TSC_IOSCR_G2_IO4_Msk     (0x1UL << TSC_IOSCR_G2_IO4_Pos)               /*!< 0x00000080 */
#define TSC_IOSCR_G2_IO4         TSC_IOSCR_G2_IO4_Msk                          /*!<GROUP2_IO4 sampling mode */
#define TSC_IOSCR_G3_IO1_Pos     (8UL)
#define TSC_IOSCR_G3_IO1_Msk     (0x1UL << TSC_IOSCR_G3_IO1_Pos)               /*!< 0x00000100 */
#define TSC_IOSCR_G3_IO1         TSC_IOSCR_G3_IO1_Msk                          /*!<GROUP3_IO1 sampling mode */
#define TSC_IOSCR_G3_IO2_Pos     (9UL)
#define TSC_IOSCR_G3_IO2_Msk     (0x1UL << TSC_IOSCR_G3_IO2_Pos)               /*!< 0x00000200 */
#define TSC_IOSCR_G3_IO2         TSC_IOSCR_G3_IO2_Msk                          /*!<GROUP3_IO2 sampling mode */
#define TSC_IOSCR_G3_IO3_Pos     (10UL)
#define TSC_IOSCR_G3_IO3_Msk     (0x1UL << TSC_IOSCR_G3_IO3_Pos)               /*!< 0x00000400 */
#define TSC_IOSCR_G3_IO3         TSC_IOSCR_G3_IO3_Msk                          /*!<GROUP3_IO3 sampling mode */
#define TSC_IOSCR_G3_IO4_Pos     (11UL)
#define TSC_IOSCR_G3_IO4_Msk     (0x1UL << TSC_IOSCR_G3_IO4_Pos)               /*!< 0x00000800 */
#define TSC_IOSCR_G3_IO4         TSC_IOSCR_G3_IO4_Msk                          /*!<GROUP3_IO4 sampling mode */
#define TSC_IOSCR_G4_IO1_Pos     (12UL)
#define TSC_IOSCR_G4_IO1_Msk     (0x1UL << TSC_IOSCR_G4_IO1_Pos)               /*!< 0x00001000 */
#define TSC_IOSCR_G4_IO1         TSC_IOSCR_G4_IO1_Msk                          /*!<GROUP4_IO1 sampling mode */
#define TSC_IOSCR_G4_IO2_Pos     (13UL)
#define TSC_IOSCR_G4_IO2_Msk     (0x1UL << TSC_IOSCR_G4_IO2_Pos)               /*!< 0x00002000 */
#define TSC_IOSCR_G4_IO2         TSC_IOSCR_G4_IO2_Msk                          /*!<GROUP4_IO2 sampling mode */
#define TSC_IOSCR_G4_IO3_Pos     (14UL)
#define TSC_IOSCR_G4_IO3_Msk     (0x1UL << TSC_IOSCR_G4_IO3_Pos)               /*!< 0x00004000 */
#define TSC_IOSCR_G4_IO3         TSC_IOSCR_G4_IO3_Msk                          /*!<GROUP4_IO3 sampling mode */
#define TSC_IOSCR_G4_IO4_Pos     (15UL)
#define TSC_IOSCR_G4_IO4_Msk     (0x1UL << TSC_IOSCR_G4_IO4_Pos)               /*!< 0x00008000 */
#define TSC_IOSCR_G4_IO4         TSC_IOSCR_G4_IO4_Msk                          /*!<GROUP4_IO4 sampling mode */
#define TSC_IOSCR_G5_IO1_Pos     (16UL)
#define TSC_IOSCR_G5_IO1_Msk     (0x1UL << TSC_IOSCR_G5_IO1_Pos)               /*!< 0x00010000 */
#define TSC_IOSCR_G5_IO1         TSC_IOSCR_G5_IO1_Msk                          /*!<GROUP5_IO1 sampling mode */
#define TSC_IOSCR_G5_IO2_Pos     (17UL)
#define TSC_IOSCR_G5_IO2_Msk     (0x1UL << TSC_IOSCR_G5_IO2_Pos)               /*!< 0x00020000 */
#define TSC_IOSCR_G5_IO2         TSC_IOSCR_G5_IO2_Msk                          /*!<GROUP5_IO2 sampling mode */
#define TSC_IOSCR_G5_IO3_Pos     (18UL)
#define TSC_IOSCR_G5_IO3_Msk     (0x1UL << TSC_IOSCR_G5_IO3_Pos)               /*!< 0x00040000 */
#define TSC_IOSCR_G5_IO3         TSC_IOSCR_G5_IO3_Msk                          /*!<GROUP5_IO3 sampling mode */
#define TSC_IOSCR_G5_IO4_Pos     (19UL)
#define TSC_IOSCR_G5_IO4_Msk     (0x1UL << TSC_IOSCR_G5_IO4_Pos)               /*!< 0x00080000 */
#define TSC_IOSCR_G5_IO4         TSC_IOSCR_G5_IO4_Msk                          /*!<GROUP5_IO4 sampling mode */
#define TSC_IOSCR_G6_IO1_Pos     (20UL)
#define TSC_IOSCR_G6_IO1_Msk     (0x1UL << TSC_IOSCR_G6_IO1_Pos)               /*!< 0x00100000 */
#define TSC_IOSCR_G6_IO1         TSC_IOSCR_G6_IO1_Msk                          /*!<GROUP6_IO1 sampling mode */
#define TSC_IOSCR_G6_IO2_Pos     (21UL)
#define TSC_IOSCR_G6_IO2_Msk     (0x1UL << TSC_IOSCR_G6_IO2_Pos)               /*!< 0x00200000 */
#define TSC_IOSCR_G6_IO2         TSC_IOSCR_G6_IO2_Msk                          /*!<GROUP6_IO2 sampling mode */
#define TSC_IOSCR_G6_IO3_Pos     (22UL)
#define TSC_IOSCR_G6_IO3_Msk     (0x1UL << TSC_IOSCR_G6_IO3_Pos)               /*!< 0x00400000 */
#define TSC_IOSCR_G6_IO3         TSC_IOSCR_G6_IO3_Msk                          /*!<GROUP6_IO3 sampling mode */
#define TSC_IOSCR_G6_IO4_Pos     (23UL)
#define TSC_IOSCR_G6_IO4_Msk     (0x1UL << TSC_IOSCR_G6_IO4_Pos)               /*!< 0x00800000 */
#define TSC_IOSCR_G6_IO4         TSC_IOSCR_G6_IO4_Msk                          /*!<GROUP6_IO4 sampling mode */
#define TSC_IOSCR_G7_IO1_Pos     (24UL)
#define TSC_IOSCR_G7_IO1_Msk     (0x1UL << TSC_IOSCR_G7_IO1_Pos)               /*!< 0x01000000 */
#define TSC_IOSCR_G7_IO1         TSC_IOSCR_G7_IO1_Msk                          /*!<GROUP7_IO1 sampling mode */
#define TSC_IOSCR_G7_IO2_Pos     (25UL)
#define TSC_IOSCR_G7_IO2_Msk     (0x1UL << TSC_IOSCR_G7_IO2_Pos)               /*!< 0x02000000 */
#define TSC_IOSCR_G7_IO2         TSC_IOSCR_G7_IO2_Msk                          /*!<GROUP7_IO2 sampling mode */
#define TSC_IOSCR_G7_IO3_Pos     (26UL)
#define TSC_IOSCR_G7_IO3_Msk     (0x1UL << TSC_IOSCR_G7_IO3_Pos)               /*!< 0x04000000 */
#define TSC_IOSCR_G7_IO3         TSC_IOSCR_G7_IO3_Msk                          /*!<GROUP7_IO3 sampling mode */
#define TSC_IOSCR_G7_IO4_Pos     (27UL)
#define TSC_IOSCR_G7_IO4_Msk     (0x1UL << TSC_IOSCR_G7_IO4_Pos)               /*!< 0x08000000 */
#define TSC_IOSCR_G7_IO4         TSC_IOSCR_G7_IO4_Msk                          /*!<GROUP7_IO4 sampling mode */

/*******************  Bit definition for TSC_IOCCR register  ******************/
#define TSC_IOCCR_G1_IO1_Pos     (0UL)
#define TSC_IOCCR_G1_IO1_Msk     (0x1UL << TSC_IOCCR_G1_IO1_Pos)               /*!< 0x00000001 */
#define TSC_IOCCR_G1_IO1         TSC_IOCCR_G1_IO1_Msk                          /*!<GROUP1_IO1 channel mode */
#define TSC_IOCCR_G1_IO2_Pos     (1UL)
#define TSC_IOCCR_G1_IO2_Msk     (0x1UL << TSC_IOCCR_G1_IO2_Pos)               /*!< 0x00000002 */
#define TSC_IOCCR_G1_IO2         TSC_IOCCR_G1_IO2_Msk                          /*!<GROUP1_IO2 channel mode */
#define TSC_IOCCR_G1_IO3_Pos     (2UL)
#define TSC_IOCCR_G1_IO3_Msk     (0x1UL << TSC_IOCCR_G1_IO3_Pos)               /*!< 0x00000004 */
#define TSC_IOCCR_G1_IO3         TSC_IOCCR_G1_IO3_Msk                          /*!<GROUP1_IO3 channel mode */
#define TSC_IOCCR_G1_IO4_Pos     (3UL)
#define TSC_IOCCR_G1_IO4_Msk     (0x1UL << TSC_IOCCR_G1_IO4_Pos)               /*!< 0x00000008 */
#define TSC_IOCCR_G1_IO4         TSC_IOCCR_G1_IO4_Msk                          /*!<GROUP1_IO4 channel mode */
#define TSC_IOCCR_G2_IO1_Pos     (4UL)
#define TSC_IOCCR_G2_IO1_Msk     (0x1UL << TSC_IOCCR_G2_IO1_Pos)               /*!< 0x00000010 */
#define TSC_IOCCR_G2_IO1         TSC_IOCCR_G2_IO1_Msk                          /*!<GROUP2_IO1 channel mode */
#define TSC_IOCCR_G2_IO2_Pos     (5UL)
#define TSC_IOCCR_G2_IO2_Msk     (0x1UL << TSC_IOCCR_G2_IO2_Pos)               /*!< 0x00000020 */
#define TSC_IOCCR_G2_IO2         TSC_IOCCR_G2_IO2_Msk                          /*!<GROUP2_IO2 channel mode */
#define TSC_IOCCR_G2_IO3_Pos     (6UL)
#define TSC_IOCCR_G2_IO3_Msk     (0x1UL << TSC_IOCCR_G2_IO3_Pos)               /*!< 0x00000040 */
#define TSC_IOCCR_G2_IO3         TSC_IOCCR_G2_IO3_Msk                          /*!<GROUP2_IO3 channel mode */
#define TSC_IOCCR_G2_IO4_Pos     (7UL)
#define TSC_IOCCR_G2_IO4_Msk     (0x1UL << TSC_IOCCR_G2_IO4_Pos)               /*!< 0x00000080 */
#define TSC_IOCCR_G2_IO4         TSC_IOCCR_G2_IO4_Msk                          /*!<GROUP2_IO4 channel mode */
#define TSC_IOCCR_G3_IO1_Pos     (8UL)
#define TSC_IOCCR_G3_IO1_Msk     (0x1UL << TSC_IOCCR_G3_IO1_Pos)               /*!< 0x00000100 */
#define TSC_IOCCR_G3_IO1         TSC_IOCCR_G3_IO1_Msk                          /*!<GROUP3_IO1 channel mode */
#define TSC_IOCCR_G3_IO2_Pos     (9UL)
#define TSC_IOCCR_G3_IO2_Msk     (0x1UL << TSC_IOCCR_G3_IO2_Pos)               /*!< 0x00000200 */
#define TSC_IOCCR_G3_IO2         TSC_IOCCR_G3_IO2_Msk                          /*!<GROUP3_IO2 channel mode */
#define TSC_IOCCR_G3_IO3_Pos     (10UL)
#define TSC_IOCCR_G3_IO3_Msk     (0x1UL << TSC_IOCCR_G3_IO3_Pos)               /*!< 0x00000400 */
#define TSC_IOCCR_G3_IO3         TSC_IOCCR_G3_IO3_Msk                          /*!<GROUP3_IO3 channel mode */
#define TSC_IOCCR_G3_IO4_Pos     (11UL)
#define TSC_IOCCR_G3_IO4_Msk     (0x1UL << TSC_IOCCR_G3_IO4_Pos)               /*!< 0x00000800 */
#define TSC_IOCCR_G3_IO4         TSC_IOCCR_G3_IO4_Msk                          /*!<GROUP3_IO4 channel mode */
#define TSC_IOCCR_G4_IO1_Pos     (12UL)
#define TSC_IOCCR_G4_IO1_Msk     (0x1UL << TSC_IOCCR_G4_IO1_Pos)               /*!< 0x00001000 */
#define TSC_IOCCR_G4_IO1         TSC_IOCCR_G4_IO1_Msk                          /*!<GROUP4_IO1 channel mode */
#define TSC_IOCCR_G4_IO2_Pos     (13UL)
#define TSC_IOCCR_G4_IO2_Msk     (0x1UL << TSC_IOCCR_G4_IO2_Pos)               /*!< 0x00002000 */
#define TSC_IOCCR_G4_IO2         TSC_IOCCR_G4_IO2_Msk                          /*!<GROUP4_IO2 channel mode */
#define TSC_IOCCR_G4_IO3_Pos     (14UL)
#define TSC_IOCCR_G4_IO3_Msk     (0x1UL << TSC_IOCCR_G4_IO3_Pos)               /*!< 0x00004000 */
#define TSC_IOCCR_G4_IO3         TSC_IOCCR_G4_IO3_Msk                          /*!<GROUP4_IO3 channel mode */
#define TSC_IOCCR_G4_IO4_Pos     (15UL)
#define TSC_IOCCR_G4_IO4_Msk     (0x1UL << TSC_IOCCR_G4_IO4_Pos)               /*!< 0x00008000 */
#define TSC_IOCCR_G4_IO4         TSC_IOCCR_G4_IO4_Msk                          /*!<GROUP4_IO4 channel mode */
#define TSC_IOCCR_G5_IO1_Pos     (16UL)
#define TSC_IOCCR_G5_IO1_Msk     (0x1UL << TSC_IOCCR_G5_IO1_Pos)               /*!< 0x00010000 */
#define TSC_IOCCR_G5_IO1         TSC_IOCCR_G5_IO1_Msk                          /*!<GROUP5_IO1 channel mode */
#define TSC_IOCCR_G5_IO2_Pos     (17UL)
#define TSC_IOCCR_G5_IO2_Msk     (0x1UL << TSC_IOCCR_G5_IO2_Pos)               /*!< 0x00020000 */
#define TSC_IOCCR_G5_IO2         TSC_IOCCR_G5_IO2_Msk                          /*!<GROUP5_IO2 channel mode */
#define TSC_IOCCR_G5_IO3_Pos     (18UL)
#define TSC_IOCCR_G5_IO3_Msk     (0x1UL << TSC_IOCCR_G5_IO3_Pos)               /*!< 0x00040000 */
#define TSC_IOCCR_G5_IO3         TSC_IOCCR_G5_IO3_Msk                          /*!<GROUP5_IO3 channel mode */
#define TSC_IOCCR_G5_IO4_Pos     (19UL)
#define TSC_IOCCR_G5_IO4_Msk     (0x1UL << TSC_IOCCR_G5_IO4_Pos)               /*!< 0x00080000 */
#define TSC_IOCCR_G5_IO4         TSC_IOCCR_G5_IO4_Msk                          /*!<GROUP5_IO4 channel mode */
#define TSC_IOCCR_G6_IO1_Pos     (20UL)
#define TSC_IOCCR_G6_IO1_Msk     (0x1UL << TSC_IOCCR_G6_IO1_Pos)               /*!< 0x00100000 */
#define TSC_IOCCR_G6_IO1         TSC_IOCCR_G6_IO1_Msk                          /*!<GROUP6_IO1 channel mode */
#define TSC_IOCCR_G6_IO2_Pos     (21UL)
#define TSC_IOCCR_G6_IO2_Msk     (0x1UL << TSC_IOCCR_G6_IO2_Pos)               /*!< 0x00200000 */
#define TSC_IOCCR_G6_IO2         TSC_IOCCR_G6_IO2_Msk                          /*!<GROUP6_IO2 channel mode */
#define TSC_IOCCR_G6_IO3_Pos     (22UL)
#define TSC_IOCCR_G6_IO3_Msk     (0x1UL << TSC_IOCCR_G6_IO3_Pos)               /*!< 0x00400000 */
#define TSC_IOCCR_G6_IO3         TSC_IOCCR_G6_IO3_Msk                          /*!<GROUP6_IO3 channel mode */
#define TSC_IOCCR_G6_IO4_Pos     (23UL)
#define TSC_IOCCR_G6_IO4_Msk     (0x1UL << TSC_IOCCR_G6_IO4_Pos)               /*!< 0x00800000 */
#define TSC_IOCCR_G6_IO4         TSC_IOCCR_G6_IO4_Msk                          /*!<GROUP6_IO4 channel mode */
#define TSC_IOCCR_G7_IO1_Pos     (24UL)
#define TSC_IOCCR_G7_IO1_Msk     (0x1UL << TSC_IOCCR_G7_IO1_Pos)               /*!< 0x01000000 */
#define TSC_IOCCR_G7_IO1         TSC_IOCCR_G7_IO1_Msk                          /*!<GROUP7_IO1 channel mode */
#define TSC_IOCCR_G7_IO2_Pos     (25UL)
#define TSC_IOCCR_G7_IO2_Msk     (0x1UL << TSC_IOCCR_G7_IO2_Pos)               /*!< 0x02000000 */
#define TSC_IOCCR_G7_IO2         TSC_IOCCR_G7_IO2_Msk                          /*!<GROUP7_IO2 channel mode */
#define TSC_IOCCR_G7_IO3_Pos     (26UL)
#define TSC_IOCCR_G7_IO3_Msk     (0x1UL << TSC_IOCCR_G7_IO3_Pos)               /*!< 0x04000000 */
#define TSC_IOCCR_G7_IO3         TSC_IOCCR_G7_IO3_Msk                          /*!<GROUP7_IO3 channel mode */
#define TSC_IOCCR_G7_IO4_Pos     (27UL)
#define TSC_IOCCR_G7_IO4_Msk     (0x1UL << TSC_IOCCR_G7_IO4_Pos)               /*!< 0x08000000 */
#define TSC_IOCCR_G7_IO4         TSC_IOCCR_G7_IO4_Msk                          /*!<GROUP7_IO4 channel mode */

/*******************  Bit definition for TSC_IOGCSR register  *****************/
#define TSC_IOGCSR_G1E_Pos       (0UL)
#define TSC_IOGCSR_G1E_Msk       (0x1UL << TSC_IOGCSR_G1E_Pos)                 /*!< 0x00000001 */
#define TSC_IOGCSR_G1E           TSC_IOGCSR_G1E_Msk                            /*!<Analog IO GROUP1 enable */
#define TSC_IOGCSR_G2E_Pos       (1UL)
#define TSC_IOGCSR_G2E_Msk       (0x1UL << TSC_IOGCSR_G2E_Pos)                 /*!< 0x00000002 */
#define TSC_IOGCSR_G2E           TSC_IOGCSR_G2E_Msk                            /*!<Analog IO GROUP2 enable */
#define TSC_IOGCSR_G3E_Pos       (2UL)
#define TSC_IOGCSR_G3E_Msk       (0x1UL << TSC_IOGCSR_G3E_Pos)                 /*!< 0x00000004 */
#define TSC_IOGCSR_G3E           TSC_IOGCSR_G3E_Msk                            /*!<Analog IO GROUP3 enable */
#define TSC_IOGCSR_G4E_Pos       (3UL)
#define TSC_IOGCSR_G4E_Msk       (0x1UL << TSC_IOGCSR_G4E_Pos)                 /*!< 0x00000008 */
#define TSC_IOGCSR_G4E           TSC_IOGCSR_G4E_Msk                            /*!<Analog IO GROUP4 enable */
#define TSC_IOGCSR_G5E_Pos       (4UL)
#define TSC_IOGCSR_G5E_Msk       (0x1UL << TSC_IOGCSR_G5E_Pos)                 /*!< 0x00000010 */
#define TSC_IOGCSR_G5E           TSC_IOGCSR_G5E_Msk                            /*!<Analog IO GROUP5 enable */
#define TSC_IOGCSR_G6E_Pos       (5UL)
#define TSC_IOGCSR_G6E_Msk       (0x1UL << TSC_IOGCSR_G6E_Pos)                 /*!< 0x00000020 */
#define TSC_IOGCSR_G6E           TSC_IOGCSR_G6E_Msk                            /*!<Analog IO GROUP6 enable */
#define TSC_IOGCSR_G7E_Pos       (6UL)
#define TSC_IOGCSR_G7E_Msk       (0x1UL << TSC_IOGCSR_G7E_Pos)                 /*!< 0x00000040 */
#define TSC_IOGCSR_G7E           TSC_IOGCSR_G7E_Msk                            /*!<Analog IO GROUP7 enable */
#define TSC_IOGCSR_G8E_Pos       (7UL)
#define TSC_IOGCSR_G8E_Msk       (0x1UL << TSC_IOGCSR_G8E_Pos)                 /*!< 0x00000080 */
#define TSC_IOGCSR_G8E           TSC_IOGCSR_G8E_Msk                            /*!<Analog IO GROUP8 enable */
#define TSC_IOGCSR_G1S_Pos       (16UL)
#define TSC_IOGCSR_G1S_Msk       (0x1UL << TSC_IOGCSR_G1S_Pos)                 /*!< 0x00010000 */
#define TSC_IOGCSR_G1S           TSC_IOGCSR_G1S_Msk                            /*!<Analog IO GROUP1 status */
#define TSC_IOGCSR_G2S_Pos       (17UL)
#define TSC_IOGCSR_G2S_Msk       (0x1UL << TSC_IOGCSR_G2S_Pos)                 /*!< 0x00020000 */
#define TSC_IOGCSR_G2S           TSC_IOGCSR_G2S_Msk                            /*!<Analog IO GROUP2 status */
#define TSC_IOGCSR_G3S_Pos       (18UL)
#define TSC_IOGCSR_G3S_Msk       (0x1UL << TSC_IOGCSR_G3S_Pos)                 /*!< 0x00040000 */
#define TSC_IOGCSR_G3S           TSC_IOGCSR_G3S_Msk                            /*!<Analog IO GROUP3 status */
#define TSC_IOGCSR_G4S_Pos       (19UL)
#define TSC_IOGCSR_G4S_Msk       (0x1UL << TSC_IOGCSR_G4S_Pos)                 /*!< 0x00080000 */
#define TSC_IOGCSR_G4S           TSC_IOGCSR_G4S_Msk                            /*!<Analog IO GROUP4 status */
#define TSC_IOGCSR_G5S_Pos       (20UL)
#define TSC_IOGCSR_G5S_Msk       (0x1UL << TSC_IOGCSR_G5S_Pos)                 /*!< 0x00100000 */
#define TSC_IOGCSR_G5S           TSC_IOGCSR_G5S_Msk                            /*!<Analog IO GROUP5 status */
#define TSC_IOGCSR_G6S_Pos       (21UL)
#define TSC_IOGCSR_G6S_Msk       (0x1UL << TSC_IOGCSR_G6S_Pos)                 /*!< 0x00200000 */
#define TSC_IOGCSR_G6S           TSC_IOGCSR_G6S_Msk                            /*!<Analog IO GROUP6 status */
#define TSC_IOGCSR_G7S_Pos       (22UL)
#define TSC_IOGCSR_G7S_Msk       (0x1UL << TSC_IOGCSR_G7S_Pos)                 /*!< 0x00400000 */
#define TSC_IOGCSR_G7S           TSC_IOGCSR_G7S_Msk                            /*!<Analog IO GROUP7 status */

/*******************  Bit definition for TSC_IOGXCR register  *****************/
#define TSC_IOGXCR_CNT_Pos       (0UL)
#define TSC_IOGXCR_CNT_Msk       (0x3FFFUL << TSC_IOGXCR_CNT_Pos)              /*!< 0x00003FFF */
#define TSC_IOGXCR_CNT           TSC_IOGXCR_CNT_Msk                            /*!<CNT[13:0] bits (Counter value) */

/******************************************************************************/
/*                                                                            */
/*                         USB Dual Role Device FS Endpoint registers         */
/*                                                                            */
/******************************************************************************/

/******************  Bits definition for USB_DRD_CNTR register  *******************/
#define USB_CNTR_HOST_Pos               (31UL)
#define USB_CNTR_HOST_Msk               (0x1UL << USB_CNTR_HOST_Pos)    /*!< 0x80000000 */
#define USB_CNTR_HOST                   USB_CNTR_HOST_Msk               /*!< Host Mode  */
#define USB_CNTR_THR512M_Pos            (16UL)
#define USB_CNTR_THR512M_Msk            (0x1UL << USB_CNTR_THR512M_Pos)  /*!< 0x00010000 */
#define USB_CNTR_THR512M                USB_CNTR_THR512M_Msk             /*!< 512byte Threshold interrupt mask */
#define USB_CNTR_CTRM_Pos               (15UL)
#define USB_CNTR_CTRM_Msk               (0x1UL << USB_CNTR_CTRM_Pos)    /*!< 0x00008000 */
#define USB_CNTR_CTRM                   USB_CNTR_CTRM_Msk               /*!< Correct Transfer Mask */
#define USB_CNTR_PMAOVRM_Pos            (14UL)
#define USB_CNTR_PMAOVRM_Msk            (0x1UL << USB_CNTR_PMAOVRM_Pos) /*!< 0x00004000 */
#define USB_CNTR_PMAOVRM                USB_CNTR_PMAOVRM_Msk            /*!< DMA OVeR/underrun Mask */
#define USB_CNTR_ERRM_Pos               (13UL)
#define USB_CNTR_ERRM_Msk               (0x1UL << USB_CNTR_ERRM_Pos)    /*!< 0x00002000 */
#define USB_CNTR_ERRM                   USB_CNTR_ERRM_Msk               /*!< ERRor Mask */
#define USB_CNTR_WKUPM_Pos              (12UL)
#define USB_CNTR_WKUPM_Msk              (0x1UL << USB_CNTR_WKUPM_Pos)   /*!< 0x00001000 */
#define USB_CNTR_WKUPM                  USB_CNTR_WKUPM_Msk              /*!< WaKe UP Mask */
#define USB_CNTR_SUSPM_Pos              (11UL)
#define USB_CNTR_SUSPM_Msk              (0x1UL << USB_CNTR_SUSPM_Pos)   /*!< 0x00000800 */
#define USB_CNTR_SUSPM                  USB_CNTR_SUSPM_Msk              /*!< SUSPend Mask */
#define USB_CNTR_RESETM_Pos             (10UL)
#define USB_CNTR_RESETM_Msk             (0x1UL << USB_CNTR_RESETM_Pos)  /*!< 0x00000400 */
#define USB_CNTR_RESETM                 USB_CNTR_RESETM_Msk             /*!< RESET Mask */
#define USB_CNTR_DCON                   USB_CNTR_RESETM_Msk             /*!< Disconnection Connection Mask */
#define USB_CNTR_SOFM_Pos               (9UL)
#define USB_CNTR_SOFM_Msk               (0x1UL << USB_CNTR_SOFM_Pos)    /*!< 0x00000200 */
#define USB_CNTR_SOFM                   USB_CNTR_SOFM_Msk               /*!< Start Of Frame Mask */
#define USB_CNTR_ESOFM_Pos              (8UL)
#define USB_CNTR_ESOFM_Msk              (0x1UL << USB_CNTR_ESOFM_Pos)   /*!< 0x00000100 */
#define USB_CNTR_ESOFM                  USB_CNTR_ESOFM_Msk              /*!< Expected Start Of Frame Mask */
#define USB_CNTR_L1REQM_Pos             (7UL)
#define USB_CNTR_L1REQM_Msk             (0x1UL << USB_CNTR_L1REQM_Pos)  /*!< 0x00000080 */
#define USB_CNTR_L1REQM                 USB_CNTR_L1REQM_Msk             /*!< LPM L1 state request interrupt Mask */
#define USB_CNTR_L1XACT_Pos             (6UL)
#define USB_CNTR_L1XACT_Msk             (0x1UL << USB_CNTR_L1XACT_Pos)  /*!< 0x00000040 */
#define USB_CNTR_L1XACT                 USB_CNTR_L1XACT_Msk             /*!< Host LPM L1 transaction request Mask */
#define USB_CNTR_L1RES_Pos              (5UL)
#define USB_CNTR_L1RES_Msk              (0x1UL << USB_CNTR_L1RES_Pos)   /*!< 0x00000020 */
#define USB_CNTR_L1RES                  USB_CNTR_L1RES_Msk              /*!< LPM L1 Resume request/ Remote Wakeup Mask */
#define USB_CNTR_L2RES_Pos              (4UL)
#define USB_CNTR_L2RES_Msk              (0x1UL << USB_CNTR_L2RES_Pos)   /*!< 0x00000010 */
#define USB_CNTR_L2RES                  USB_CNTR_L2RES_Msk              /*!< L2 Remote Wakeup / Resume driver Mask */
#define USB_CNTR_SUSPEN_Pos             (3UL)
#define USB_CNTR_SUSPEN_Msk             (0x1UL << USB_CNTR_SUSPEN_Pos)  /*!< 0x00000008 */
#define USB_CNTR_SUSPEN                 USB_CNTR_SUSPEN_Msk             /*!< Suspend state enable Mask */
#define USB_CNTR_SUSPRDY_Pos            (2UL)
#define USB_CNTR_SUSPRDY_Msk            (0x1UL << USB_CNTR_SUSPRDY_Pos) /*!< 0x00000004 */
#define USB_CNTR_SUSPRDY                USB_CNTR_SUSPRDY_Msk            /*!< Suspend state effective Mask */
#define USB_CNTR_PDWN_Pos               (1UL)
#define USB_CNTR_PDWN_Msk               (0x1UL << USB_CNTR_PDWN_Pos)    /*!< 0x00000002 */
#define USB_CNTR_PDWN                   USB_CNTR_PDWN_Msk               /*!< Power DoWN Mask */
#define USB_CNTR_USBRST_Pos             (0UL)
#define USB_CNTR_USBRST_Msk             (0x1UL << USB_CNTR_USBRST_Pos)  /*!< 0x00000001 */
#define USB_CNTR_USBRST                 USB_CNTR_USBRST_Msk             /*!< USB Reset Mask */

/******************  Bits definition for USB_DRD_ISTR register  *******************/
#define USB_ISTR_IDN_Pos                (0UL)
#define USB_ISTR_IDN_Msk                (0xFUL << USB_ISTR_IDN_Pos)     /*!< 0x0000000F */
#define USB_ISTR_IDN                    USB_ISTR_IDN_Msk                /*!< EndPoint IDentifier (read-only bit) Mask */
#define USB_ISTR_DIR_Pos                (4UL)
#define USB_ISTR_DIR_Msk                (0x1UL << USB_ISTR_DIR_Pos)     /*!< 0x00000010 */
#define USB_ISTR_DIR                    USB_ISTR_DIR_Msk                /*!< DIRection of transaction (read-only bit) Mask */
#define USB_ISTR_L1REQ_Pos              (7UL)
#define USB_ISTR_L1REQ_Msk              (0x1UL << USB_ISTR_L1REQ_Pos)   /*!< 0x00000080 */
#define USB_ISTR_L1REQ                  USB_ISTR_L1REQ_Msk              /*!< LPM L1 state request Mask */
#define USB_ISTR_ESOF_Pos               (8UL)
#define USB_ISTR_ESOF_Msk               (0x1UL << USB_ISTR_ESOF_Pos)    /*!< 0x00000100 */
#define USB_ISTR_ESOF                   USB_ISTR_ESOF_Msk               /*!< Expected Start Of Frame (clear-only bit) Mask */
#define USB_ISTR_SOF_Pos                (9UL)
#define USB_ISTR_SOF_Msk                (0x1UL << USB_ISTR_SOF_Pos)     /*!< 0x00000200 */
#define USB_ISTR_SOF                    USB_ISTR_SOF_Msk                /*!< Start Of Frame (clear-only bit) Mask */
#define USB_ISTR_RESET_Pos              (10UL)
#define USB_ISTR_RESET_Msk              (0x1UL << USB_ISTR_RESET_Pos)   /*!< 0x00000400 */
#define USB_ISTR_RESET                  USB_ISTR_RESET_Msk              /*!< RESET Mask */
#define USB_ISTR_DCON_Pos               (10UL)
#define USB_ISTR_DCON_Msk               (0x1UL << USB_ISTR_DCON_Pos)    /*!< 0x00000400 */
#define USB_ISTR_DCON                   USB_ISTR_DCON_Msk               /*!< HOST MODE-Device Connection or disconnection Mask */
#define USB_ISTR_SUSP_Pos               (11UL)
#define USB_ISTR_SUSP_Msk               (0x1UL << USB_ISTR_SUSP_Pos)    /*!< 0x00000800 */
#define USB_ISTR_SUSP                   USB_ISTR_SUSP_Msk               /*!< SUSPend (clear-only bit) Mask */
#define USB_ISTR_WKUP_Pos               (12UL)
#define USB_ISTR_WKUP_Msk               (0x1UL << USB_ISTR_WKUP_Pos)    /*!< 0x00001000 */
#define USB_ISTR_WKUP                   USB_ISTR_WKUP_Msk               /*!< WaKe UP (clear-only bit) Mask */
#define USB_ISTR_ERR_Pos                (13UL)
#define USB_ISTR_ERR_Msk                (0x1UL << USB_ISTR_ERR_Pos)     /*!< 0x00002000 */
#define USB_ISTR_ERR                    USB_ISTR_ERR_Msk                /*!< ERRor (clear-only bit) Mask */
#define USB_ISTR_PMAOVR_Pos             (14UL)
#define USB_ISTR_PMAOVR_Msk             (0x1UL << USB_ISTR_PMAOVR_Pos)  /*!< 0x00004000 */
#define USB_ISTR_PMAOVR                 USB_ISTR_PMAOVR_Msk             /*!< PMA OVeR/underrun (clear-only bit) Mask */
#define USB_ISTR_CTR_Pos                (15UL)
#define USB_ISTR_CTR_Msk                (0x1UL << USB_ISTR_CTR_Pos)     /*!< 0x00008000 */
#define USB_ISTR_CTR                    USB_ISTR_CTR_Msk                /*!< Correct TRansfer (clear-only bit) Mask */
#define USB_ISTR_THR512_Pos             (16UL)
#define USB_ISTR_THR512_Msk             (0x1UL << USB_ISTR_THR512_Pos)  /*!< 0x00010000 */
#define USB_ISTR_THR512                 USB_ISTR_THR512_Msk             /*!< 512byte threshold interrupt (used with isochrnous single buffer ) */
#define USB_ISTR_DCON_STAT_Pos          (29UL)
#define USB_ISTR_DCON_STAT_Msk          (0x1UL << USB_ISTR_DCON_STAT_Pos)/*!< 0x20000000 */
#define USB_ISTR_DCON_STAT              USB_ISTR_DCON_STAT_Msk           /*!< Device Connection status (connected/Disconnected) don't cause an interrupt */
#define USB_ISTR_LS_DCONN_Pos           (30UL)
#define USB_ISTR_LS_DCONN_Msk           (0x1UL << USB_ISTR_LS_DCONN_Pos)/*!< 0x40000000 */
#define USB_ISTR_LS_DCONN               USB_ISTR_LS_DCONN_Msk           /*!< LS_DCONN Mask */

/******************  Bits definition for USB_DRD_FNR register  ********************/
#define USB_FNR_FN_Pos                  (0UL)
#define USB_FNR_FN_Msk                  (0x7FFUL << USB_FNR_FN_Pos)     /*!< 0x000007FF */
#define USB_FNR_FN                      USB_FNR_FN_Msk                  /*!< Frame Number Mask */
#define USB_FNR_LSOF_Pos                (11UL)
#define USB_FNR_LSOF_Msk                (0x3UL << USB_FNR_LSOF_Pos)     /*!< 0x00001800 */
#define USB_FNR_LSOF                    USB_FNR_LSOF_Msk                /*!< Lost SOF  Mask */
#define USB_FNR_LCK_Pos                 (13UL)
#define USB_FNR_LCK_Msk                 (0x1UL << USB_FNR_LCK_Pos)      /*!< 0x00002000 */
#define USB_FNR_LCK                     USB_FNR_LCK_Msk                 /*!< LoCKed Mask */
#define USB_FNR_RXDM_Pos                (14UL)
#define USB_FNR_RXDM_Msk                (0x1UL << USB_FNR_RXDM_Pos)     /*!< 0x00004000 */
#define USB_FNR_RXDM                    USB_FNR_RXDM_Msk                /*!< status of D- data line Mask */
#define USB_FNR_RXDP_Pos                (15UL)
#define USB_FNR_RXDP_Msk                (0x1UL << USB_FNR_RXDP_Pos)     /*!< 0x00008000 */
#define USB_FNR_RXDP                    USB_FNR_RXDP_Msk                /*!< status of D+ data line Mask */

/******************  Bits definition for USB_DRD_DADDR register    ****************/
#define USB_DADDR_ADD_Pos               (0UL)
#define USB_DADDR_ADD_Msk               (0x7FUL << USB_DADDR_ADD_Pos)   /*!< 0x0000007F */
#define USB_DADDR_ADD                   USB_DADDR_ADD_Msk               /*!<  ADD[6:0] bits (Device Address)Mask */
#define USB_DADDR_ADD0_Pos              (0UL)
#define USB_DADDR_ADD0_Msk              (0x1UL << USB_DADDR_ADD0_Pos)   /*!< 0x00000001 */
#define USB_DADDR_ADD0                  USB_DADDR_ADD0_Msk              /*!< Bit 0 Mask */
#define USB_DADDR_ADD1_Pos              (1UL)
#define USB_DADDR_ADD1_Msk              (0x1UL << USB_DADDR_ADD1_Pos)   /*!< 0x00000002 */
#define USB_DADDR_ADD1                  USB_DADDR_ADD1_Msk              /*!< Bit 1 Mask */
#define USB_DADDR_ADD2_Pos              (2UL)
#define USB_DADDR_ADD2_Msk              (0x1UL << USB_DADDR_ADD2_Pos)   /*!< 0x00000004 */
#define USB_DADDR_ADD2                  USB_DADDR_ADD2_Msk              /*!< Bit 2 Mask */
#define USB_DADDR_ADD3_Pos              (3UL)
#define USB_DADDR_ADD3_Msk              (0x1UL << USB_DADDR_ADD3_Pos)   /*!< 0x00000008 */
#define USB_DADDR_ADD3                  USB_DADDR_ADD3_Msk              /*!< Bit 3 Mask */
#define USB_DADDR_ADD4_Pos              (4UL)
#define USB_DADDR_ADD4_Msk              (0x1UL << USB_DADDR_ADD4_Pos)   /*!< 0x00000010 */
#define USB_DADDR_ADD4                  USB_DADDR_ADD4_Msk              /*!< Bit 4 Mask */
#define USB_DADDR_ADD5_Pos              (5UL)
#define USB_DADDR_ADD5_Msk              (0x1UL << USB_DADDR_ADD5_Pos)   /*!< 0x00000020 */
#define USB_DADDR_ADD5                  USB_DADDR_ADD5_Msk              /*!< Bit 5 Mask */
#define USB_DADDR_ADD6_Pos              (6UL)
#define USB_DADDR_ADD6_Msk              (0x1UL << USB_DADDR_ADD6_Pos)   /*!< 0x00000040 */
#define USB_DADDR_ADD6                  USB_DADDR_ADD6_Msk              /*!< Bit 6 Mask */
#define USB_DADDR_EF_Pos                (7UL)
#define USB_DADDR_EF_Msk                (0x1UL << USB_DADDR_EF_Pos)     /*!< 0x00000080 */
#define USB_DADDR_EF                    USB_DADDR_EF_Msk                /*!< Enable Function Mask */

/******************  Bit definition for USB_DRD_BTABLE register  ******************/
#define USB_BTABLE_BTABLE_Pos          (3UL)
#define USB_BTABLE_BTABLE_Msk          (0xFFF8UL << USB_BTABLE_BTABLE_Pos)/*!< 0x00000000 */
#define USB_BTABLE_BTABLE              USB_BTABLE_BTABLE_Msk              /*!< Buffer Table Mask */

/*******************  Bit definition for LPMCSR register  *********************/
#define USB_LPMCSR_LMPEN_Pos           (0UL)
#define USB_LPMCSR_LMPEN_Msk           (0x1UL << USB_LPMCSR_LMPEN_Pos)  /*!< 0x00000001 */
#define USB_LPMCSR_LMPEN               USB_LPMCSR_LMPEN_Msk             /*!< LPM support enable Mask */
#define USB_LPMCSR_LPMACK_Pos          (1UL)
#define USB_LPMCSR_LPMACK_Msk          (0x1UL << USB_LPMCSR_LPMACK_Pos) /*!< 0x00000002 */
#define USB_LPMCSR_LPMACK              USB_LPMCSR_LPMACK_Msk            /*!< LPM Token acknowledge enable Mask */
#define USB_LPMCSR_REMWAKE_Pos         (3UL)
#define USB_LPMCSR_REMWAKE_Msk         (0x1UL << USB_LPMCSR_REMWAKE_Pos)/*!< 0x00000008 */
#define USB_LPMCSR_REMWAKE             USB_LPMCSR_REMWAKE_Msk           /*!< bRemoteWake value received with last ACKed LPM Token Mask */
#define USB_LPMCSR_BESL_Pos            (4UL)
#define USB_LPMCSR_BESL_Msk            (0xFUL << USB_LPMCSR_BESL_Pos)   /*!< 0x000000F0 */
#define USB_LPMCSR_BESL                USB_LPMCSR_BESL_Msk              /*!< BESL value received with last ACKed LPM Token Mask */

/******************  Bits definition for USB_DRD_BCDR register  *******************/
#define USB_BCDR_BCDEN_Pos             (0UL)
#define USB_BCDR_BCDEN_Msk             (0x1UL << USB_BCDR_BCDEN_Pos)    /*!< 0x00000001 */
#define USB_BCDR_BCDEN                 USB_BCDR_BCDEN_Msk               /*!< Battery charging detector (BCD) enable Mask */
#define USB_BCDR_DCDEN_Pos             (1UL)
#define USB_BCDR_DCDEN_Msk             (0x1UL << USB_BCDR_DCDEN_Pos)    /*!< 0x00000002 */
#define USB_BCDR_DCDEN                 USB_BCDR_DCDEN_Msk               /*!< Data contact detection (DCD) mode enable Mask */
#define USB_BCDR_PDEN_Pos              (2UL)
#define USB_BCDR_PDEN_Msk              (0x1UL << USB_BCDR_PDEN_Pos)     /*!< 0x00000004 */
#define USB_BCDR_PDEN                  USB_BCDR_PDEN_Msk                /*!< Primary detection (PD) mode enable Mask */
#define USB_BCDR_SDEN_Pos              (3UL)
#define USB_BCDR_SDEN_Msk              (0x1UL << USB_BCDR_SDEN_Pos)     /*!< 0x00000008 */
#define USB_BCDR_SDEN                  USB_BCDR_SDEN_Msk                /*!< Secondary detection (SD) mode enable Mask */
#define USB_BCDR_DCDET_Pos             (4UL)
#define USB_BCDR_DCDET_Msk             (0x1UL << USB_BCDR_DCDET_Pos)    /*!< 0x00000010 */
#define USB_BCDR_DCDET                 USB_BCDR_DCDET_Msk               /*!< Data contact detection (DCD) status Mask */
#define USB_BCDR_PDET_Pos              (5UL)
#define USB_BCDR_PDET_Msk              (0x1UL << USB_BCDR_PDET_Pos)     /*!< 0x00000020 */
#define USB_BCDR_PDET                  USB_BCDR_PDET_Msk                /*!< Primary detection (PD) status Mask */
#define USB_BCDR_SDET_Pos              (6UL)
#define USB_BCDR_SDET_Msk              (0x1UL << USB_BCDR_SDET_Pos)     /*!< 0x00000040 */
#define USB_BCDR_SDET                  USB_BCDR_SDET_Msk                /*!< Secondary detection (SD) status Mask */
#define USB_BCDR_PS2DET_Pos            (7UL)
#define USB_BCDR_PS2DET_Msk            (0x1UL << USB_BCDR_PS2DET_Pos)   /*!< 0x00000080 */
#define USB_BCDR_PS2DET                USB_BCDR_PS2DET_Msk              /*!< PS2 port or proprietary charger detected Mask */
#define USB_BCDR_DPPU_Pos              (15UL)
#define USB_BCDR_DPPU_Msk              (0x1UL << USB_BCDR_DPPU_Pos)     /*!< 0x00008000 */
#define USB_BCDR_DPPU                  USB_BCDR_DPPU_Msk                /*!< DP Pull-up Enable Mask */
#define USB_BCDR_DPPD_Pos              (15UL)
#define USB_BCDR_DPPD_Msk              (0x1UL << USB_BCDR_DPPD_Pos)     /*!< 0x00008000 */
#define USB_BCDR_DPPD                  USB_BCDR_DPPD_Msk                /*!< DP Pull-Down Enable Mask */

/******************  Bits definition for USB_DRD_CHEP register  *******************/
#define USB_CHEP_ERRRX_Pos             (26UL)
#define USB_CHEP_ERRRX_Msk             (0x01UL << USB_CHEP_ERRRX_Pos)   /*!< 0x04000000 */
#define USB_CHEP_ERRRX                 USB_CHEP_ERRRX_Msk               /*!< Receive error */
#define USB_EP_ERRRX                   USB_CHEP_ERRRX_Msk               /*!< EP Receive error */
#define USB_CH_ERRRX                   USB_CHEP_ERRRX_Msk               /*!< CH Receive error */
#define USB_CHEP_ERRTX_Pos             (25UL)
#define USB_CHEP_ERRTX_Msk             (0x01UL << USB_CHEP_ERRTX_Pos)   /*!< 0x02000000 */
#define USB_CHEP_ERRTX                 USB_CHEP_ERRTX_Msk               /*!< Transmit error */
#define USB_EP_ERRTX                   USB_CHEP_ERRTX_Msk               /*!< EP Transmit error */
#define USB_CH_ERRTX                   USB_CHEP_ERRTX_Msk               /*!< CH Transmit error */
#define USB_CHEP_LSEP_Pos              (24UL)
#define USB_CHEP_LSEP_Msk              (0x01UL << USB_CHEP_LSEP_Pos)    /*!< 0x01000000 */
#define USB_CHEP_LSEP                  USB_CHEP_LSEP_Msk                /*!< Low Speed Endpoint (host with Hub Only) */
#define USB_CHEP_NAK_Pos               (23UL)
#define USB_CHEP_NAK_Msk               (0x01UL << USB_CHEP_NAK_Pos)     /*!< 0x00800000 */
#define USB_CHEP_NAK                   USB_CHEP_NAK_Msk                 /*!< Previous NAK detected */
#define USB_CHEP_DEVADDR_Pos           (16UL)
#define USB_CHEP_DEVADDR_Msk           (0x7FUL << USB_CHEP_DEVADDR_Pos)  /*!< 0x7F000000 */
#define USB_CHEP_DEVADDR               USB_CHEP_DEVADDR_Msk             /* Target Endpoint address*/
#define USB_CHEP_VTRX_Pos              (15UL)
#define USB_CHEP_VTRX_Msk              (0x1UL << USB_CHEP_VTRX_Pos)     /*!< 0x00008000 */
#define USB_CHEP_VTRX                  USB_CHEP_VTRX_Msk                /*!< USB valid transaction received Mask */
#define USB_EP_VTRX                    USB_CHEP_VTRX_Msk                /*!< USB Endpoint valid transaction received Mask */
#define USB_CH_VTRX                    USB_CHEP_VTRX_Msk                /*!< USB valid Channel transaction received Mask */
#define USB_CHEP_DTOG_RX_Pos           (14UL)
#define USB_CHEP_DTOG_RX_Msk           (0x1UL << USB_CHEP_DTOG_RX_Pos)  /*!< 0x00004000 */
#define USB_CHEP_DTOG_RX               USB_CHEP_DTOG_RX_Msk             /*!< Data Toggle, for reception transfers Mask */
#define USB_EP_DTOG_RX                 USB_CHEP_DTOG_RX_Msk             /*!< EP Data Toggle, for reception transfers Mask */
#define USB_CH_DTOG_RX                 USB_CHEP_DTOG_RX_Msk             /*!< CH Data Toggle, for reception transfers Mask */
#define USB_CHEP_RX_STRX_Pos           (12UL)
#define USB_CHEP_RX_STRX_Msk           (0x3UL << USB_CHEP_RX_STRX_Pos)  /*!< 0x00003000 */
#define USB_CHEP_RX_STRX               USB_CHEP_RX_STRX_Msk             /*!< Status bits, for reception transfers Mask */
#define USB_EP_RX_STRX                 USB_CHEP_RX_STRX_Msk             /*!< Status bits, for EP reception transfers Mask */
#define USB_CH_RX_STRX                 USB_CHEP_RX_STRX_Msk             /*!< Status bits, for CH reception transfers Mask */
#define USB_CHEP_SETUP_Pos             (11UL)
#define USB_CHEP_SETUP_Msk             (0x1UL << USB_CHEP_SETUP_Pos)    /*!< 0x00000800 */
#define USB_CHEP_SETUP                 USB_CHEP_SETUP_Msk               /*!< Setup transaction completed Mask */
#define USB_EP_SETUP                   USB_CHEP_SETUP_Msk               /*!< EP Setup transaction completed Mask */
#define USB_CH_SETUP                   USB_CHEP_SETUP_Msk               /*!< CH Setup transaction completed Mask */
#define USB_CHEP_UTYPE_Pos             (9UL)
#define USB_CHEP_UTYPE_Msk             (0x3UL << USB_CHEP_UTYPE_Pos)    /*!< 0x00000600 */
#define USB_CHEP_UTYPE                 USB_CHEP_UTYPE_Msk               /*!< USB type of transaction Mask */
#define USB_EP_UTYPE                   USB_CHEP_UTYPE_Msk               /*!< USB type of EP transaction Mask */
#define USB_CH_UTYPE                   USB_CHEP_UTYPE_Msk               /*!< USB type of CH transaction Mask */
#define USB_CHEP_KIND_Pos              (8UL)
#define USB_CHEP_KIND_Msk              (0x1UL << USB_CHEP_KIND_Pos)     /*!< 0x00000100 */
#define USB_CHEP_KIND                  USB_CHEP_KIND_Msk                /*!< EndPoint KIND Mask */
#define USB_EP_KIND                    USB_CHEP_KIND_Msk                /*!< EndPoint KIND Mask */
#define USB_CH_KIND                    USB_CHEP_KIND_Msk                /*!< Channel KIND Mask */
#define USB_CHEP_VTTX_Pos              (7UL)
#define USB_CHEP_VTTX_Msk              (0x1UL << USB_CHEP_VTTX_Pos)     /*!< 0x00000080 */
#define USB_CHEP_VTTX                  USB_CHEP_VTTX_Msk                /*!< Valid USB transaction transmitted Mask */
#define USB_EP_VTTX                    USB_CHEP_VTTX_Msk                /*!< USB Endpoint valid transaction transmitted Mask */
#define USB_CH_VTTX                    USB_CHEP_VTTX_Msk                /*!< USB valid Channel transaction transmitted Mask */
#define USB_CHEP_DTOG_TX_Pos           (6UL)
#define USB_CHEP_DTOG_TX_Msk           (0x1UL << USB_CHEP_DTOG_TX_Pos)  /*!< 0x00000040 */
#define USB_CHEP_DTOG_TX               USB_CHEP_DTOG_TX_Msk             /*!< Data Toggle, for transmission transfers Mask */
#define USB_EP_DTOG_TX                 USB_CHEP_DTOG_TX_Msk             /*!< EP Data Toggle, for transmission transfers Mask */
#define USB_CH_DTOG_TX                 USB_CHEP_DTOG_TX_Msk             /*!< CH Data Toggle, for transmission transfers Mask */
#define USB_CHEP_TX_STTX_Pos           (4UL)
#define USB_CHEP_TX_STTX_Msk           (0x3UL << USB_CHEP_TX_STTX_Pos)  /*!< 0x00000030 */
#define USB_CHEP_TX_STTX               USB_CHEP_TX_STTX_Msk             /*!< Status bits, for transmission transfers Mask */
#define USB_EP_TX_STTX                 USB_CHEP_TX_STTX_Msk             /*!< Status bits, for EP transmission transfers Mask */
#define USB_CH_TX_STTX                 USB_CHEP_TX_STTX_Msk             /*!< Status bits, for CH transmission transfers Mask */
#define USB_CHEP_ADDR_Pos              (0UL)
#define USB_CHEP_ADDR_Msk              (0xFUL << USB_CHEP_ADDR_Pos)     /*!< 0x0000000F */
#define USB_CHEP_ADDR                  USB_CHEP_ADDR_Msk                /*!< Endpoint address Mask */


/* EndPoint Register MASK (no toggle fields) */
#define USB_CHEP_REG_MASK                          (USB_CHEP_ERRRX | USB_CHEP_ERRTX | USB_CHEP_LSEP | \
                                                    USB_CHEP_DEVADDR | USB_CHEP_VTRX | USB_CHEP_SETUP | \
                                                    USB_CHEP_UTYPE | USB_CHEP_KIND | USB_CHEP_VTTX | USB_CHEP_ADDR | \
                                                    USB_CHEP_NAK) /* 0x07FF8F8F */

#define USB_CHEP_TX_DTOGMASK                       (USB_CHEP_TX_STTX | USB_CHEP_REG_MASK)
#define USB_CHEP_RX_DTOGMASK                       (USB_CHEP_RX_STRX | USB_CHEP_REG_MASK)

#define USB_CHEP_TX_DTOG1                          (0x00000010UL)           /*!< Channel/EndPoint TX Data Toggle bit1 */
#define USB_CHEP_TX_DTOG2                          (0x00000020UL)           /*!< Channel/EndPoint TX Data Toggle bit2 */
#define USB_CHEP_RX_DTOG1                          (0x00001000UL)           /*!< Channel/EndPoint RX Data Toggle bit1 */
#define USB_CHEP_RX_DTOG2                          (0x00002000UL)           /*!< Channel/EndPoint RX Data Toggle bit1 */

/*!< EP_TYPE[1:0] Channel/EndPoint TYPE */
#define USB_EP_TYPE_MASK                           (0x00000600UL)           /*!< Channel/EndPoint TYPE Mask */
#define USB_EP_BULK                                (0x00000000UL)           /*!< Channel/EndPoint BULK */
#define USB_EP_CONTROL                             (0x00000200UL)           /*!< Channel/EndPoint CONTROL */
#define USB_EP_ISOCHRONOUS                         (0x00000400UL)           /*!< Channel/EndPoint ISOCHRONOUS */
#define USB_EP_INTERRUPT                           (0x00000600UL)           /*!< Channel/EndPoint INTERRUPT */

#define USB_EP_T_MASK                              ((~USB_EP_UTYPE) & USB_CHEP_REG_MASK) /* =0x898F */
#define USB_CH_T_MASK                              ((~USB_CH_UTYPE) & USB_CHEP_REG_MASK) /* =0x898F */

#define USB_EP_KIND_MASK                           ((~USB_EP_KIND) & USB_CHEP_REG_MASK) /*!< EP_KIND EndPoint KIND */
#define USB_CH_KIND_MASK                           ((~USB_CH_KIND) & USB_CHEP_REG_MASK) /*!< EP_KIND EndPoint KIND */

/*!< STAT_TX[1:0] STATus for TX transfer */
#define USB_EP_TX_DIS                              (0x00000000UL)           /*!< EndPoint TX Disabled */
#define USB_EP_TX_STALL                            (0x00000010UL)           /*!< EndPoint TX STALLed */
#define USB_EP_TX_NAK                              (0x00000020UL)           /*!< EndPoint TX NAKed */
#define USB_EP_TX_VALID                            (0x00000030UL)           /*!< EndPoint TX VALID */

#define USB_CH_TX_DIS                              (0x00000000UL)           /*!< Channel TX Disabled */
#define USB_CH_TX_STALL                            (0x00000010UL)           /*!< Channel TX STALLed */
#define USB_CH_TX_NAK                              (0x00000020UL)           /*!< Channel TX NAKed */
#define USB_CH_TX_VALID                            (0x00000030UL)           /*!< Channel TX VALID */

#define USB_EP_TX_ACK_SBUF                         (0x00000000UL)           /*!< ACK single buffer mode */
#define USB_EP_TX_ACK_DBUF                         (0x00000030UL)           /*!< ACK Double buffer mode */

#define USB_CH_TX_ACK_SBUF                         (0x00000000UL)           /*!< ACK single buffer mode */
#define USB_CH_TX_ACK_DBUF                         (0x00000030UL)           /*!< ACK Double buffer mode */

/*!< STAT_RX[1:0] STATus for RX transfer */
#define USB_EP_RX_DIS                              (0x00000000UL)           /*!< EndPoint RX Disabled */
#define USB_EP_RX_STALL                            (0x00001000UL)           /*!< EndPoint RX STALLed */
#define USB_EP_RX_NAK                              (0x00002000UL)           /*!< EndPoint RX NAKed */
#define USB_EP_RX_VALID                            (0x00003000UL)           /*!< EndPoint RX VALID */

#define USB_EP_RX_ACK_SBUF                         (0x00000000UL)           /*!< ACK single buffer mode */
#define USB_EP_RX_ACK_DBUF                         (0x00003000UL)           /*!< ACK Double buffer mode */



#define USB_CH_RX_DIS                              (0x00000000UL)           /*!< EndPoint RX Disabled */
#define USB_CH_RX_STALL                            (0x00001000UL)           /*!< EndPoint RX STALLed */
#define USB_CH_RX_NAK                              (0x00002000UL)           /*!< Channel RX NAKed */
#define USB_CH_RX_VALID                            (0x00003000UL)           /*!< Channel RX VALID */

#define USB_CH_RX_ACK_SBUF                         (0x00000000UL)           /*!< ACK single buffer mode */
#define USB_CH_RX_ACK_DBUF                         (0x00003000UL)           /*!< ACK Double buffer mode */

/*! <used For Double Buffer Enable Disable */
#define USB_CHEP_DB_MSK                            (0xFFFF0F0FUL)

/*Buffer Descriptor Mask*/
#define USB_PMA_TXBD_ADDMSK                        (0xFFFF0000UL)
#define USB_PMA_TXBD_COUNTMSK                      (0x0000FFFFUL)
#define USB_PMA_RXBD_ADDMSK                        (0xFFFF0000UL)
#define USB_PMA_RXBD_COUNTMSK                      (0x03FFFFFFUL)

/******************************************************************************/
/*                                                                            */
/*      Universal Synchronous Asynchronous Receiver Transmitter (USART)       */
/*                                                                            */
/******************************************************************************/
/******************  Bit definition for USART_CR1 register  *******************/
#define USART_CR1_UE_Pos                    (0UL)
#define USART_CR1_UE_Msk                    (0x1UL << USART_CR1_UE_Pos)             /*!< 0x00000001 */
#define USART_CR1_UE                        USART_CR1_UE_Msk                        /*!< USART Enable */
#define USART_CR1_UESM_Pos                  (1UL)
#define USART_CR1_UESM_Msk                  (0x1UL << USART_CR1_UESM_Pos)           /*!< 0x00000002 */
#define USART_CR1_UESM                      USART_CR1_UESM_Msk                      /*!< USART Enable in STOP Mode */
#define USART_CR1_RE_Pos                    (2UL)
#define USART_CR1_RE_Msk                    (0x1UL << USART_CR1_RE_Pos)             /*!< 0x00000004 */
#define USART_CR1_RE                        USART_CR1_RE_Msk                        /*!< Receiver Enable */
#define USART_CR1_TE_Pos                    (3UL)
#define USART_CR1_TE_Msk                    (0x1UL << USART_CR1_TE_Pos)             /*!< 0x00000008 */
#define USART_CR1_TE                        USART_CR1_TE_Msk                        /*!< Transmitter Enable */
#define USART_CR1_IDLEIE_Pos                (4UL)
#define USART_CR1_IDLEIE_Msk                (0x1UL << USART_CR1_IDLEIE_Pos)         /*!< 0x00000010 */
#define USART_CR1_IDLEIE                    USART_CR1_IDLEIE_Msk                    /*!< IDLE Interrupt Enable */
#define USART_CR1_RXNEIE_Pos                (5UL)
#define USART_CR1_RXNEIE_Msk                (0x1UL << USART_CR1_RXNEIE_Pos)         /*!< 0x00000020 */
#define USART_CR1_RXNEIE                    USART_CR1_RXNEIE_Msk                    /*!< RXNE Interrupt Enable */
#define USART_CR1_RXNEIE_RXFNEIE_Pos        USART_CR1_RXNEIE_Pos
#define USART_CR1_RXNEIE_RXFNEIE_Msk        USART_CR1_RXNEIE_Msk                    /*!< 0x00000020 */
#define USART_CR1_RXNEIE_RXFNEIE            USART_CR1_RXNEIE_Msk                    /*!< RXNE and RX FIFO Not Empty Interrupt Enable */
#define USART_CR1_TCIE_Pos                  (6UL)
#define USART_CR1_TCIE_Msk                  (0x1UL << USART_CR1_TCIE_Pos)           /*!< 0x00000040 */
#define USART_CR1_TCIE                      USART_CR1_TCIE_Msk                      /*!< Transmission Complete Interrupt Enable */
#define USART_CR1_TXEIE_Pos                 (7UL)
#define USART_CR1_TXEIE_Msk                 (0x1UL << USART_CR1_TXEIE_Pos)          /*!< 0x00000080 */
#define USART_CR1_TXEIE                     USART_CR1_TXEIE_Msk                     /*!< TXE Interrupt Enable */
#define USART_CR1_TXEIE_TXFNFIE_Pos         (7UL)
#define USART_CR1_TXEIE_TXFNFIE_Msk         (0x1UL << USART_CR1_TXEIE_Pos)          /*!< 0x00000080 */
#define USART_CR1_TXEIE_TXFNFIE             USART_CR1_TXEIE                         /*!< TXE and TX FIFO Not Full Interrupt Enable */
#define USART_CR1_PEIE_Pos                  (8UL)
#define USART_CR1_PEIE_Msk                  (0x1UL << USART_CR1_PEIE_Pos)           /*!< 0x00000100 */
#define USART_CR1_PEIE                      USART_CR1_PEIE_Msk                      /*!< PE Interrupt Enable */
#define USART_CR1_PS_Pos                    (9UL)
#define USART_CR1_PS_Msk                    (0x1UL << USART_CR1_PS_Pos)             /*!< 0x00000200 */
#define USART_CR1_PS                        USART_CR1_PS_Msk                        /*!< Parity Selection */
#define USART_CR1_PCE_Pos                   (10UL)
#define USART_CR1_PCE_Msk                   (0x1UL << USART_CR1_PCE_Pos)            /*!< 0x00000400 */
#define USART_CR1_PCE                       USART_CR1_PCE_Msk                       /*!< Parity Control Enable */
#define USART_CR1_WAKE_Pos                  (11UL)
#define USART_CR1_WAKE_Msk                  (0x1UL << USART_CR1_WAKE_Pos)           /*!< 0x00000800 */
#define USART_CR1_WAKE                      USART_CR1_WAKE_Msk                      /*!< Receiver Wakeup method */
#define USART_CR1_M_Pos                     (12UL)
#define USART_CR1_M_Msk                     (0x10001UL << USART_CR1_M_Pos)          /*!< 0x10001000 */
#define USART_CR1_M                         USART_CR1_M_Msk                         /*!< Word length */
#define USART_CR1_M0_Pos                    (12UL)
#define USART_CR1_M0_Msk                    (0x1UL << USART_CR1_M0_Pos)             /*!< 0x00001000 */
#define USART_CR1_M0                        USART_CR1_M0_Msk                        /*!< Word length - Bit 0 */
#define USART_CR1_MME_Pos                   (13UL)
#define USART_CR1_MME_Msk                   (0x1UL << USART_CR1_MME_Pos)            /*!< 0x00002000 */
#define USART_CR1_MME                       USART_CR1_MME_Msk                       /*!< Mute Mode Enable */
#define USART_CR1_CMIE_Pos                  (14UL)
#define USART_CR1_CMIE_Msk                  (0x1UL << USART_CR1_CMIE_Pos)           /*!< 0x00004000 */
#define USART_CR1_CMIE                      USART_CR1_CMIE_Msk                      /*!< Character match interrupt enable */
#define USART_CR1_OVER8_Pos                 (15UL)
#define USART_CR1_OVER8_Msk                 (0x1UL << USART_CR1_OVER8_Pos)          /*!< 0x00008000 */
#define USART_CR1_OVER8                     USART_CR1_OVER8_Msk                     /*!< Oversampling by 8-bit or 16-bit mode */
#define USART_CR1_DEDT_Pos                  (16UL)
#define USART_CR1_DEDT_Msk                  (0x1FUL << USART_CR1_DEDT_Pos)          /*!< 0x001F0000 */
#define USART_CR1_DEDT                      USART_CR1_DEDT_Msk                      /*!< DEDT[4:0] bits (Driver Enable Deassertion Time) */
#define USART_CR1_DEDT_0                    (0x01UL << USART_CR1_DEDT_Pos)          /*!< 0x00010000 */
#define USART_CR1_DEDT_1                    (0x02UL << USART_CR1_DEDT_Pos)          /*!< 0x00020000 */
#define USART_CR1_DEDT_2                    (0x04UL << USART_CR1_DEDT_Pos)          /*!< 0x00040000 */
#define USART_CR1_DEDT_3                    (0x08UL << USART_CR1_DEDT_Pos)          /*!< 0x00080000 */
#define USART_CR1_DEDT_4                    (0x10UL << USART_CR1_DEDT_Pos)          /*!< 0x00100000 */
#define USART_CR1_DEAT_Pos                  (21UL)
#define USART_CR1_DEAT_Msk                  (0x1FUL << USART_CR1_DEAT_Pos)          /*!< 0x03E00000 */
#define USART_CR1_DEAT                      USART_CR1_DEAT_Msk                      /*!< DEAT[4:0] bits (Driver Enable Assertion Time) */
#define USART_CR1_DEAT_0                    (0x01UL << USART_CR1_DEAT_Pos)          /*!< 0x00200000 */
#define USART_CR1_DEAT_1                    (0x02UL << USART_CR1_DEAT_Pos)          /*!< 0x00400000 */
#define USART_CR1_DEAT_2                    (0x04UL << USART_CR1_DEAT_Pos)          /*!< 0x00800000 */
#define USART_CR1_DEAT_3                    (0x08UL << USART_CR1_DEAT_Pos)          /*!< 0x01000000 */
#define USART_CR1_DEAT_4                    (0x10UL << USART_CR1_DEAT_Pos)          /*!< 0x02000000 */
#define USART_CR1_RTOIE_Pos                 (26UL)
#define USART_CR1_RTOIE_Msk                 (0x1UL << USART_CR1_RTOIE_Pos)          /*!< 0x04000000 */
#define USART_CR1_RTOIE                     USART_CR1_RTOIE_Msk                     /*!< Receive Time Out interrupt enable */
#define USART_CR1_EOBIE_Pos                 (27UL)
#define USART_CR1_EOBIE_Msk                 (0x1UL << USART_CR1_EOBIE_Pos)          /*!< 0x08000000 */
#define USART_CR1_EOBIE                     USART_CR1_EOBIE_Msk                     /*!< End of Block interrupt enable */
#define USART_CR1_M1_Pos                    (28UL)
#define USART_CR1_M1_Msk                    (0x1UL << USART_CR1_M1_Pos)             /*!< 0x10000000 */
#define USART_CR1_M1                        USART_CR1_M1_Msk                        /*!< Word length - Bit 1 */
#define USART_CR1_FIFOEN_Pos                (29UL)
#define USART_CR1_FIFOEN_Msk                (0x1UL << USART_CR1_FIFOEN_Pos)         /*!< 0x20000000 */
#define USART_CR1_FIFOEN                    USART_CR1_FIFOEN_Msk                    /*!< FIFO mode enable */
#define USART_CR1_TXFEIE_Pos                (30UL)
#define USART_CR1_TXFEIE_Msk                (0x1UL << USART_CR1_TXFEIE_Pos)         /*!< 0x40000000 */
#define USART_CR1_TXFEIE                    USART_CR1_TXFEIE_Msk                    /*!< TXFIFO empty interrupt enable */
#define USART_CR1_RXFFIE_Pos                (31UL)
#define USART_CR1_RXFFIE_Msk                (0x1UL << USART_CR1_RXFFIE_Pos)         /*!< 0x80000000 */
#define USART_CR1_RXFFIE                    USART_CR1_RXFFIE_Msk                    /*!< RXFIFO Full interrupt enable */

/******************  Bit definition for USART_CR2 register  *******************/
#define USART_CR2_SLVEN_Pos                 (0UL)
#define USART_CR2_SLVEN_Msk                 (0x1UL << USART_CR2_SLVEN_Pos)          /*!< 0x00000001 */
#define USART_CR2_SLVEN                     USART_CR2_SLVEN_Msk                     /*!< Synchronous Slave mode enable */
#define USART_CR2_DIS_NSS_Pos               (3UL)
#define USART_CR2_DIS_NSS_Msk               (0x1UL << USART_CR2_DIS_NSS_Pos)        /*!< 0x00000008 */
#define USART_CR2_DIS_NSS                   USART_CR2_DIS_NSS_Msk                   /*!< Slave Select (NSS) pin management */
#define USART_CR2_ADDM7_Pos                 (4UL)
#define USART_CR2_ADDM7_Msk                 (0x1UL << USART_CR2_ADDM7_Pos)          /*!< 0x00000010 */
#define USART_CR2_ADDM7                     USART_CR2_ADDM7_Msk                     /*!< 7-bit or 4-bit Address Detection */
#define USART_CR2_LBDL_Pos                  (5UL)
#define USART_CR2_LBDL_Msk                  (0x1UL << USART_CR2_LBDL_Pos)           /*!< 0x00000020 */
#define USART_CR2_LBDL                      USART_CR2_LBDL_Msk                      /*!< LIN Break Detection Length */
#define USART_CR2_LBDIE_Pos                 (6UL)
#define USART_CR2_LBDIE_Msk                 (0x1UL << USART_CR2_LBDIE_Pos)          /*!< 0x00000040 */
#define USART_CR2_LBDIE                     USART_CR2_LBDIE_Msk                     /*!< LIN Break Detection Interrupt Enable */
#define USART_CR2_LBCL_Pos                  (8UL)
#define USART_CR2_LBCL_Msk                  (0x1UL << USART_CR2_LBCL_Pos)           /*!< 0x00000100 */
#define USART_CR2_LBCL                      USART_CR2_LBCL_Msk                      /*!< Last Bit Clock pulse */
#define USART_CR2_CPHA_Pos                  (9UL)
#define USART_CR2_CPHA_Msk                  (0x1UL << USART_CR2_CPHA_Pos)           /*!< 0x00000200 */
#define USART_CR2_CPHA                      USART_CR2_CPHA_Msk                      /*!< Clock Phase */
#define USART_CR2_CPOL_Pos                  (10UL)
#define USART_CR2_CPOL_Msk                  (0x1UL << USART_CR2_CPOL_Pos)           /*!< 0x00000400 */
#define USART_CR2_CPOL                      USART_CR2_CPOL_Msk                      /*!< Clock Polarity */
#define USART_CR2_CLKEN_Pos                 (11UL)
#define USART_CR2_CLKEN_Msk                 (0x1UL << USART_CR2_CLKEN_Pos)          /*!< 0x00000800 */
#define USART_CR2_CLKEN                     USART_CR2_CLKEN_Msk                     /*!< Clock Enable */
#define USART_CR2_STOP_Pos                  (12UL)
#define USART_CR2_STOP_Msk                  (0x3UL << USART_CR2_STOP_Pos)           /*!< 0x00003000 */
#define USART_CR2_STOP                      USART_CR2_STOP_Msk                      /*!< STOP[1:0] bits (STOP bits) */
#define USART_CR2_STOP_0                    (0x1UL << USART_CR2_STOP_Pos)           /*!< 0x00001000 */
#define USART_CR2_STOP_1                    (0x2UL << USART_CR2_STOP_Pos)           /*!< 0x00002000 */
#define USART_CR2_LINEN_Pos                 (14UL)
#define USART_CR2_LINEN_Msk                 (0x1UL << USART_CR2_LINEN_Pos)          /*!< 0x00004000 */
#define USART_CR2_LINEN                     USART_CR2_LINEN_Msk                     /*!< LIN mode enable */
#define USART_CR2_SWAP_Pos                  (15UL)
#define USART_CR2_SWAP_Msk                  (0x1UL << USART_CR2_SWAP_Pos)           /*!< 0x00008000 */
#define USART_CR2_SWAP                      USART_CR2_SWAP_Msk                      /*!< SWAP TX/RX pins */
#define USART_CR2_RXINV_Pos                 (16UL)
#define USART_CR2_RXINV_Msk                 (0x1UL << USART_CR2_RXINV_Pos)          /*!< 0x00010000 */
#define USART_CR2_RXINV                     USART_CR2_RXINV_Msk                     /*!< RX pin active level inversion */
#define USART_CR2_TXINV_Pos                 (17UL)
#define USART_CR2_TXINV_Msk                 (0x1UL << USART_CR2_TXINV_Pos)          /*!< 0x00020000 */
#define USART_CR2_TXINV                     USART_CR2_TXINV_Msk                     /*!< TX pin active level inversion */
#define USART_CR2_DATAINV_Pos               (18UL)
#define USART_CR2_DATAINV_Msk               (0x1UL << USART_CR2_DATAINV_Pos)        /*!< 0x00040000 */
#define USART_CR2_DATAINV                   USART_CR2_DATAINV_Msk                   /*!< Binary data inversion */
#define USART_CR2_MSBFIRST_Pos              (19UL)
#define USART_CR2_MSBFIRST_Msk              (0x1UL << USART_CR2_MSBFIRST_Pos)       /*!< 0x00080000 */
#define USART_CR2_MSBFIRST                  USART_CR2_MSBFIRST_Msk                  /*!< Most Significant Bit First */
#define USART_CR2_ABREN_Pos                 (20UL)
#define USART_CR2_ABREN_Msk                 (0x1UL << USART_CR2_ABREN_Pos)          /*!< 0x00100000 */
#define USART_CR2_ABREN                     USART_CR2_ABREN_Msk                     /*!< Auto Baud-Rate Enable*/
#define USART_CR2_ABRMODE_Pos               (21UL)
#define USART_CR2_ABRMODE_Msk               (0x3UL << USART_CR2_ABRMODE_Pos)        /*!< 0x00600000 */
#define USART_CR2_ABRMODE                   USART_CR2_ABRMODE_Msk                   /*!< ABRMOD[1:0] bits (Auto Baud-Rate Mode) */
#define USART_CR2_ABRMODE_0                 (0x1UL << USART_CR2_ABRMODE_Pos)        /*!< 0x00200000 */
#define USART_CR2_ABRMODE_1                 (0x2UL << USART_CR2_ABRMODE_Pos)        /*!< 0x00400000 */
#define USART_CR2_RTOEN_Pos                 (23UL)
#define USART_CR2_RTOEN_Msk                 (0x1UL << USART_CR2_RTOEN_Pos)          /*!< 0x00800000 */
#define USART_CR2_RTOEN                     USART_CR2_RTOEN_Msk                     /*!< Receiver Time-Out enable */
#define USART_CR2_ADD_Pos                   (24UL)
#define USART_CR2_ADD_Msk                   (0xFFUL << USART_CR2_ADD_Pos)           /*!< 0xFF000000 */
#define USART_CR2_ADD                       USART_CR2_ADD_Msk                       /*!< Address of the USART node */

/******************  Bit definition for USART_CR3 register  *******************/
#define USART_CR3_EIE_Pos                   (0UL)
#define USART_CR3_EIE_Msk                   (0x1UL << USART_CR3_EIE_Pos)            /*!< 0x00000001 */
#define USART_CR3_EIE                       USART_CR3_EIE_Msk                       /*!< Error Interrupt Enable */
#define USART_CR3_IREN_Pos                  (1UL)
#define USART_CR3_IREN_Msk                  (0x1UL << USART_CR3_IREN_Pos)           /*!< 0x00000002 */
#define USART_CR3_IREN                      USART_CR3_IREN_Msk                      /*!< IrDA mode Enable */
#define USART_CR3_IRLP_Pos                  (2UL)
#define USART_CR3_IRLP_Msk                  (0x1UL << USART_CR3_IRLP_Pos)           /*!< 0x00000004 */
#define USART_CR3_IRLP                      USART_CR3_IRLP_Msk                      /*!< IrDA Low-Power */
#define USART_CR3_HDSEL_Pos                 (3UL)
#define USART_CR3_HDSEL_Msk                 (0x1UL << USART_CR3_HDSEL_Pos)          /*!< 0x00000008 */
#define USART_CR3_HDSEL                     USART_CR3_HDSEL_Msk                     /*!< Half-Duplex Selection */
#define USART_CR3_NACK_Pos                  (4UL)
#define USART_CR3_NACK_Msk                  (0x1UL << USART_CR3_NACK_Pos)           /*!< 0x00000010 */
#define USART_CR3_NACK                      USART_CR3_NACK_Msk                      /*!< SmartCard NACK enable */
#define USART_CR3_SCEN_Pos                  (5UL)
#define USART_CR3_SCEN_Msk                  (0x1UL << USART_CR3_SCEN_Pos)           /*!< 0x00000020 */
#define USART_CR3_SCEN                      USART_CR3_SCEN_Msk                      /*!< SmartCard mode enable */
#define USART_CR3_DMAR_Pos                  (6UL)
#define USART_CR3_DMAR_Msk                  (0x1UL << USART_CR3_DMAR_Pos)           /*!< 0x00000040 */
#define USART_CR3_DMAR                      USART_CR3_DMAR_Msk                      /*!< DMA Enable Receiver */
#define USART_CR3_DMAT_Pos                  (7UL)
#define USART_CR3_DMAT_Msk                  (0x1UL << USART_CR3_DMAT_Pos)           /*!< 0x00000080 */
#define USART_CR3_DMAT                      USART_CR3_DMAT_Msk                      /*!< DMA Enable Transmitter */
#define USART_CR3_RTSE_Pos                  (8UL)
#define USART_CR3_RTSE_Msk                  (0x1UL << USART_CR3_RTSE_Pos)           /*!< 0x00000100 */
#define USART_CR3_RTSE                      USART_CR3_RTSE_Msk                      /*!< RTS Enable */
#define USART_CR3_CTSE_Pos                  (9UL)
#define USART_CR3_CTSE_Msk                  (0x1UL << USART_CR3_CTSE_Pos)           /*!< 0x00000200 */
#define USART_CR3_CTSE                      USART_CR3_CTSE_Msk                      /*!< CTS Enable */
#define USART_CR3_CTSIE_Pos                 (10UL)
#define USART_CR3_CTSIE_Msk                 (0x1UL << USART_CR3_CTSIE_Pos)          /*!< 0x00000400 */
#define USART_CR3_CTSIE                     USART_CR3_CTSIE_Msk                     /*!< CTS Interrupt Enable */
#define USART_CR3_ONEBIT_Pos                (11UL)
#define USART_CR3_ONEBIT_Msk                (0x1UL << USART_CR3_ONEBIT_Pos)         /*!< 0x00000800 */
#define USART_CR3_ONEBIT                    USART_CR3_ONEBIT_Msk                    /*!< One sample bit method enable */
#define USART_CR3_OVRDIS_Pos                (12UL)
#define USART_CR3_OVRDIS_Msk                (0x1UL << USART_CR3_OVRDIS_Pos)         /*!< 0x00001000 */
#define USART_CR3_OVRDIS                    USART_CR3_OVRDIS_Msk                    /*!< Overrun Disable */
#define USART_CR3_DDRE_Pos                  (13UL)
#define USART_CR3_DDRE_Msk                  (0x1UL << USART_CR3_DDRE_Pos)           /*!< 0x00002000 */
#define USART_CR3_DDRE                      USART_CR3_DDRE_Msk                      /*!< DMA Disable on Reception Error */
#define USART_CR3_DEM_Pos                   (14UL)
#define USART_CR3_DEM_Msk                   (0x1UL << USART_CR3_DEM_Pos)            /*!< 0x00004000 */
#define USART_CR3_DEM                       USART_CR3_DEM_Msk                       /*!< Driver Enable Mode */
#define USART_CR3_DEP_Pos                   (15UL)
#define USART_CR3_DEP_Msk                   (0x1UL << USART_CR3_DEP_Pos)            /*!< 0x00008000 */
#define USART_CR3_DEP                       USART_CR3_DEP_Msk                       /*!< Driver Enable Polarity Selection */
#define USART_CR3_SCARCNT_Pos               (17UL)
#define USART_CR3_SCARCNT_Msk               (0x7UL << USART_CR3_SCARCNT_Pos)        /*!< 0x000E0000 */
#define USART_CR3_SCARCNT                   USART_CR3_SCARCNT_Msk                   /*!< SCARCNT[2:0] bits (SmartCard Auto-Retry Count) */
#define USART_CR3_SCARCNT_0                 (0x1UL << USART_CR3_SCARCNT_Pos)        /*!< 0x00020000 */
#define USART_CR3_SCARCNT_1                 (0x2UL << USART_CR3_SCARCNT_Pos)        /*!< 0x00040000 */
#define USART_CR3_SCARCNT_2                 (0x4UL << USART_CR3_SCARCNT_Pos)        /*!< 0x00080000 */
#define USART_CR3_TXFTIE_Pos                (23UL)
#define USART_CR3_TXFTIE_Msk                (0x1UL << USART_CR3_TXFTIE_Pos)         /*!< 0x00800000 */
#define USART_CR3_TXFTIE                    USART_CR3_TXFTIE_Msk                    /*!< TXFIFO threshold interrupt enable */
#define USART_CR3_TCBGTIE_Pos               (24UL)
#define USART_CR3_TCBGTIE_Msk               (0x1UL << USART_CR3_TCBGTIE_Pos)        /*!< 0x01000000 */
#define USART_CR3_TCBGTIE                   USART_CR3_TCBGTIE_Msk                   /*!< Transmission Complete Before Guard Time Interrupt Enable */
#define USART_CR3_RXFTCFG_Pos               (25UL)
#define USART_CR3_RXFTCFG_Msk               (0x7UL << USART_CR3_RXFTCFG_Pos)        /*!< 0x0E000000 */
#define USART_CR3_RXFTCFG                   USART_CR3_RXFTCFG_Msk                   /*!< RXFIFO FIFO threshold configuration */
#define USART_CR3_RXFTCFG_0                 (0x1UL << USART_CR3_RXFTCFG_Pos)        /*!< 0x02000000 */
#define USART_CR3_RXFTCFG_1                 (0x2UL << USART_CR3_RXFTCFG_Pos)        /*!< 0x04000000 */
#define USART_CR3_RXFTCFG_2                 (0x4UL << USART_CR3_RXFTCFG_Pos)        /*!< 0x08000000 */
#define USART_CR3_RXFTIE_Pos                (28UL)
#define USART_CR3_RXFTIE_Msk                (0x1UL << USART_CR3_RXFTIE_Pos)         /*!< 0x10000000 */
#define USART_CR3_RXFTIE                    USART_CR3_RXFTIE_Msk                    /*!< RXFIFO threshold interrupt enable */
#define USART_CR3_TXFTCFG_Pos               (29UL)
#define USART_CR3_TXFTCFG_Msk               (0x7UL << USART_CR3_TXFTCFG_Pos)        /*!< 0xE0000000 */
#define USART_CR3_TXFTCFG                   USART_CR3_TXFTCFG_Msk                   /*!< TXFIFO threshold configuration */
#define USART_CR3_TXFTCFG_0                 (0x1UL << USART_CR3_TXFTCFG_Pos)        /*!< 0x20000000 */
#define USART_CR3_TXFTCFG_1                 (0x2UL << USART_CR3_TXFTCFG_Pos)        /*!< 0x40000000 */
#define USART_CR3_TXFTCFG_2                 (0x4UL << USART_CR3_TXFTCFG_Pos)        /*!< 0x80000000 */

/******************  Bit definition for USART_BRR register  *******************/
#define USART_BRR_LPUART_Pos                (0UL)
#define USART_BRR_LPUART_Msk                (0xFFFFFUL << USART_BRR_LPUART_Pos)     /*!< 0x000FFFFF */
#define USART_BRR_LPUART                    USART_BRR_LPUART_Msk                    /*!< LPUART Baud rate register [19:0] */
#define USART_BRR_BRR                       ((uint16_t)0xFFFF)                      /*!< USART  Baud rate register [15:0] */

/******************  Bit definition for USART_GTPR register  ******************/
#define USART_GTPR_PSC_Pos                  (0UL)
#define USART_GTPR_PSC_Msk                  (0xFFUL << USART_GTPR_PSC_Pos)          /*!< 0x000000FF */
#define USART_GTPR_PSC                      USART_GTPR_PSC_Msk                      /*!< PSC[7:0] bits (Prescaler value) */
#define USART_GTPR_GT_Pos                   (8UL)
#define USART_GTPR_GT_Msk                   (0xFFUL << USART_GTPR_GT_Pos)           /*!< 0x0000FF00 */
#define USART_GTPR_GT                       USART_GTPR_GT_Msk                       /*!< GT[7:0] bits (Guard time value) */

/*******************  Bit definition for USART_RTOR register  *****************/
#define USART_RTOR_RTO_Pos                  (0UL)
#define USART_RTOR_RTO_Msk                  (0xFFFFFFUL << USART_RTOR_RTO_Pos)      /*!< 0x00FFFFFF */
#define USART_RTOR_RTO                      USART_RTOR_RTO_Msk                      /*!< Receiver Time Out Value */
#define USART_RTOR_BLEN_Pos                 (24UL)
#define USART_RTOR_BLEN_Msk                 (0xFFUL << USART_RTOR_BLEN_Pos)         /*!< 0xFF000000 */
#define USART_RTOR_BLEN                     USART_RTOR_BLEN_Msk                     /*!< Block Length */

/*******************  Bit definition for USART_RQR register  ******************/
#define USART_RQR_ABRRQ                     ((uint16_t)0x0001)                      /*!< Auto-Baud Rate Request */
#define USART_RQR_SBKRQ                     ((uint16_t)0x0002)                      /*!< Send Break Request */
#define USART_RQR_MMRQ                      ((uint16_t)0x0004)                      /*!< Mute Mode Request */
#define USART_RQR_RXFRQ                     ((uint16_t)0x0008)                      /*!< Receive Data flush Request */
#define USART_RQR_TXFRQ                     ((uint16_t)0x0010)                      /*!< Transmit data flush Request */

/*******************  Bit definition for USART_ISR register  ******************/
#define USART_ISR_PE_Pos                    (0UL)
#define USART_ISR_PE_Msk                    (0x1UL << USART_ISR_PE_Pos)             /*!< 0x00000001 */
#define USART_ISR_PE                        USART_ISR_PE_Msk                        /*!< Parity Error */
#define USART_ISR_FE_Pos                    (1UL)
#define USART_ISR_FE_Msk                    (0x1UL << USART_ISR_FE_Pos)             /*!< 0x00000002 */
#define USART_ISR_FE                        USART_ISR_FE_Msk                        /*!< Framing Error */
#define USART_ISR_NE_Pos                    (2UL)
#define USART_ISR_NE_Msk                    (0x1UL << USART_ISR_NE_Pos)             /*!< 0x00000004 */
#define USART_ISR_NE                        USART_ISR_NE_Msk                        /*!< Noise detected Flag */
#define USART_ISR_ORE_Pos                   (3UL)
#define USART_ISR_ORE_Msk                   (0x1UL << USART_ISR_ORE_Pos)            /*!< 0x00000008 */
#define USART_ISR_ORE                       USART_ISR_ORE_Msk                       /*!< OverRun Error */
#define USART_ISR_IDLE_Pos                  (4UL)
#define USART_ISR_IDLE_Msk                  (0x1UL << USART_ISR_IDLE_Pos)           /*!< 0x00000010 */
#define USART_ISR_IDLE                      USART_ISR_IDLE_Msk                      /*!< IDLE line detected */
#define USART_ISR_RXNE_Pos                  (5UL)
#define USART_ISR_RXNE_Msk                  (0x1UL << USART_ISR_RXNE_Pos)           /*!< 0x00000020 */
#define USART_ISR_RXNE                      USART_ISR_RXNE_Msk                      /*!< Read Data Register Not Empty */
#define USART_ISR_RXNE_RXFNE_Pos            USART_ISR_RXNE_Pos
#define USART_ISR_RXNE_RXFNE_Msk            USART_ISR_RXNE_Msk                      /*!< 0x00000020 */
#define USART_ISR_RXNE_RXFNE                USART_ISR_RXNE_Msk                      /*!< Read Data Register or RX FIFO Not Empty */
#define USART_ISR_TC_Pos                    (6UL)
#define USART_ISR_TC_Msk                    (0x1UL << USART_ISR_TC_Pos)             /*!< 0x00000040 */
#define USART_ISR_TC                        USART_ISR_TC_Msk                        /*!< Transmission Complete */
#define USART_ISR_TXE_Pos                   (7UL)
#define USART_ISR_TXE_Msk                   (0x1UL << USART_ISR_TXE_Pos)            /*!< 0x00000080 */
#define USART_ISR_TXE                       USART_ISR_TXE_Msk                       /*!< Transmit Data Register Empty */
#define USART_ISR_TXE_TXFNF_Pos             USART_ISR_TXE_Pos
#define USART_ISR_TXE_TXFNF_Msk             USART_ISR_TXE_Msk                       /*!< 0x00000080 */
#define USART_ISR_TXE_TXFNF                 USART_ISR_TXE_Msk                       /*!< Transmit Data Register Empty or TX FIFO Not Full Flag */
#define USART_ISR_LBDF_Pos                  (8UL)
#define USART_ISR_LBDF_Msk                  (0x1UL << USART_ISR_LBDF_Pos)           /*!< 0x00000100 */
#define USART_ISR_LBDF                      USART_ISR_LBDF_Msk                      /*!< LIN Break Detection Flag */
#define USART_ISR_CTSIF_Pos                 (9UL)
#define USART_ISR_CTSIF_Msk                 (0x1UL << USART_ISR_CTSIF_Pos)          /*!< 0x00000200 */
#define USART_ISR_CTSIF                     USART_ISR_CTSIF_Msk                     /*!< CTS interrupt flag */
#define USART_ISR_CTS_Pos                   (10UL)
#define USART_ISR_CTS_Msk                   (0x1UL << USART_ISR_CTS_Pos)            /*!< 0x00000400 */
#define USART_ISR_CTS                       USART_ISR_CTS_Msk                       /*!< CTS flag */
#define USART_ISR_RTOF_Pos                  (11UL)
#define USART_ISR_RTOF_Msk                  (0x1UL << USART_ISR_RTOF_Pos)           /*!< 0x00000800 */
#define USART_ISR_RTOF                      USART_ISR_RTOF_Msk                      /*!< Receiver Time Out */
#define USART_ISR_EOBF_Pos                  (12UL)
#define USART_ISR_EOBF_Msk                  (0x1UL << USART_ISR_EOBF_Pos)           /*!< 0x00001000 */
#define USART_ISR_EOBF                      USART_ISR_EOBF_Msk                      /*!< End Of Block Flag */
#define USART_ISR_UDR_Pos                   (13UL)
#define USART_ISR_UDR_Msk                   (0x1UL << USART_ISR_UDR_Pos)            /*!< 0x00002000 */
#define USART_ISR_UDR                       USART_ISR_UDR_Msk                       /*!< SPI slave underrun error flag */
#define USART_ISR_ABRE_Pos                  (14UL)
#define USART_ISR_ABRE_Msk                  (0x1UL << USART_ISR_ABRE_Pos)           /*!< 0x00004000 */
#define USART_ISR_ABRE                      USART_ISR_ABRE_Msk                      /*!< Auto-Baud Rate Error */
#define USART_ISR_ABRF_Pos                  (15UL)
#define USART_ISR_ABRF_Msk                  (0x1UL << USART_ISR_ABRF_Pos)           /*!< 0x00008000 */
#define USART_ISR_ABRF                      USART_ISR_ABRF_Msk                      /*!< Auto-Baud Rate Flag */
#define USART_ISR_BUSY_Pos                  (16UL)
#define USART_ISR_BUSY_Msk                  (0x1UL << USART_ISR_BUSY_Pos)           /*!< 0x00010000 */
#define USART_ISR_BUSY                      USART_ISR_BUSY_Msk                      /*!< Busy Flag */
#define USART_ISR_CMF_Pos                   (17UL)
#define USART_ISR_CMF_Msk                   (0x1UL << USART_ISR_CMF_Pos)            /*!< 0x00020000 */
#define USART_ISR_CMF                       USART_ISR_CMF_Msk                       /*!< Character Match Flag */
#define USART_ISR_SBKF_Pos                  (18UL)
#define USART_ISR_SBKF_Msk                  (0x1UL << USART_ISR_SBKF_Pos)           /*!< 0x00040000 */
#define USART_ISR_SBKF                      USART_ISR_SBKF_Msk                      /*!< Send Break Flag */
#define USART_ISR_RWU_Pos                   (19UL)
#define USART_ISR_RWU_Msk                   (0x1UL << USART_ISR_RWU_Pos)            /*!< 0x00080000 */
#define USART_ISR_RWU                       USART_ISR_RWU_Msk                       /*!< Receive Wake Up from mute mode Flag */
#define USART_ISR_TEACK_Pos                 (21UL)
#define USART_ISR_TEACK_Msk                 (0x1UL << USART_ISR_TEACK_Pos)          /*!< 0x00200000 */
#define USART_ISR_TEACK                     USART_ISR_TEACK_Msk                     /*!< Transmit Enable Acknowledge Flag */
#define USART_ISR_REACK_Pos                 (22UL)
#define USART_ISR_REACK_Msk                 (0x1UL << USART_ISR_REACK_Pos)          /*!< 0x00400000 */
#define USART_ISR_REACK                     USART_ISR_REACK_Msk                     /*!< Receive Enable Acknowledge Flag */
#define USART_ISR_TXFE_Pos                  (23UL)
#define USART_ISR_TXFE_Msk                  (0x1UL << USART_ISR_TXFE_Pos)           /*!< 0x00800000 */
#define USART_ISR_TXFE                      USART_ISR_TXFE_Msk                      /*!< TXFIFO Empty */
#define USART_ISR_RXFF_Pos                  (24UL)
#define USART_ISR_RXFF_Msk                  (0x1UL << USART_ISR_RXFF_Pos)           /*!< 0x01000000 */
#define USART_ISR_RXFF                      USART_ISR_RXFF_Msk                      /*!< RXFIFO Full */
#define USART_ISR_TCBGT_Pos                 (25UL)
#define USART_ISR_TCBGT_Msk                 (0x1UL << USART_ISR_TCBGT_Pos)          /*!< 0x02000000 */
#define USART_ISR_TCBGT                     USART_ISR_TCBGT_Msk                     /*!< Transmission Complete Before Guard Time completion */
#define USART_ISR_RXFT_Pos                  (26UL)
#define USART_ISR_RXFT_Msk                  (0x1UL << USART_ISR_RXFT_Pos)           /*!< 0x04000000 */
#define USART_ISR_RXFT                      USART_ISR_RXFT_Msk                      /*!< RXFIFO threshold flag */
#define USART_ISR_TXFT_Pos                  (27UL)
#define USART_ISR_TXFT_Msk                  (0x1UL << USART_ISR_TXFT_Pos)           /*!< 0x08000000 */
#define USART_ISR_TXFT                      USART_ISR_TXFT_Msk                      /*!< TXFIFO threshold flag */

/*******************  Bit definition for USART_ICR register  ******************/
#define USART_ICR_PECF_Pos                  (0UL)
#define USART_ICR_PECF_Msk                  (0x1UL << USART_ICR_PECF_Pos)           /*!< 0x00000001 */
#define USART_ICR_PECF                      USART_ICR_PECF_Msk                      /*!< Parity Error Clear Flag */
#define USART_ICR_FECF_Pos                  (1UL)
#define USART_ICR_FECF_Msk                  (0x1UL << USART_ICR_FECF_Pos)           /*!< 0x00000002 */
#define USART_ICR_FECF                      USART_ICR_FECF_Msk                      /*!< Framing Error Clear Flag */
#define USART_ICR_NECF_Pos                  (2UL)
#define USART_ICR_NECF_Msk                  (0x1UL << USART_ICR_NECF_Pos)           /*!< 0x00000004 */
#define USART_ICR_NECF                      USART_ICR_NECF_Msk                      /*!< Noise detected Clear Flag */
#define USART_ICR_ORECF_Pos                 (3UL)
#define USART_ICR_ORECF_Msk                 (0x1UL << USART_ICR_ORECF_Pos)          /*!< 0x00000008 */
#define USART_ICR_ORECF                     USART_ICR_ORECF_Msk                     /*!< OverRun Error Clear Flag */
#define USART_ICR_IDLECF_Pos                (4UL)
#define USART_ICR_IDLECF_Msk                (0x1UL << USART_ICR_IDLECF_Pos)         /*!< 0x00000010 */
#define USART_ICR_IDLECF                    USART_ICR_IDLECF_Msk                    /*!< IDLE line detected Clear Flag */
#define USART_ICR_TXFECF_Pos                (5UL)
#define USART_ICR_TXFECF_Msk                (0x1UL << USART_ICR_TXFECF_Pos)         /*!< 0x00000020 */
#define USART_ICR_TXFECF                    USART_ICR_TXFECF_Msk                    /*!< TXFIFO empty Clear flag */
#define USART_ICR_TCCF_Pos                  (6UL)
#define USART_ICR_TCCF_Msk                  (0x1UL << USART_ICR_TCCF_Pos)           /*!< 0x00000040 */
#define USART_ICR_TCCF                      USART_ICR_TCCF_Msk                      /*!< Transmission Complete Clear Flag */
#define USART_ICR_TCBGTCF_Pos               (7UL)
#define USART_ICR_TCBGTCF_Msk               (0x1UL << USART_ICR_TCBGTCF_Pos)        /*!< 0x00000080 */
#define USART_ICR_TCBGTCF                   USART_ICR_TCBGTCF_Msk                   /*!< Transmission Complete Before Guard Time Clear Flag */
#define USART_ICR_LBDCF_Pos                 (8UL)
#define USART_ICR_LBDCF_Msk                 (0x1UL << USART_ICR_LBDCF_Pos)          /*!< 0x00000100 */
#define USART_ICR_LBDCF                     USART_ICR_LBDCF_Msk                     /*!< LIN Break Detection Clear Flag */
#define USART_ICR_CTSCF_Pos                 (9UL)
#define USART_ICR_CTSCF_Msk                 (0x1UL << USART_ICR_CTSCF_Pos)          /*!< 0x00000200 */
#define USART_ICR_CTSCF                     USART_ICR_CTSCF_Msk                     /*!< CTS Interrupt Clear Flag */
#define USART_ICR_RTOCF_Pos                 (11UL)
#define USART_ICR_RTOCF_Msk                 (0x1UL << USART_ICR_RTOCF_Pos)          /*!< 0x00000800 */
#define USART_ICR_RTOCF                     USART_ICR_RTOCF_Msk                     /*!< Receiver Time Out Clear Flag */
#define USART_ICR_EOBCF_Pos                 (12UL)
#define USART_ICR_EOBCF_Msk                 (0x1UL << USART_ICR_EOBCF_Pos)          /*!< 0x00001000 */
#define USART_ICR_EOBCF                     USART_ICR_EOBCF_Msk                     /*!< End Of Block Clear Flag */
#define USART_ICR_UDRCF_Pos                 (13UL)
#define USART_ICR_UDRCF_Msk                 (0x1UL << USART_ICR_UDRCF_Pos)          /*!< 0x00002000 */
#define USART_ICR_UDRCF                     USART_ICR_UDRCF_Msk                     /*!< SPI Slave Underrun Clear Flag */
#define USART_ICR_CMCF_Pos                  (17UL)
#define USART_ICR_CMCF_Msk                  (0x1UL << USART_ICR_CMCF_Pos)           /*!< 0x00020000 */
#define USART_ICR_CMCF                      USART_ICR_CMCF_Msk                      /*!< Character Match Clear Flag */

/*******************  Bit definition for USART_RDR register  ******************/
#define USART_RDR_RDR                       ((uint16_t)0x01FF)                      /*!< RDR[8:0] bits (Receive Data value) */

/*******************  Bit definition for USART_TDR register  ******************/
#define USART_TDR_TDR                       ((uint16_t)0x01FF)                      /*!< TDR[8:0] bits (Transmit Data value) */

/*******************  Bit definition for USART_PRESC register  ****************/
#define USART_PRESC_PRESCALER_Pos           (0UL)
#define USART_PRESC_PRESCALER_Msk           (0xFUL << USART_PRESC_PRESCALER_Pos)    /*!< 0x0000000F */
#define USART_PRESC_PRESCALER               USART_PRESC_PRESCALER_Msk               /*!< PRESCALER[3:0] bits (Clock prescaler) */
#define USART_PRESC_PRESCALER_0             (0x1UL << USART_PRESC_PRESCALER_Pos)    /*!< 0x00000001 */
#define USART_PRESC_PRESCALER_1             (0x2UL << USART_PRESC_PRESCALER_Pos)    /*!< 0x00000002 */
#define USART_PRESC_PRESCALER_2             (0x4UL << USART_PRESC_PRESCALER_Pos)    /*!< 0x00000004 */
#define USART_PRESC_PRESCALER_3             (0x8UL << USART_PRESC_PRESCALER_Pos)    /*!< 0x00000008 */

/*******************  Bit definition for USART_AUTOCR register  ******************/
#define USART_AUTOCR_TDN_Pos                (0UL)
#define USART_AUTOCR_TDN_Msk                (0xFFFFUL << USART_AUTOCR_TDN_Pos)      /*!< 0x0000FFFF */
#define USART_AUTOCR_TDN                    USART_AUTOCR_TDN_Msk                    /*!< TDN[15:0] bits (Transmission Data Number) */
#define USART_AUTOCR_TRIGPOL_Pos            (16UL)
#define USART_AUTOCR_TRIGPOL_Msk            (0x1UL << USART_AUTOCR_TRIGPOL_Pos)     /*!< 0x00010000 */
#define USART_AUTOCR_TRIGPOL                USART_AUTOCR_TRIGPOL_Msk                /*!< Trigger Polarity Bit (Rising/Falling edge) */
#define USART_AUTOCR_TRIGEN_Pos             (17UL)
#define USART_AUTOCR_TRIGEN_Msk             (0x1UL << USART_AUTOCR_TRIGEN_Pos)      /*!< 0x00020000 */
#define USART_AUTOCR_TRIGEN                 USART_AUTOCR_TRIGEN_Msk                 /*!< Trigger Enable Bit */
#define USART_AUTOCR_IDLEDIS_Pos            (18UL)
#define USART_AUTOCR_IDLEDIS_Msk            (0x1UL << USART_AUTOCR_IDLEDIS_Pos)     /*!< 0x00040000 */
#define USART_AUTOCR_IDLEDIS                USART_AUTOCR_IDLEDIS_Msk                /*!< Idle Frame Transmission Disable Bit*/
#define USART_AUTOCR_TRIGSEL_Pos            (19UL)
#define USART_AUTOCR_TRIGSEL_Msk            (0xFUL << USART_AUTOCR_TRIGSEL_Pos)     /*!< 0x00780000 */
#define USART_AUTOCR_TRIGSEL                USART_AUTOCR_TRIGSEL_Msk                /*!< Trigger Selection Bits */
#define USART_AUTOCR_TRIGSEL_0              (0x0001UL << USART_AUTOCR_TRIGSEL_Pos)  /*!< 0x00000001 */
#define USART_AUTOCR_TRIGSEL_1              (0x0002UL << USART_AUTOCR_TRIGSEL_Pos)  /*!< 0x00000002 */
#define USART_AUTOCR_TRIGSEL_2              (0x0004UL << USART_AUTOCR_TRIGSEL_Pos)  /*!< 0x00000004 */
#define USART_AUTOCR_TRIGSEL_3              (0x0008UL << USART_AUTOCR_TRIGSEL_Pos)  /*!< 0x00000008 */


/******************************************************************************/
/*                                                                            */
/*                       Public Key Accelerator (PKA)                         */
/*                                                                            */
/******************************************************************************/
/*******************  Bit definition for PKA_CR register  *********************/
#define PKA_CR_EN_Pos                       (0UL)
#define PKA_CR_EN_Msk                       (0x1UL << PKA_CR_EN_Pos)                       /*!< 0x00000001 */
#define PKA_CR_EN                           PKA_CR_EN_Msk                                  /*!< PKA enable */
#define PKA_CR_START_Pos                    (1UL)
#define PKA_CR_START_Msk                    (0x1UL << PKA_CR_START_Pos)                    /*!< 0x00000002 */
#define PKA_CR_START                        PKA_CR_START_Msk                               /*!< Start operation */
#define PKA_CR_MODE_Pos                     (8UL)
#define PKA_CR_MODE_Msk                     (0x3FUL << PKA_CR_MODE_Pos)                    /*!< 0x00003F00 */
#define PKA_CR_MODE                         PKA_CR_MODE_Msk                                /*!< MODE[5:0] PKA operation code */
#define PKA_CR_MODE_0                       (0x01UL << PKA_CR_MODE_Pos)                    /*!< 0x00000100 */
#define PKA_CR_MODE_1                       (0x02UL << PKA_CR_MODE_Pos)                    /*!< 0x00000200 */
#define PKA_CR_MODE_2                       (0x04UL << PKA_CR_MODE_Pos)                    /*!< 0x00000400 */
#define PKA_CR_MODE_3                       (0x08UL << PKA_CR_MODE_Pos)                    /*!< 0x00000800 */
#define PKA_CR_MODE_4                       (0x10UL << PKA_CR_MODE_Pos)                    /*!< 0x00001000 */
#define PKA_CR_MODE_5                       (0x20UL << PKA_CR_MODE_Pos)                    /*!< 0x00002000 */
#define PKA_CR_PROCENDIE_Pos                (17UL)
#define PKA_CR_PROCENDIE_Msk                (0x1UL << PKA_CR_PROCENDIE_Pos)                /*!< 0x00020000 */
#define PKA_CR_PROCENDIE                    PKA_CR_PROCENDIE_Msk                           /*!< End of operation interrupt enable */
#define PKA_CR_RAMERRIE_Pos                 (19UL)
#define PKA_CR_RAMERRIE_Msk                 (0x1UL << PKA_CR_RAMERRIE_Pos)                 /*!< 0x00080000 */
#define PKA_CR_RAMERRIE                     PKA_CR_RAMERRIE_Msk                            /*!< RAM error interrupt enable */
#define PKA_CR_ADDRERRIE_Pos                (20UL)
#define PKA_CR_ADDRERRIE_Msk                (0x1UL << PKA_CR_ADDRERRIE_Pos)                /*!< 0x00100000 */
#define PKA_CR_ADDRERRIE                    PKA_CR_ADDRERRIE_Msk                           /*!< Address error interrupt enable */
#define PKA_CR_OPERRIE_Pos                  (21UL)
#define PKA_CR_OPERRIE_Msk                  (0x1UL << PKA_CR_OPERRIE_Pos)                  /*!< 0x00200000 */
#define PKA_CR_OPERRIE                      PKA_CR_OPERRIE_Msk                             /*!< Operation Error interrupt enable */
#define PKA_CR_CMFIE_Pos                    (22UL)
#define PKA_CR_CMFIE_Msk                    (0x1UL << PKA_CR_CMFIE_Pos)                    /*!< 0x00400000 */
#define PKA_CR_CMFIE                        PKA_CR_CMFIE_Msk                               /*!< Chaining mode flags interrupt enable */

/*******************  Bit definition for PKA_SR register  *********************/
#define PKA_SR_INITOK_Pos                   (0UL)
#define PKA_SR_INITOK_Msk                   (0x1UL << PKA_SR_INITOK_Pos)                   /*!< 0x00000001 */
#define PKA_SR_INITOK                       PKA_SR_INITOK_Msk                              /*!< PKA initialisation flag */
#define PKA_SR_LMF_Pos                      (1UL)
#define PKA_SR_LMF_Msk                      (0x1UL << PKA_SR_LMF_Pos)                      /*!< 0x00000002 */
#define PKA_SR_LMF                          PKA_SR_LMF_Msk                                 /*!< PKA Limited mode flag */
#define PKA_SR_CCEN_Pos                     (2UL)
#define PKA_SR_CCEN_Msk                     (0x1UL << PKA_SR_CCEN_Pos)                     /*!< 0x00000004 */
#define PKA_SR_CCEN                         PKA_SR_CCEN_Msk                                /*!< PKA Coupling and chaining mode enable */
#define PKA_SR_RNGOKF_Pos                   (8UL)
#define PKA_SR_RNGOKF_Msk                   (0x1UL << PKA_SR_RNGOKF_Pos)                   /*!< 0x00000100 */
#define PKA_SR_RNGOKF                       PKA_SR_RNGOKF_Msk                              /*!< PKA RNG OK flag */
#define PKA_SR_DATAOKF_Pos                  (9UL)
#define PKA_SR_DATAOKF_Msk                  (0x1UL << PKA_SR_DATAOKF_Pos)                  /*!< 0x00000200 */
#define PKA_SR_DATAOKF                      PKA_SR_DATAOKF_Msk                             /*!< PKA Data OK flag */
#define PKA_SR_INCRERRF_Pos                 (10UL)
#define PKA_SR_INCRERRF_Msk                 (0x1UL << PKA_SR_INCRERRF_Pos)                 /*!< 0x00000400 */
#define PKA_SR_INCRERRF                     PKA_SR_INCRERRF_Msk                            /*!< PKA Increment error flag */
#define PKA_SR_DATAZF_Pos                   (11UL)
#define PKA_SR_DATAZF_Msk                   (0x1UL << PKA_SR_DATAZF_Pos)                   /*!< 0x00000800 */
#define PKA_SR_DATAZF                       PKA_SR_DATAZF_Msk                              /*!< PKA Data zeroed error flag */
#define PKA_SR_TRZERRF_Pos                  (12UL)
#define PKA_SR_TRZERRF_Msk                  (0x1UL << PKA_SR_TRZERRF_Pos)                  /*!< 0x00001000 */
#define PKA_SR_TRZERRF                      PKA_SR_TRZERRF_Msk                             /*!< PKA Trailing zeros error flag */
#define PKA_SR_MDERRF_Pos                   (13UL)
#define PKA_SR_MDERRF_Msk                   (0x1UL << PKA_SR_MDERRF_Pos)                   /*!< 0x00002000 */
#define PKA_SR_MDERRF                       PKA_SR_MDERRF_Msk                              /*!< PKA Mode error flag */
#define PKA_SR_RNGERRF_Pos                  (14UL)
#define PKA_SR_RNGERRF_Msk                  (0x1UL << PKA_SR_RNGERRF_Pos)                  /*!< 0x00004000 */
#define PKA_SR_RNGERRF                      PKA_SR_RNGERRF_Msk                             /*!< PKA RNG error flag */
#define PKA_SR_BUSY_Pos                     (16UL)
#define PKA_SR_BUSY_Msk                     (0x1UL << PKA_SR_BUSY_Pos)                     /*!< 0x00010000 */
#define PKA_SR_BUSY                         PKA_SR_BUSY_Msk                                /*!< PKA operation is in progress */
#define PKA_SR_PROCENDF_Pos                 (17UL)
#define PKA_SR_PROCENDF_Msk                 (0x1UL << PKA_SR_PROCENDF_Pos)                 /*!< 0x00020000 */
#define PKA_SR_PROCENDF                     PKA_SR_PROCENDF_Msk                            /*!< PKA end of operation flag */
#define PKA_SR_RAMERRF_Pos                  (19UL)
#define PKA_SR_RAMERRF_Msk                  (0x1UL << PKA_SR_RAMERRF_Pos)                  /*!< 0x00080000 */
#define PKA_SR_RAMERRF                      PKA_SR_RAMERRF_Msk                             /*!< PKA RAM error flag */
#define PKA_SR_ADDRERRF_Pos                 (20UL)
#define PKA_SR_ADDRERRF_Msk                 (0x1UL << PKA_SR_ADDRERRF_Pos)                 /*!< 0x00100000 */
#define PKA_SR_ADDRERRF                     PKA_SR_ADDRERRF_Msk                            /*!< Address error flag */
#define PKA_SR_OPERRF_Pos                   (21UL)
#define PKA_SR_OPERRF_Msk                   (0x1UL << PKA_SR_OPERRF_Pos)                   /*!< 0x00200000 */
#define PKA_SR_OPERRF                       PKA_SR_OPERRF_Msk                              /*!< PKA operation Error flag*/
#define PKA_SR_CMF_Pos                      (22UL)
#define PKA_SR_CMF_Msk                      (0x1UL << PKA_SR_CMF_Pos)                      /*!< 0x00400000 */
#define PKA_SR_CMF                          PKA_SR_CMF_Msk                                 /*!< Chaining mode flag */

/*******************  Bit definition for PKA_CLRFR register  ******************/
#define PKA_CLRFR_PROCENDFC_Pos             (17UL)
#define PKA_CLRFR_PROCENDFC_Msk             (0x1UL << PKA_CLRFR_PROCENDFC_Pos)             /*!< 0x00020000 */
#define PKA_CLRFR_PROCENDFC                 PKA_CLRFR_PROCENDFC_Msk                        /*!< Clear PKA end of operation flag */
#define PKA_CLRFR_RAMERRFC_Pos              (19UL)
#define PKA_CLRFR_RAMERRFC_Msk              (0x1UL << PKA_CLRFR_RAMERRFC_Pos)              /*!< 0x00080000 */
#define PKA_CLRFR_RAMERRFC                  PKA_CLRFR_RAMERRFC_Msk                         /*!< Clear PKA RAM error flag */
#define PKA_CLRFR_ADDRERRFC_Pos             (20UL)
#define PKA_CLRFR_ADDRERRFC_Msk             (0x1UL << PKA_CLRFR_ADDRERRFC_Pos)             /*!< 0x00100000 */
#define PKA_CLRFR_ADDRERRFC                 PKA_CLRFR_ADDRERRFC_Msk                        /*!< Clear address error flag */
#define PKA_CLRFR_OPERRFC_Pos               (21UL)
#define PKA_CLRFR_OPERRFC_Msk               (0x1UL << PKA_CLRFR_OPERRFC_Pos)               /*!< 0x00200000 */
#define PKA_CLRFR_OPERRFC                   PKA_CLRFR_OPERRFC_Msk                          /*!< Clear PKA operation Error flag */
#define PKA_CLRFR_CMFC_Pos                  (22UL)
#define PKA_CLRFR_CMFC_Msk                  (0x1UL << PKA_CLRFR_CMFC_Pos)                  /*!< 0x00400000 */
#define PKA_CLRFR_CMFC                      PKA_CLRFR_CMFC_Msk                             /*!< Clear chaining mode flag */

/*******************  Bits definition for PKA RAM  *************************/
#define PKA_RAM_OFFSET                                 (0x0400UL)                          /*!< PKA RAM address offset */

/* Compute Montgomery parameter input data */
#define PKA_MONTGOMERY_PARAM_IN_MOD_NB_BITS            ((0x0408UL - PKA_RAM_OFFSET)>>2)    /*!< Input modulus number of bits */
#define PKA_MONTGOMERY_PARAM_IN_MODULUS                ((0x1088UL - PKA_RAM_OFFSET)>>2)    /*!< Input modulus */

/* Compute Montgomery parameter output data */
#define PKA_MONTGOMERY_PARAM_OUT_PARAMETER             ((0x0620UL - PKA_RAM_OFFSET)>>2)    /*!< Output Montgomery parameter */

/* Compute modular exponentiation input data */
#define PKA_MODULAR_EXP_IN_EXP_NB_BITS                 ((0x0400UL - PKA_RAM_OFFSET)>>2)    /*!< Input exponent number of bits */
#define PKA_MODULAR_EXP_IN_OP_NB_BITS                  ((0x0408UL - PKA_RAM_OFFSET)>>2)    /*!< Input operand number of bits */
#define PKA_MODULAR_EXP_IN_MONTGOMERY_PARAM            ((0x0620UL - PKA_RAM_OFFSET)>>2)    /*!< Input storage area for Montgomery parameter */
#define PKA_MODULAR_EXP_IN_EXPONENT_BASE               ((0x0C68UL - PKA_RAM_OFFSET)>>2)    /*!< Input base of the exponentiation */
#define PKA_MODULAR_EXP_IN_EXPONENT                    ((0x0E78UL - PKA_RAM_OFFSET)>>2)    /*!< Input exponent to process */
#define PKA_MODULAR_EXP_IN_MODULUS                     ((0x1088UL - PKA_RAM_OFFSET)>>2)    /*!< Input modulus */
#define PKA_MODULAR_EXP_PROTECT_IN_EXPONENT_BASE       ((0x16C8UL - PKA_RAM_OFFSET)>>2)    /*!< Input base of the protected exponentiation */
#define PKA_MODULAR_EXP_PROTECT_IN_EXPONENT            ((0x14B8UL - PKA_RAM_OFFSET)>>2)    /*!< Input exponent to process protected exponentiation*/
#define PKA_MODULAR_EXP_PROTECT_IN_MODULUS             ((0x0838UL - PKA_RAM_OFFSET)>>2)    /*!< Input modulus to process protected exponentiation */
#define PKA_MODULAR_EXP_PROTECT_IN_PHI                 ((0x0C68UL - PKA_RAM_OFFSET)>>2)    /*!< Input phi to process protected exponentiation */

/* Compute modular exponentiation output data */
#define PKA_MODULAR_EXP_OUT_RESULT                     ((0x0838UL - PKA_RAM_OFFSET)>>2)    /*!< Output result of the exponentiation */
#define PKA_MODULAR_EXP_OUT_ERROR                      ((0x1298UL - PKA_RAM_OFFSET)>>2)    /*!< Output error of the exponentiation */
#define PKA_MODULAR_EXP_OUT_MONTGOMERY_PARAM           ((0x0620UL - PKA_RAM_OFFSET)>>2)    /*!< Output storage area for Montgomery parameter */
#define PKA_MODULAR_EXP_OUT_EXPONENT_BASE              ((0x0C68UL - PKA_RAM_OFFSET)>>2)    /*!< Output base of the exponentiation */

/* Compute ECC scalar multiplication input data */
#define PKA_ECC_SCALAR_MUL_IN_EXP_NB_BITS              ((0x0400UL - PKA_RAM_OFFSET)>>2)    /*!< Input curve prime order n number of bits */
#define PKA_ECC_SCALAR_MUL_IN_OP_NB_BITS               ((0x0408UL - PKA_RAM_OFFSET)>>2)    /*!< Input modulus number of bits */
#define PKA_ECC_SCALAR_MUL_IN_A_COEFF_SIGN             ((0x0410UL - PKA_RAM_OFFSET)>>2)    /*!< Input sign of the 'a' coefficient */
#define PKA_ECC_SCALAR_MUL_IN_A_COEFF                  ((0x0418UL - PKA_RAM_OFFSET)>>2)    /*!< Input ECC curve 'a' coefficient */
#define PKA_ECC_SCALAR_MUL_IN_B_COEFF                  ((0x0520UL - PKA_RAM_OFFSET)>>2)    /*!< Input ECC curve 'b' coefficient */
#define PKA_ECC_SCALAR_MUL_IN_MOD_GF                   ((0x1088UL - PKA_RAM_OFFSET)>>2)    /*!< Input modulus GF(p) */
#define PKA_ECC_SCALAR_MUL_IN_K                        ((0x12A0UL - PKA_RAM_OFFSET)>>2)    /*!< Input 'k' of KP */
#define PKA_ECC_SCALAR_MUL_IN_INITIAL_POINT_X          ((0x0578UL - PKA_RAM_OFFSET)>>2)    /*!< Input initial point P X coordinate */
#define PKA_ECC_SCALAR_MUL_IN_INITIAL_POINT_Y          ((0x0470UL - PKA_RAM_OFFSET)>>2)    /*!< Input initial point P Y coordinate */
#define PKA_ECC_SCALAR_MUL_IN_N_PRIME_ORDER            ((0x0F88UL - PKA_RAM_OFFSET)>>2)    /*!< Input prime order n */

/* Compute ECC scalar multiplication output data */
#define PKA_ECC_SCALAR_MUL_OUT_RESULT_X                ((0x0578UL - PKA_RAM_OFFSET)>>2)    /*!< Output result X coordinate */
#define PKA_ECC_SCALAR_MUL_OUT_RESULT_Y                ((0x05D0UL - PKA_RAM_OFFSET)>>2)    /*!< Output result Y coordinate */
#define PKA_ECC_SCALAR_MUL_OUT_ERROR                   ((0x0680UL - PKA_RAM_OFFSET)>>2)    /*!< Output result error */

/* Point check input data */
#define PKA_POINT_CHECK_IN_MOD_NB_BITS                 ((0x0408UL - PKA_RAM_OFFSET)>>2)    /*!< Input modulus number of bits */
#define PKA_POINT_CHECK_IN_A_COEFF_SIGN                ((0x0410UL - PKA_RAM_OFFSET)>>2)    /*!< Input sign of the 'a' coefficient */
#define PKA_POINT_CHECK_IN_A_COEFF                     ((0x0418UL - PKA_RAM_OFFSET)>>2)    /*!< Input ECC curve 'a' coefficient */
#define PKA_POINT_CHECK_IN_B_COEFF                     ((0x0520UL - PKA_RAM_OFFSET)>>2)    /*!< Input ECC curve 'b' coefficient */
#define PKA_POINT_CHECK_IN_MOD_GF                      ((0x0470UL - PKA_RAM_OFFSET)>>2)    /*!< Input modulus GF(p) */
#define PKA_POINT_CHECK_IN_INITIAL_POINT_X             ((0x0578UL - PKA_RAM_OFFSET)>>2)    /*!< Input initial point P X coordinate */
#define PKA_POINT_CHECK_IN_INITIAL_POINT_Y             ((0x05D0UL - PKA_RAM_OFFSET)>>2)    /*!< Input initial point P Y coordinate */
#define PKA_POINT_CHECK_IN_MONTGOMERY_PARAM            ((0x04C8UL - PKA_RAM_OFFSET)>>2)    /*!< Input storage area for Montgomery parameter */

/* Point check output data */
#define PKA_POINT_CHECK_OUT_ERROR                      ((0x0680UL - PKA_RAM_OFFSET)>>2)    /*!< Output error */

/* ECDSA signature input data */
#define PKA_ECDSA_SIGN_IN_ORDER_NB_BITS                ((0x0400UL - PKA_RAM_OFFSET)>>2)    /*!< Input order number of bits */
#define PKA_ECDSA_SIGN_IN_MOD_NB_BITS                  ((0x0408UL - PKA_RAM_OFFSET)>>2)    /*!< Input modulus number of bits */
#define PKA_ECDSA_SIGN_IN_A_COEFF_SIGN                 ((0x0410UL - PKA_RAM_OFFSET)>>2)    /*!< Input sign of the 'a' coefficient */
#define PKA_ECDSA_SIGN_IN_A_COEFF                      ((0x0418UL - PKA_RAM_OFFSET)>>2)    /*!< Input ECC curve 'a' coefficient */
#define PKA_ECDSA_SIGN_IN_B_COEFF                      ((0x0520UL - PKA_RAM_OFFSET)>>2)    /*!< Input ECC curve 'b' coefficient */
#define PKA_ECDSA_SIGN_IN_MOD_GF                       ((0x1088UL - PKA_RAM_OFFSET)>>2)    /*!< Input modulus GF(p) */
#define PKA_ECDSA_SIGN_IN_K                            ((0x12A0UL - PKA_RAM_OFFSET)>>2)    /*!< Input k value of the ECDSA */
#define PKA_ECDSA_SIGN_IN_INITIAL_POINT_X              ((0x0578UL - PKA_RAM_OFFSET)>>2)    /*!< Input initial point P X coordinate */
#define PKA_ECDSA_SIGN_IN_INITIAL_POINT_Y              ((0x0470UL - PKA_RAM_OFFSET)>>2)    /*!< Input initial point P Y coordinate */
#define PKA_ECDSA_SIGN_IN_HASH_E                       ((0x0FE8UL - PKA_RAM_OFFSET)>>2)    /*!< Input e, hash of the message */
#define PKA_ECDSA_SIGN_IN_PRIVATE_KEY_D                ((0x0F28UL - PKA_RAM_OFFSET)>>2)    /*!< Input d, private key */
#define PKA_ECDSA_SIGN_IN_ORDER_N                      ((0x0F88UL - PKA_RAM_OFFSET)>>2)    /*!< Input n, order of the curve */

/* ECDSA signature output data */
#define PKA_ECDSA_SIGN_OUT_ERROR                       ((0x0FE0UL - PKA_RAM_OFFSET)>>2)    /*!< Output error */
#define PKA_ECDSA_SIGN_OUT_SIGNATURE_R                 ((0x0730UL - PKA_RAM_OFFSET)>>2)    /*!< Output signature r */
#define PKA_ECDSA_SIGN_OUT_SIGNATURE_S                 ((0x0788UL - PKA_RAM_OFFSET)>>2)    /*!< Output signature s */
#define PKA_ECDSA_SIGN_OUT_FINAL_POINT_X               ((0x1400UL - PKA_RAM_OFFSET)>>2)    /*!< Extended output result point X coordinate */
#define PKA_ECDSA_SIGN_OUT_FINAL_POINT_Y               ((0x1458UL - PKA_RAM_OFFSET)>>2)    /*!< Extended output result point Y coordinate */

/* ECDSA verification input data */
#define PKA_ECDSA_VERIF_IN_ORDER_NB_BITS               ((0x0408UL - PKA_RAM_OFFSET)>>2)    /*!< Input order number of bits */
#define PKA_ECDSA_VERIF_IN_MOD_NB_BITS                 ((0x04C8UL - PKA_RAM_OFFSET)>>2)    /*!< Input modulus number of bits */
#define PKA_ECDSA_VERIF_IN_A_COEFF_SIGN                ((0x0468UL - PKA_RAM_OFFSET)>>2)    /*!< Input sign of the 'a' coefficient */
#define PKA_ECDSA_VERIF_IN_A_COEFF                     ((0x0470UL - PKA_RAM_OFFSET)>>2)    /*!< Input ECC curve 'a' coefficient */
#define PKA_ECDSA_VERIF_IN_MOD_GF                      ((0x04D0UL - PKA_RAM_OFFSET)>>2)    /*!< Input modulus GF(p) */
#define PKA_ECDSA_VERIF_IN_INITIAL_POINT_X             ((0x0678UL - PKA_RAM_OFFSET)>>2)    /*!< Input initial point P X coordinate */
#define PKA_ECDSA_VERIF_IN_INITIAL_POINT_Y             ((0x06D0UL - PKA_RAM_OFFSET)>>2)    /*!< Input initial point P Y coordinate */
#define PKA_ECDSA_VERIF_IN_PUBLIC_KEY_POINT_X          ((0x12F8UL - PKA_RAM_OFFSET)>>2)    /*!< Input public key point X coordinate */
#define PKA_ECDSA_VERIF_IN_PUBLIC_KEY_POINT_Y          ((0x1350UL - PKA_RAM_OFFSET)>>2)    /*!< Input public key point Y coordinate */
#define PKA_ECDSA_VERIF_IN_SIGNATURE_R                 ((0x10E0UL - PKA_RAM_OFFSET)>>2)    /*!< Input r, part of the signature */
#define PKA_ECDSA_VERIF_IN_SIGNATURE_S                 ((0x0C68UL - PKA_RAM_OFFSET)>>2)    /*!< Input s, part of the signature */
#define PKA_ECDSA_VERIF_IN_HASH_E                      ((0x13A8UL - PKA_RAM_OFFSET)>>2)    /*!< Input e, hash of the message */
#define PKA_ECDSA_VERIF_IN_ORDER_N                     ((0x1088UL - PKA_RAM_OFFSET)>>2)    /*!< Input n, order of the curve */

/* ECDSA verification output data */
#define PKA_ECDSA_VERIF_OUT_RESULT                     ((0x05D0UL - PKA_RAM_OFFSET)>>2)    /*!< Output result */

/* RSA CRT exponentiation input data */
#define PKA_RSA_CRT_EXP_IN_MOD_NB_BITS                 ((0x0408UL - PKA_RAM_OFFSET)>>2)    /*!< Input operands number of bits */
#define PKA_RSA_CRT_EXP_IN_DP_CRT                      ((0x0730UL - PKA_RAM_OFFSET)>>2)    /*!< Input Dp CRT parameter */
#define PKA_RSA_CRT_EXP_IN_DQ_CRT                      ((0x0E78UL - PKA_RAM_OFFSET)>>2)    /*!< Input Dq CRT parameter */
#define PKA_RSA_CRT_EXP_IN_QINV_CRT                    ((0x0948UL - PKA_RAM_OFFSET)>>2)    /*!< Input qInv CRT parameter */
#define PKA_RSA_CRT_EXP_IN_PRIME_P                     ((0x0B60UL - PKA_RAM_OFFSET)>>2)    /*!< Input Prime p */
#define PKA_RSA_CRT_EXP_IN_PRIME_Q                     ((0x1088UL - PKA_RAM_OFFSET)>>2)    /*!< Input Prime q */
#define PKA_RSA_CRT_EXP_IN_EXPONENT_BASE               ((0x12A0UL - PKA_RAM_OFFSET)>>2)    /*!< Input base of the exponentiation */

/* RSA CRT exponentiation output data */
#define PKA_RSA_CRT_EXP_OUT_RESULT                     ((0x0838UL - PKA_RAM_OFFSET)>>2)    /*!< Output result */

/* Modular reduction input data */
#define PKA_MODULAR_REDUC_IN_OP_LENGTH                 ((0x0400UL - PKA_RAM_OFFSET)>>2)    /*!< Input operand length */
#define PKA_MODULAR_REDUC_IN_MOD_LENGTH                ((0x0408UL - PKA_RAM_OFFSET)>>2)    /*!< Input modulus length */
#define PKA_MODULAR_REDUC_IN_OPERAND                   ((0x0A50UL - PKA_RAM_OFFSET)>>2)    /*!< Input operand */
#define PKA_MODULAR_REDUC_IN_MODULUS                   ((0x0C68UL - PKA_RAM_OFFSET)>>2)    /*!< Input modulus */

/* Modular reduction output data */
#define PKA_MODULAR_REDUC_OUT_RESULT                   ((0xE78UL - PKA_RAM_OFFSET)>>2)     /*!< Output result */

/* Arithmetic addition input data */
#define PKA_ARITHMETIC_ADD_IN_OP_NB_BITS               ((0x0408UL - PKA_RAM_OFFSET)>>2)    /*!< Input operand number of bits */
#define PKA_ARITHMETIC_ADD_IN_OP1                      ((0x0A50UL - PKA_RAM_OFFSET)>>2)    /*!< Input operand op1 */
#define PKA_ARITHMETIC_ADD_IN_OP2                      ((0x0C68UL - PKA_RAM_OFFSET)>>2)    /*!< Input operand op2 */

/* Arithmetic addition output data */
#define PKA_ARITHMETIC_ADD_OUT_RESULT                  ((0x0E78UL - PKA_RAM_OFFSET)>>2)    /*!< Output result */

/* Arithmetic subtraction input data */
#define PKA_ARITHMETIC_SUB_IN_OP_NB_BITS               ((0x0408UL - PKA_RAM_OFFSET)>>2)    /*!< Input operand number of bits */
#define PKA_ARITHMETIC_SUB_IN_OP1                      ((0x0A50UL - PKA_RAM_OFFSET)>>2)    /*!< Input operand op1 */
#define PKA_ARITHMETIC_SUB_IN_OP2                      ((0x0C68UL - PKA_RAM_OFFSET)>>2)    /*!< Input operand op2 */

/* Arithmetic subtraction output data */
#define PKA_ARITHMETIC_SUB_OUT_RESULT                  ((0x0E78UL - PKA_RAM_OFFSET)>>2)    /*!< Output result */

/* Arithmetic multiplication input data */
#define PKA_ARITHMETIC_MUL_NB_BITS                     ((0x0408UL - PKA_RAM_OFFSET)>>2)    /*!< Input operand number of bits */
#define PKA_ARITHMETIC_MUL_IN_OP1                      ((0x0A50UL - PKA_RAM_OFFSET)>>2)    /*!< Input operand op1 */
#define PKA_ARITHMETIC_MUL_IN_OP2                      ((0x0C68UL - PKA_RAM_OFFSET)>>2)    /*!< Input operand op2 */

/* Arithmetic multiplication output data */
#define PKA_ARITHMETIC_MUL_OUT_RESULT                  ((0x0E78UL - PKA_RAM_OFFSET)>>2)    /*!< Output result */

/* Comparison input data */
#define PKA_COMPARISON_IN_OP_NB_BITS                   ((0x0408UL - PKA_RAM_OFFSET)>>2)    /*!< Input operand number of bits */
#define PKA_COMPARISON_IN_OP1                          ((0x0A50UL - PKA_RAM_OFFSET)>>2)    /*!< Input operand op1 */
#define PKA_COMPARISON_IN_OP2                          ((0x0C68UL - PKA_RAM_OFFSET)>>2)    /*!< Input operand op2 */

/* Comparison output data */
#define PKA_COMPARISON_OUT_RESULT                      ((0x0E78UL - PKA_RAM_OFFSET)>>2)    /*!< Output result */

/* Modular addition input data */
#define PKA_MODULAR_ADD_NB_BITS                        ((0x0408UL - PKA_RAM_OFFSET)>>2)    /*!< Input operand number of bits */
#define PKA_MODULAR_ADD_IN_OP1                         ((0x0A50UL - PKA_RAM_OFFSET)>>2)    /*!< Input operand op1 */
#define PKA_MODULAR_ADD_IN_OP2                         ((0x0C68UL - PKA_RAM_OFFSET)>>2)    /*!< Input operand op2 */
#define PKA_MODULAR_ADD_IN_OP3_MOD                     ((0x1088UL - PKA_RAM_OFFSET)>>2)    /*!< Input operand op3 (modulus) */

/* Modular addition output data */
#define PKA_MODULAR_ADD_OUT_RESULT                     ((0x0E78UL - PKA_RAM_OFFSET)>>2)    /*!< Output result */

/* Modular inversion input data */
#define PKA_MODULAR_INV_NB_BITS                        ((0x0408UL - PKA_RAM_OFFSET)>>2)    /*!< Input operand number of bits */
#define PKA_MODULAR_INV_IN_OP1                         ((0x0A50UL - PKA_RAM_OFFSET)>>2)    /*!< Input operand op1 */
#define PKA_MODULAR_INV_IN_OP2_MOD                     ((0x0C68UL - PKA_RAM_OFFSET)>>2)    /*!< Input operand op2 (modulus) */

/* Modular inversion output data */
#define PKA_MODULAR_INV_OUT_RESULT                     ((0x0E78UL - PKA_RAM_OFFSET)>>2)    /*!< Output result */

/* Modular subtraction input data */
#define PKA_MODULAR_SUB_IN_OP_NB_BITS                  ((0x0408UL - PKA_RAM_OFFSET)>>2)    /*!< Input operand number of bits */
#define PKA_MODULAR_SUB_IN_OP1                         ((0x0A50UL - PKA_RAM_OFFSET)>>2)    /*!< Input operand op1 */
#define PKA_MODULAR_SUB_IN_OP2                         ((0x0C68UL - PKA_RAM_OFFSET)>>2)    /*!< Input operand op2 */
#define PKA_MODULAR_SUB_IN_OP3_MOD                     ((0x1088UL - PKA_RAM_OFFSET)>>2)    /*!< Input operand op3 */

/* Modular subtraction output data */
#define PKA_MODULAR_SUB_OUT_RESULT                     ((0x0E78UL - PKA_RAM_OFFSET)>>2)    /*!< Output result */

/* Montgomery multiplication input data */
#define PKA_MONTGOMERY_MUL_IN_OP_NB_BITS               ((0x0408UL - PKA_RAM_OFFSET)>>2)    /*!< Input operand number of bits */
#define PKA_MONTGOMERY_MUL_IN_OP1                      ((0x0A50UL - PKA_RAM_OFFSET)>>2)    /*!< Input operand op1 */
#define PKA_MONTGOMERY_MUL_IN_OP2                      ((0x0C68UL - PKA_RAM_OFFSET)>>2)    /*!< Input operand op2 */
#define PKA_MONTGOMERY_MUL_IN_OP3_MOD                  ((0x1088UL - PKA_RAM_OFFSET)>>2)    /*!< Input modulus */

/* Montgomery multiplication output data */
#define PKA_MONTGOMERY_MUL_OUT_RESULT                  ((0x0E78UL - PKA_RAM_OFFSET)>>2)    /*!< Output result */

/* Generic Arithmetic input data */
#define PKA_ARITHMETIC_ALL_OPS_NB_BITS                 ((0x0408UL - PKA_RAM_OFFSET)>>2)    /*!< Input operand number of bits */
#define PKA_ARITHMETIC_ALL_OPS_IN_OP1                  ((0x0A50UL - PKA_RAM_OFFSET)>>2)    /*!< Input operand op1 */
#define PKA_ARITHMETIC_ALL_OPS_IN_OP2                  ((0x0C68UL - PKA_RAM_OFFSET)>>2)    /*!< Input operand op2 */
#define PKA_ARITHMETIC_ALL_OPS_IN_OP3                  ((0x1088UL - PKA_RAM_OFFSET)>>2)    /*!< Input operand op2 */

/* Generic Arithmetic output data */
#define PKA_ARITHMETIC_ALL_OPS_OUT_RESULT              ((0x0E78UL - PKA_RAM_OFFSET)>>2)    /*!< Output result for arithmetic operations */

/* Compute ECC complete addition input data */
#define PKA_ECC_COMPLETE_ADD_IN_MOD_NB_BITS            ((0x0408UL - PKA_RAM_OFFSET)>>2)    /*!< Input Modulus number of bits */
#define PKA_ECC_COMPLETE_ADD_IN_A_COEFF_SIGN           ((0x0410UL - PKA_RAM_OFFSET)>>2)    /*!< Input sign of the 'a' coefficient */
#define PKA_ECC_COMPLETE_ADD_IN_A_COEFF                ((0x0418UL - PKA_RAM_OFFSET)>>2)    /*!< Input ECC curve '|a|' coefficient */
#define PKA_ECC_COMPLETE_ADD_IN_MOD_P                  ((0x0470UL - PKA_RAM_OFFSET)>>2)    /*!< Input modulus GF(p) */
#define PKA_ECC_COMPLETE_ADD_IN_POINT1_X               ((0x0628UL - PKA_RAM_OFFSET)>>2)    /*!< Input initial point P X coordinate */
#define PKA_ECC_COMPLETE_ADD_IN_POINT1_Y               ((0x0680UL - PKA_RAM_OFFSET)>>2)    /*!< Input initial point P Y coordinate */
#define PKA_ECC_COMPLETE_ADD_IN_POINT1_Z               ((0x06D8UL - PKA_RAM_OFFSET)>>2)    /*!< Input initial point P Z coordinate */
#define PKA_ECC_COMPLETE_ADD_IN_POINT2_X               ((0x0730UL - PKA_RAM_OFFSET)>>2)    /*!< Input initial point Q X coordinate */
#define PKA_ECC_COMPLETE_ADD_IN_POINT2_Y               ((0x0788UL - PKA_RAM_OFFSET)>>2)    /*!< Input initial point Q Y coordinate */
#define PKA_ECC_COMPLETE_ADD_IN_POINT2_Z               ((0x07E0UL - PKA_RAM_OFFSET)>>2)    /*!< Input initial point Q Z coordinate */

/* Compute ECC complete addition output data */
#define PKA_ECC_COMPLETE_ADD_OUT_RESULT_X              ((0x0D60UL - PKA_RAM_OFFSET)>>2)    /*!< Output result X coordinate */
#define PKA_ECC_COMPLETE_ADD_OUT_RESULT_Y              ((0x0DB8UL - PKA_RAM_OFFSET)>>2)    /*!< Output result Y coordinate */
#define PKA_ECC_COMPLETE_ADD_OUT_RESULT_Z              ((0x0E10UL - PKA_RAM_OFFSET)>>2)    /*!< Output result Z coordinate */

/* Compute ECC double base ladder input data */
#define PKA_ECC_DOUBLE_LADDER_IN_PRIME_ORDER_NB_BITS   ((0x0400UL - PKA_RAM_OFFSET)>>2)    /*!< Input n, order of the curve */
#define PKA_ECC_DOUBLE_LADDER_IN_MOD_NB_BITS           ((0x0408UL - PKA_RAM_OFFSET)>>2)    /*!< Input Modulus number of bits */
#define PKA_ECC_DOUBLE_LADDER_IN_A_COEFF_SIGN          ((0x0410UL - PKA_RAM_OFFSET)>>2)    /*!< Input sign of the 'a' coefficient */
#define PKA_ECC_DOUBLE_LADDER_IN_A_COEFF               ((0x0418UL - PKA_RAM_OFFSET)>>2)    /*!< Input ECC curve '|a|' coefficient */
#define PKA_ECC_DOUBLE_LADDER_IN_MOD_P                 ((0x0470UL - PKA_RAM_OFFSET)>>2)    /*!< Input modulus GF(p) */
#define PKA_ECC_DOUBLE_LADDER_IN_K_INTEGER             ((0x0520UL - PKA_RAM_OFFSET)>>2)    /*!< Input 'k' integer coefficient */
#define PKA_ECC_DOUBLE_LADDER_IN_M_INTEGER             ((0x0578UL - PKA_RAM_OFFSET)>>2)    /*!< Input 'm' integer coefficient */
#define PKA_ECC_DOUBLE_LADDER_IN_POINT1_X              ((0x0628UL - PKA_RAM_OFFSET)>>2)    /*!< Input initial point P X coordinate */
#define PKA_ECC_DOUBLE_LADDER_IN_POINT1_Y              ((0x0680UL - PKA_RAM_OFFSET)>>2)    /*!< Input initial point P Y coordinate */
#define PKA_ECC_DOUBLE_LADDER_IN_POINT1_Z              ((0x06D8UL - PKA_RAM_OFFSET)>>2)    /*!< Input initial point P Z coordinate */
#define PKA_ECC_DOUBLE_LADDER_IN_POINT2_X              ((0x0730UL - PKA_RAM_OFFSET)>>2)    /*!< Input initial point Q X coordinate */
#define PKA_ECC_DOUBLE_LADDER_IN_POINT2_Y              ((0x0788UL - PKA_RAM_OFFSET)>>2)    /*!< Input initial point Q Y coordinate */
#define PKA_ECC_DOUBLE_LADDER_IN_POINT2_Z              ((0x07E0UL - PKA_RAM_OFFSET)>>2)    /*!< Input initial point Q Z coordinate */

/* Compute ECC double base ladder output data */
#define PKA_ECC_DOUBLE_LADDER_OUT_RESULT_X             ((0x0578UL - PKA_RAM_OFFSET)>>2)    /*!< Output result X coordinate (affine coordinate) */
#define PKA_ECC_DOUBLE_LADDER_OUT_RESULT_Y             ((0x05D0UL - PKA_RAM_OFFSET)>>2)    /*!< Output result Y coordinate (affine coordinate) */
#define PKA_ECC_DOUBLE_LADDER_OUT_ERROR                ((0x0520UL - PKA_RAM_OFFSET)>>2)    /*!< Output result error */

/* Compute ECC projective to affine conversion input data */
#define PKA_ECC_PROJECTIVE_AFF_IN_MOD_NB_BITS          ((0x0408UL - PKA_RAM_OFFSET)>>2)    /*!< Input Modulus number of bits */
#define PKA_ECC_PROJECTIVE_AFF_IN_MOD_P                ((0x0470UL - PKA_RAM_OFFSET)>>2)    /*!< Input modulus GF(p) */
#define PKA_ECC_PROJECTIVE_AFF_IN_POINT_X              ((0x0D60UL - PKA_RAM_OFFSET)>>2)    /*!< Input initial projective point P X coordinate */
#define PKA_ECC_PROJECTIVE_AFF_IN_POINT_Y              ((0x0DB8UL - PKA_RAM_OFFSET)>>2)    /*!< Input initial projective point P Y coordinate */
#define PKA_ECC_PROJECTIVE_AFF_IN_POINT_Z              ((0x0E10UL - PKA_RAM_OFFSET)>>2)    /*!< Input initial projective point P Z coordinate */
#define PKA_ECC_PROJECTIVE_AFF_IN_MONTGOMERY_PARAM_R2  ((0x04C8UL - PKA_RAM_OFFSET)>>2)    /*!< Input storage area for Montgomery parameter */

/* Compute ECC projective to affine conversion output data */
#define PKA_ECC_PROJECTIVE_AFF_OUT_RESULT_X            ((0x0578UL - PKA_RAM_OFFSET)>>2)    /*!< Output result x affine coordinate */
#define PKA_ECC_PROJECTIVE_AFF_OUT_RESULT_Y            ((0x05D0UL - PKA_RAM_OFFSET)>>2)    /*!< Output result y affine coordinate */
#define PKA_ECC_PROJECTIVE_AFF_OUT_ERROR               ((0x0680UL - PKA_RAM_OFFSET)>>2)    /*!< Output result error */


/******************************************************************************/
/*                                                                            */
/*                                 VREFBUF                                    */
/*                                                                            */
/******************************************************************************/
/*******************  Bit definition for VREFBUF_CSR register  ****************/
#define VREFBUF_CSR_ENVR_Pos    (0UL)
#define VREFBUF_CSR_ENVR_Msk    (0x1UL << VREFBUF_CSR_ENVR_Pos)                     /*!< 0x00000001 */
#define VREFBUF_CSR_ENVR        VREFBUF_CSR_ENVR_Msk                                /*!<Voltage reference buffer enable */
#define VREFBUF_CSR_HIZ_Pos     (1UL)
#define VREFBUF_CSR_HIZ_Msk     (0x1UL << VREFBUF_CSR_HIZ_Pos)                      /*!< 0x00000002 */
#define VREFBUF_CSR_HIZ         VREFBUF_CSR_HIZ_Msk                                 /*!<High impedance mode             */
#define VREFBUF_CSR_VRS_Pos     (4UL)
#define VREFBUF_CSR_VRS_Msk     (0x7UL << VREFBUF_CSR_VRS_Pos)                      /*!< 0x00000004 */
#define VREFBUF_CSR_VRS         VREFBUF_CSR_VRS_Msk                                 /*!<Voltage reference scale         */
#define VREFBUF_CSR_VRS_0       (0x01UL<< VREFBUF_CSR_VRS_Pos)                      /*!< 0x000O0010 */
#define VREFBUF_CSR_VRS_1       (0x02UL<< VREFBUF_CSR_VRS_Pos)                      /*!< 0x00000020 */
#define VREFBUF_CSR_VRS_2       (0x04UL<< VREFBUF_CSR_VRS_Pos)                      /*!< 0x00000030 */
#define VREFBUF_CSR_VRR_Pos     (3UL)
#define VREFBUF_CSR_VRR_Msk     (0x1UL << VREFBUF_CSR_VRR_Pos)                      /*!< 0x00000008 */
#define VREFBUF_CSR_VRR         VREFBUF_CSR_VRR_Msk                                 /*!<Voltage reference buffer ready  */

/*******************  Bit definition for VREFBUF_CCR register  ******************/
#define VREFBUF_CCR_TRIM_Pos                (0UL)
#define VREFBUF_CCR_TRIM_Msk                (0x3FUL << VREFBUF_CCR_TRIM_Pos)        /*!< 0x0000003F */
#define VREFBUF_CCR_TRIM                    VREFBUF_CCR_TRIM_Msk                    /*!<TRIM[5:0] bits (Trimming code)  */

/******************************************************************************/
/*                                                                            */
/*                            Window WATCHDOG                                 */
/*                                                                            */
/******************************************************************************/
/*******************  Bit definition for WWDG_CR register  ********************/
#define WWDG_CR_T_Pos                       (0UL)
#define WWDG_CR_T_Msk                       (0x7FUL << WWDG_CR_T_Pos)               /*!< 0x0000007F */
#define WWDG_CR_T                           WWDG_CR_T_Msk                           /*!<T[6:0] bits (7-Bit counter (MSB to LSB)) */
#define WWDG_CR_T_0                         (0x01UL << WWDG_CR_T_Pos)               /*!< 0x00000001 */
#define WWDG_CR_T_1                         (0x02UL << WWDG_CR_T_Pos)               /*!< 0x00000002 */
#define WWDG_CR_T_2                         (0x04UL << WWDG_CR_T_Pos)               /*!< 0x00000004 */
#define WWDG_CR_T_3                         (0x08UL << WWDG_CR_T_Pos)               /*!< 0x00000008 */
#define WWDG_CR_T_4                         (0x10UL << WWDG_CR_T_Pos)               /*!< 0x00000010 */
#define WWDG_CR_T_5                         (0x20UL << WWDG_CR_T_Pos)               /*!< 0x00000020 */
#define WWDG_CR_T_6                         (0x40UL << WWDG_CR_T_Pos)               /*!< 0x00000040 */
#define WWDG_CR_WDGA_Pos                    (7UL)
#define WWDG_CR_WDGA_Msk                    (0x1UL << WWDG_CR_WDGA_Pos)             /*!< 0x00000080 */
#define WWDG_CR_WDGA                        WWDG_CR_WDGA_Msk                        /*!<Activation bit */

/*******************  Bit definition for WWDG_CFR register  *******************/
#define WWDG_CFR_W_Pos                      (0UL)
#define WWDG_CFR_W_Msk                      (0x7FUL << WWDG_CFR_W_Pos)              /*!< 0x0000007F */
#define WWDG_CFR_W                          WWDG_CFR_W_Msk                          /*!<W[6:0] bits (7-bit window value) */
#define WWDG_CFR_W_0                        (0x01UL << WWDG_CFR_W_Pos)              /*!< 0x00000001 */
#define WWDG_CFR_W_1                        (0x02UL << WWDG_CFR_W_Pos)              /*!< 0x00000002 */
#define WWDG_CFR_W_2                        (0x04UL << WWDG_CFR_W_Pos)              /*!< 0x00000004 */
#define WWDG_CFR_W_3                        (0x08UL << WWDG_CFR_W_Pos)              /*!< 0x00000008 */
#define WWDG_CFR_W_4                        (0x10UL << WWDG_CFR_W_Pos)              /*!< 0x00000010 */
#define WWDG_CFR_W_5                        (0x20UL << WWDG_CFR_W_Pos)              /*!< 0x00000020 */
#define WWDG_CFR_W_6                        (0x40UL << WWDG_CFR_W_Pos)              /*!< 0x00000040 */
#define WWDG_CFR_WDGTB_Pos                  (11UL)
#define WWDG_CFR_WDGTB_Msk                  (0x7UL << WWDG_CFR_WDGTB_Pos)           /*!< 0x00003800 */
#define WWDG_CFR_WDGTB                      WWDG_CFR_WDGTB_Msk                      /*!<WDGTB[2:0] bits (Timer Base) */
#define WWDG_CFR_WDGTB_0                    (0x1UL << WWDG_CFR_WDGTB_Pos)           /*!< 0x00000800 */
#define WWDG_CFR_WDGTB_1                    (0x2UL << WWDG_CFR_WDGTB_Pos)           /*!< 0x00001000 */
#define WWDG_CFR_WDGTB_2                    (0x4UL << WWDG_CFR_WDGTB_Pos)           /*!< 0x00002000 */
#define WWDG_CFR_EWI_Pos                    (9UL)
#define WWDG_CFR_EWI_Msk                    (0x1UL << WWDG_CFR_EWI_Pos)             /*!< 0x00000200 */
#define WWDG_CFR_EWI                        WWDG_CFR_EWI_Msk                        /*!<Early Wakeup Interrupt */

/*******************  Bit definition for WWDG_SR register  ********************/
#define WWDG_SR_EWIF_Pos                    (0UL)
#define WWDG_SR_EWIF_Msk                    (0x1UL << WWDG_SR_EWIF_Pos)             /*!< 0x00000001 */
#define WWDG_SR_EWIF                        WWDG_SR_EWIF_Msk                        /*!<Early Wakeup Interrupt Flag */

/******************************************************************************/
/*                                                                            */
/*                          XSPI  (OCTOSPI)                                   */
/*                                                                            */
/******************************************************************************/
/************  Bit definition for XSPI_CR register  **************************/
#define XSPI_CR_EN_Pos                   (0UL)
#define XSPI_CR_EN_Msk                   (0x1UL << XSPI_CR_EN_Pos)                        /*!< 0x00000001 */
#define XSPI_CR_EN                       XSPI_CR_EN_Msk                                   /*!< Enable */
#define XSPI_CR_ABORT_Pos                (1UL)
#define XSPI_CR_ABORT_Msk                (0x1UL << XSPI_CR_ABORT_Pos)                     /*!< 0x00000002 */
#define XSPI_CR_ABORT                    XSPI_CR_ABORT_Msk                                /*!< Abort request */
#define XSPI_CR_DMAEN_Pos                (2UL)
#define XSPI_CR_DMAEN_Msk                (0x1UL << XSPI_CR_DMAEN_Pos)                     /*!< 0x00000004 */
#define XSPI_CR_DMAEN                    XSPI_CR_DMAEN_Msk                                /*!< DMA Enable */
#define XSPI_CR_TCEN_Pos                 (3UL)
#define XSPI_CR_TCEN_Msk                 (0x1UL << XSPI_CR_TCEN_Pos)                      /*!< 0x00000008 */
#define XSPI_CR_TCEN                     XSPI_CR_TCEN_Msk                                 /*!< Timeout Counter Enable */
#define XSPI_CR_DMM_Pos                  (6UL)
#define XSPI_CR_DMM_Msk                  (0x1UL << XSPI_CR_DMM_Pos)                       /*!< 0x00000040 */
#define XSPI_CR_DMM                      XSPI_CR_DMM_Msk                                  /*!< Dual Memory Mode */
#define XSPI_CR_MSEL_Pos                 (7UL)
#define XSPI_CR_MSEL_Msk                 (0x1UL << XSPI_CR_MSEL_Pos)                      /*!< 0x00000080 */
#define XSPI_CR_MSEL                     XSPI_CR_MSEL_Msk                                 /*!< Memory Select */
#define XSPI_CR_FTHRES_Pos               (8UL)
#define XSPI_CR_FTHRES_Msk               (0x3FUL << XSPI_CR_FTHRES_Pos)                   /*!< 0x00003F00 */
#define XSPI_CR_FTHRES                   XSPI_CR_FTHRES_Msk                               /*!< FIFO Threshold Level */
#define XSPI_CR_TEIE_Pos                 (16UL)
#define XSPI_CR_TEIE_Msk                 (0x1UL << XSPI_CR_TEIE_Pos)                      /*!< 0x00010000 */
#define XSPI_CR_TEIE                     XSPI_CR_TEIE_Msk                                 /*!< Transfer Error Interrupt Enable */
#define XSPI_CR_TCIE_Pos                 (17UL)
#define XSPI_CR_TCIE_Msk                 (0x1UL << XSPI_CR_TCIE_Pos)                      /*!< 0x00020000 */
#define XSPI_CR_TCIE                     XSPI_CR_TCIE_Msk                                 /*!< Transfer Complete Interrupt Enable */
#define XSPI_CR_FTIE_Pos                 (18UL)
#define XSPI_CR_FTIE_Msk                 (0x1UL << XSPI_CR_FTIE_Pos)                      /*!< 0x00040000 */
#define XSPI_CR_FTIE                     XSPI_CR_FTIE_Msk                                 /*!< FIFO Threshold Interrupt Enable */
#define XSPI_CR_SMIE_Pos                 (19UL)
#define XSPI_CR_SMIE_Msk                 (0x1UL << XSPI_CR_SMIE_Pos)                      /*!< 0x00080000 */
#define XSPI_CR_SMIE                     XSPI_CR_SMIE_Msk                                 /*!< Status Match Interrupt Enable */
#define XSPI_CR_TOIE_Pos                 (20UL)
#define XSPI_CR_TOIE_Msk                 (0x1UL << XSPI_CR_TOIE_Pos)                      /*!< 0x00100000 */
#define XSPI_CR_TOIE                     XSPI_CR_TOIE_Msk                                 /*!< TimeOut Interrupt Enable */
#define XSPI_CR_APMS_Pos                 (22UL)
#define XSPI_CR_APMS_Msk                 (0x1UL << XSPI_CR_APMS_Pos)                      /*!< 0x00400000 */
#define XSPI_CR_APMS                     XSPI_CR_APMS_Msk                                 /*!< Automatic Poll Mode Stop */
#define XSPI_CR_PMM_Pos                  (23UL)
#define XSPI_CR_PMM_Msk                  (0x1UL << XSPI_CR_PMM_Pos)                       /*!< 0x00800000 */
#define XSPI_CR_PMM                      XSPI_CR_PMM_Msk                                  /*!< Polling Match Mode */
#define XSPI_CR_FMODE_Pos                (28UL)
#define XSPI_CR_FMODE_Msk                (0x3UL << XSPI_CR_FMODE_Pos)                     /*!< 0x30000000 */
#define XSPI_CR_FMODE                    XSPI_CR_FMODE_Msk                                /*!< Functional Mode */
#define XSPI_CR_FMODE_0                  (0x1UL << XSPI_CR_FMODE_Pos)                     /*!< 0x10000000 */
#define XSPI_CR_FMODE_1                  (0x2UL << XSPI_CR_FMODE_Pos)                     /*!< 0x20000000 */

/*************  Bit definition for XSPI_DCR1 register  ***********************/
#define XSPI_DCR1_CKMODE_Pos             (0UL)
#define XSPI_DCR1_CKMODE_Msk             (0x1UL << XSPI_DCR1_CKMODE_Pos)                  /*!< 0x00000001 */
#define XSPI_DCR1_CKMODE                 XSPI_DCR1_CKMODE_Msk                             /*!< Mode 0 / Mode 3 */
#define XSPI_DCR1_FRCK_Pos               (1UL)
#define XSPI_DCR1_FRCK_Msk               (0x1UL << XSPI_DCR1_FRCK_Pos)                    /*!< 0x00000002 */
#define XSPI_DCR1_FRCK                   XSPI_DCR1_FRCK_Msk                               /*!< Free Running Clock */
#define XSPI_OCTOSPI_DCR1_DLYBYP_Pos     (3UL)
#define XSPI_OCTOSPI_DCR1_DLYBYP_Msk     (0x1UL << XSPI_OCTOSPI_DCR1_DLYBYP_Pos)          /*!< 0x00000008 */
#define XSPI_OCTOSPI_DCR1_DLYBYP         XSPI_OCTOSPI_DCR1_DLYBYP_Msk                     /*!< Delay Block Bypass only for OCTOSPI */
#define XSPI_DCR1_CSHT_Pos               (8UL)
#define XSPI_DCR1_CSHT_Msk               (0x3FUL << XSPI_DCR1_CSHT_Pos)                   /*!< 0x00003F00 */
#define XSPI_DCR1_CSHT                   XSPI_DCR1_CSHT_Msk                               /*!< Chip Select High Time */
#define XSPI_DCR1_DEVSIZE_Pos            (16UL)
#define XSPI_DCR1_DEVSIZE_Msk            (0x1FUL << XSPI_DCR1_DEVSIZE_Pos)                /*!< 0x001F0000 */
#define XSPI_DCR1_DEVSIZE                XSPI_DCR1_DEVSIZE_Msk                            /*!< Device Size */
#define XSPI_DCR1_MTYP_Pos               (24UL)
#define XSPI_DCR1_MTYP_Msk               (0x7UL << XSPI_DCR1_MTYP_Pos)                    /*!< 0x07000000 */
#define XSPI_DCR1_MTYP                   XSPI_DCR1_MTYP_Msk                               /*!< Memory Type */
#define XSPI_DCR1_MTYP_0                 (0x1UL << XSPI_DCR1_MTYP_Pos)                    /*!< 0x01000000 */
#define XSPI_DCR1_MTYP_1                 (0x2UL << XSPI_DCR1_MTYP_Pos)                    /*!< 0x02000000 */
#define XSPI_DCR1_MTYP_2                 (0x4UL << XSPI_DCR1_MTYP_Pos)                    /*!< 0x04000000 */

/**************** Bit definition for XSPI_DCR2 register  *********************/
#define XSPI_DCR2_PRESCALER_Pos          (0UL)
#define XSPI_DCR2_PRESCALER_Msk          (0xFFUL << XSPI_DCR2_PRESCALER_Pos)              /*!< 0x000000FF */
#define XSPI_DCR2_PRESCALER              XSPI_DCR2_PRESCALER_Msk                          /*!< Clock prescaler */
#define XSPI_DCR2_WRAPSIZE_Pos           (16UL)
#define XSPI_DCR2_WRAPSIZE_Msk           (0x7UL << XSPI_DCR2_WRAPSIZE_Pos)                /*!< 0x00070000 */
#define XSPI_DCR2_WRAPSIZE               XSPI_DCR2_WRAPSIZE_Msk                           /*!< Wrap Size */
#define XSPI_DCR2_WRAPSIZE_0             (0x1UL << XSPI_DCR2_WRAPSIZE_Pos)                /*!< 0x00010000 */
#define XSPI_DCR2_WRAPSIZE_1             (0x2UL << XSPI_DCR2_WRAPSIZE_Pos)                /*!< 0x00020000 */
#define XSPI_DCR2_WRAPSIZE_2             (0x4UL << XSPI_DCR2_WRAPSIZE_Pos)                /*!< 0x00040000 */

/****************  Bit definition for XSPI_DCR3 register  ********************/
#define XSPI_OCTOSPI_DCR3_MAXTRAN_Pos    (0UL)
#define XSPI_OCTOSPI_DCR3_MAXTRAN_Msk    (0xFFUL << XSPI_OCTOSPI_DCR3_MAXTRAN_Pos)        /*!< 0x000000FF */
#define XSPI_OCTOSPI_DCR3_MAXTRAN        XSPI_OCTOSPI_DCR3_MAXTRAN_Msk                    /*!< Maximum transfer only for OCTOSPI */
#define XSPI_DCR3_CSBOUND_Pos            (16UL)
#define XSPI_DCR3_CSBOUND_Msk            (0x1FUL << XSPI_DCR3_CSBOUND_Pos)                /*!< 0x001F0000 */
#define XSPI_DCR3_CSBOUND                XSPI_DCR3_CSBOUND_Msk                            /*!< Maximum transfer */
/****************  Bit definition for XSPI_DCR4 register  ********************/
#define XSPI_DCR4_REFRESH_Pos            (0UL)
#define XSPI_DCR4_REFRESH_Msk            (0xFFFFFFFFUL << XSPI_DCR4_REFRESH_Pos)          /*!< 0xFFFFFFFF */
#define XSPI_DCR4_REFRESH                XSPI_DCR4_REFRESH_Msk                            /*!< Refresh rate */

/*****************  Bit definition for XSPI_SR  register  ********************/
#define XSPI_SR_TEF_Pos                  (0UL)
#define XSPI_SR_TEF_Msk                  (0x1UL << XSPI_SR_TEF_Pos)                       /*!< 0x00000001 */
#define XSPI_SR_TEF                      XSPI_SR_TEF_Msk                                  /*!< Transfer Error Flag */
#define XSPI_SR_TCF_Pos                  (1UL)
#define XSPI_SR_TCF_Msk                  (0x1UL << XSPI_SR_TCF_Pos)                       /*!< 0x00000002 */
#define XSPI_SR_TCF                      XSPI_SR_TCF_Msk                                  /*!< Transfer Complete Flag */
#define XSPI_SR_FTF_Pos                  (2UL)
#define XSPI_SR_FTF_Msk                  (0x1UL << XSPI_SR_FTF_Pos)                       /*!< 0x00000004 */
#define XSPI_SR_FTF                      XSPI_SR_FTF_Msk                                  /*!< FIFO Threshold Flag */
#define XSPI_SR_SMF_Pos                  (3UL)
#define XSPI_SR_SMF_Msk                  (0x1UL << XSPI_SR_SMF_Pos)                       /*!< 0x00000008 */
#define XSPI_SR_SMF                      XSPI_SR_SMF_Msk                                  /*!< Status Match Flag */
#define XSPI_SR_TOF_Pos                  (4UL)
#define XSPI_SR_TOF_Msk                  (0x1UL << XSPI_SR_TOF_Pos)                       /*!< 0x00000010 */
#define XSPI_SR_TOF                      XSPI_SR_TOF_Msk                                  /*!< Timeout Flag */
#define XSPI_SR_BUSY_Pos                 (5UL)
#define XSPI_SR_BUSY_Msk                 (0x1UL << XSPI_SR_BUSY_Pos)                      /*!< 0x00000020 */
#define XSPI_SR_BUSY                     XSPI_SR_BUSY_Msk                                 /*!< Busy */
#define XSPI_SR_FLEVEL_Pos               (8UL)
#define XSPI_SR_FLEVEL_Msk               (0x7FUL << XSPI_SR_FLEVEL_Pos)                   /*!< 0x00007F00 */
#define XSPI_SR_FLEVEL                   XSPI_SR_FLEVEL_Msk                               /*!< FIFO Level */

/****************  Bit definition for XSPI_FCR register  *********************/
#define XSPI_FCR_CTEF_Pos                (0UL)
#define XSPI_FCR_CTEF_Msk                (0x1UL << XSPI_FCR_CTEF_Pos)                     /*!< 0x00000001 */
#define XSPI_FCR_CTEF                    XSPI_FCR_CTEF_Msk                                /*!< Clear Transfer Error Flag */
#define XSPI_FCR_CTCF_Pos                (1UL)
#define XSPI_FCR_CTCF_Msk                (0x1UL << XSPI_FCR_CTCF_Pos)                     /*!< 0x00000002 */
#define XSPI_FCR_CTCF                    XSPI_FCR_CTCF_Msk                                /*!< Clear Transfer Complete Flag */
#define XSPI_FCR_CSMF_Pos                (3UL)
#define XSPI_FCR_CSMF_Msk                (0x1UL << XSPI_FCR_CSMF_Pos)                     /*!< 0x00000008 */
#define XSPI_FCR_CSMF                    XSPI_FCR_CSMF_Msk                                /*!< Clear Status Match Flag */
#define XSPI_FCR_CTOF_Pos                (4UL)
#define XSPI_FCR_CTOF_Msk                (0x1UL << XSPI_FCR_CTOF_Pos)                     /*!< 0x00000010 */
#define XSPI_FCR_CTOF                    XSPI_FCR_CTOF_Msk                                /*!< Clear Timeout Flag */

/****************  Bit definition for XSPI_DLR register  *********************/
#define XSPI_DLR_DL_Pos                  (0UL)
#define XSPI_DLR_DL_Msk                  (0xFFFFFFFFUL << XSPI_DLR_DL_Pos)                /*!< 0xFFFFFFFF */
#define XSPI_DLR_DL                      XSPI_DLR_DL_Msk                                  /*!< Data Length */

/*****************  Bit definition for XSPI_AR register  *********************/
#define XSPI_AR_ADDRESS_Pos              (0UL)
#define XSPI_AR_ADDRESS_Msk              (0xFFFFFFFFUL << XSPI_AR_ADDRESS_Pos)            /*!< 0xFFFFFFFF */
#define XSPI_AR_ADDRESS                  XSPI_AR_ADDRESS_Msk                              /*!< Address */

/*****************  Bit definition for XSPI_DR register  *********************/
#define XSPI_DR_DATA_Pos                 (0UL)
#define XSPI_DR_DATA_Msk                 (0xFFFFFFFFUL << XSPI_DR_DATA_Pos)               /*!< 0xFFFFFFFF */
#define XSPI_DR_DATA                     XSPI_DR_DATA_Msk                                 /*!< Data */

/***************  Bit definition for XSPI_PSMKR register  ********************/
#define XSPI_PSMKR_MASK_Pos              (0UL)
#define XSPI_PSMKR_MASK_Msk              (0xFFFFFFFFUL << XSPI_PSMKR_MASK_Pos)            /*!< 0xFFFFFFFF */
#define XSPI_PSMKR_MASK                  XSPI_PSMKR_MASK_Msk                              /*!< Status mask */

/***************  Bit definition for XSPI_PSMAR register  ********************/
#define XSPI_PSMAR_MATCH_Pos             (0UL)
#define XSPI_PSMAR_MATCH_Msk             (0xFFFFFFFFUL << XSPI_PSMAR_MATCH_Pos)           /*!< 0xFFFFFFFF */
#define XSPI_PSMAR_MATCH                 XSPI_PSMAR_MATCH_Msk                             /*!< Status match */

/****************  Bit definition for XSPI_PIR register  *********************/
#define XSPI_PIR_INTERVAL_Pos            (0UL)
#define XSPI_PIR_INTERVAL_Msk            (0xFFFFUL << XSPI_PIR_INTERVAL_Pos)              /*!< 0x0000FFFF */
#define XSPI_PIR_INTERVAL                XSPI_PIR_INTERVAL_Msk                            /*!< Polling Interval */

/****************  Bit definition for XSPI_CCR register  *********************/
#define XSPI_CCR_IMODE_Pos               (0UL)
#define XSPI_CCR_IMODE_Msk               (0x7UL << XSPI_CCR_IMODE_Pos)                    /*!< 0x00000007 */
#define XSPI_CCR_IMODE                   XSPI_CCR_IMODE_Msk                               /*!< Instruction Mode */
#define XSPI_CCR_IMODE_0                 (0x1UL << XSPI_CCR_IMODE_Pos)                    /*!< 0x00000001 */
#define XSPI_CCR_IMODE_1                 (0x2UL << XSPI_CCR_IMODE_Pos)                    /*!< 0x00000002 */
#define XSPI_CCR_IMODE_2                 (0x4UL << XSPI_CCR_IMODE_Pos)                    /*!< 0x00000004 */
#define XSPI_CCR_IDTR_Pos                (3UL)
#define XSPI_CCR_IDTR_Msk                (0x1UL << XSPI_CCR_IDTR_Pos)                     /*!< 0x00000008 */
#define XSPI_CCR_IDTR                    XSPI_CCR_IDTR_Msk                                /*!< Instruction Double Transfer Rate */
#define XSPI_CCR_ISIZE_Pos               (4UL)
#define XSPI_CCR_ISIZE_Msk               (0x3UL << XSPI_CCR_ISIZE_Pos)                    /*!< 0x00000030 */
#define XSPI_CCR_ISIZE                   XSPI_CCR_ISIZE_Msk                               /*!< Instruction Size */
#define XSPI_CCR_ISIZE_0                 (0x1UL << XSPI_CCR_ISIZE_Pos)                    /*!< 0x00000010 */
#define XSPI_CCR_ISIZE_1                 (0x2UL << XSPI_CCR_ISIZE_Pos)                    /*!< 0x00000020 */
#define XSPI_CCR_ADMODE_Pos              (8UL)
#define XSPI_CCR_ADMODE_Msk              (0x7UL << XSPI_CCR_ADMODE_Pos)                   /*!< 0x00000700 */
#define XSPI_CCR_ADMODE                  XSPI_CCR_ADMODE_Msk                              /*!< Address Mode */
#define XSPI_CCR_ADMODE_0                (0x1UL << XSPI_CCR_ADMODE_Pos)                   /*!< 0x00000100 */
#define XSPI_CCR_ADMODE_1                (0x2UL << XSPI_CCR_ADMODE_Pos)                   /*!< 0x00000200 */
#define XSPI_CCR_ADMODE_2                (0x4UL << XSPI_CCR_ADMODE_Pos)                   /*!< 0x00000400 */
#define XSPI_CCR_ADDTR_Pos               (11UL)
#define XSPI_CCR_ADDTR_Msk               (0x1UL << XSPI_CCR_ADDTR_Pos)                    /*!< 0x00000800 */
#define XSPI_CCR_ADDTR                   XSPI_CCR_ADDTR_Msk                               /*!< Address Double Transfer Rate */
#define XSPI_CCR_ADSIZE_Pos              (12UL)
#define XSPI_CCR_ADSIZE_Msk              (0x3UL << XSPI_CCR_ADSIZE_Pos)                   /*!< 0x00003000 */
#define XSPI_CCR_ADSIZE                  XSPI_CCR_ADSIZE_Msk                              /*!< Address Size */
#define XSPI_CCR_ADSIZE_0                (0x1UL << XSPI_CCR_ADSIZE_Pos)                   /*!< 0x00001000 */
#define XSPI_CCR_ADSIZE_1                (0x2UL << XSPI_CCR_ADSIZE_Pos)                   /*!< 0x00002000 */
#define XSPI_CCR_ABMODE_Pos              (16UL)
#define XSPI_CCR_ABMODE_Msk              (0x7UL << XSPI_CCR_ABMODE_Pos)                   /*!< 0x00070000 */
#define XSPI_CCR_ABMODE                  XSPI_CCR_ABMODE_Msk                              /*!< Alternate Bytes Mode */
#define XSPI_CCR_ABMODE_0                (0x1UL << XSPI_CCR_ABMODE_Pos)                   /*!< 0x00010000 */
#define XSPI_CCR_ABMODE_1                (0x2UL << XSPI_CCR_ABMODE_Pos)                   /*!< 0x00020000 */
#define XSPI_CCR_ABMODE_2                (0x4UL << XSPI_CCR_ABMODE_Pos)                   /*!< 0x00040000 */
#define XSPI_CCR_ABDTR_Pos               (19UL)
#define XSPI_CCR_ABDTR_Msk               (0x1UL << XSPI_CCR_ABDTR_Pos)                    /*!< 0x00080000 */
#define XSPI_CCR_ABDTR                   XSPI_CCR_ABDTR_Msk                               /*!< Alternate Bytes Double Transfer Rate */
#define XSPI_CCR_ABSIZE_Pos              (20UL)
#define XSPI_CCR_ABSIZE_Msk              (0x3UL << XSPI_CCR_ABSIZE_Pos)                   /*!< 0x00300000 */
#define XSPI_CCR_ABSIZE                  XSPI_CCR_ABSIZE_Msk                              /*!< Alternate Bytes Size */
#define XSPI_CCR_ABSIZE_0                (0x1UL << XSPI_CCR_ABSIZE_Pos)                   /*!< 0x00100000 */
#define XSPI_CCR_ABSIZE_1                (0x2UL << XSPI_CCR_ABSIZE_Pos)                   /*!< 0x00200000 */
#define XSPI_CCR_DMODE_Pos               (24UL)
#define XSPI_CCR_DMODE_Msk               (0x7UL << XSPI_CCR_DMODE_Pos)                    /*!< 0x07000000 */
#define XSPI_CCR_DMODE                   XSPI_CCR_DMODE_Msk                               /*!< Data Mode */
#define XSPI_CCR_DMODE_0                 (0x1UL << XSPI_CCR_DMODE_Pos)                    /*!< 0x01000000 */
#define XSPI_CCR_DMODE_1                 (0x2UL << XSPI_CCR_DMODE_Pos)                    /*!< 0x02000000 */
#define XSPI_CCR_DMODE_2                 (0x4UL << XSPI_CCR_DMODE_Pos)                    /*!< 0x04000000 */
#define XSPI_CCR_DDTR_Pos                (27UL)
#define XSPI_CCR_DDTR_Msk                (0x1UL << XSPI_CCR_DDTR_Pos)                     /*!< 0x08000000 */
#define XSPI_CCR_DDTR                    XSPI_CCR_DDTR_Msk                                /*!< Data Double Transfer Rate */
#define XSPI_CCR_DQSE_Pos                (29UL)
#define XSPI_CCR_DQSE_Msk                (0x1UL << XSPI_CCR_DQSE_Pos)                     /*!< 0x20000000 */
#define XSPI_CCR_DQSE                    XSPI_CCR_DQSE_Msk                                /*!< DQS Enable */
#define XSPI_CCR_SIOO_Pos                (31UL)
#define XSPI_CCR_SIOO_Msk                (0x1UL << XSPI_CCR_SIOO_Pos)                     /*!< 0x80000000 */
#define XSPI_CCR_SIOO                    XSPI_CCR_SIOO_Msk                                /*!< Send Instruction Only Once Mode */

/****************  Bit definition for XSPI_TCR register  *********************/
#define XSPI_TCR_DCYC_Pos                (0UL)
#define XSPI_TCR_DCYC_Msk                (0x1FUL << XSPI_TCR_DCYC_Pos)                    /*!< 0x0000001F */
#define XSPI_TCR_DCYC                    XSPI_TCR_DCYC_Msk                                /*!< Number of Dummy Cycles */
#define XSPI_TCR_DHQC_Pos                (28UL)
#define XSPI_TCR_DHQC_Msk                (0x1UL << XSPI_TCR_DHQC_Pos)                     /*!< 0x10000000 */
#define XSPI_TCR_DHQC                    XSPI_TCR_DHQC_Msk                                /*!< Delay Hold Quarter Cycle */
#define XSPI_TCR_SSHIFT_Pos              (30UL)
#define XSPI_TCR_SSHIFT_Msk              (0x1UL << XSPI_TCR_SSHIFT_Pos)                   /*!< 0x40000000 */
#define XSPI_TCR_SSHIFT                  XSPI_TCR_SSHIFT_Msk                              /*!< Sample Shift */

/*****************  Bit definition for XSPI_IR register  *********************/
#define XSPI_IR_INSTRUCTION_Pos          (0UL)
#define XSPI_IR_INSTRUCTION_Msk          (0xFFFFFFFFUL << XSPI_IR_INSTRUCTION_Pos)        /*!< 0xFFFFFFFF */
#define XSPI_IR_INSTRUCTION              XSPI_IR_INSTRUCTION_Msk                          /*!< Instruction */

/****************  Bit definition for XSPI_ABR register  *********************/
#define XSPI_ABR_ALTERNATE_Pos           (0UL)
#define XSPI_ABR_ALTERNATE_Msk           (0xFFFFFFFFUL << XSPI_ABR_ALTERNATE_Pos)         /*!< 0xFFFFFFFF */
#define XSPI_ABR_ALTERNATE               XSPI_ABR_ALTERNATE_Msk                           /*!< Alternate Bytes */

/****************  Bit definition for XSPI_LPTR register  ********************/
#define XSPI_LPTR_TIMEOUT_Pos            (0UL)
#define XSPI_LPTR_TIMEOUT_Msk            (0xFFFFUL << XSPI_LPTR_TIMEOUT_Pos)              /*!< 0x0000FFFF */
#define XSPI_LPTR_TIMEOUT                XSPI_LPTR_TIMEOUT_Msk                            /*!< Timeout period */

/****************  Bit definition for XSPI_WPCCR register  *******************/
#define XSPI_WPCCR_IMODE_Pos             (0UL)
#define XSPI_WPCCR_IMODE_Msk             (0x7UL << XSPI_WPCCR_IMODE_Pos)                  /*!< 0x00000007 */
#define XSPI_WPCCR_IMODE                 XSPI_WPCCR_IMODE_Msk                             /*!< Instruction Mode */
#define XSPI_WPCCR_IMODE_0               (0x1UL << XSPI_WPCCR_IMODE_Pos)                  /*!< 0x00000001 */
#define XSPI_WPCCR_IMODE_1               (0x2UL << XSPI_WPCCR_IMODE_Pos)                  /*!< 0x00000002 */
#define XSPI_WPCCR_IMODE_2               (0x4UL << XSPI_WPCCR_IMODE_Pos)                  /*!< 0x00000004 */
#define XSPI_WPCCR_IDTR_Pos              (3UL)
#define XSPI_WPCCR_IDTR_Msk              (0x1UL << XSPI_WPCCR_IDTR_Pos)                   /*!< 0x00000008 */
#define XSPI_WPCCR_IDTR                  XSPI_WPCCR_IDTR_Msk                              /*!< Instruction Double Transfer Rate */
#define XSPI_WPCCR_ISIZE_Pos             (4UL)
#define XSPI_WPCCR_ISIZE_Msk             (0x3UL << XSPI_WPCCR_ISIZE_Pos)                  /*!< 0x00000030 */
#define XSPI_WPCCR_ISIZE                 XSPI_WPCCR_ISIZE_Msk                             /*!< Instruction Size */
#define XSPI_WPCCR_ISIZE_0               (0x1UL << XSPI_WPCCR_ISIZE_Pos)                  /*!< 0x00000010 */
#define XSPI_WPCCR_ISIZE_1               (0x2UL << XSPI_WPCCR_ISIZE_Pos)                  /*!< 0x00000020 */
#define XSPI_WPCCR_ADMODE_Pos            (8UL)
#define XSPI_WPCCR_ADMODE_Msk            (0x7UL << XSPI_WPCCR_ADMODE_Pos)                 /*!< 0x00000700 */
#define XSPI_WPCCR_ADMODE                XSPI_WPCCR_ADMODE_Msk                            /*!< Address Mode */
#define XSPI_WPCCR_ADMODE_0              (0x1UL << XSPI_WPCCR_ADMODE_Pos)                 /*!< 0x00000100 */
#define XSPI_WPCCR_ADMODE_1              (0x2UL << XSPI_WPCCR_ADMODE_Pos)                 /*!< 0x00000200 */
#define XSPI_WPCCR_ADMODE_2              (0x4UL << XSPI_WPCCR_ADMODE_Pos)                 /*!< 0x00000400 */
#define XSPI_WPCCR_ADDTR_Pos             (11UL)
#define XSPI_WPCCR_ADDTR_Msk             (0x1UL << XSPI_WPCCR_ADDTR_Pos)                  /*!< 0x00000800 */
#define XSPI_WPCCR_ADDTR                 XSPI_WPCCR_ADDTR_Msk                             /*!< Address Double Transfer Rate */
#define XSPI_WPCCR_ADSIZE_Pos            (12UL)
#define XSPI_WPCCR_ADSIZE_Msk            (0x3UL << XSPI_WPCCR_ADSIZE_Pos)                 /*!< 0x00003000 */
#define XSPI_WPCCR_ADSIZE                XSPI_WPCCR_ADSIZE_Msk                            /*!< Address Size */
#define XSPI_WPCCR_ADSIZE_0              (0x1UL << XSPI_WPCCR_ADSIZE_Pos)                 /*!< 0x00001000 */
#define XSPI_WPCCR_ADSIZE_1              (0x2UL << XSPI_WPCCR_ADSIZE_Pos)                 /*!< 0x00002000 */
#define XSPI_WPCCR_ABMODE_Pos            (16UL)
#define XSPI_WPCCR_ABMODE_Msk            (0x7UL << XSPI_WPCCR_ABMODE_Pos)                 /*!< 0x00070000 */
#define XSPI_WPCCR_ABMODE                XSPI_WPCCR_ABMODE_Msk                            /*!< Alternate Bytes Mode */
#define XSPI_WPCCR_ABMODE_0              (0x1UL << XSPI_WPCCR_ABMODE_Pos)                 /*!< 0x00010000 */
#define XSPI_WPCCR_ABMODE_1              (0x2UL << XSPI_WPCCR_ABMODE_Pos)                 /*!< 0x00020000 */
#define XSPI_WPCCR_ABMODE_2              (0x4UL << XSPI_WPCCR_ABMODE_Pos)                 /*!< 0x00040000 */
#define XSPI_WPCCR_ABDTR_Pos             (19UL)
#define XSPI_WPCCR_ABDTR_Msk             (0x1UL << XSPI_WPCCR_ABDTR_Pos)                  /*!< 0x00080000 */
#define XSPI_WPCCR_ABDTR                 XSPI_WPCCR_ABDTR_Msk                             /*!< Alternate Bytes Double Transfer Rate */
#define XSPI_WPCCR_ABSIZE_Pos            (20UL)
#define XSPI_WPCCR_ABSIZE_Msk            (0x3UL << XSPI_WPCCR_ABSIZE_Pos)                 /*!< 0x00300000 */
#define XSPI_WPCCR_ABSIZE                XSPI_WPCCR_ABSIZE_Msk                            /*!< Alternate Bytes Size */
#define XSPI_WPCCR_ABSIZE_0              (0x1UL << XSPI_WPCCR_ABSIZE_Pos)                 /*!< 0x00100000 */
#define XSPI_WPCCR_ABSIZE_1              (0x2UL << XSPI_WPCCR_ABSIZE_Pos)                 /*!< 0x00200000 */
#define XSPI_WPCCR_DMODE_Pos             (24UL)
#define XSPI_WPCCR_DMODE_Msk             (0x7UL << XSPI_WPCCR_DMODE_Pos)                  /*!< 0x07000000 */
#define XSPI_WPCCR_DMODE                 XSPI_WPCCR_DMODE_Msk                             /*!< Data Mode */
#define XSPI_WPCCR_DMODE_0               (0x1UL << XSPI_WPCCR_DMODE_Pos)                  /*!< 0x01000000 */
#define XSPI_WPCCR_DMODE_1               (0x2UL << XSPI_WPCCR_DMODE_Pos)                  /*!< 0x02000000 */
#define XSPI_WPCCR_DMODE_2               (0x4UL << XSPI_WPCCR_DMODE_Pos)                  /*!< 0x04000000 */
#define XSPI_WPCCR_DDTR_Pos              (27UL)
#define XSPI_WPCCR_DDTR_Msk              (0x1UL << XSPI_WPCCR_DDTR_Pos)                   /*!< 0x08000000 */
#define XSPI_WPCCR_DDTR                  XSPI_WPCCR_DDTR_Msk                              /*!< Data Double Transfer Rate */
#define XSPI_WPCCR_DQSE_Pos              (29UL)
#define XSPI_WPCCR_DQSE_Msk              (0x1UL << XSPI_WPCCR_DQSE_Pos)                   /*!< 0x20000000 */
#define XSPI_WPCCR_DQSE                  XSPI_WPCCR_DQSE_Msk                              /*!< DQS Enable */

/****************  Bit definition for XSPI_WPTCR register  *******************/
#define XSPI_WPTCR_DCYC_Pos              (0UL)
#define XSPI_WPTCR_DCYC_Msk              (0x1FUL << XSPI_WPTCR_DCYC_Pos)                  /*!< 0x0000001F */
#define XSPI_WPTCR_DCYC                  XSPI_WPTCR_DCYC_Msk                              /*!< Number of Dummy Cycles */
#define XSPI_WPTCR_DHQC_Pos              (28UL)
#define XSPI_WPTCR_DHQC_Msk              (0x1UL << XSPI_WPTCR_DHQC_Pos)                   /*!< 0x10000000 */
#define XSPI_WPTCR_DHQC                  XSPI_WPTCR_DHQC_Msk                              /*!< Delay Hold Quarter Cycle */
#define XSPI_WPTCR_SSHIFT_Pos            (30UL)
#define XSPI_WPTCR_SSHIFT_Msk            (0x1UL << XSPI_WPTCR_SSHIFT_Pos)                 /*!< 0x40000000 */
#define XSPI_WPTCR_SSHIFT                XSPI_WPTCR_SSHIFT_Msk                            /*!< Sample Shift */

/*****************  Bit definition for XSPI_WPIR register  *******************/
#define XSPI_WPIR_INSTRUCTION_Pos        (0UL)
#define XSPI_WPIR_INSTRUCTION_Msk        (0xFFFFFFFFUL << XSPI_WPIR_INSTRUCTION_Pos)      /*!< 0xFFFFFFFF */
#define XSPI_WPIR_INSTRUCTION            XSPI_WPIR_INSTRUCTION_Msk                        /*!< Instruction */

/****************  Bit definition for XSPI_WPABR register  *******************/
#define XSPI_WPABR_ALTERNATE_Pos         (0UL)
#define XSPI_WPABR_ALTERNATE_Msk         (0xFFFFFFFFUL << XSPI_WPABR_ALTERNATE_Pos)       /*!< 0xFFFFFFFF */
#define XSPI_WPABR_ALTERNATE             XSPI_WPABR_ALTERNATE_Msk                         /*!< Alternate Bytes */

/****************  Bit definition for XSPI_WCCRregister  *********************/
#define XSPI_WCCR_IMODE_Pos              (0UL)
#define XSPI_WCCR_IMODE_Msk              (0x7UL << XSPI_WCCR_IMODE_Pos)                   /*!< 0x00000007 */
#define XSPI_WCCR_IMODE                  XSPI_WCCR_IMODE_Msk                              /*!< Instruction Mode */
#define XSPI_WCCR_IMODE_0                (0x1UL << XSPI_WCCR_IMODE_Pos)                   /*!< 0x00000001 */
#define XSPI_WCCR_IMODE_1                (0x2UL << XSPI_WCCR_IMODE_Pos)                   /*!< 0x00000002 */
#define XSPI_WCCR_IMODE_2                (0x4UL << XSPI_WCCR_IMODE_Pos)                   /*!< 0x00000004 */
#define XSPI_WCCR_IDTR_Pos               (3UL)
#define XSPI_WCCR_IDTR_Msk               (0x1UL << XSPI_WCCR_IDTR_Pos)                    /*!< 0x00000008 */
#define XSPI_WCCR_IDTR                   XSPI_WCCR_IDTR_Msk                               /*!< Instruction Double Transfer Rate */
#define XSPI_WCCR_ISIZE_Pos              (4UL)
#define XSPI_WCCR_ISIZE_Msk              (0x3UL << XSPI_WCCR_ISIZE_Pos)                   /*!< 0x00000030 */
#define XSPI_WCCR_ISIZE                  XSPI_WCCR_ISIZE_Msk                              /*!< Instruction Size */
#define XSPI_WCCR_ISIZE_0                (0x1UL << XSPI_WCCR_ISIZE_Pos)                   /*!< 0x00000010 */
#define XSPI_WCCR_ISIZE_1                (0x2UL << XSPI_WCCR_ISIZE_Pos)                   /*!< 0x00000020 */
#define XSPI_WCCR_ADMODE_Pos             (8UL)
#define XSPI_WCCR_ADMODE_Msk             (0x7UL << XSPI_WCCR_ADMODE_Pos)                  /*!< 0x00000700 */
#define XSPI_WCCR_ADMODE                 XSPI_WCCR_ADMODE_Msk                             /*!< Address Mode */
#define XSPI_WCCR_ADMODE_0               (0x1UL << XSPI_WCCR_ADMODE_Pos)                  /*!< 0x00000100 */
#define XSPI_WCCR_ADMODE_1               (0x2UL << XSPI_WCCR_ADMODE_Pos)                  /*!< 0x00000200 */
#define XSPI_WCCR_ADMODE_2               (0x4UL << XSPI_WCCR_ADMODE_Pos)                  /*!< 0x00000400 */
#define XSPI_WCCR_ADDTR_Pos              (11UL)
#define XSPI_WCCR_ADDTR_Msk              (0x1UL << XSPI_WCCR_ADDTR_Pos)                   /*!< 0x00000800 */
#define XSPI_WCCR_ADDTR                  XSPI_WCCR_ADDTR_Msk                              /*!< Address Double Transfer Rate */
#define XSPI_WCCR_ADSIZE_Pos             (12UL)
#define XSPI_WCCR_ADSIZE_Msk             (0x3UL << XSPI_WCCR_ADSIZE_Pos)                  /*!< 0x00003000 */
#define XSPI_WCCR_ADSIZE                 XSPI_WCCR_ADSIZE_Msk                             /*!< Address Size */
#define XSPI_WCCR_ADSIZE_0               (0x1UL << XSPI_WCCR_ADSIZE_Pos)                  /*!< 0x00001000 */
#define XSPI_WCCR_ADSIZE_1               (0x2UL << XSPI_WCCR_ADSIZE_Pos)                  /*!< 0x00002000 */
#define XSPI_WCCR_ABMODE_Pos             (16UL)
#define XSPI_WCCR_ABMODE_Msk             (0x7UL << XSPI_WCCR_ABMODE_Pos)                  /*!< 0x00070000 */
#define XSPI_WCCR_ABMODE                 XSPI_WCCR_ABMODE_Msk                             /*!< Alternate Bytes Mode */
#define XSPI_WCCR_ABMODE_0               (0x1UL << XSPI_WCCR_ABMODE_Pos)                  /*!< 0x00010000 */
#define XSPI_WCCR_ABMODE_1               (0x2UL << XSPI_WCCR_ABMODE_Pos)                  /*!< 0x00020000 */
#define XSPI_WCCR_ABMODE_2               (0x4UL << XSPI_WCCR_ABMODE_Pos)                  /*!< 0x00040000 */
#define XSPI_WCCR_ABDTR_Pos              (19UL)
#define XSPI_WCCR_ABDTR_Msk              (0x1UL << XSPI_WCCR_ABDTR_Pos)                   /*!< 0x00080000 */
#define XSPI_WCCR_ABDTR                  XSPI_WCCR_ABDTR_Msk                              /*!< Alternate Bytes Double Transfer Rate */
#define XSPI_WCCR_ABSIZE_Pos             (20UL)
#define XSPI_WCCR_ABSIZE_Msk             (0x3UL << XSPI_WCCR_ABSIZE_Pos)                  /*!< 0x00300000 */
#define XSPI_WCCR_ABSIZE                 XSPI_WCCR_ABSIZE_Msk                             /*!< Alternate Bytes Size */
#define XSPI_WCCR_ABSIZE_0               (0x1UL << XSPI_WCCR_ABSIZE_Pos)                  /*!< 0x00100000 */
#define XSPI_WCCR_ABSIZE_1               (0x2UL << XSPI_WCCR_ABSIZE_Pos)                  /*!< 0x00200000 */
#define XSPI_WCCR_DMODE_Pos              (24UL)
#define XSPI_WCCR_DMODE_Msk              (0x7UL << XSPI_WCCR_DMODE_Pos)                   /*!< 0x07000000 */
#define XSPI_WCCR_DMODE                  XSPI_WCCR_DMODE_Msk                              /*!< Data Mode */
#define XSPI_WCCR_DMODE_0                (0x1UL << XSPI_WCCR_DMODE_Pos)                   /*!< 0x01000000 */
#define XSPI_WCCR_DMODE_1                (0x2UL << XSPI_WCCR_DMODE_Pos)                   /*!< 0x02000000 */
#define XSPI_WCCR_DMODE_2                (0x4UL << XSPI_WCCR_DMODE_Pos)                   /*!< 0x04000000 */
#define XSPI_WCCR_DDTR_Pos               (27UL)
#define XSPI_WCCR_DDTR_Msk               (0x1UL << XSPI_WCCR_DDTR_Pos)                    /*!< 0x08000000 */
#define XSPI_WCCR_DDTR                   XSPI_WCCR_DDTR_Msk                               /*!< Data Double Transfer Rate */
#define XSPI_WCCR_DQSE_Pos               (29UL)
#define XSPI_WCCR_DQSE_Msk               (0x1UL << XSPI_WCCR_DQSE_Pos)                    /*!< 0x20000000 */
#define XSPI_WCCR_DQSE                   XSPI_WCCR_DQSE_Msk                               /*!< DQS Enable */

/****************  Bit definition for XSPI_WTCR register  ********************/
#define XSPI_WTCR_DCYC_Pos               (0UL)
#define XSPI_WTCR_DCYC_Msk               (0x1FUL << XSPI_WTCR_DCYC_Pos)                   /*!< 0x0000001F */
#define XSPI_WTCR_DCYC                   XSPI_WTCR_DCYC_Msk                               /*!< Number of Dummy Cycles */

/****************  Bit definition for XSPI_WIR register  *********************/
#define XSPI_WIR_INSTRUCTION_Pos         (0UL)
#define XSPI_WIR_INSTRUCTION_Msk         (0xFFFFFFFFUL << XSPI_WIR_INSTRUCTION_Pos)       /*!< 0xFFFFFFFF */
#define XSPI_WIR_INSTRUCTION             XSPI_WIR_INSTRUCTION_Msk                         /*!< Instruction */

/****************  Bit definition for XSPI_WABR register  ********************/
#define XSPI_WABR_ALTERNATE_Pos          (0UL)
#define XSPI_WABR_ALTERNATE_Msk          (0xFFFFFFFFUL << XSPI_WABR_ALTERNATE_Pos)        /*!< 0xFFFFFFFF */
#define XSPI_WABR_ALTERNATE              XSPI_WABR_ALTERNATE_Msk                          /*!< Alternate Bytes */

/****************  Bit definition for XSPI_HLCR register  ********************/
#define XSPI_HLCR_LM_Pos                 (0UL)
#define XSPI_HLCR_LM_Msk                 (0x1UL << XSPI_HLCR_LM_Pos)                      /*!< 0x00000001 */
#define XSPI_HLCR_LM                     XSPI_HLCR_LM_Msk                                 /*!< Latency Mode */
#define XSPI_HLCR_WZL_Pos                (1UL)
#define XSPI_HLCR_WZL_Msk                (0x1UL << XSPI_HLCR_WZL_Pos)                     /*!< 0x00000002 */
#define XSPI_HLCR_WZL                    XSPI_HLCR_WZL_Msk                                /*!< Write Zero Latency */
#define XSPI_HLCR_TACC_Pos               (8UL)
#define XSPI_HLCR_TACC_Msk               (0xFFUL << XSPI_HLCR_TACC_Pos)                   /*!< 0x0000FF00 */
#define XSPI_HLCR_TACC                   XSPI_HLCR_TACC_Msk                               /*!< Access Time */
#define XSPI_HLCR_TRWR_Pos               (16UL)
#define XSPI_HLCR_TRWR_Msk               (0xFFUL << XSPI_HLCR_TRWR_Pos)                   /*!< 0x00FF0000 */
#define XSPI_HLCR_TRWR                   XSPI_HLCR_TRWR_Msk                               /*!< Read Write Recovery Time */

/** @addtogroup STM32U3xx_Peripheral_Exported_macros
  * @{
  */
#if defined(CPU_IN_SECURE_STATE)
/******************************* ADC Instances ********************************/
#define IS_ADC_ALL_INSTANCE(INSTANCE) (((INSTANCE) == ADC1_NS) || ((INSTANCE) == ADC1_S) || \
                                       ((INSTANCE) == ADC2_NS) || ((INSTANCE) == ADC2_S))

#define IS_ADC_MULTIMODE_MASTER_INSTANCE(INSTANCE) (((INSTANCE) == ADC1_NS) || ((INSTANCE) == ADC1_S))

#define IS_ADC_COMMON_INSTANCE(INSTANCE) (((INSTANCE) == ADC12_COMMON_NS) || ((INSTANCE) == ADC12_COMMON_S))

/******************************* AES Instances ********************************/
#define IS_AES_ALL_INSTANCE(INSTANCE) (((INSTANCE) == AES_NS) || ((INSTANCE) == AES_S))

/******************************* CCB Instances ********************************/
#define IS_CCB_ALL_INSTANCE(INSTANCE) (((INSTANCE) == CCB_NS) || ((INSTANCE) == CCB_S))


/******************************* PKA Instances ********************************/
#define IS_PKA_ALL_INSTANCE(INSTANCE) (((INSTANCE) == PKA_NS) || ((INSTANCE) == PKA_S))

/******************************* HASH Instances ********************************/
#define IS_HASH_ALL_INSTANCE(INSTANCE) (((INSTANCE) == HASH_NS) || ((INSTANCE) == HASH_S))

/******************************** FDCAN Instances *****************************/
#define IS_FDCAN_ALL_INSTANCE(INSTANCE) (((INSTANCE) == FDCAN1_NS) || ((INSTANCE) == FDCAN1_S))

/******************************** COMP Instances ******************************/
#define IS_COMP_ALL_INSTANCE(INSTANCE) (((INSTANCE) == COMP1_NS) || ((INSTANCE) == COMP1_S) || \
                                        ((INSTANCE) == COMP2_NS) || ((INSTANCE) == COMP2_S))

/******************** COMP Instances with window mode capability **************/
#define IS_COMP_WINDOWMODE_INSTANCE(INSTANCE) (((INSTANCE) == COMP1_NS) || ((INSTANCE) == COMP1_S) || \
                                               ((INSTANCE) == COMP2_NS) || ((INSTANCE) == COMP2_S))

/******************************* CRC Instances ********************************/
#define IS_CRC_ALL_INSTANCE(INSTANCE) (((INSTANCE) == CRC_NS) || ((INSTANCE) == CRC_S))

/******************************* DAC Instances ********************************/
#define IS_DAC_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DAC1_NS) || ((INSTANCE) == DAC1_S))

/******************************* DELAYBLOCK Instances *******************************/
#define IS_DLYB_ALL_INSTANCE(INSTANCE)  (((INSTANCE) == DLYB_SDMMC1_NS)   || \
                                         ((INSTANCE) == DLYB_SDMMC1_S)    || \
                                         ((INSTANCE) == DLYB_OCTOSPI1_NS) || \
                                         ((INSTANCE) == DLYB_OCTOSPI1_S))

/******************************** DMA Instances *******************************/
#define IS_DMA_ALL_INSTANCE(INSTANCE) (((INSTANCE) == GPDMA1_Channel0_NS)  || ((INSTANCE) == GPDMA1_Channel0_S)  || \
                                       ((INSTANCE) == GPDMA1_Channel1_NS)  || ((INSTANCE) == GPDMA1_Channel1_S)  || \
                                       ((INSTANCE) == GPDMA1_Channel2_NS)  || ((INSTANCE) == GPDMA1_Channel2_S)  || \
                                       ((INSTANCE) == GPDMA1_Channel3_NS)  || ((INSTANCE) == GPDMA1_Channel3_S)  || \
                                       ((INSTANCE) == GPDMA1_Channel4_NS)  || ((INSTANCE) == GPDMA1_Channel4_S)  || \
                                       ((INSTANCE) == GPDMA1_Channel5_NS)  || ((INSTANCE) == GPDMA1_Channel5_S)  || \
                                       ((INSTANCE) == GPDMA1_Channel6_NS)  || ((INSTANCE) == GPDMA1_Channel6_S)  || \
                                       ((INSTANCE) == GPDMA1_Channel7_NS)  || ((INSTANCE) == GPDMA1_Channel7_S)  || \
                                       ((INSTANCE) == GPDMA1_Channel8_NS)  || ((INSTANCE) == GPDMA1_Channel8_S)  || \
                                       ((INSTANCE) == GPDMA1_Channel9_NS)  || ((INSTANCE) == GPDMA1_Channel9_S)  || \
                                       ((INSTANCE) == GPDMA1_Channel10_NS) || ((INSTANCE) == GPDMA1_Channel10_S) || \
                                       ((INSTANCE) == GPDMA1_Channel11_NS) || ((INSTANCE) == GPDMA1_Channel11_S))

#define IS_GPDMA_INSTANCE(INSTANCE)   (((INSTANCE) == GPDMA1_Channel0_NS)  || ((INSTANCE) == GPDMA1_Channel0_S)  || \
                                       ((INSTANCE) == GPDMA1_Channel1_NS)  || ((INSTANCE) == GPDMA1_Channel1_S)  || \
                                       ((INSTANCE) == GPDMA1_Channel2_NS)  || ((INSTANCE) == GPDMA1_Channel2_S)  || \
                                       ((INSTANCE) == GPDMA1_Channel3_NS)  || ((INSTANCE) == GPDMA1_Channel3_S)  || \
                                       ((INSTANCE) == GPDMA1_Channel4_NS)  || ((INSTANCE) == GPDMA1_Channel4_S)  || \
                                       ((INSTANCE) == GPDMA1_Channel5_NS)  || ((INSTANCE) == GPDMA1_Channel5_S)  || \
                                       ((INSTANCE) == GPDMA1_Channel6_NS)  || ((INSTANCE) == GPDMA1_Channel6_S)  || \
                                       ((INSTANCE) == GPDMA1_Channel7_NS)  || ((INSTANCE) == GPDMA1_Channel7_S)  || \
                                       ((INSTANCE) == GPDMA1_Channel8_NS)  || ((INSTANCE) == GPDMA1_Channel8_S)  || \
                                       ((INSTANCE) == GPDMA1_Channel9_NS)  || ((INSTANCE) == GPDMA1_Channel9_S)  || \
                                       ((INSTANCE) == GPDMA1_Channel10_NS) || ((INSTANCE) == GPDMA1_Channel10_S) || \
                                       ((INSTANCE) == GPDMA1_Channel11_NS) || ((INSTANCE) == GPDMA1_Channel11_S))

#define IS_DMA_2D_ADDRESSING_INSTANCE(INSTANCE) (((INSTANCE) == GPDMA1_Channel10_NS)  || ((INSTANCE) == GPDMA1_Channel10_S)  || \
                                                 ((INSTANCE) == GPDMA1_Channel11_NS)  || ((INSTANCE) == GPDMA1_Channel11_S))

#define IS_DMA_PFREQ_INSTANCE(INSTANCE) (((INSTANCE) == GPDMA1_Channel0_S) || ((INSTANCE) == GPDMA1_Channel0_NS)  || \
                                         ((INSTANCE) == GPDMA1_Channel1_S) || ((INSTANCE) == GPDMA1_Channel1_NS))

/******************************* GPIO Instances *******************************/
#define IS_GPIO_ALL_INSTANCE(INSTANCE)      (((INSTANCE) == GPIOA_NS) || ((INSTANCE) == GPIOA_S) || \
                                             ((INSTANCE) == GPIOB_NS) || ((INSTANCE) == GPIOB_S) || \
                                             ((INSTANCE) == GPIOC_NS) || ((INSTANCE) == GPIOC_S) || \
                                             ((INSTANCE) == GPIOD_NS) || ((INSTANCE) == GPIOD_S) || \
                                             ((INSTANCE) == GPIOE_NS) || ((INSTANCE) == GPIOE_S) || \
                                             ((INSTANCE) == GPIOG_NS) || ((INSTANCE) == GPIOG_S) || \
                                             ((INSTANCE) == GPIOH_NS) || ((INSTANCE) == GPIOH_S))

  /******************************* GPIO AF Instances ****************************/
  /* On U3, all GPIO Bank support AF */
#define IS_GPIO_AF_INSTANCE(INSTANCE)       IS_GPIO_ALL_INSTANCE(INSTANCE)

  /**************************** GPIO Lock Instances *****************************/
  /* On U3, all GPIO Bank support the Lock mechanism */
#define IS_GPIO_LOCK_INSTANCE(INSTANCE)     IS_GPIO_ALL_INSTANCE(INSTANCE)

/******************************** I2C Instances *******************************/
#define IS_I2C_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2C1_NS) || ((INSTANCE) == I2C1_S) || \
                                       ((INSTANCE) == I2C2_NS) || ((INSTANCE) == I2C2_S) || \
                                       ((INSTANCE) == I2C3_NS) || ((INSTANCE) == I2C3_S))

/****************** I2C Instances : wakeup capability from stop modes *********/
#define IS_I2C_WAKEUP_FROMSTOP_INSTANCE(INSTANCE) IS_I2C_ALL_INSTANCE(INSTANCE)

/******************* I2C Instances : Group belongingness *********************/
#define IS_I2C_GRP1_INSTANCE(INSTANCE) (((INSTANCE) == I2C1_NS) || ((INSTANCE) == I2C1_S) || \
                                        ((INSTANCE) == I2C2_NS) || ((INSTANCE) == I2C2_S))

#define IS_I2C_GRP2_INSTANCE(INSTANCE) (((INSTANCE) == I2C3_NS) || ((INSTANCE) == I2C3_S))

/******************************** I3C Instances *******************************/
#define IS_I3C_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I3C1_NS) || ((INSTANCE) == I3C1_S) || \
                                       ((INSTANCE) == I3C2_NS) || ((INSTANCE) == I3C2_S))

/******************* I3C Instances : Group belongingness *********************/
#define IS_I3C_GRP1_INSTANCE(INSTANCE) (((INSTANCE) == I3C1_NS) || ((INSTANCE) == I3C1_S) || \
                                        ((INSTANCE) == I3C2_NS) || ((INSTANCE) == I3C2_S))

/****************************** OPAMP Instances *******************************/
#define IS_OPAMP_ALL_INSTANCE(INSTANCE) (((INSTANCE) == OPAMP1_NS) || ((INSTANCE) == OPAMP1_S) || \
                                         ((INSTANCE) == OPAMP2_NS) || ((INSTANCE) == OPAMP2_S))

/******************************* OSPI Instances *******************************/
#define IS_OSPI_ALL_INSTANCE(INSTANCE) (((INSTANCE) == OCTOSPI1_NS) || ((INSTANCE) == OCTOSPI1_S))

/****************************** RAMCFG Instances ********************************/
#define IS_RAMCFG_ALL_INSTANCE(INSTANCE) (((INSTANCE) == RAMCFG_SRAM1_NS) || ((INSTANCE) == RAMCFG_SRAM1_S)  || \
                                          ((INSTANCE) == RAMCFG_SRAM2_NS) || ((INSTANCE) == RAMCFG_SRAM2_S))

/***************************** RAMCFG PED Instances *****************************/
#define IS_RAMCFG_PED_INSTANCE(INSTANCE) (((INSTANCE) == RAMCFG_SRAM2_NS)  || ((INSTANCE) == RAMCFG_SRAM2_S))

/***************************** RAMCFG IT Instances ******************************/
#define IS_RAMCFG_IT_INSTANCE(INSTANCE) (((INSTANCE) == RAMCFG_SRAM2_NS)  || ((INSTANCE) == RAMCFG_SRAM2_S))

/************************ RAMCFG Write Protection Instances *********************/
#define IS_RAMCFG_WP_INSTANCE(INSTANCE) (((INSTANCE) == RAMCFG_SRAM2_NS)  || ((INSTANCE) == RAMCFG_SRAM2_S))

/************************ RAMCFG Erase Instances ********************************/
#define IS_RAMCFG_ER_INSTANCE(INSTANCE) (((INSTANCE) == RAMCFG_SRAM1_NS) || ((INSTANCE) == RAMCFG_SRAM1_S)  || \
                                         ((INSTANCE) == RAMCFG_SRAM2_NS) || ((INSTANCE) == RAMCFG_SRAM2_S))

/******************************* RNG Instances ********************************/
#define IS_RNG_ALL_INSTANCE(INSTANCE)  (((INSTANCE) == RNG_NS) || ((INSTANCE) == RNG_S))

/****************************** RTC Instances *********************************/
#define IS_RTC_ALL_INSTANCE(INSTANCE) (((INSTANCE) == RTC_NS) || ((INSTANCE) == RTC_S))

/******************************** SAI Instances *******************************/
#define IS_SAI_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SAI1_Block_A_NS) || ((INSTANCE) == SAI1_Block_A_S) || \
                                       ((INSTANCE) == SAI1_Block_B_NS) || ((INSTANCE) == SAI1_Block_B_S))

/****************************** SDMMC Instances *******************************/
#define IS_SDMMC_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SDMMC1_NS) || ((INSTANCE) == SDMMC1_S))

/****************************** SMBUS Instances *******************************/
#define IS_SMBUS_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2C1_NS) || ((INSTANCE) == I2C1_S) || \
                                         ((INSTANCE) == I2C2_NS) || ((INSTANCE) == I2C2_S) || \
                                         ((INSTANCE) == I2C3_NS) || ((INSTANCE) == I2C3_S))

/******************* SMBUS Instances : Group belongingness *********************/
#define IS_SMBUS_GRP1_INSTANCE(INSTANCE) (((INSTANCE) == I2C1_NS) || ((INSTANCE) == I2C1_S) || \
                                          ((INSTANCE) == I2C2_NS) || ((INSTANCE) == I2C2_S))

#define IS_SMBUS_GRP2_INSTANCE(INSTANCE) (((INSTANCE) == I2C3_NS) || ((INSTANCE) == I2C3_S))

/******************************** SPI Instances *******************************/
#define IS_SPI_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI1_NS) || ((INSTANCE) == SPI1_S) || \
                                       ((INSTANCE) == SPI2_NS) || ((INSTANCE) == SPI2_S) || \
                                       ((INSTANCE) == SPI3_NS) || ((INSTANCE) == SPI3_S))

#define IS_SPI_LIMITED_INSTANCE(INSTANCE) (((INSTANCE) == SPI3_NS) || ((INSTANCE) == SPI3_S))

#define IS_SPI_FULL_INSTANCE(INSTANCE) (((INSTANCE) == SPI1_NS) || ((INSTANCE) == SPI1_S) || \
                                        ((INSTANCE) == SPI2_NS) || ((INSTANCE) == SPI2_S))

/******************* SPI Instances : Group belongingness *********************/
#define IS_SPI_GRP1_INSTANCE(INSTANCE) (((INSTANCE) == SPI1_NS) || ((INSTANCE) == SPI1_S) || \
                                        ((INSTANCE) == SPI2_NS) || ((INSTANCE) == SPI2_S))

#define IS_SPI_GRP2_INSTANCE(INSTANCE)  (((INSTANCE) == SPI3_NS) || ((INSTANCE) == SPI3_S))

/****************** LPTIM Instances : All supported instances *****************/
#define IS_LPTIM_INSTANCE(INSTANCE)     (((INSTANCE) == LPTIM1_NS) || ((INSTANCE) == LPTIM1_S) ||\
                                         ((INSTANCE) == LPTIM2_NS) || ((INSTANCE) == LPTIM2_S) ||\
                                         ((INSTANCE) == LPTIM3_NS) || ((INSTANCE) == LPTIM3_S) ||\
                                         ((INSTANCE) == LPTIM4_NS) || ((INSTANCE) == LPTIM4_S))

/****************** LPTIM Instances : DMA supported instances *****************/
#define IS_LPTIM_DMA_INSTANCE(INSTANCE)  (((INSTANCE) == LPTIM1_NS) || ((INSTANCE) == LPTIM1_S) ||\
                                          ((INSTANCE) == LPTIM2_NS) || ((INSTANCE) == LPTIM2_S) ||\
                                          ((INSTANCE) == LPTIM3_NS) || ((INSTANCE) == LPTIM3_S))

/************* LPTIM Instances : at least 1 capture/compare channel ***********/
#define IS_LPTIM_CC1_INSTANCE(INSTANCE) (((INSTANCE) == LPTIM1_NS)  || ((INSTANCE) == LPTIM1_S) ||\
                                         ((INSTANCE) == LPTIM2_NS)  || ((INSTANCE) == LPTIM2_S) ||\
                                         ((INSTANCE) == LPTIM3_NS)  || ((INSTANCE) == LPTIM3_S))

/************* LPTIM Instances : at least 2 capture/compare channel ***********/
#define IS_LPTIM_CC2_INSTANCE(INSTANCE) (((INSTANCE) == LPTIM1_NS) || ((INSTANCE) == LPTIM1_S) ||\
                                         ((INSTANCE) == LPTIM2_NS) || ((INSTANCE) == LPTIM2_S) ||\
                                         ((INSTANCE) == LPTIM3_NS) || ((INSTANCE) == LPTIM3_S))

/****************** LPTIM Instances : supporting encoder interface **************/
#define IS_LPTIM_ENCODER_INTERFACE_INSTANCE(INSTANCE)  (((INSTANCE) == LPTIM1_NS) || ((INSTANCE) == LPTIM1_S) ||\
                                                        ((INSTANCE) == LPTIM2_NS) || ((INSTANCE) == LPTIM2_S))

/****************** LPTIM Instances : supporting Input Capture **************/
#define IS_LPTIM_INPUT_CAPTURE_INSTANCE(INSTANCE)  (((INSTANCE) == LPTIM1_NS) || ((INSTANCE) == LPTIM1_S) ||\
                                                    ((INSTANCE) == LPTIM2_NS) || ((INSTANCE) == LPTIM2_S) ||\
                                                    ((INSTANCE) == LPTIM3_NS) || ((INSTANCE) == LPTIM3_S))

/****************** TIM Instances : All supported instances *******************/
#define IS_TIM_INSTANCE(INSTANCE)       (((INSTANCE) == TIM1_NS)  || ((INSTANCE) == TIM1_S)  || \
                                         ((INSTANCE) == TIM2_NS)  || ((INSTANCE) == TIM2_S)  || \
                                         ((INSTANCE) == TIM3_NS)  || ((INSTANCE) == TIM3_S)  || \
                                         ((INSTANCE) == TIM4_NS)  || ((INSTANCE) == TIM4_S)  || \
                                         ((INSTANCE) == TIM6_NS)  || ((INSTANCE) == TIM6_S)  || \
                                         ((INSTANCE) == TIM7_NS)  || ((INSTANCE) == TIM7_S)  || \
                                         ((INSTANCE) == TIM15_NS) || ((INSTANCE) == TIM15_S) || \
                                         ((INSTANCE) == TIM16_NS) || ((INSTANCE) == TIM16_S) || \
                                         ((INSTANCE) == TIM17_NS) || ((INSTANCE) == TIM17_S))

/****************** TIM Instances : supporting 32 bits counter ****************/
#define IS_TIM_32B_COUNTER_INSTANCE(INSTANCE) (((INSTANCE) == TIM2_NS)  || ((INSTANCE) == TIM2_S)  || \
                                               ((INSTANCE) == TIM3_NS)  || ((INSTANCE) == TIM3_S)  || \
                                               ((INSTANCE) == TIM4_NS)  || ((INSTANCE) == TIM4_S))

/****************** TIM Instances : supporting the break function *************/
#define IS_TIM_BREAK_INSTANCE(INSTANCE)    (((INSTANCE) == TIM1_NS)  || ((INSTANCE) == TIM1_S)  || \
                                            ((INSTANCE) == TIM15_NS) || ((INSTANCE) == TIM15_S) || \
                                            ((INSTANCE) == TIM16_NS) || ((INSTANCE) == TIM16_S) || \
                                            ((INSTANCE) == TIM17_NS) || ((INSTANCE) == TIM17_S))

/************** TIM Instances : supporting Break source selection *************/
#define IS_TIM_BREAKSOURCE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS)  || ((INSTANCE) == TIM1_S)  || \
                                               ((INSTANCE) == TIM15_NS) || ((INSTANCE) == TIM15_S) || \
                                               ((INSTANCE) == TIM16_NS) || ((INSTANCE) == TIM16_S) || \
                                               ((INSTANCE) == TIM17_NS) || ((INSTANCE) == TIM17_S))

/****************** TIM Instances : supporting 2 break inputs *****************/
#define IS_TIM_BKIN2_INSTANCE(INSTANCE)    (((INSTANCE) == TIM1_NS)  || ((INSTANCE) == TIM1_S))

/************* TIM Instances : at least 1 capture/compare channel *************/
#define IS_TIM_CC1_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1_NS)  || ((INSTANCE) == TIM1_S)  || \
                                         ((INSTANCE) == TIM2_NS)  || ((INSTANCE) == TIM2_S)  || \
                                         ((INSTANCE) == TIM3_NS)  || ((INSTANCE) == TIM3_S)  || \
                                         ((INSTANCE) == TIM4_NS)  || ((INSTANCE) == TIM4_S)  || \
                                         ((INSTANCE) == TIM15_NS) || ((INSTANCE) == TIM15_S) || \
                                         ((INSTANCE) == TIM16_NS) || ((INSTANCE) == TIM16_S) || \
                                         ((INSTANCE) == TIM17_NS) || ((INSTANCE) == TIM17_S))

/************ TIM Instances : at least 2 capture/compare channels *************/
#define IS_TIM_CC2_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1_NS)  || ((INSTANCE) == TIM1_S)  || \
                                         ((INSTANCE) == TIM2_NS)  || ((INSTANCE) == TIM2_S)  || \
                                         ((INSTANCE) == TIM3_NS)  || ((INSTANCE) == TIM3_S)  || \
                                         ((INSTANCE) == TIM4_NS)  || ((INSTANCE) == TIM4_S)  || \
                                         ((INSTANCE) == TIM15_NS) || ((INSTANCE) == TIM15_S))

/************ TIM Instances : at least 3 capture/compare channels *************/
#define IS_TIM_CC3_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1_NS)  || ((INSTANCE) == TIM1_S)  || \
                                         ((INSTANCE) == TIM2_NS)  || ((INSTANCE) == TIM2_S)  || \
                                         ((INSTANCE) == TIM3_NS)  || ((INSTANCE) == TIM3_S)  || \
                                         ((INSTANCE) == TIM4_NS)  || ((INSTANCE) == TIM4_S))

/************ TIM Instances : at least 4 capture/compare channels *************/
#define IS_TIM_CC4_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1_NS)  || ((INSTANCE) == TIM1_S)  || \
                                         ((INSTANCE) == TIM2_NS)  || ((INSTANCE) == TIM2_S)  || \
                                         ((INSTANCE) == TIM3_NS)  || ((INSTANCE) == TIM3_S)  || \
                                         ((INSTANCE) == TIM4_NS)  || ((INSTANCE) == TIM4_S))

/****************** TIM Instances : at least 5 capture/compare channels *******/
#define IS_TIM_CC5_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1_NS)  || ((INSTANCE) == TIM1_S))

/****************** TIM Instances : at least 6 capture/compare channels *******/
#define IS_TIM_CC6_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1_NS)  || ((INSTANCE) == TIM1_S))

/************ TIM Instances : DMA requests generation (TIMx_DIER.COMDE) *******/
#define IS_TIM_CCDMA_INSTANCE(INSTANCE)    (((INSTANCE) == TIM1_NS)  || ((INSTANCE) == TIM1_S)  || \
                                            ((INSTANCE) == TIM2_NS)  || ((INSTANCE) == TIM2_S)  || \
                                            ((INSTANCE) == TIM3_NS)  || ((INSTANCE) == TIM3_S)  || \
                                            ((INSTANCE) == TIM4_NS)  || ((INSTANCE) == TIM4_S)  || \
                                            ((INSTANCE) == TIM15_NS) || ((INSTANCE) == TIM15_S) || \
                                            ((INSTANCE) == TIM16_NS) || ((INSTANCE) == TIM16_S) || \
                                            ((INSTANCE) == TIM17_NS) || ((INSTANCE) == TIM17_S))

/****************** TIM Instances : DMA requests generation (TIMx_DIER.UDE) ***/
#define IS_TIM_DMA_INSTANCE(INSTANCE)      (((INSTANCE) == TIM1_NS)  || ((INSTANCE) == TIM1_S)  || \
                                            ((INSTANCE) == TIM2_NS)  || ((INSTANCE) == TIM2_S)  || \
                                            ((INSTANCE) == TIM3_NS)  || ((INSTANCE) == TIM3_S)  || \
                                            ((INSTANCE) == TIM4_NS)  || ((INSTANCE) == TIM4_S)  || \
                                            ((INSTANCE) == TIM6_NS)  || ((INSTANCE) == TIM6_S)  || \
                                            ((INSTANCE) == TIM7_NS)  || ((INSTANCE) == TIM7_S)  || \
                                            ((INSTANCE) == TIM15_NS) || ((INSTANCE) == TIM15_S) || \
                                            ((INSTANCE) == TIM16_NS) || ((INSTANCE) == TIM16_S) || \
                                            ((INSTANCE) == TIM17_NS) || ((INSTANCE) == TIM17_S))

/************ TIM Instances : DMA requests generation (TIMx_DIER.CCxDE) *******/
#define IS_TIM_DMA_CC_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1_NS)  || ((INSTANCE) == TIM1_S)  || \
                                            ((INSTANCE) == TIM2_NS)  || ((INSTANCE) == TIM2_S)  || \
                                            ((INSTANCE) == TIM3_NS)  || ((INSTANCE) == TIM3_S)  || \
                                            ((INSTANCE) == TIM4_NS)  || ((INSTANCE) == TIM4_S)  || \
                                            ((INSTANCE) == TIM15_NS) || ((INSTANCE) == TIM15_S) || \
                                            ((INSTANCE) == TIM16_NS) || ((INSTANCE) == TIM16_S) || \
                                            ((INSTANCE) == TIM17_NS) || ((INSTANCE) == TIM17_S))

/******************** TIM Instances : DMA burst feature ***********************/
#define IS_TIM_DMABURST_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS)  || ((INSTANCE) == TIM1_S)  || \
                                            ((INSTANCE) == TIM2_NS)  || ((INSTANCE) == TIM2_S)  || \
                                            ((INSTANCE) == TIM3_NS)  || ((INSTANCE) == TIM3_S)  || \
                                            ((INSTANCE) == TIM4_NS)  || ((INSTANCE) == TIM4_S)  || \
                                            ((INSTANCE) == TIM15_NS) || ((INSTANCE) == TIM15_S) || \
                                            ((INSTANCE) == TIM16_NS) || ((INSTANCE) == TIM16_S) || \
                                            ((INSTANCE) == TIM17_NS) || ((INSTANCE) == TIM17_S))

/******************* TIM Instances : output(s) available **********************/
#define IS_TIM_CCX_INSTANCE(INSTANCE, CHANNEL) \
    (((((INSTANCE) == TIM1_NS)  || ((INSTANCE) == TIM1_S))  && \
     (((CHANNEL) == TIM_CHANNEL_1) ||          \
      ((CHANNEL) == TIM_CHANNEL_2) ||          \
      ((CHANNEL) == TIM_CHANNEL_3) ||          \
      ((CHANNEL) == TIM_CHANNEL_4) ||          \
      ((CHANNEL) == TIM_CHANNEL_5) ||          \
      ((CHANNEL) == TIM_CHANNEL_6)))           \
     ||                                        \
     ((((INSTANCE) == TIM2_NS)  || ((INSTANCE) == TIM2_S))  && \
     (((CHANNEL) == TIM_CHANNEL_1) ||          \
      ((CHANNEL) == TIM_CHANNEL_2) ||          \
      ((CHANNEL) == TIM_CHANNEL_3) ||          \
      ((CHANNEL) == TIM_CHANNEL_4)))           \
     ||                                        \
     ((((INSTANCE) == TIM3_NS)  || ((INSTANCE) == TIM3_S))  && \
     (((CHANNEL) == TIM_CHANNEL_1) ||          \
      ((CHANNEL) == TIM_CHANNEL_2) ||          \
      ((CHANNEL) == TIM_CHANNEL_3) ||          \
      ((CHANNEL) == TIM_CHANNEL_4)))           \
     ||                                        \
     ((((INSTANCE) == TIM4_NS)  || ((INSTANCE) == TIM4_S))  && \
     (((CHANNEL) == TIM_CHANNEL_1) ||          \
      ((CHANNEL) == TIM_CHANNEL_2) ||          \
      ((CHANNEL) == TIM_CHANNEL_3) ||          \
      ((CHANNEL) == TIM_CHANNEL_4)))           \
     ||                                        \
     ((((INSTANCE) == TIM15_NS) || ((INSTANCE) == TIM15_S)) && \
     (((CHANNEL) == TIM_CHANNEL_1) ||          \
      ((CHANNEL) == TIM_CHANNEL_2)))           \
     ||                                        \
     ((((INSTANCE) == TIM16_NS) || ((INSTANCE) == TIM16_S)) && \
     (((CHANNEL) == TIM_CHANNEL_1)))           \
     ||                                        \
     ((((INSTANCE) == TIM17_NS) || ((INSTANCE) == TIM17_S)) && \
     (((CHANNEL) == TIM_CHANNEL_1))))

/****************** TIM Instances : supporting complementary output(s) ********/
#define IS_TIM_CCXN_INSTANCE(INSTANCE, CHANNEL) \
    (((((INSTANCE) == TIM1_NS)  || ((INSTANCE) == TIM1_S))  && \
     (((CHANNEL) == TIM_CHANNEL_1) ||           \
      ((CHANNEL) == TIM_CHANNEL_2) ||           \
      ((CHANNEL) == TIM_CHANNEL_3) ||           \
      ((CHANNEL) == TIM_CHANNEL_4)))            \
    ||                                          \
    ((((INSTANCE) == TIM15_NS) || ((INSTANCE) == TIM15_S)) && \
     ((CHANNEL) == TIM_CHANNEL_1))              \
    ||                                          \
    ((((INSTANCE) == TIM16_NS) || ((INSTANCE) == TIM16_S)) && \
     ((CHANNEL) == TIM_CHANNEL_1))              \
    ||                                          \
    ((((INSTANCE) == TIM17_NS) || ((INSTANCE) == TIM17_S)) && \
     ((CHANNEL) == TIM_CHANNEL_1)))

/****************** TIM Instances : supporting clock division *****************/
#define IS_TIM_CLOCK_DIVISION_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1_NS)  || ((INSTANCE) == TIM1_S)  || \
                                                    ((INSTANCE) == TIM2_NS)  || ((INSTANCE) == TIM2_S)  || \
                                                    ((INSTANCE) == TIM3_NS)  || ((INSTANCE) == TIM3_S)  || \
                                                    ((INSTANCE) == TIM4_NS)  || ((INSTANCE) == TIM4_S)  || \
                                                    ((INSTANCE) == TIM15_NS) || ((INSTANCE) == TIM15_S) || \
                                                    ((INSTANCE) == TIM16_NS) || ((INSTANCE) == TIM16_S) || \
                                                    ((INSTANCE) == TIM17_NS) || ((INSTANCE) == TIM17_S))

/****** TIM Instances : supporting external clock mode 1 for ETRF input *******/
#define IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS)  || ((INSTANCE) == TIM1_S)  || \
                                                        ((INSTANCE) == TIM2_NS)  || ((INSTANCE) == TIM2_S)  || \
                                                        ((INSTANCE) == TIM3_NS)  || ((INSTANCE) == TIM3_S)  || \
                                                        ((INSTANCE) == TIM4_NS)  || ((INSTANCE) == TIM4_S))

/****** TIM Instances : supporting external clock mode 2 for ETRF input *******/
#define IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS)  || ((INSTANCE) == TIM1_S)  || \
                                                        ((INSTANCE) == TIM2_NS)  || ((INSTANCE) == TIM2_S)  || \
                                                        ((INSTANCE) == TIM3_NS)  || ((INSTANCE) == TIM3_S)  || \
                                                        ((INSTANCE) == TIM4_NS)  || ((INSTANCE) == TIM4_S))

/****************** TIM Instances : supporting external clock mode 1 for TIX inputs*/
#define IS_TIM_CLOCKSOURCE_TIX_INSTANCE(INSTANCE)      (((INSTANCE) == TIM1_NS)  || ((INSTANCE) == TIM1_S)  || \
                                                        ((INSTANCE) == TIM2_NS)  || ((INSTANCE) == TIM2_S)  || \
                                                        ((INSTANCE) == TIM3_NS)  || ((INSTANCE) == TIM3_S)  || \
                                                        ((INSTANCE) == TIM4_NS)  || ((INSTANCE) == TIM4_S)  || \
                                                        ((INSTANCE) == TIM15_NS) || ((INSTANCE) == TIM15_S))

/****************** TIM Instances : supporting internal trigger inputs(ITRX) *******/
#define IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(INSTANCE)     (((INSTANCE) == TIM1_NS)  || ((INSTANCE) == TIM1_S)  || \
                                                        ((INSTANCE) == TIM2_NS)  || ((INSTANCE) == TIM2_S)  || \
                                                        ((INSTANCE) == TIM3_NS)  || ((INSTANCE) == TIM3_S)  || \
                                                        ((INSTANCE) == TIM4_NS)  || ((INSTANCE) == TIM4_S)  || \
                                                        ((INSTANCE) == TIM15_NS) || ((INSTANCE) == TIM15_S))

/****************** TIM Instances : supporting combined 3-phase PWM mode ******/
#define IS_TIM_COMBINED3PHASEPWM_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS)  || ((INSTANCE) == TIM1_S))

/****************** TIM Instances : supporting commutation event generation ***/
#define IS_TIM_COMMUTATION_EVENT_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS)  || ((INSTANCE) == TIM1_S)  || \
                                                     ((INSTANCE) == TIM15_NS) || ((INSTANCE) == TIM15_S) || \
                                                     ((INSTANCE) == TIM16_NS) || ((INSTANCE) == TIM16_S) || \
                                                     ((INSTANCE) == TIM17_NS) || ((INSTANCE) == TIM17_S))

/****************** TIM Instances : supporting counting mode selection ********/
#define IS_TIM_COUNTER_MODE_SELECT_INSTANCE(INSTANCE)  (((INSTANCE) == TIM1_NS)  || ((INSTANCE) == TIM1_S)  || \
                                                        ((INSTANCE) == TIM2_NS)  || ((INSTANCE) == TIM2_S)  || \
                                                        ((INSTANCE) == TIM3_NS)  || ((INSTANCE) == TIM3_S)  || \
                                                        ((INSTANCE) == TIM4_NS)  || ((INSTANCE) == TIM4_S))

/****************** TIM Instances : supporting encoder interface **************/
#define IS_TIM_ENCODER_INTERFACE_INSTANCE(INSTANCE)  (((INSTANCE) == TIM1_NS)  || ((INSTANCE) == TIM1_S)  || \
                                                      ((INSTANCE) == TIM2_NS)  || ((INSTANCE) == TIM2_S)  || \
                                                      ((INSTANCE) == TIM3_NS)  || ((INSTANCE) == TIM3_S)  || \
                                                      ((INSTANCE) == TIM4_NS)  || ((INSTANCE) == TIM4_S))

/****************** TIM Instances : supporting Hall sensor interface **********/
#define IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS)   || ((INSTANCE) == TIM1_S)  || \
                                                         ((INSTANCE) == TIM2_NS)   || ((INSTANCE) == TIM2_S)  || \
                                                         ((INSTANCE) == TIM3_NS)   || ((INSTANCE) == TIM3_S)  || \
                                                         ((INSTANCE) == TIM4_NS)   || ((INSTANCE) == TIM4_S)  || \
                                                         ((INSTANCE) == TIM15_NS)  || ((INSTANCE) == TIM15_S))

/**************** TIM Instances : external trigger input available ************/
#define IS_TIM_ETR_INSTANCE(INSTANCE)      (((INSTANCE) == TIM1_NS)  || ((INSTANCE) == TIM1_S)  || \
                                            ((INSTANCE) == TIM2_NS)  || ((INSTANCE) == TIM2_S)  || \
                                            ((INSTANCE) == TIM3_NS)  || ((INSTANCE) == TIM3_S)  || \
                                            ((INSTANCE) == TIM4_NS)  || ((INSTANCE) == TIM4_S))

/************* TIM Instances : supporting ETR source selection ***************/
#define IS_TIM_ETRSEL_INSTANCE(INSTANCE)    (((INSTANCE) == TIM1_NS)  || ((INSTANCE) == TIM1_S)  || \
                                             ((INSTANCE) == TIM2_NS)  || ((INSTANCE) == TIM2_S)  || \
                                             ((INSTANCE) == TIM3_NS)  || ((INSTANCE) == TIM3_S)  || \
                                             ((INSTANCE) == TIM4_NS)  || ((INSTANCE) == TIM4_S))

/****** TIM Instances : Master mode available (TIMx_CR2.MMS available )********/
#define IS_TIM_MASTER_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1_NS)  || ((INSTANCE) == TIM1_S)  || \
                                            ((INSTANCE) == TIM2_NS)  || ((INSTANCE) == TIM2_S)  || \
                                            ((INSTANCE) == TIM3_NS)  || ((INSTANCE) == TIM3_S)  || \
                                            ((INSTANCE) == TIM4_NS)  || ((INSTANCE) == TIM4_S)  || \
                                            ((INSTANCE) == TIM6_NS)  || ((INSTANCE) == TIM6_S)  || \
                                            ((INSTANCE) == TIM7_NS)  || ((INSTANCE) == TIM7_S)  || \
                                            ((INSTANCE) == TIM15_NS) || ((INSTANCE) == TIM15_S))

/*********** TIM Instances : Slave mode available (TIMx_SMCR available )*******/
#define IS_TIM_SLAVE_INSTANCE(INSTANCE)    (((INSTANCE) == TIM1_NS)  || ((INSTANCE) == TIM1_S)  || \
                                            ((INSTANCE) == TIM2_NS)  || ((INSTANCE) == TIM2_S)  || \
                                            ((INSTANCE) == TIM3_NS)  || ((INSTANCE) == TIM3_S)  || \
                                            ((INSTANCE) == TIM4_NS)  || ((INSTANCE) == TIM4_S)  || \
                                            ((INSTANCE) == TIM15_NS) || ((INSTANCE) == TIM15_S))

/****************** TIM Instances : supporting OCxREF clear *******************/
#define IS_TIM_OCXREF_CLEAR_INSTANCE(INSTANCE)        (((INSTANCE) == TIM1_NS)  || ((INSTANCE) == TIM1_S)  || \
                                                       ((INSTANCE) == TIM2_NS)  || ((INSTANCE) == TIM2_S)  || \
                                                       ((INSTANCE) == TIM3_NS)  || ((INSTANCE) == TIM3_S)  || \
                                                       ((INSTANCE) == TIM4_NS)  || ((INSTANCE) == TIM4_S)  || \
                                                       ((INSTANCE) == TIM15_NS) || ((INSTANCE) == TIM15_S) || \
                                                       ((INSTANCE) == TIM16_NS) || ((INSTANCE) == TIM16_S) || \
                                                       ((INSTANCE) == TIM17_NS) || ((INSTANCE) == TIM17_S))

/****************** TIM Instances : supporting bitfield OCCS in SMCR register *******************/
#define IS_TIM_OCCS_INSTANCE(INSTANCE)       (((INSTANCE) == TIM1_NS)  || ((INSTANCE) == TIM1_S)  || \
                                              ((INSTANCE) == TIM2_NS)  || ((INSTANCE) == TIM2_S)  || \
                                              ((INSTANCE) == TIM3_NS)  || ((INSTANCE) == TIM3_S)  || \
                                              ((INSTANCE) == TIM4_NS)  || ((INSTANCE) == TIM4_S))

/****************** TIM Instances : remapping capability **********************/
#define IS_TIM_REMAP_INSTANCE(INSTANCE)    (((INSTANCE) == TIM1_NS)  || ((INSTANCE) == TIM1_S)  || \
                                            ((INSTANCE) == TIM2_NS)  || ((INSTANCE) == TIM2_S)  || \
                                            ((INSTANCE) == TIM3_NS)  || ((INSTANCE) == TIM3_S)  || \
                                            ((INSTANCE) == TIM4_NS)  || ((INSTANCE) == TIM4_S))

/****************** TIM Instances : supporting repetition counter *************/
#define IS_TIM_REPETITION_COUNTER_INSTANCE(INSTANCE)  (((INSTANCE) == TIM1_NS)  || ((INSTANCE) == TIM1_S)  || \
                                                       ((INSTANCE) == TIM15_NS) || ((INSTANCE) == TIM15_S) || \
                                                       ((INSTANCE) == TIM16_NS) || ((INSTANCE) == TIM16_S) || \
                                                       ((INSTANCE) == TIM17_NS) || ((INSTANCE) == TIM17_S))

/****************** TIM Instances : supporting ADC triggering through TRGO2 ***/
#define IS_TIM_TRGO2_INSTANCE(INSTANCE)    (((INSTANCE) == TIM1_NS)  || ((INSTANCE) == TIM1_S))

/******************* TIM Instances : Timer input XOR function *****************/
#define IS_TIM_XOR_INSTANCE(INSTANCE)      (((INSTANCE) == TIM1_NS)  || ((INSTANCE) == TIM1_S)  || \
                                            ((INSTANCE) == TIM2_NS)  || ((INSTANCE) == TIM2_S)  || \
                                            ((INSTANCE) == TIM3_NS)  || ((INSTANCE) == TIM3_S)  || \
                                            ((INSTANCE) == TIM4_NS)  || ((INSTANCE) == TIM4_S)  || \
                                            ((INSTANCE) == TIM15_NS) || ((INSTANCE) == TIM15_S))

/******************* TIM Instances : Timer input selection ********************/
#define IS_TIM_TISEL_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS)  || ((INSTANCE) == TIM1_S) ||\
                                         ((INSTANCE) == TIM2_NS)  || ((INSTANCE) == TIM2_S) ||\
                                         ((INSTANCE) == TIM3_NS)  || ((INSTANCE) == TIM3_S) ||\
                                         ((INSTANCE) == TIM4_NS)  || ((INSTANCE) == TIM4_S) ||\
                                         ((INSTANCE) == TIM15_NS) || ((INSTANCE) == TIM15_S)||\
                                         ((INSTANCE) == TIM16_NS) || ((INSTANCE) == TIM16_S)||\
                                         ((INSTANCE) == TIM17_NS) || ((INSTANCE) == TIM17_S))

/******************* TIM Instances : supporting HSE32 as input  ********************/
#define IS_TIM_HSE32_INSTANCE(INSTANCE) (((INSTANCE) == TIM16_NS)  || ((INSTANCE) == TIM16_S) ||\
                                         ((INSTANCE) == TIM17_NS)  || ((INSTANCE) == TIM17_S))

/****************** TIM Instances : Advanced timer instances *******************/
#define IS_TIM_ADVANCED_INSTANCE(INSTANCE)       (((INSTANCE) == TIM1_NS)  || ((INSTANCE) == TIM1_S))

/****************************** TSC Instances *********************************/
#define IS_TSC_ALL_INSTANCE(INSTANCE) (((INSTANCE) == TSC_NS) || ((INSTANCE) == TSC_S))

/******************** USART Instances : Synchronous mode **********************/
#define IS_USART_INSTANCE(INSTANCE) (((INSTANCE) == USART1_NS) || ((INSTANCE) == USART1_S) || \
                                     ((INSTANCE) == USART3_NS) || ((INSTANCE) == USART3_S))

/******************** UART Instances : Asynchronous mode **********************/
#define IS_UART_INSTANCE(INSTANCE) (((INSTANCE) == USART1_NS) || ((INSTANCE) == USART1_S) || \
                                    ((INSTANCE) == USART3_NS) || ((INSTANCE) == USART3_S) || \
                                    ((INSTANCE) == UART4_NS)  || ((INSTANCE) == UART4_S)  || \
                                    ((INSTANCE) == UART5_NS)  || ((INSTANCE) == UART5_S))

/*********************** UART Instances : FIFO mode ***************************/
#define IS_UART_FIFO_INSTANCE(INSTANCE) (((INSTANCE) == USART1_NS)  || ((INSTANCE) == USART1_S) || \
                                         ((INSTANCE) == USART3_NS)  || ((INSTANCE) == USART3_S) || \
                                         ((INSTANCE) == UART4_NS)   || ((INSTANCE) == UART4_S)  || \
                                         ((INSTANCE) == UART5_NS)   || ((INSTANCE) == UART5_S)  || \
                                         ((INSTANCE) == LPUART1_NS) || ((INSTANCE) == LPUART1_S))

/*********************** UART Instances : SPI Slave mode **********************/
#define IS_UART_SPI_SLAVE_INSTANCE(INSTANCE) (((INSTANCE) == USART1_NS) || ((INSTANCE) == USART1_S) || \
                                              ((INSTANCE) == USART3_NS) || ((INSTANCE) == USART3_S))

/****************** UART Instances : Auto Baud Rate detection ****************/
#define IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(INSTANCE) (((INSTANCE) == USART1_NS) || ((INSTANCE) == USART1_S) || \
                                                            ((INSTANCE) == USART3_NS) || ((INSTANCE) == USART3_S) || \
                                                            ((INSTANCE) == UART4_NS)  || ((INSTANCE) == UART4_S)  || \
                                                            ((INSTANCE) == UART5_NS)  || ((INSTANCE) == UART5_S))

/****************** UART Instances : Driver Enable *****************/
#define IS_UART_DRIVER_ENABLE_INSTANCE(INSTANCE)     (((INSTANCE) == USART1_NS)  || ((INSTANCE) == USART1_S) || \
                                                      ((INSTANCE) == USART3_NS)  || ((INSTANCE) == USART3_S) || \
                                                      ((INSTANCE) == UART4_NS)   || ((INSTANCE) == UART4_S)  || \
                                                      ((INSTANCE) == UART5_NS)   || ((INSTANCE) == UART5_S)  || \
                                                      ((INSTANCE) == LPUART1_NS) || ((INSTANCE) == LPUART1_S))

/******************** UART Instances : Half-Duplex mode **********************/
#define IS_UART_HALFDUPLEX_INSTANCE(INSTANCE)   (((INSTANCE) == USART1_NS)  || ((INSTANCE) == USART1_S) || \
                                                 ((INSTANCE) == USART3_NS)  || ((INSTANCE) == USART3_S) || \
                                                 ((INSTANCE) == UART4_NS)   || ((INSTANCE) == UART4_S)  || \
                                                 ((INSTANCE) == UART5_NS)   || ((INSTANCE) == UART5_S)  || \
                                                 ((INSTANCE) == LPUART1_NS) || ((INSTANCE) == LPUART1_S))

/****************** UART Instances : Hardware Flow control ********************/
#define IS_UART_HWFLOW_INSTANCE(INSTANCE) (((INSTANCE) == USART1_NS)  || ((INSTANCE) == USART1_S) || \
                                           ((INSTANCE) == USART3_NS)  || ((INSTANCE) == USART3_S) || \
                                           ((INSTANCE) == UART4_NS)   || ((INSTANCE) == UART4_S)  || \
                                           ((INSTANCE) == UART5_NS)   || ((INSTANCE) == UART5_S)  || \
                                           ((INSTANCE) == LPUART1_NS) || ((INSTANCE) == LPUART1_S))

/******************** UART Instances : LIN mode **********************/
#define IS_UART_LIN_INSTANCE(INSTANCE)   (((INSTANCE) == USART1_NS) || ((INSTANCE) == USART1_S) || \
                                          ((INSTANCE) == USART3_NS) || ((INSTANCE) == USART3_S) || \
                                          ((INSTANCE) == UART4_NS)  || ((INSTANCE) == UART4_S)  || \
                                          ((INSTANCE) == UART5_NS)  || ((INSTANCE) == UART5_S))

/******************** UART Instances : Wake-up from Stop mode **********************/
#define IS_UART_WAKEUP_FROMSTOP_INSTANCE(INSTANCE)   (((INSTANCE) == USART1_NS)  || ((INSTANCE) == USART1_S) || \
                                                      ((INSTANCE) == USART3_NS)  || ((INSTANCE) == USART3_S) || \
                                                      ((INSTANCE) == UART4_NS)   || ((INSTANCE) == UART4_S)  || \
                                                      ((INSTANCE) == UART5_NS)   || ((INSTANCE) == UART5_S)  || \
                                                      ((INSTANCE) == LPUART1_NS) || ((INSTANCE) == LPUART1_S))

/*********************** UART Instances : IRDA mode ***************************/
#define IS_IRDA_INSTANCE(INSTANCE) (((INSTANCE) == USART1_NS) || ((INSTANCE) == USART1_S) || \
                                    ((INSTANCE) == USART3_NS) || ((INSTANCE) == USART3_S) || \
                                    ((INSTANCE) == UART4_NS)  || ((INSTANCE) == UART4_S)  || \
                                    ((INSTANCE) == UART5_NS)  || ((INSTANCE) == UART5_S))

/********************* USART Instances : Smard card mode ***********************/
#define IS_SMARTCARD_INSTANCE(INSTANCE) (((INSTANCE) == USART1_NS) || ((INSTANCE) == USART1_S) || \
                                         ((INSTANCE) == USART3_NS) || ((INSTANCE) == USART3_S))

/******************** LPUART Instance *****************************************/
#define IS_LPUART_INSTANCE(INSTANCE)    (((INSTANCE) == LPUART1_NS) || ((INSTANCE) == LPUART1_S))

/*********************** UART Instances : AUTONOMOUS mode ***************************/
#define IS_UART_AUTONOMOUS_INSTANCE(INSTANCE) (((INSTANCE) == USART1_NS)  || ((INSTANCE) == USART1_S) || \
                                               ((INSTANCE) == USART3_NS)  || ((INSTANCE) == USART3_S) || \
                                               ((INSTANCE) == UART4_NS)   || ((INSTANCE) == UART4_S)  || \
                                               ((INSTANCE) == UART5_NS)   || ((INSTANCE) == UART5_S)  || \
                                               ((INSTANCE) == LPUART1_NS) || ((INSTANCE) == LPUART1_S))

/****************************** IWDG Instances ********************************/
#define IS_IWDG_ALL_INSTANCE(INSTANCE)  (((INSTANCE) == IWDG_NS) || ((INSTANCE) == IWDG_S))

/****************************** WWDG Instances ********************************/
#define IS_WWDG_ALL_INSTANCE(INSTANCE)  (((INSTANCE) == WWDG_NS) || ((INSTANCE) == WWDG_S))

/******************************* MDF/ADF Instances ****************************/
#define IS_MDF_ALL_INSTANCE(INSTANCE) (((INSTANCE) == ADF1_Filter0_NS)  || ((INSTANCE) == ADF1_Filter0_S))

/******************************* USB DRD FS HCD Instances *************************/
#define IS_HCD_ALL_INSTANCE(INSTANCE) (((INSTANCE) == USB_DRD_FS_NS) || ((INSTANCE) == USB_DRD_FS_S))

/******************************* USB DRD FS PCD Instances *************************/
#define IS_PCD_ALL_INSTANCE(INSTANCE) (((INSTANCE) == USB_DRD_FS_NS) || ((INSTANCE) == USB_DRD_FS_S))

#else /* CPU_IN_SECURE_STATE */
/******************************* ADC Instances ********************************/
#define IS_ADC_ALL_INSTANCE(INSTANCE) (((INSTANCE) == ADC1_NS) || ((INSTANCE) == ADC2_NS))

#define IS_ADC_MULTIMODE_MASTER_INSTANCE(INSTANCE) ((INSTANCE) == ADC1_NS)

#define IS_ADC_COMMON_INSTANCE(INSTANCE) ((INSTANCE) == ADC12_COMMON_NS)

/******************************* AES Instances ********************************/
#define IS_AES_ALL_INSTANCE(INSTANCE) ((INSTANCE) == AES_NS)

/******************************* CCB Instances ********************************/
#define IS_CCB_ALL_INSTANCE(INSTANCE) ((INSTANCE) == CCB_NS)

/******************************* PKA Instances ********************************/
#define IS_PKA_ALL_INSTANCE(INSTANCE) ((INSTANCE) == PKA_NS)

/******************************* HASH Instances ********************************/
#define IS_HASH_ALL_INSTANCE(INSTANCE) ((INSTANCE) == HASH_NS)

/******************************** FDCAN Instances *****************************/
#define IS_FDCAN_ALL_INSTANCE(INSTANCE) ((INSTANCE) == FDCAN1_NS)

/******************************** COMP Instances ******************************/
#define IS_COMP_ALL_INSTANCE(INSTANCE) (((INSTANCE) == COMP1_NS) || ((INSTANCE) == COMP2_NS))

/******************** COMP Instances with window mode capability **************/
#define IS_COMP_WINDOWMODE_INSTANCE(INSTANCE) (((INSTANCE) == COMP1_NS) || ((INSTANCE) == COMP2_NS))

/******************************* CRC Instances ********************************/
#define IS_CRC_ALL_INSTANCE(INSTANCE) (((INSTANCE) == CRC_NS))

/******************************* DAC Instances ********************************/
#define IS_DAC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == DAC1_NS)

/******************************* DELAYBLOCK Instances *************************/
#define IS_DLYB_ALL_INSTANCE(INSTANCE)  (((INSTANCE) == DLYB_SDMMC1_NS)   || \
                                         ((INSTANCE) == DLYB_OCTOSPI1_NS))

/******************************** DMA Instances *******************************/
#define IS_DMA_ALL_INSTANCE(INSTANCE) (((INSTANCE) == GPDMA1_Channel0_NS)  || \
                                       ((INSTANCE) == GPDMA1_Channel1_NS)  || \
                                       ((INSTANCE) == GPDMA1_Channel2_NS)  || \
                                       ((INSTANCE) == GPDMA1_Channel3_NS)  || \
                                       ((INSTANCE) == GPDMA1_Channel4_NS)  || \
                                       ((INSTANCE) == GPDMA1_Channel5_NS)  || \
                                       ((INSTANCE) == GPDMA1_Channel6_NS)  || \
                                       ((INSTANCE) == GPDMA1_Channel7_NS)  || \
                                       ((INSTANCE) == GPDMA1_Channel8_NS)  || \
                                       ((INSTANCE) == GPDMA1_Channel9_NS)  || \
                                       ((INSTANCE) == GPDMA1_Channel10_NS) || \
                                       ((INSTANCE) == GPDMA1_Channel11_NS))

#define IS_GPDMA_INSTANCE(INSTANCE)   (((INSTANCE) == GPDMA1_Channel0_NS)  || \
                                       ((INSTANCE) == GPDMA1_Channel1_NS)  || \
                                       ((INSTANCE) == GPDMA1_Channel2_NS)  || \
                                       ((INSTANCE) == GPDMA1_Channel3_NS)  || \
                                       ((INSTANCE) == GPDMA1_Channel4_NS)  || \
                                       ((INSTANCE) == GPDMA1_Channel5_NS)  || \
                                       ((INSTANCE) == GPDMA1_Channel6_NS)  || \
                                       ((INSTANCE) == GPDMA1_Channel7_NS)  || \
                                       ((INSTANCE) == GPDMA1_Channel8_NS)  || \
                                       ((INSTANCE) == GPDMA1_Channel9_NS)  || \
                                       ((INSTANCE) == GPDMA1_Channel10_NS) || \
                                       ((INSTANCE) == GPDMA1_Channel11_NS))

#define IS_DMA_2D_ADDRESSING_INSTANCE(INSTANCE) (((INSTANCE) == GPDMA1_Channel10_NS)  || \
                                                 ((INSTANCE) == GPDMA1_Channel11_NS))

#define IS_DMA_PFREQ_INSTANCE(INSTANCE) (((INSTANCE) == GPDMA1_Channel0_NS)  || \
                                         ((INSTANCE) == GPDMA1_Channel1_NS))

/******************************* GPIO Instances *******************************/
#define IS_GPIO_ALL_INSTANCE(INSTANCE)      (((INSTANCE) == GPIOA_NS) || ((INSTANCE) == GPIOB_NS) || \
                                             ((INSTANCE) == GPIOC_NS) || ((INSTANCE) == GPIOD_NS) || \
                                             ((INSTANCE) == GPIOE_NS) || ((INSTANCE) == GPIOG_NS) || \
                                             ((INSTANCE) == GPIOH_NS))

  /******************************* GPIO AF Instances ****************************/
  /* On U3, all GPIO Bank support AF */
#define IS_GPIO_AF_INSTANCE(INSTANCE)       IS_GPIO_ALL_INSTANCE(INSTANCE)

  /**************************** GPIO Lock Instances *****************************/
  /* On U3, all GPIO Bank support the Lock mechanism */
#define IS_GPIO_LOCK_INSTANCE(INSTANCE)     IS_GPIO_ALL_INSTANCE(INSTANCE)

/******************************** I2C Instances *******************************/
#define IS_I2C_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2C1_NS) || \
                                       ((INSTANCE) == I2C2_NS) || \
                                       ((INSTANCE) == I2C3_NS))

/****************** I2C Instances : wakeup capability from stop modes *********/
#define IS_I2C_WAKEUP_FROMSTOP_INSTANCE(INSTANCE) IS_I2C_ALL_INSTANCE(INSTANCE)

/******************* I2C Instances : Group belongingness *********************/
#define IS_I2C_GRP1_INSTANCE(INSTANCE) (((INSTANCE) == I2C1_NS) || \
                                        ((INSTANCE) == I2C2_NS))

#define IS_I2C_GRP2_INSTANCE(INSTANCE) ((INSTANCE) == I2C3_NS)

/******************************** I3C Instances *******************************/
#define IS_I3C_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I3C1_NS) || \
                                       ((INSTANCE) == I3C2_NS))

/******************* I3C Instances : Group belongingness *********************/
#define IS_I3C_GRP1_INSTANCE(INSTANCE) (((INSTANCE) == I3C1_NS) || \
                                        ((INSTANCE) == I3C2_NS))

/****************************** OPAMP Instances *******************************/
#define IS_OPAMP_ALL_INSTANCE(INSTANCE) (((INSTANCE) == OPAMP1_NS) || ((INSTANCE) == OPAMP2_NS))

/******************************* OSPI Instances *******************************/
#define IS_OSPI_ALL_INSTANCE(INSTANCE)  ((INSTANCE) == OCTOSPI1_NS)

/****************************** RAMCFG Instances ********************************/
#define IS_RAMCFG_ALL_INSTANCE(INSTANCE) (((INSTANCE) == RAMCFG_SRAM1_NS) || \
                                          ((INSTANCE) == RAMCFG_SRAM2_NS))

/***************************** RAMCFG PED Instances *****************************/
#define IS_RAMCFG_PED_INSTANCE(INSTANCE) ((INSTANCE) == RAMCFG_SRAM2_NS)

/***************************** RAMCFG IT Instances ******************************/
#define IS_RAMCFG_IT_INSTANCE(INSTANCE) ((INSTANCE) == RAMCFG_SRAM2_NS)

/************************ RAMCFG Write Protection Instances *********************/
#define IS_RAMCFG_WP_INSTANCE(INSTANCE) ((INSTANCE) == RAMCFG_SRAM2_NS)

/************************ RAMCFG Erase Instances ********************************/
#define IS_RAMCFG_ER_INSTANCE(INSTANCE) (((INSTANCE) == RAMCFG_SRAM1_NS)  || \
                                         ((INSTANCE) == RAMCFG_SRAM2_NS))

/******************************* RNG Instances ********************************/
#define IS_RNG_ALL_INSTANCE(INSTANCE)  (((INSTANCE) == RNG_NS))

/****************************** RTC Instances *********************************/
#define IS_RTC_ALL_INSTANCE(INSTANCE) (((INSTANCE) == RTC_NS))

/******************************** SAI Instances *******************************/
#define IS_SAI_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SAI1_Block_A_NS) || ((INSTANCE) == SAI1_Block_B_NS))

/****************************** SDMMC Instances *******************************/
#define IS_SDMMC_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SDMMC1_NS))

/****************************** SMBUS Instances *******************************/
#define IS_SMBUS_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2C1_NS) || \
                                         ((INSTANCE) == I2C2_NS) || \
                                         ((INSTANCE) == I2C3_NS))

/******************* SMBUS Instances : Group belongingness *********************/
#define IS_SMBUS_GRP1_INSTANCE(INSTANCE) (((INSTANCE) == I2C1_NS) || \
                                          ((INSTANCE) == I2C2_NS))

#define IS_SMBUS_GRP2_INSTANCE(INSTANCE) ((INSTANCE) == I2C3_NS)

/******************************** SPI Instances *******************************/
#define IS_SPI_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI1_NS) || \
                                       ((INSTANCE) == SPI2_NS) || \
                                       ((INSTANCE) == SPI3_NS))

#define IS_SPI_LIMITED_INSTANCE(INSTANCE) ((INSTANCE) == SPI3_NS)

#define IS_SPI_FULL_INSTANCE(INSTANCE) (((INSTANCE) == SPI1_NS) || \
                                        ((INSTANCE) == SPI2_NS))

/******************* SPI Instances : Group belongingness *********************/
#define IS_SPI_GRP1_INSTANCE(INSTANCE) (((INSTANCE) == SPI1_NS) || \
                                        ((INSTANCE) == SPI2_NS))

#define IS_SPI_GRP2_INSTANCE(INSTANCE) ((INSTANCE) == SPI3_NS)

/****************** LPTIM Instances : All supported instances *****************/
#define IS_LPTIM_INSTANCE(INSTANCE)     (((INSTANCE) == LPTIM1_NS) ||\
                                         ((INSTANCE) == LPTIM2_NS) ||\
                                         ((INSTANCE) == LPTIM3_NS) ||\
                                         ((INSTANCE) == LPTIM4_NS))

/****************** LPTIM Instances : DMA supported instances *****************/
#define IS_LPTIM_DMA_INSTANCE(INSTANCE)  (((INSTANCE) == LPTIM1_NS) ||\
                                          ((INSTANCE) == LPTIM2_NS) ||\
                                          ((INSTANCE) == LPTIM3_NS))

/************* LPTIM Instances : at least 1 capture/compare channel ***********/
#define IS_LPTIM_CC1_INSTANCE(INSTANCE) (((INSTANCE) == LPTIM1_NS) ||\
                                         ((INSTANCE) == LPTIM2_NS) ||\
                                         ((INSTANCE) == LPTIM3_NS))

/************* LPTIM Instances : at least 2 capture/compare channel ***********/
#define IS_LPTIM_CC2_INSTANCE(INSTANCE) (((INSTANCE) == LPTIM1_NS) ||\
                                         ((INSTANCE) == LPTIM2_NS) ||\
                                         ((INSTANCE) == LPTIM3_NS))

/****************** LPTIM Instances : supporting encoder interface **************/
#define IS_LPTIM_ENCODER_INTERFACE_INSTANCE(INSTANCE)  (((INSTANCE) == LPTIM1_NS) ||\
                                                        ((INSTANCE) == LPTIM2_NS))

/****************** LPTIM Instances : supporting Input Capture **************/
#define IS_LPTIM_INPUT_CAPTURE_INSTANCE(INSTANCE)  (((INSTANCE) == LPTIM1_NS) ||\
                                                    ((INSTANCE) == LPTIM2_NS) ||\
                                                    ((INSTANCE) == LPTIM3_NS))

/****************** TIM Instances : All supported instances *******************/
#define IS_TIM_INSTANCE(INSTANCE)       (((INSTANCE) == TIM1_NS)  || \
                                         ((INSTANCE) == TIM2_NS)  || \
                                         ((INSTANCE) == TIM3_NS)  || \
                                         ((INSTANCE) == TIM4_NS)  || \
                                         ((INSTANCE) == TIM6_NS)  || \
                                         ((INSTANCE) == TIM7_NS)  || \
                                         ((INSTANCE) == TIM15_NS) || \
                                         ((INSTANCE) == TIM16_NS) || \
                                         ((INSTANCE) == TIM17_NS))

/****************** TIM Instances : supporting 32 bits counter ****************/
#define IS_TIM_32B_COUNTER_INSTANCE(INSTANCE) (((INSTANCE) == TIM2_NS)  || \
                                               ((INSTANCE) == TIM3_NS)  || \
                                               ((INSTANCE) == TIM4_NS))

/****************** TIM Instances : supporting the break function *************/
#define IS_TIM_BREAK_INSTANCE(INSTANCE)    (((INSTANCE) == TIM1_NS)  || \
                                            ((INSTANCE) == TIM15_NS) || \
                                            ((INSTANCE) == TIM16_NS) || \
                                            ((INSTANCE) == TIM17_NS) )

/************** TIM Instances : supporting Break source selection *************/
#define IS_TIM_BREAKSOURCE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS)  || \
                                               ((INSTANCE) == TIM15_NS) || \
                                               ((INSTANCE) == TIM16_NS) || \
                                               ((INSTANCE) == TIM17_NS))

/****************** TIM Instances : supporting 2 break inputs *****************/
#define IS_TIM_BKIN2_INSTANCE(INSTANCE)    ((INSTANCE) == TIM1_NS)

/************* TIM Instances : at least 1 capture/compare channel *************/
#define IS_TIM_CC1_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1_NS)  || \
                                         ((INSTANCE) == TIM2_NS)  || \
                                         ((INSTANCE) == TIM3_NS)  || \
                                         ((INSTANCE) == TIM4_NS)  || \
                                         ((INSTANCE) == TIM15_NS) || \
                                         ((INSTANCE) == TIM16_NS) || \
                                         ((INSTANCE) == TIM17_NS))

/************ TIM Instances : at least 2 capture/compare channels *************/
#define IS_TIM_CC2_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1_NS)  || \
                                         ((INSTANCE) == TIM2_NS)  || \
                                         ((INSTANCE) == TIM3_NS)  || \
                                         ((INSTANCE) == TIM4_NS)  || \
                                         ((INSTANCE) == TIM15_NS))

/************ TIM Instances : at least 3 capture/compare channels *************/
#define IS_TIM_CC3_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1_NS)  || \
                                         ((INSTANCE) == TIM2_NS)  || \
                                         ((INSTANCE) == TIM3_NS)  || \
                                         ((INSTANCE) == TIM4_NS))

/************ TIM Instances : at least 4 capture/compare channels *************/
#define IS_TIM_CC4_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1_NS)  || \
                                         ((INSTANCE) == TIM2_NS)  || \
                                         ((INSTANCE) == TIM3_NS)  || \
                                         ((INSTANCE) == TIM4_NS))

/****************** TIM Instances : at least 5 capture/compare channels *******/
#define IS_TIM_CC5_INSTANCE(INSTANCE)   ((INSTANCE) == TIM1_NS)

/****************** TIM Instances : at least 6 capture/compare channels *******/
#define IS_TIM_CC6_INSTANCE(INSTANCE)   ((INSTANCE) == TIM1_NS)

/************ TIM Instances : DMA requests generation (TIMx_DIER.COMDE) *******/
#define IS_TIM_CCDMA_INSTANCE(INSTANCE)    (((INSTANCE) == TIM1_NS)  || \
                                            ((INSTANCE) == TIM2_NS)  || \
                                            ((INSTANCE) == TIM3_NS)  || \
                                            ((INSTANCE) == TIM4_NS)  || \
                                            ((INSTANCE) == TIM15_NS) || \
                                            ((INSTANCE) == TIM16_NS) || \
                                            ((INSTANCE) == TIM17_NS))

/****************** TIM Instances : DMA requests generation (TIMx_DIER.UDE) ***/
#define IS_TIM_DMA_INSTANCE(INSTANCE)      (((INSTANCE) == TIM1_NS)  || \
                                            ((INSTANCE) == TIM2_NS)  || \
                                            ((INSTANCE) == TIM3_NS)  || \
                                            ((INSTANCE) == TIM4_NS)  || \
                                            ((INSTANCE) == TIM6_NS)  || \
                                            ((INSTANCE) == TIM7_NS)  || \
                                            ((INSTANCE) == TIM15_NS) || \
                                            ((INSTANCE) == TIM16_NS) || \
                                            ((INSTANCE) == TIM17_NS))

/************ TIM Instances : DMA requests generation (TIMx_DIER.CCxDE) *******/
#define IS_TIM_DMA_CC_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1_NS)  || \
                                            ((INSTANCE) == TIM2_NS)  || \
                                            ((INSTANCE) == TIM3_NS)  || \
                                            ((INSTANCE) == TIM4_NS)  || \
                                            ((INSTANCE) == TIM15_NS) || \
                                            ((INSTANCE) == TIM16_NS) || \
                                            ((INSTANCE) == TIM17_NS))

/******************** TIM Instances : DMA burst feature ***********************/
#define IS_TIM_DMABURST_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS)  || \
                                            ((INSTANCE) == TIM2_NS)  || \
                                            ((INSTANCE) == TIM3_NS)  || \
                                            ((INSTANCE) == TIM4_NS)  || \
                                            ((INSTANCE) == TIM15_NS) || \
                                            ((INSTANCE) == TIM16_NS) || \
                                            ((INSTANCE) == TIM17_NS))

/******************* TIM Instances : output(s) available **********************/
#define IS_TIM_CCX_INSTANCE(INSTANCE, CHANNEL) \
    ((((INSTANCE) == TIM1_NS)  && \
     (((CHANNEL) == TIM_CHANNEL_1) ||          \
      ((CHANNEL) == TIM_CHANNEL_2) ||          \
      ((CHANNEL) == TIM_CHANNEL_3) ||          \
      ((CHANNEL) == TIM_CHANNEL_4) ||          \
      ((CHANNEL) == TIM_CHANNEL_5) ||          \
      ((CHANNEL) == TIM_CHANNEL_6)))           \
     ||                                        \
     (((INSTANCE) == TIM2_NS)  && \
     (((CHANNEL) == TIM_CHANNEL_1) ||          \
      ((CHANNEL) == TIM_CHANNEL_2) ||          \
      ((CHANNEL) == TIM_CHANNEL_3) ||          \
      ((CHANNEL) == TIM_CHANNEL_4)))           \
     ||                                        \
     (((INSTANCE) == TIM3_NS)  && \
     (((CHANNEL) == TIM_CHANNEL_1) ||          \
      ((CHANNEL) == TIM_CHANNEL_2) ||          \
      ((CHANNEL) == TIM_CHANNEL_3) ||          \
      ((CHANNEL) == TIM_CHANNEL_4)))           \
     ||                                        \
     (((INSTANCE) == TIM4_NS)  && \
     (((CHANNEL) == TIM_CHANNEL_1) ||          \
      ((CHANNEL) == TIM_CHANNEL_2) ||          \
      ((CHANNEL) == TIM_CHANNEL_3) ||          \
      ((CHANNEL) == TIM_CHANNEL_4)))           \
     ||                                        \
     (((INSTANCE) == TIM15_NS) && \
     (((CHANNEL) == TIM_CHANNEL_1) ||          \
      ((CHANNEL) == TIM_CHANNEL_2)))           \
     ||                                        \
     (((INSTANCE) == TIM16_NS) && \
     (((CHANNEL) == TIM_CHANNEL_1)))           \
     ||                                        \
     (((INSTANCE) == TIM17_NS) && \
     (((CHANNEL) == TIM_CHANNEL_1))))

/****************** TIM Instances : supporting complementary output(s) ********/
#define IS_TIM_CCXN_INSTANCE(INSTANCE, CHANNEL) \
    ((((INSTANCE) == TIM1_NS)  && \
     (((CHANNEL) == TIM_CHANNEL_1) ||           \
      ((CHANNEL) == TIM_CHANNEL_2) ||           \
      ((CHANNEL) == TIM_CHANNEL_3) ||           \
      ((CHANNEL) == TIM_CHANNEL_4)))            \
    ||                                          \
    (((INSTANCE) == TIM15_NS) && \
     ((CHANNEL) == TIM_CHANNEL_1))              \
    ||                                          \
    (((INSTANCE) == TIM16_NS) && \
     ((CHANNEL) == TIM_CHANNEL_1))              \
    ||                                          \
    (((INSTANCE) == TIM17_NS) && \
     ((CHANNEL) == TIM_CHANNEL_1)))

/****************** TIM Instances : supporting clock division *****************/
#define IS_TIM_CLOCK_DIVISION_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1_NS)  || \
                                                    ((INSTANCE) == TIM2_NS)  || \
                                                    ((INSTANCE) == TIM3_NS)  || \
                                                    ((INSTANCE) == TIM4_NS)  || \
                                                    ((INSTANCE) == TIM15_NS) || \
                                                    ((INSTANCE) == TIM16_NS) || \
                                                    ((INSTANCE) == TIM17_NS))

/****** TIM Instances : supporting external clock mode 1 for ETRF input *******/
#define IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS)  || \
                                                        ((INSTANCE) == TIM2_NS)  || \
                                                        ((INSTANCE) == TIM3_NS)  || \
                                                        ((INSTANCE) == TIM4_NS))

/****** TIM Instances : supporting external clock mode 2 for ETRF input *******/
#define IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS)  || \
                                                        ((INSTANCE) == TIM2_NS)  || \
                                                        ((INSTANCE) == TIM3_NS)  || \
                                                        ((INSTANCE) == TIM4_NS))

/****************** TIM Instances : supporting external clock mode 1 for TIX inputs*/
#define IS_TIM_CLOCKSOURCE_TIX_INSTANCE(INSTANCE)      (((INSTANCE) == TIM1_NS)  || \
                                                        ((INSTANCE) == TIM2_NS)  || \
                                                        ((INSTANCE) == TIM3_NS)  || \
                                                        ((INSTANCE) == TIM4_NS)  || \
                                                        ((INSTANCE) == TIM15_NS))

/****************** TIM Instances : supporting internal trigger inputs(ITRX) *******/
#define IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(INSTANCE)     (((INSTANCE) == TIM1_NS)  || \
                                                        ((INSTANCE) == TIM2_NS)  || \
                                                        ((INSTANCE) == TIM3_NS)  || \
                                                        ((INSTANCE) == TIM4_NS)  || \
                                                        ((INSTANCE) == TIM15_NS))

/****************** TIM Instances : supporting combined 3-phase PWM mode ******/
#define IS_TIM_COMBINED3PHASEPWM_INSTANCE(INSTANCE) ((INSTANCE) == TIM1_NS)

/****************** TIM Instances : supporting commutation event generation ***/
#define IS_TIM_COMMUTATION_EVENT_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS)  || \
                                                     ((INSTANCE) == TIM15_NS) || \
                                                     ((INSTANCE) == TIM16_NS) || \
                                                     ((INSTANCE) == TIM17_NS))

/****************** TIM Instances : supporting counting mode selection ********/
#define IS_TIM_COUNTER_MODE_SELECT_INSTANCE(INSTANCE)  (((INSTANCE) == TIM1_NS)  || \
                                                        ((INSTANCE) == TIM2_NS)  || \
                                                        ((INSTANCE) == TIM3_NS)  || \
                                                        ((INSTANCE) == TIM4_NS))

/****************** TIM Instances : supporting encoder interface **************/
#define IS_TIM_ENCODER_INTERFACE_INSTANCE(INSTANCE)  (((INSTANCE) == TIM1_NS)  || \
                                                      ((INSTANCE) == TIM2_NS)  || \
                                                      ((INSTANCE) == TIM3_NS)  || \
                                                      ((INSTANCE) == TIM4_NS))

/****************** TIM Instances : supporting Hall sensor interface **********/
#define IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS)  || \
                                                         ((INSTANCE) == TIM2_NS)  || \
                                                         ((INSTANCE) == TIM3_NS)  || \
                                                         ((INSTANCE) == TIM4_NS)  || \
                                                         ((INSTANCE) == TIM15_NS))

/**************** TIM Instances : external trigger input available ************/
#define IS_TIM_ETR_INSTANCE(INSTANCE)      (((INSTANCE) == TIM1_NS)  || \
                                            ((INSTANCE) == TIM2_NS)  || \
                                            ((INSTANCE) == TIM3_NS)  || \
                                            ((INSTANCE) == TIM4_NS))

/************* TIM Instances : supporting ETR source selection ***************/
#define IS_TIM_ETRSEL_INSTANCE(INSTANCE)    (((INSTANCE) == TIM1_NS)  || \
                                             ((INSTANCE) == TIM2_NS)  || \
                                             ((INSTANCE) == TIM3_NS)  || \
                                             ((INSTANCE) == TIM4_NS))

/****** TIM Instances : Master mode available (TIMx_CR2.MMS available )********/
#define IS_TIM_MASTER_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1_NS)  || \
                                            ((INSTANCE) == TIM2_NS)  || \
                                            ((INSTANCE) == TIM3_NS)  || \
                                            ((INSTANCE) == TIM4_NS)  || \
                                            ((INSTANCE) == TIM6_NS)  || \
                                            ((INSTANCE) == TIM7_NS)  || \
                                            ((INSTANCE) == TIM15_NS))

/*********** TIM Instances : Slave mode available (TIMx_SMCR available )*******/
#define IS_TIM_SLAVE_INSTANCE(INSTANCE)    (((INSTANCE) == TIM1_NS)  || \
                                            ((INSTANCE) == TIM2_NS)  || \
                                            ((INSTANCE) == TIM3_NS)  || \
                                            ((INSTANCE) == TIM4_NS)  || \
                                            ((INSTANCE) == TIM15_NS))

/****************** TIM Instances : supporting OCxREF clear *******************/
#define IS_TIM_OCXREF_CLEAR_INSTANCE(INSTANCE)        (((INSTANCE) == TIM1_NS)  || \
                                                       ((INSTANCE) == TIM2_NS)  || \
                                                       ((INSTANCE) == TIM3_NS)  || \
                                                       ((INSTANCE) == TIM4_NS)  || \
                                                       ((INSTANCE) == TIM15_NS) || \
                                                       ((INSTANCE) == TIM16_NS) || \
                                                       ((INSTANCE) == TIM17_NS))

/****************** TIM Instances : supporting bitfield OCCS in SMCR register *******************/
#define IS_TIM_OCCS_INSTANCE(INSTANCE)       (((INSTANCE) == TIM1_NS)  || \
                                              ((INSTANCE) == TIM2_NS)  || \
                                              ((INSTANCE) == TIM3_NS)  || \
                                              ((INSTANCE) == TIM4_NS))

/****************** TIM Instances : remapping capability **********************/
#define IS_TIM_REMAP_INSTANCE(INSTANCE)    (((INSTANCE) == TIM1_NS)  || \
                                            ((INSTANCE) == TIM2_NS)  || \
                                            ((INSTANCE) == TIM3_NS)  || \
                                            ((INSTANCE) == TIM4_NS))

/****************** TIM Instances : supporting repetition counter *************/
#define IS_TIM_REPETITION_COUNTER_INSTANCE(INSTANCE)  (((INSTANCE) == TIM1_NS)  || \
                                                       ((INSTANCE) == TIM15_NS) || \
                                                       ((INSTANCE) == TIM16_NS) || \
                                                       ((INSTANCE) == TIM17_NS))

/****************** TIM Instances : supporting ADC triggering through TRGO2 ***/
#define IS_TIM_TRGO2_INSTANCE(INSTANCE)    ((INSTANCE) == TIM1_NS)

/******************* TIM Instances : Timer input XOR function *****************/
#define IS_TIM_XOR_INSTANCE(INSTANCE)      (((INSTANCE) == TIM1_NS)  || \
                                            ((INSTANCE) == TIM2_NS)  || \
                                            ((INSTANCE) == TIM3_NS)  || \
                                            ((INSTANCE) == TIM4_NS)  || \
                                            ((INSTANCE) == TIM15_NS))

/******************* TIM Instances : Timer input selection ********************/
#define IS_TIM_TISEL_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) ||\
                                         ((INSTANCE) == TIM2_NS) ||\
                                         ((INSTANCE) == TIM3_NS) ||\
                                         ((INSTANCE) == TIM4_NS) ||\
                                         ((INSTANCE) == TIM15_NS)||\
                                         ((INSTANCE) == TIM16_NS)||\
                                         ((INSTANCE) == TIM17_NS))

/******************* TIM Instances : supporting HSE32 as input  ********************/
#define IS_TIM_HSE32_INSTANCE(INSTANCE) (((INSTANCE) == TIM16_NS) ||\
                                         ((INSTANCE) == TIM17_NS))

/****************** TIM Instances : Advanced timer instances *******************/
#define IS_TIM_ADVANCED_INSTANCE(INSTANCE)       ((INSTANCE) == TIM1_NS)

/****************************** TSC Instances *********************************/
#define IS_TSC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == TSC_NS)

/******************** USART Instances : Synchronous mode **********************/
#define IS_USART_INSTANCE(INSTANCE) (((INSTANCE) == USART1_NS) || \
                                     ((INSTANCE) == USART3_NS))

/******************** UART Instances : Asynchronous mode **********************/
#define IS_UART_INSTANCE(INSTANCE) (((INSTANCE) == USART1_NS) || \
                                    ((INSTANCE) == USART3_NS) || \
                                    ((INSTANCE) == UART4_NS)  || \
                                    ((INSTANCE) == UART5_NS))

/*********************** UART Instances : FIFO mode ***************************/
#define IS_UART_FIFO_INSTANCE(INSTANCE) (((INSTANCE) == USART1_NS)  || \
                                         ((INSTANCE) == USART3_NS)  || \
                                         ((INSTANCE) == UART4_NS)   || \
                                         ((INSTANCE) == UART5_NS)   || \
                                         ((INSTANCE) == LPUART1_NS))

/*********************** UART Instances : SPI Slave mode **********************/
#define IS_UART_SPI_SLAVE_INSTANCE(INSTANCE) (((INSTANCE) == USART1_NS) || \
                                              ((INSTANCE) == USART3_NS))

/****************** UART Instances : Auto Baud Rate detection ****************/
#define IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(INSTANCE) (((INSTANCE) == USART1_NS) || \
                                                            ((INSTANCE) == USART3_NS) || \
                                                            ((INSTANCE) == UART4_NS)  || \
                                                            ((INSTANCE) == UART5_NS))

/****************** UART Instances : Driver Enable *****************/
#define IS_UART_DRIVER_ENABLE_INSTANCE(INSTANCE)     (((INSTANCE) == USART1_NS)  || \
                                                      ((INSTANCE) == USART3_NS)  || \
                                                      ((INSTANCE) == UART4_NS)   || \
                                                      ((INSTANCE) == UART5_NS)   || \
                                                      ((INSTANCE) == LPUART1_NS))

/******************** UART Instances : Half-Duplex mode **********************/
#define IS_UART_HALFDUPLEX_INSTANCE(INSTANCE)   (((INSTANCE) == USART1_NS)  || \
                                                 ((INSTANCE) == USART3_NS)  || \
                                                 ((INSTANCE) == UART4_NS)   || \
                                                 ((INSTANCE) == UART5_NS)   || \
                                                 ((INSTANCE) == LPUART1_NS))

/****************** UART Instances : Hardware Flow control ********************/
#define IS_UART_HWFLOW_INSTANCE(INSTANCE) (((INSTANCE) == USART1_NS)  || \
                                           ((INSTANCE) == USART3_NS)  || \
                                           ((INSTANCE) == UART4_NS)   || \
                                           ((INSTANCE) == UART5_NS)   || \
                                           ((INSTANCE) == LPUART1_NS))

/******************** UART Instances : LIN mode **********************/
#define IS_UART_LIN_INSTANCE(INSTANCE)   (((INSTANCE) == USART1_NS) || \
                                          ((INSTANCE) == USART3_NS) || \
                                          ((INSTANCE) == UART4_NS)  || \
                                          ((INSTANCE) == UART5_NS))

/******************** UART Instances : Wake-up from Stop mode **********************/
#define IS_UART_WAKEUP_FROMSTOP_INSTANCE(INSTANCE)   (((INSTANCE) == USART1_NS)  || \
                                                      ((INSTANCE) == USART3_NS)  || \
                                                      ((INSTANCE) == UART4_NS)   || \
                                                      ((INSTANCE) == UART5_NS)   || \
                                                      ((INSTANCE) == LPUART1_NS))

/*********************** UART Instances : IRDA mode ***************************/
#define IS_IRDA_INSTANCE(INSTANCE) (((INSTANCE) == USART1_NS) || \
                                    ((INSTANCE) == USART3_NS) || \
                                    ((INSTANCE) == UART4_NS)  || \
                                    ((INSTANCE) == UART5_NS))

/********************* USART Instances : Smard card mode ***********************/
#define IS_SMARTCARD_INSTANCE(INSTANCE) (((INSTANCE) == USART1_NS) || \
                                         ((INSTANCE) == USART3_NS))

/******************** LPUART Instance *****************************************/
#define IS_LPUART_INSTANCE(INSTANCE)    ((INSTANCE) == LPUART1_NS)

/*********************** UART Instances : AUTONOMOUS mode ***************************/
#define IS_UART_AUTONOMOUS_INSTANCE(INSTANCE) (((INSTANCE) == USART1_NS)  || \
                                               ((INSTANCE) == USART3_NS)  || \
                                               ((INSTANCE) == UART4_NS)   || \
                                               ((INSTANCE) == UART5_NS)   || \
                                               ((INSTANCE) == LPUART1_NS))

/****************************** IWDG Instances ********************************/
#define IS_IWDG_ALL_INSTANCE(INSTANCE)        ((INSTANCE) == IWDG_NS)

/****************************** WWDG Instances ********************************/
#define IS_WWDG_ALL_INSTANCE(INSTANCE)        ((INSTANCE) == WWDG_NS)

/******************************* MDF/ADF Instances ****************************/
#define IS_MDF_ALL_INSTANCE(INSTANCE) ((INSTANCE) == ADF1_Filter0_NS)

/******************************* USB DRD FS HCD Instances *************************/
#define IS_HCD_ALL_INSTANCE(INSTANCE) ((INSTANCE) == USB_DRD_FS_NS)

/******************************* USB DRD FS PCD Instances *************************/
#define IS_PCD_ALL_INSTANCE(INSTANCE) ((INSTANCE) == USB_DRD_FS_NS)

#endif /* CPU_IN_SECURE_STATE */
/** @} */ /* End of group STM32U5xx_Peripheral_Exported_macros */

/** @} */ /* End of group STM32U385xx */

/** @} */ /* End of group ST */

#ifdef __cplusplus
}
#endif

#endif  /* STM32U385xx_H */

