/*
 * ADS124S08_LIB.c
 *
 *  Created on: Nov 10, 2024
 *      Author: zafst
 */

#include "ADS124S08_LIB.h"
#include "ADS124S08_Port.h"

typedef enum ADS124S08_INIT_STATE
{
	ADS124S08_NOT_INITIALIZED,
	ADS124S08_INITIALIZED,

}e_ADS124S08_INIT_STATE;

e_ADS124S08_INIT_STATE InitStates[ADS124S08_MAX_NUM_CHIPS] = {ADS124S08_NOT_INITIALIZED};
e_ADS124S08_SEND_CRC SendCRCEnabled[ADS124S08_MAX_NUM_CHIPS] = {ADS124S08_SEND_CRC_DISABLED};
e_ADS124S08_SEND_STAT SendStatEnabled[ADS124S08_MAX_NUM_CHIPS] = {ADS124S08_SEND_STAT_DISABLED};


/* Data Handling Functions*/
e_ADS124S08_State ADS124S08_Read_Data(e_ADS124S08_ChipID ChipID,uint8_t* Data,uint8_t size)
{

	uint8_t Command = ADS124S08_READ_DATA_COMMAND;

	if(ADS124S08_PORT_Read_Data(ChipID, Command, Data, size) == ADS124S08_OK)
	{
		return ADS124S08_OK;
	}
	else
	{
		return ADS124S08_ERROR;
	}
}

e_ADS124S08_State ADS124S08_Read_Register(e_ADS124S08_ChipID ChipID,uint8_t RegAddres,uint8_t NumRegs,uint8_t* Data)
{
	uint8_t CommandData[2] = {0};
	CommandData[0] = (RegAddres | 0b00100000);
	CommandData[1] = (NumRegs) & 0b00011111; // mit und verknüpfen um auf max Register zu Begrenzen

	if(ADS124S08_PORT_Read_Register(ChipID, CommandData, NumRegs, Data) == ADS124S08_OK)
	{
		return ADS124S08_OK;
	}
	else
	{
		return ADS124S08_ERROR;
	}
}
e_ADS124S08_State ADS124S08_Write_Register(e_ADS124S08_ChipID ChipID,uint8_t RegAddres,uint8_t NumRegs,uint8_t* Data)
{
	uint8_t CommandData[2] = {0};

	CommandData[0] = (RegAddres | 0b01000000);
	CommandData[1] = (NumRegs) & 0b00011111; // mit und verknüpfen um auf max Register zu Begrenzen

	if(ADS124S08_PORT_Write_Register(ChipID, CommandData, NumRegs, Data) == ADS124S08_OK)
	{
		return ADS124S08_OK;
	}
	else
	{
		return ADS124S08_ERROR;
	}
}

e_ADS124S08_State ADS124S08_DATA_READY_INTERRUPT(e_ADS124S08_ChipID ChipID)
{
	if(ChipID < ADS124S08_MAX_NUM_CHIPS)
	{
		if(InitStates[ChipID] == ADS124S08_INITIALIZED)
		{
			uint8_t ADC_DATA_SIZE = ADS124S08_DATA_MIN_SIZE;
			int32_t ADC_RAW_DATA = 0;
			uint8_t ADC_STATUS = 0;
			uint8_t ADC_CRC = 0;

			switch(SendStatEnabled[ChipID])
			{
				case ADS124S08_SEND_STAT_DISABLED:
				{
					break;
				}
				case ADS124S08_SEND_STAT_ENABLED:
				{
					ADC_DATA_SIZE++;
					break;
				}

			}
			switch(SendCRCEnabled[ChipID])
			{
				case ADS124S08_SEND_CRC_DISABLED:
				{
					break;
				}
				case ADS124S08_SEND_CRC_ENABLED:
				{
					ADC_DATA_SIZE++;
					break;
				}
			}

			uint8_t ADC_DATA[ADC_DATA_SIZE];

			for(uint_fast8_t i = 0; i< ADC_DATA_SIZE;i++) // Sicherheitshalber mit 0 initialisieren
			{
				ADC_DATA[i] = 0;
			}

			if(ADS124S08_Read_Data(ChipID, ADC_DATA,ADC_DATA_SIZE) == ADS124S08_OK)
			{
				if(SendCRCEnabled[ChipID] == ADS124S08_SEND_CRC_ENABLED)
				{
					if(ADS124S08_PORT_CHECK_CRC(ADC_DATA, ADC_DATA_SIZE-1,ADC_CRC) == ADS124S08_OK)
					{
						if(SendStatEnabled[ChipID] == ADS124S08_SEND_STAT_ENABLED)
						{
							ADC_STATUS = ADC_DATA[0];
							ADC_RAW_DATA = ADC_DATA[1]<<16 | ADC_DATA[2]<<8 | ADC_DATA[3];

							if(ADC_RAW_DATA & 0x800000)
							{
								ADC_RAW_DATA = ADC_RAW_DATA | 0xFF000000;
							}
							else
							{
								ADC_RAW_DATA = ADC_RAW_DATA;
							}

							ADS124S08_DATA_READ_CALLBACK(ChipID, ADC_RAW_DATA, ADC_STATUS);

							return ADS124S08_OK;
						}
						else
						{
							ADC_RAW_DATA = ADC_DATA[0]<<16 | ADC_DATA[1]<<8 | ADC_DATA[2];
							if(ADC_RAW_DATA & 0x800000)
							{
								ADC_RAW_DATA = ADC_RAW_DATA | 0xFF000000;
							}
							else
							{
								ADC_RAW_DATA = ADC_RAW_DATA;
							}
							ADS124S08_DATA_READ_CALLBACK(ChipID, ADC_RAW_DATA, ADC_STATUS);

							return ADS124S08_OK;
						}
					}
					else
					{
						return ADS124S08_ERROR;
					}
				}
				else
				{
					if(SendStatEnabled[ChipID] == ADS124S08_SEND_STAT_ENABLED)
					{
						ADC_STATUS = ADC_DATA[0];
						ADC_RAW_DATA = ADC_DATA[1]<<16 | ADC_DATA[2]<<8 | ADC_DATA[3];

						if(ADC_RAW_DATA & 0x800000)
						{
							ADC_RAW_DATA = ADC_RAW_DATA | 0xFF000000;
						}
						else
						{
							ADC_RAW_DATA = ADC_RAW_DATA;
						}

						ADS124S08_DATA_READ_CALLBACK(ChipID, ADC_RAW_DATA, ADC_STATUS);
						return ADS124S08_OK;
					}
					else
					{
						ADC_RAW_DATA = ADC_DATA[0]<<16 | ADC_DATA[1]<<8 | ADC_DATA[2];

						if(ADC_RAW_DATA & 0x800000)
						{
							ADC_RAW_DATA = ADC_RAW_DATA | 0xFF000000;
						}
						else
						{
							ADC_RAW_DATA = ADC_RAW_DATA;
						}

						ADS124S08_DATA_READ_CALLBACK(ChipID, ADC_RAW_DATA, ADC_STATUS);
						return ADS124S08_OK;
					}
				}
			}
			else
			{
				return ADS124S08_ERROR;
			}
		}
		else
		{
			return ADS124S08_ERROR;
		}
	}
	else
	{
		return ADS124S08_ERROR;
	}

}


__weak e_ADS124S08_State ADS124S08_DATA_READ_CALLBACK(e_ADS124S08_ChipID ChipID,int32_t Data,uint8_t Status)
{
	UNUSED(ChipID);
	UNUSED(Data);


	return ADS124S08_OK;
}

e_ADS124S08_State ADS124S08_SET_POSITIVE_ANALOG_INPUT_CHANNEL(e_ADS124S08_ChipID ChipID,e_ADS124S08_POS_IN_SEL POS_IN)
{
	if(ChipID < ADS124S08_MAX_NUM_CHIPS)
	{
		if(InitStates[ChipID] == ADS124S08_INITIALIZED)
		{
			if(POS_IN <= ADS124S08_POS_IN_AIN_COM)
			{
				uint8_t tempReg = 0;

				if(ADS124S08_Read_Register(ChipID, REG_ADS124S08_INPUT_MUX, 1, &tempReg) == ADS124S08_OK)
				{
					tempReg = tempReg & ADS124S08_POSITIVE_IN_SEL_CLEAR_MASK;	//Positiv IN Einstellung loeschen
					tempReg = tempReg | (POS_IN << ADS124S08_POSITIVE_IN_SEL_BASE_SHIFT);	//Neuen Kanal Wählen

					if(ADS124S08_Write_Register(ChipID, REG_ADS124S08_INPUT_MUX, 1, &tempReg) == ADS124S08_OK)
					{
						return ADS124S08_OK;
					}
					else
					{
						return ADS124S08_ERROR;	// Fehler Register schreiben
					}
				}
				else
				{
					return ADS124S08_ERROR;	//Fehler inputmux Register Lesen
				}
			}
			else
			{
				return ADS124S08_ERROR;		// Fehler Eingang auserhalb erlaubten Berich
			}
		}
		else
		{
			return ADS124S08_ERROR;		//Fehler ADC nicht Initialisiert
		}
	}
	else
	{
		return ADS124S08_ERROR;			//Fehler ChipID auserhalb erlaubten Bereich
	}
}

e_ADS124S08_State ADS124S08_SET_NEGATIVE_ANALOG_INPUT_CHANNEL(e_ADS124S08_ChipID ChipID,e_ADS124S08_NEG_IN_SEL NEG_IN)
{
	if(ChipID < ADS124S08_MAX_NUM_CHIPS)
	{
		if(InitStates[ChipID] == ADS124S08_INITIALIZED)
		{
			if(NEG_IN <= ADS124S08_NEG_IN_AIN_COM)
			{
				uint8_t tempReg = 0;

				if(ADS124S08_Read_Register(ChipID, REG_ADS124S08_INPUT_MUX, 1, &tempReg) == ADS124S08_OK)
				{
					tempReg = tempReg & ADS124S08_NEGATIVE_IN_SEL_CLEAR_MASK;	//Negativ IN Einstellung loeschen
					tempReg = tempReg | (NEG_IN << ADS124S08_NEGATIVE_IN_SEL_BASE_SHIFT);	//Neuen Kanal Wählen

					if(ADS124S08_Write_Register(ChipID, REG_ADS124S08_INPUT_MUX, 1, &tempReg) == ADS124S08_OK)
					{
						return ADS124S08_OK;
					}
					else
					{
						return ADS124S08_ERROR;	// Fehler Register schreiben
					}
				}
				else
				{
					return ADS124S08_ERROR;	//Fehler inputmux Register Lesen
				}
			}
			else
			{
				return ADS124S08_ERROR;		// Fehler Eingang auserhalb erlaubten Berich
			}
		}
		else
		{
			return ADS124S08_ERROR;		//Fehler ADC nicht Initialisiert
		}
	}
	else
	{
		return ADS124S08_ERROR;			//Fehler ChipID auserhalb erlaubten Bereich
	}
}

e_ADS124S08_State ADS124S08_SET_PGA_SETTINGS(e_ADS124S08_ChipID ChipID,e_ADS124S08_PROG_CONV_DELAY Delay,e_ADS124S08_PGA_MODE Mode,e_ADS124S08_GAIN_SETTING Gain)
{
	if(ChipID < ADS124S08_MAX_NUM_CHIPS)
	{
		if(InitStates[ChipID] == ADS124S08_INITIALIZED)
		{
			uint8_t tempReg = 0;

			tempReg = tempReg | Delay << ADS124S08_PROG_CONV_DELAY_BASE_SHIFT;
			tempReg = tempReg | Mode << ADS124S08_PGA_MODE_BASE_SHIFT;
			tempReg = tempReg | Gain << ADS124S08_PGA_GAIN_BASE_SHIFT;

			if(ADS124S08_Write_Register(ChipID, REG_ADS124S08_GAIN_SETTINGS, 1, &tempReg) == ADS124S08_OK)
			{
				return ADS124S08_OK;
			}
			else
			{
				return ADS124S08_ERROR;
			}
		}
		else
		{
			return ADS124S08_ERROR;
		}
	}
	else
	{
		return ADS124S08_ERROR;
	}
}

e_ADS124S08_State ADS124S08_SET_DATA_RATE(e_ADS124S08_ChipID ChipID,e_ADS124S08_DATA_RATE DataRate)
{
	if(ChipID < ADS124S08_MAX_NUM_CHIPS)
	{
		if(InitStates[ChipID] == ADS124S08_INITIALIZED)
		{
			uint8_t tempReg = 0;

			if(ADS124S08_Read_Register(ChipID, REG_ADS124S08_DATA_RATE, 1, &tempReg) == ADS124S08_OK)
			{
				tempReg = tempReg & ADS124S08_DATA_RATE_CLEAR_MASK;
				tempReg = tempReg | DataRate << ADS124S08_DATA_RATE_BASE_SHIFT;

				if(ADS124S08_Write_Register(ChipID, REG_ADS124S08_DATA_RATE, 1, &tempReg) == ADS124S08_OK)
				{
					return ADS124S08_OK;
				}
				else
				{
					return ADS124S08_ERROR;
				}
			}
			else
			{
				return ADS124S08_ERROR;
			}
		}
		else
		{
			return ADS124S08_ERROR;
		}
	}
	else
	{
		return ADS124S08_ERROR;
	}
}

e_ADS124S08_State ADS124S08_SET_FILTER_MODE(e_ADS124S08_ChipID ChipID,ADS124S08_FILTER_MODE Mode)
{
	if(ChipID < ADS124S08_MAX_NUM_CHIPS)
	{
		if(InitStates[ChipID] == ADS124S08_INITIALIZED)
		{
			uint8_t tempReg = 0;

			if(ADS124S08_Read_Register(ChipID, REG_ADS124S08_DATA_RATE, 1, &tempReg) == ADS124S08_OK)
			{
				tempReg = tempReg & ADS124S08_SEL_FILTER_CLEAR_MASK;
				tempReg = tempReg | Mode << ADS124S08_SEL_FILTER_MODE_BASE_SHIFT;

				if(ADS124S08_Write_Register(ChipID, REG_ADS124S08_DATA_RATE, 1, &tempReg) == ADS124S08_OK)
				{
					return ADS124S08_OK;
				}
				else
				{
					return ADS124S08_ERROR;
				}
			}
			else
			{
				return ADS124S08_ERROR;
			}
		}
		else
		{
			return ADS124S08_ERROR;
		}
	}
	else
	{
		return ADS124S08_ERROR;
	}
}
e_ADS124S08_State ADS124S08_SET_CONV_MODE(e_ADS124S08_ChipID ChipID,e_ADS124S08_CONV_MODE Mode)
{
	if(ChipID < ADS124S08_MAX_NUM_CHIPS)
	{
		if(InitStates[ChipID] == ADS124S08_INITIALIZED)
		{
			uint8_t tempReg = 0;

			if(ADS124S08_Read_Register(ChipID, REG_ADS124S08_DATA_RATE, 1, &tempReg) == ADS124S08_OK)
			{
				tempReg = tempReg & ADS124S08_CONV_MODE_CLEAR_MASK;
				tempReg = tempReg | Mode << ADS124S08_CONV_MODE_BASE_SHIFT;

				if(ADS124S08_Write_Register(ChipID, REG_ADS124S08_DATA_RATE, 1, &tempReg) == ADS124S08_OK)
				{
					return ADS124S08_OK;
				}
				else
				{
					return ADS124S08_ERROR;
				}
			}
			else
			{
				return ADS124S08_ERROR;
			}
		}
		else
		{
			return ADS124S08_ERROR;
		}
	}
	else
	{
		return ADS124S08_ERROR;
	}
}
e_ADS124S08_State ADS124S08_SET_CLOCK_MODE(e_ADS124S08_ChipID ChipID,e_ADS124S08_CLOCK_MODE Mode)
{
	if(ChipID < ADS124S08_MAX_NUM_CHIPS)
	{
		if(InitStates[ChipID] == ADS124S08_INITIALIZED)
		{
			uint8_t tempReg = 0;

			if(ADS124S08_Read_Register(ChipID, REG_ADS124S08_DATA_RATE, 1, &tempReg) == ADS124S08_OK)
			{
				tempReg = tempReg & ADS124S08_SEL_CLOCK_CLEAR_MASK;
				tempReg = tempReg | Mode << ADS124S08_SEL_CLOCK_BASE_SHIFT;

				if(ADS124S08_Write_Register(ChipID, REG_ADS124S08_DATA_RATE, 1, &tempReg) == ADS124S08_OK)
				{
					return ADS124S08_OK;
				}
				else
				{
					return ADS124S08_ERROR;
				}
			}
			else
			{
				return ADS124S08_ERROR;
			}
		}
		else
		{
			return ADS124S08_ERROR;
		}
	}
	else
	{
		return ADS124S08_ERROR;
	}
}
e_ADS124S08_State ADS124S08_SET_CHOP_MODE(e_ADS124S08_ChipID ChipID,e_ADS124S08_GLOBAL_CHOP_MODE Mode)
{
	if(ChipID < ADS124S08_MAX_NUM_CHIPS)
	{
		if(InitStates[ChipID] == ADS124S08_INITIALIZED)
		{
			uint8_t tempReg = 0;

			if(ADS124S08_Read_Register(ChipID, REG_ADS124S08_DATA_RATE, 1, &tempReg) == ADS124S08_OK)
			{
				tempReg = tempReg & ADS124S08_GLOBAL_CHOP_MODE_CLEAR_MASK;
				tempReg = tempReg | Mode << ADS124S08_GLOBAL_CHOP_MODE_BASE_SHIFT;

				if(ADS124S08_Write_Register(ChipID, REG_ADS124S08_DATA_RATE, 1, &tempReg) == ADS124S08_OK)
				{
					return ADS124S08_OK;
				}
				else
				{
					return ADS124S08_ERROR;
				}
			}
			else
			{
				return ADS124S08_ERROR;
			}
		}
		else
		{
			return ADS124S08_ERROR;
		}
	}
	else
	{
		return ADS124S08_ERROR;
	}
}

e_ADS124S08_State ADS124S08_SET_REFERENCE_SETTINGS(e_ADS124S08_ChipID ChipID,e_ADS124S08_INTERNAL_REFERENCE_CONFIGURATION Int_Ref_Conv,e_ADS124S08_REFERENCE_IN_SEL Ref_In_Sel,e_ADS124S08_REFN_BUFFER_MODE Ref_N_Buf_Mode,e_ADS124S08_REFP_BUFFER_MODE Ref_P_Buf_Mode,e_ADS124S08_REFERENCE_MONITOR_MODE Ref_Mon_Mode)
{
	if(ChipID < ADS124S08_MAX_NUM_CHIPS)
	{
		if(InitStates[ChipID] == ADS124S08_INITIALIZED)
		{
			uint8_t tempReg = 0;

			tempReg = tempReg | Int_Ref_Conv << ADS124S08_INTERNAL_REFERENCE_CONF_BASE_SHIFT;
			tempReg = tempReg | Ref_In_Sel << ADS124S08_REFERENCE_IN_SEL_BASE_SHIFT;
			tempReg = tempReg | Ref_N_Buf_Mode << ADS124S08_REFN_BUFFER_BYPASS_BASE_SHIFT;
			tempReg = tempReg | Ref_P_Buf_Mode << ADS124S08_REFP_BUFFER_BYPASS_BASE_SHIFT;
			tempReg = tempReg | Ref_Mon_Mode << ADS124S08_REFERENCE_MON_MODE_BASE_SHIFT;

			if(ADS124S08_Write_Register(ChipID, REG_ADS124S08_REFERENCE_CONTROL, 1, &tempReg) == ADS124S08_OK)
			{
				return ADS124S08_OK;
			}
			else
			{
				return ADS124S08_ERROR;
			}
		}
		else
		{
			return ADS124S08_ERROR;
		}
	}
	else
	{
		return ADS124S08_ERROR;
	}
}

e_ADS124S08_State ADS124S08_SET_EXCITATION_CURRENT(e_ADS124S08_ChipID ChipID, e_ADS124S08_EXCITATION_CURRENT Current)
{
	if(ChipID < ADS124S08_MAX_NUM_CHIPS)
	{
		if(InitStates[ChipID] == ADS124S08_INITIALIZED)
		{
			uint8_t tempReg = 0;

			tempReg = tempReg | Current << ADS124S08_SET_EXCITATION_CURRENT_BASE_SHIFT;

			if(ADS124S08_Write_Register(ChipID, REG_ADS124S08_EXCITATION_CURRENT_1, 1, &tempReg) == ADS124S08_OK)
			{
				return ADS124S08_OK;
			}
			else
			{
				return ADS124S08_ERROR;
			}
		}
		else
		{
			return ADS124S08_ERROR;
		}
	}
	else
	{
		return ADS124S08_ERROR;
	}
}

e_ADS124S08_State ADS124S08_SET_IDAC_OUTPUT(e_ADS124S08_ChipID ChipID,e_ADS124S08_IDAC_CHANNEL Channel, e_ADS124S08_IDAC_OUTPUT Output)
{
	if(ChipID <ADS124S08_MAX_NUM_CHIPS)
	{
		if(InitStates[ChipID] == ADS124S08_INITIALIZED)
		{
			uint8_t tempReg = 0;

			if(ADS124S08_Read_Register(ChipID, REG_ADS124S08_EXCITATION_CURRENT_2, 1, &tempReg) == ADS124S08_OK)
			{
				switch(Channel)
				{
				case ADS124S08_IDAC_CHANNEL_1:
				{
					tempReg = tempReg & ADS124S08_IDAC_1_OUTPUT_CLEAR_MASK;
					tempReg = tempReg | Output << ADS124S08_IDAC_1_OUTPUT_BASE_SHIFT;
					break;
				}
				case ADS124S08_IDAC_CHANNEL_2:
				{
					tempReg = tempReg & ADS124S08_IDAC_2_OUTPUT_CLEAR_MASK;
					tempReg = tempReg | Output << ADS124S08_IDAC_2_OUTPUT_BASE_SHIFT;
					break;
				}
				default:
				{
					return ADS124S08_ERROR;
				}
				}

				if(ADS124S08_Write_Register(ChipID, REG_ADS124S08_EXCITATION_CURRENT_2, 1, &tempReg) == ADS124S08_OK)
				{
					return ADS124S08_OK;
				}
				else
				{
					return ADS124S08_ERROR;
				}
			}
			else
			{
				return ADS124S08_ERROR;
			}
		}
		else
		{
			return ADS124S08_ERROR;
		}
	}
	else
	{
		return ADS124S08_ERROR;
	}
}
e_ADS124S08_State ADS124S08_SYSTEM_CONTROL(e_ADS124S08_ChipID ChipID,e_ADS124S08_SEND_STAT SendStat,e_ADS124S08_SEND_CRC SendCRC, e_ADS124S08_ENABLE_SPI_TIMEOUT SpiTimeout,e_ADS124S08_CAL_SAMPLES CalSamples)
{
	if(ChipID < ADS124S08_MAX_NUM_CHIPS)
	{
		uint8_t tempReg = 0;
		if(ADS124S08_Read_Register(ChipID, REG_ADS124S08_SYSTEM_CONTROL, 1, &tempReg) == ADS124S08_OK)
		{
			if(SendStat == ADS124S08_SEND_STAT_ENABLED)
			{
				SendStatEnabled[ChipID] = ADS124S08_SEND_STAT_ENABLED;
				tempReg = tempReg & ADS124S08_ENABLE_SEND_STAT_CLEAR_MASK;
				tempReg = tempReg | ADS124S08_SEND_STAT_ENABLED << ADS124S08_ENABLE_SEND_STAT_BASE_SHIFT;
			}
			else if(SendStat == ADS124S08_SEND_STAT_DISABLED)
			{
				SendStatEnabled[ChipID] = ADS124S08_SEND_STAT_DISABLED;
				tempReg = tempReg & ADS124S08_ENABLE_SEND_STAT_CLEAR_MASK;
				tempReg = tempReg | ADS124S08_SEND_STAT_DISABLED << ADS124S08_ENABLE_SEND_STAT_BASE_SHIFT;
			}
			else
			{
				return ADS124S08_ERROR;
			}

			if(SendCRC == ADS124S08_SEND_CRC_ENABLED)
			{
				SendCRCEnabled[ChipID] = ADS124S08_SEND_CRC_ENABLED;
				tempReg = tempReg & ADS124S08_ENABLE_CRC_CLEAR_MASK;
				tempReg = tempReg | ADS124S08_SEND_CRC_ENABLED << ADS124S08_ENABLE_CRC_BASE_SHIFT;
			}
			else if(SendCRC == ADS124S08_SEND_CRC_DISABLED)
			{
				SendCRCEnabled[ChipID] = ADS124S08_SEND_CRC_DISABLED;
				tempReg = tempReg & ADS124S08_ENABLE_CRC_CLEAR_MASK;
				tempReg = tempReg | ADS124S08_SEND_CRC_DISABLED << ADS124S08_ENABLE_CRC_BASE_SHIFT;
			}
			else
			{
				return ADS124S08_ERROR;
			}

			if(SpiTimeout == ADS124S08_SPI_TIMEOUT_ENABLED)
			{
				tempReg = tempReg & ADS124S08_SPI_TIMEOUT_ENABLE_CLEAR_MASK;
				tempReg = tempReg | ADS124S08_SPI_TIMEOUT_ENABLED << ADS124S08_SPI_TIMEOUT_ENABLE_BASE_SHIFT;
			}
			else if(SpiTimeout == ADS124S08_SPI_TIMEOUT_DISABLED)
			{
				tempReg = tempReg & ADS124S08_SPI_TIMEOUT_ENABLE_CLEAR_MASK;
				tempReg = tempReg | ADS124S08_SPI_TIMEOUT_DISABLED << ADS124S08_SPI_TIMEOUT_ENABLE_BASE_SHIFT;
			}
			else
			{
				return ADS124S08_ERROR;
			}

			if(ADS124S08_Write_Register(ChipID, REG_ADS124S08_SYSTEM_CONTROL, 1, &tempReg) == ADS124S08_OK)
			{
				return ADS124S08_OK;
			}
			else
			{
				return ADS124S08_ERROR;
			}
		}
		else
		{
			return ADS124S08_ERROR;
		}
	}
	else
	{
		return ADS124S08_ERROR;
	}
}

e_ADS124S08_State ADS124S08_INIT(e_ADS124S08_ChipID ChipID)
{
	if(ChipID < ADS124S08_MAX_NUM_CHIPS)
	{
		if(ADS124S08_RESET(ChipID) != ADS124S08_OK)
		{
			return ADS124S08_ERROR;
		}
		if(ADS124S08_SET_DATA_RATE(ChipID, ADS124S08_DATA_RATE_2_5SPS) != ADS124S08_OK)
		{
			return ADS124S08_ERROR;
		}
		if(ADS124S08_SET_FILTER_MODE(ChipID, ADS124S08_FILTER_MODE_SINC3) != ADS124S08_OK)
		{
			return ADS124S08_ERROR;
		}
		if(ADS124S08_SET_CONV_MODE(ChipID, ADS124S08_CONV_MODE_CONTINOUS) != ADS124S08_OK)
		{
			return ADS124S08_ERROR;
		}
		if(ADS124S08_SET_CLOCK_MODE(ChipID, ADS124S08_CLOCK_MODE_INTERNAL) != ADS124S08_OK)
		{
			return ADS124S08_ERROR;
		}
		if(ADS124S08_SET_CHOP_MODE(ChipID, ADS124S08_GLOBAL_CHOP_MODE_DISABLED) != ADS124S08_OK)
		{
			return ADS124S08_ERROR;
		}
		if(ADS124S08_SET_REFERENCE_SETTINGS(ChipID, ADS124S08_INTERNAL_REFERENCE_ALWAYS_ON, ADS124S08_REFERENCE_IN_REFP0_REFN0, ADS124S08_REFN_BUFFER_NOT_BYPASSED, ADS124S08_REFP_BUFFER_NOT_BYPASSED, ADS124S08_REFERENCE_MONITOR_DISABLED) != ADS124S08_OK)
		{
			return ADS124S08_ERROR;
		}
		if(ADS124S08_SET_PGA_SETTINGS(ChipID, ADS124S08_PROG_CONV_DELAY_14_x_tMOD, ADS124S08_PGA_ENABLED, ADS124S08_GAIN_1) != ADS124S08_OK)
		{
			return ADS124S08_ERROR;
		}
		InitStates[ChipID] = ADS124S08_INITIALIZED;

		return ADS124S08_OK;

	}
	else
	{
		return ADS124S08_ERROR;
	}
}

e_ADS124S08_State ADS124S08_START_CONVERSION(e_ADS124S08_ChipID ChipID)
{
	if(ChipID < ADS124S08_MAX_NUM_CHIPS)
	{
		if(InitStates[ChipID] == ADS124S08_INITIALIZED)
		{
			if(ADS124S08_PORT_SEND_COMMAND(ChipID, ADS124S08_START_CONVERSION_COMMAND) == ADS124S08_OK)
			{
				return ADS124S08_OK;
			}
			else
			{
				return ADS124S08_ERROR;
			}
		}
		else
		{
			return ADS124S08_ERROR;
		}
	}
	else
	{
		return ADS124S08_ERROR;
	}
}
e_ADS124S08_State ADS124S08_STOP_CONVERSION(e_ADS124S08_ChipID ChipID)
{
	if(ChipID < ADS124S08_MAX_NUM_CHIPS)
	{
		if(InitStates[ChipID] == ADS124S08_INITIALIZED)
		{
			if(ADS124S08_PORT_SEND_COMMAND(ChipID, ADS124S08_STOP_CONVERSION_COMMAND) == ADS124S08_OK)
			{
				return ADS124S08_OK;
			}
			else
			{
				return ADS124S08_ERROR;
			}
		}
		else
		{
			return ADS124S08_ERROR;
		}
	}
	else
	{
		return ADS124S08_ERROR;
	}
}
e_ADS124S08_State ADS124S08_RESET(e_ADS124S08_ChipID ChipID)
{
	if(ChipID < ADS124S08_MAX_NUM_CHIPS)
	{
		if(ADS124S08_PORT_SEND_COMMAND(ChipID, ADS124S08_RESET_COMMAND) == ADS124S08_OK)
		{
			uint8_t tempStatus = 0;
			uint8_t returnStatus = 0;
			uint8_t Wait_Counter = 0;

			do
			{
				Wait_Counter++;
				if(ADS124S08_Read_Register(ChipID, REG_ADS124S08_DEVICE_STATUS, 1, &tempStatus) == ADS124S08_OK)
				{
					returnStatus = 0;
				}
				else
				{
					returnStatus = 1;
					break;
				}

				if(Wait_Counter > 200)
				{
					returnStatus = 1;
					break;
				}
			}while ((tempStatus & (0x01<< ADS124S08_FLAG_NOT_RDY)) != 0);

			if(returnStatus == 0)
			{
				InitStates[ChipID] = ADS124S08_INITIALIZED;
				return ADS124S08_OK;
			}
			else
			{
				return ADS124S08_ERROR;
			}
		}
		else
		{
			return ADS124S08_ERROR;
		}
	}
	else
	{
		return ADS124S08_ERROR;
	}
}

e_ADS124S08_State ADS124S08_PERFORM_SFOCAL(e_ADS124S08_ChipID ChipID)
{
	if(ChipID < ADS124S08_MAX_NUM_CHIPS)
		{
			if(InitStates[ChipID] == ADS124S08_INITIALIZED)
			{
				if(ADS124S08_PORT_SEND_COMMAND(ChipID, ADS124S08_SFOCAL_COMMAND) == ADS124S08_OK)
				{
					return ADS124S08_OK;
				}
				else
				{
					return ADS124S08_ERROR;
				}
			}
			else
			{
				return ADS124S08_ERROR;
			}
		}
		else
		{
			return ADS124S08_ERROR;
		}
}

e_ADS124S08_State ADS124S08_PERFORM_SYOCAL(e_ADS124S08_ChipID ChipID)
{
	if(ChipID < ADS124S08_MAX_NUM_CHIPS)
		{
			if(InitStates[ChipID] == ADS124S08_INITIALIZED)
			{
				if(ADS124S08_PORT_SEND_COMMAND(ChipID, ADS124S08_SYOCAL_COMMAND) == ADS124S08_OK)
				{
					return ADS124S08_OK;
				}
				else
				{
					return ADS124S08_ERROR;
				}
			}
			else
			{
				return ADS124S08_ERROR;
			}
		}
		else
		{
			return ADS124S08_ERROR;
		}
}

