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ADS124S08 Bibliothek hinzugefügt, erste möglichkeit wie auswertung funktionieren könnte hinzugefügt, sollte aber noch weniger blockierend gemacht werden

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raphael stade
2026-01-09 23:00:37 +01:00
parent 3f9dd014de
commit c7e27f2219
134 changed files with 197450 additions and 0 deletions
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4426
Software/Station_SW/Drivers/STM32U3xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h Normal file
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Software/Station_SW/Drivers/STM32U3xx_HAL_Driver/Inc/stm32u3xx_hal.h Normal file
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/**
******************************************************************************
* @file stm32u3xx_hal.h
* @author MCD Application Team
* @brief This file contains all the functions prototypes for the HAL
* module driver.
******************************************************************************
* @attention
*
* Copyright (c) 2023 STMicroelectronics.
* All rights reserved.
*
* This software is licensed under terms that can be found in the LICENSE file
* in the root directory of this software component.
* If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __STM32U3xx_HAL_H
#define __STM32U3xx_HAL_H
#ifdef __cplusplus
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include "stm32u3xx_hal_conf.h"
/** @addtogroup STM32U3xx_HAL_Driver
* @{
*/
/** @addtogroup HAL
* @{
*/
/* Exported types ------------------------------------------------------------*/
/** @defgroup HAL_Exported_Types HAL Exported Types
* @{
*/
/** @defgroup HAL_TICK_FREQ Tick Frequency
* @{
*/
typedef enum
{
HAL_TICK_FREQ_10HZ = 100U,
HAL_TICK_FREQ_100HZ = 10U,
HAL_TICK_FREQ_1KHZ = 1U,
HAL_TICK_FREQ_DEFAULT = HAL_TICK_FREQ_1KHZ
} HAL_TickFreqTypeDef;
/**
* @}
*/
/**
* @}
*/
/* Exported variables --------------------------------------------------------*/
/** @defgroup HAL_Exported_Variables HAL Exported Variables
* @{
*/
extern __IO uint32_t uwTick;
extern uint32_t uwTickPrio;
extern HAL_TickFreqTypeDef uwTickFreq;
/**
* @}
*/
/* Exported constants --------------------------------------------------------*/
/**
* @brief STM32U3xx HAL Driver version number
*/
#define __STM32U3xx_HAL_VERSION_MAIN (0x01U) /*!< [31:24] main version */
#define __STM32U3xx_HAL_VERSION_SUB1 (0x02U) /*!< [23:16] sub1 version */
#define __STM32U3xx_HAL_VERSION_SUB2 (0x00U) /*!< [15:8] sub2 version */
#define __STM32U3xx_HAL_VERSION_RC (0x00U) /*!< [7:0] release candidate */
#define __STM32U3xx_HAL_VERSION ((__STM32U3xx_HAL_VERSION_MAIN << 24U)\
|(__STM32U3xx_HAL_VERSION_SUB1 << 16U)\
|(__STM32U3xx_HAL_VERSION_SUB2 << 8U )\
|(__STM32U3xx_HAL_VERSION_RC))
/** @defgroup SYSCFG_Exported_Constants SYSCFG Exported Constants
* @{
*/
/** @defgroup SYSCFG_FPU_Interrupts FPU Interrupts
* @{
*/
#define SYSCFG_IT_FPU_IOC SYSCFG_FPUIMR_FPU_IOIE /*!< Floating Point Unit Invalid operation Interrupt */
#define SYSCFG_IT_FPU_DZC SYSCFG_FPUIMR_FPU_DZIE /*!< Floating Point Unit Divide-by-zero Interrupt */
#define SYSCFG_IT_FPU_UFC SYSCFG_FPUIMR_FPU_UFIE /*!< Floating Point Unit Underflow Interrupt */
#define SYSCFG_IT_FPU_OFC SYSCFG_FPUIMR_FPU_OFIE /*!< Floating Point Unit Overflow Interrupt */
#define SYSCFG_IT_FPU_IDC SYSCFG_FPUIMR_FPU_IDIE /*!< Floating Point Unit Input denormal Interrupt */
#define SYSCFG_IT_FPU_IXC SYSCFG_FPUIMR_FPU_IXIE /*!< Floating Point Unit Inexact Interrupt */
#define SYSCFG_IT_FPU_ALL (SYSCFG_IT_FPU_IOC| \
SYSCFG_IT_FPU_DZC| \
SYSCFG_IT_FPU_UFC| \
SYSCFG_IT_FPU_OFC| \
SYSCFG_IT_FPU_IDC| \
SYSCFG_IT_FPU_IXC) /*!< All */
/**
* @}
*/
/** @defgroup SYSCFG_Compensation_Cell_Selection Compensation Cell Selection
* @{
*/
#define SYSCFG_IO_VDD_CELL SYSCFG_CCCSR_EN1 /*!< Compensation cell for the I/O supplied by VDD */
#define SYSCFG_IO_VDDIO2_CELL SYSCFG_CCCSR_EN2 /*!< Compensation cell for the I/O supplied by VDDIO2 */
/**
* @}
*/
/** @defgroup SYSCFG_IO_Compensation_Code_Config IO Compensation Code config
* @{
*/
#define SYSCFG_IO_CELL_CODE 0U /*!< Code from the cell */
#define SYSCFG_IO_REGISTER_CODE 1U /*!< Code from the values in the cell code register */
/**
* @}
*/
/** @defgroup SYSCFG_HAL_EC_IR_MOD SYSCFG IR Modulation
* @{
*/
#define SYSCFG_IR_MOD_TIM16 0U /*!< TIM16 is selected as IR Modulation envelope source */
#define SYSCFG_IR_MOD_USART1 SYSCFG_CFGR1_IR_MOD_0 /*!< USART1 is selected as IR Modulation envelope source */
#define SYSCFG_IR_MOD_UART4 SYSCFG_CFGR1_IR_MOD_1 /*!< UART4 is selected as IR Modulation envelope source */
/**
* @}
*/
/** @defgroup SYSCFG_HAL_EC_IR_OUTPOL SYSCFG IR Output Polarity
* @{
*/
#define SYSCFG_IR_OUTPUTPOL_NONINVERTED 0U /*!< Output of IR (IROut) non-inverted */
#define SYSCFG_IR_OUTPUTPOL_INVERTED SYSCFG_CFGR1_IR_POL /*!< Output of IR (IROut) inverted */
/**
* @}
*/
/** @defgroup SYSCFG_VREFBUF_VoltageScale VREFBUF Voltage Scale
* @{
*/
#define SYSCFG_VREFBUF_VOLTAGE_SCALE0 ((uint32_t)0x00000000)
/*!< Voltage reference scale 0 (VREF_OUT1) */
#define SYSCFG_VREFBUF_VOLTAGE_SCALE1 VREFBUF_CSR_VRS_0
/*!< Voltage reference scale 1 (VREF_OUT2) */
#define SYSCFG_VREFBUF_VOLTAGE_SCALE2 VREFBUF_CSR_VRS_1
/*!< Voltage reference scale 2 (VREF_OUT3) */
#define SYSCFG_VREFBUF_VOLTAGE_SCALE3 (VREFBUF_CSR_VRS_0 | VREFBUF_CSR_VRS_1)
/*!< Voltage reference scale 3 (VREF_OUT4) */
/**
* @}
*/
/** @defgroup SYSCFG_VREFBUF_HighImpedance VREFBUF High Impedance
* @{
*/
#define SYSCFG_VREFBUF_HIGH_IMPEDANCE_DISABLE ((uint32_t)0x00000000) /*!< VREF_plus pin is internally connected to
Voltage reference buffer output */
#define SYSCFG_VREFBUF_HIGH_IMPEDANCE_ENABLE VREFBUF_CSR_HIZ /*!< VREF_plus pin is high impedance */
/**
* @}
*/
/** @defgroup SYSCFG_FastModePlus_GPIO Fast-mode Plus on GPIO
* @{
*/
/** @brief Fast-mode Plus driving capability on a specific GPIO
*/
#define SYSCFG_FASTMODEPLUS_PB6 SYSCFG_CFGR1_PB6_FMP /*!< Enable Fast-mode Plus on PB6 */
#define SYSCFG_FASTMODEPLUS_PB7 SYSCFG_CFGR1_PB7_FMP /*!< Enable Fast-mode Plus on PB7 */
#define SYSCFG_FASTMODEPLUS_PB8 SYSCFG_CFGR1_PB8_FMP /*!< Enable Fast-mode Plus on PB8 */
#define SYSCFG_FASTMODEPLUS_PB9 SYSCFG_CFGR1_PB9_FMP /*!< Enable Fast-mode Plus on PB9 */
#define SYSCFG_FASTMODEPLUS_ALL (SYSCFG_FASTMODEPLUS_PB6| \
SYSCFG_FASTMODEPLUS_PB7| \
SYSCFG_FASTMODEPLUS_PB8| \
SYSCFG_FASTMODEPLUS_PB9) /*!< All */
/**
* @}
*/
/** @defgroup SYSCFG_Lock_items SYSCFG Lock items
* @brief SYSCFG items to set lock on
* @{
*/
#define SYSCFG_MPU_NSEC SYSCFG_CNSLCKR_LOCKNSMPU
/*!< Non-secure MPU lock (privileged secure or non-secure only) */
#define SYSCFG_VTOR_NSEC SYSCFG_CNSLCKR_LOCKNSVTOR
/*!< Non-secure VTOR lock (privileged secure or non-secure only) */
#if defined (CPU_IN_SECURE_STATE)
#define SYSCFG_SAU (SYSCFG_CSLCKR_LOCKSAU << 16U)
/*!< SAU lock (privileged secure code only) */
#define SYSCFG_MPU_SEC (SYSCFG_CSLCKR_LOCKSMPU << 16U)
/*!< Secure MPU lock (privileged secure code only) */
#define SYSCFG_VTOR_AIRCR_SEC (SYSCFG_CSLCKR_LOCKSVTAIRCR << 16U)
/*!< VTOR_S and AIRCR lock (privileged secure code only) */
#define SYSCFG_LOCK_ALL (SYSCFG_MPU_NSEC|SYSCFG_VTOR_NSEC|SYSCFG_SAU|SYSCFG_MPU_SEC|SYSCFG_VTOR_AIRCR_SEC)
/*!< All */
#else
#define SYSCFG_LOCK_ALL (SYSCFG_MPU_NSEC|SYSCFG_VTOR_NSEC)
/*!< All (privileged secure or non-secure only) */
#endif /* CPU_IN_SECURE_STATE */
/**
* @}
*/
/** @defgroup SYSCFG_Attributes_items SYSCFG Attributes items
* @brief SYSCFG items to configure secure or non-secure attributes on
* @{
*/
#define SYSCFG_CLK SYSCFG_SECCFGR_SYSCFGSEC /*!< SYSCFG clock control */
#define SYSCFG_CLASSB SYSCFG_SECCFGR_CLASSBSEC /*!< Class B */
#define SYSCFG_FPU SYSCFG_SECCFGR_FPUSEC /*!< FPU */
#define SYSCFG_ALL (SYSCFG_CLK | SYSCFG_CLASSB | SYSCFG_FPU) /*!< All */
/**
* @}
*/
/** @defgroup SYSCFG_attributes SYSCFG attributes
* @brief SYSCFG secure or non-secure attributes
* @{
*/
#define SYSCFG_SEC 0x00000001U /*!< Secure attribute */
#define SYSCFG_NSEC 0x00000000U /*!< Non-secure attribute */
/**
* @}
*/
/**
* @}
*/
/* Exported macros -----------------------------------------------------------*/
/** @defgroup DBGMCU_Exported_Macros DBGMCU Exported Macros
* @{
*/
/** @brief Freeze/Unfreeze Peripherals in Debug mode
*/
#if defined(DBGMCU_APB1FZR1_DBG_TIM2_STOP)
#define __HAL_DBGMCU_FREEZE_TIM2() SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_TIM2_STOP)
#define __HAL_DBGMCU_UNFREEZE_TIM2() CLEAR_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_TIM2_STOP)
#endif /* DBGMCU_APB1FZR1_DBG_TIM2_STOP */
#if defined(DBGMCU_APB1FZR1_DBG_TIM3_STOP)
#define __HAL_DBGMCU_FREEZE_TIM3() SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_TIM3_STOP)
#define __HAL_DBGMCU_UNFREEZE_TIM3() CLEAR_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_TIM3_STOP)
#endif /* DBGMCU_APB1FZR1_DBG_TIM3_STOP */
#if defined(DBGMCU_APB1FZR1_DBG_TIM4_STOP)
#define __HAL_DBGMCU_FREEZE_TIM4() SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_TIM4_STOP)
#define __HAL_DBGMCU_UNFREEZE_TIM4() CLEAR_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_TIM4_STOP)
#endif /* DBGMCU_APB1FZR1_DBG_TIM4_STOP */
#if defined(DBGMCU_APB1FZR1_DBG_TIM6_STOP)
#define __HAL_DBGMCU_FREEZE_TIM6() SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_TIM6_STOP)
#define __HAL_DBGMCU_UNFREEZE_TIM6() CLEAR_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_TIM6_STOP)
#endif /* DBGMCU_APB1FZR1_DBG_TIM6_STOP */
#if defined(DBGMCU_APB1FZR1_DBG_TIM7_STOP)
#define __HAL_DBGMCU_FREEZE_TIM7() SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_TIM7_STOP)
#define __HAL_DBGMCU_UNFREEZE_TIM7() CLEAR_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_TIM7_STOP)
#endif /* DBGMCU_APB1FZR1_DBG_TIM7_STOP */
#if defined(DBGMCU_APB1FZR1_DBG_WWDG_STOP)
#define __HAL_DBGMCU_FREEZE_WWDG() SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_WWDG_STOP)
#define __HAL_DBGMCU_UNFREEZE_WWDG() CLEAR_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_WWDG_STOP)
#endif /* DBGMCU_APB1FZR1_DBG_WWDG_STOP */
#if defined(DBGMCU_APB1FZR1_DBG_IWDG_STOP)
#define __HAL_DBGMCU_FREEZE_IWDG() SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_IWDG_STOP)
#define __HAL_DBGMCU_UNFREEZE_IWDG() CLEAR_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_IWDG_STOP)
#endif /* DBGMCU_APB1FZR1_DBG_IWDG_STOP */
#if defined(DBGMCU_APB1FZR1_DBG_I2C1_STOP)
#define __HAL_DBGMCU_FREEZE_I2C1() SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_I2C1_STOP)
#define __HAL_DBGMCU_UNFREEZE_I2C1() CLEAR_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_I2C1_STOP)
#endif /* DBGMCU_APB1FZR1_DBG_I2C1_STOP */
#if defined(DBGMCU_APB1FZR1_DBG_I2C2_STOP)
#define __HAL_DBGMCU_FREEZE_I2C2() SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_I2C2_STOP)
#define __HAL_DBGMCU_UNFREEZE_I2C2() CLEAR_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_I2C2_STOP)
#endif /* DBGMCU_APB1FZR1_DBG_I2C2_STOP */
#if defined(DBGMCU_APB1FZR1_DBG_I3C1_STOP)
#define __HAL_DBGMCU_FREEZE_I3C1() SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_I3C1_STOP)
#define __HAL_DBGMCU_UNFREEZE_I3C1() CLEAR_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_I3C1_STOP)
#endif /* DBGMCU_APB1FZR1_DBG_I3C1_STOP */
#if defined(DBGMCU_APB1FZR1_DBG_RTC_STOP)
#define __HAL_DBGMCU_FREEZE_RTC() SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_RTC_STOP)
#define __HAL_DBGMCU_UNFREEZE_RTC() CLEAR_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_RTC_STOP)
#endif /* DBGMCU_APB1FZR1_DBG_RTC_STOP */
#if defined(DBGMCU_APB1FZR2_DBG_LPTIM2_STOP)
#define __HAL_DBGMCU_FREEZE_LPTIM2() SET_BIT(DBGMCU->APB1FZR2, DBGMCU_APB1FZR2_DBG_LPTIM2_STOP)
#define __HAL_DBGMCU_UNFREEZE_LPTIM2() CLEAR_BIT(DBGMCU->APB1FZR2, DBGMCU_APB1FZR2_DBG_LPTIM2_STOP)
#endif /* DBGMCU_APB1FZR2_DBG_LPTIM2_STOP */
#if defined(DBGMCU_APB2FZR_DBG_TIM1_STOP)
#define __HAL_DBGMCU_FREEZE_TIM1() SET_BIT(DBGMCU->APB2FZR, DBGMCU_APB2FZR_DBG_TIM1_STOP)
#define __HAL_DBGMCU_UNFREEZE_TIM1() CLEAR_BIT(DBGMCU->APB2FZR, DBGMCU_APB2FZR_DBG_TIM1_STOP)
#endif /* DBGMCU_APB2FZR_DBG_TIM1_STOP */
#if defined(DBGMCU_APB2FZR_DBG_TIM15_STOP)
#define __HAL_DBGMCU_FREEZE_TIM15() SET_BIT(DBGMCU->APB2FZR, DBGMCU_APB2FZR_DBG_TIM15_STOP)
#define __HAL_DBGMCU_UNFREEZE_TIM15() CLEAR_BIT(DBGMCU->APB2FZR, DBGMCU_APB2FZR_DBG_TIM15_STOP)
#endif /* DBGMCU_APB2FZR_DBG_TIM15_STOP */
#if defined(DBGMCU_APB2FZR_DBG_TIM16_STOP)
#define __HAL_DBGMCU_FREEZE_TIM16() SET_BIT(DBGMCU->APB2FZR, DBGMCU_APB2FZR_DBG_TIM16_STOP)
#define __HAL_DBGMCU_UNFREEZE_TIM16() CLEAR_BIT(DBGMCU->APB2FZR, DBGMCU_APB2FZR_DBG_TIM16_STOP)
#endif /* DBGMCU_APB2FZR_DBG_TIM16_STOP */
#if defined(DBGMCU_APB2FZR_DBG_TIM17_STOP)
#define __HAL_DBGMCU_FREEZE_TIM17() SET_BIT(DBGMCU->APB2FZR, DBGMCU_APB2FZR_DBG_TIM17_STOP)
#define __HAL_DBGMCU_UNFREEZE_TIM17() CLEAR_BIT(DBGMCU->APB2FZR, DBGMCU_APB2FZR_DBG_TIM17_STOP)
#endif /* DBGMCU_APB2FZR_DBG_TIM17_STOP */
#if defined(DBGMCU_APB2FZR_DBG_I3C2_STOP)
#define __HAL_DBGMCU_FREEZE_I3C2() SET_BIT(DBGMCU->APB2FZR, DBGMCU_APB2FZR_DBG_I3C2_STOP)
#define __HAL_DBGMCU_UNFREEZE_I3C2() CLEAR_BIT(DBGMCU->APB2FZR, DBGMCU_APB2FZR_DBG_I3C2_STOP)
#endif /* DBGMCU_APB2FZR_DBG_I3C2_STOP */
#if defined(DBGMCU_APB3FZR_DBG_I2C3_STOP)
#define __HAL_DBGMCU_FREEZE_I2C3() SET_BIT(DBGMCU->APB3FZR, DBGMCU_APB3FZR_DBG_I2C3_STOP)
#define __HAL_DBGMCU_UNFREEZE_I2C3() CLEAR_BIT(DBGMCU->APB3FZR, DBGMCU_APB3FZR_DBG_I2C3_STOP)
#endif /* DBGMCU_APB3FZR_DBG_I2C3_STOP */
#if defined(DBGMCU_APB3FZR_DBG_LPTIM1_STOP)
#define __HAL_DBGMCU_FREEZE_LPTIM1() SET_BIT(DBGMCU->APB3FZR, DBGMCU_APB3FZR_DBG_LPTIM1_STOP)
#define __HAL_DBGMCU_UNFREEZE_LPTIM1() CLEAR_BIT(DBGMCU->APB3FZR, DBGMCU_APB3FZR_DBG_LPTIM1_STOP)
#endif /* DBGMCU_APB3FZR_DBG_LPTIM1_STOP */
#if defined(DBGMCU_APB3FZR_DBG_LPTIM3_STOP)
#define __HAL_DBGMCU_FREEZE_LPTIM3() SET_BIT(DBGMCU->APB3FZR, DBGMCU_APB3FZR_DBG_LPTIM3_STOP)
#define __HAL_DBGMCU_UNFREEZE_LPTIM3() CLEAR_BIT(DBGMCU->APB3FZR, DBGMCU_APB3FZR_DBG_LPTIM3_STOP)
#endif /* DBGMCU_APB3FZR_DBG_LPTIM3_STOP */
#if defined(DBGMCU_APB3FZR_DBG_LPTIM4_STOP)
#define __HAL_DBGMCU_FREEZE_LPTIM4() SET_BIT(DBGMCU->APB3FZR, DBGMCU_APB3FZR_DBG_LPTIM4_STOP)
#define __HAL_DBGMCU_UNFREEZE_LPTIM4() CLEAR_BIT(DBGMCU->APB3FZR, DBGMCU_APB3FZR_DBG_LPTIM4_STOP)
#endif /* DBGMCU_APB3FZR_DBG_LPTIM4_STOP */
#if defined(DBGMCU_AHB1FZR_DBG_GPDMA0_STOP)
#define __HAL_DBGMCU_FREEZE_GPDMA0() SET_BIT(DBGMCU->AHB1FZR, DBGMCU_AHB1FZR_DBG_GPDMA0_STOP)
#define __HAL_DBGMCU_UNFREEZE_GPDMA0() CLEAR_BIT(DBGMCU->AHB1FZR, DBGMCU_AHB1FZR_DBG_GPDMA0_STOP)
#endif /* DBGMCU_AHB1FZR_DBG_GPDMA0_STOP */
#if defined(DBGMCU_AHB1FZR_DBG_GPDMA1_STOP)
#define __HAL_DBGMCU_FREEZE_GPDMA1() SET_BIT(DBGMCU->AHB1FZR, DBGMCU_AHB1FZR_DBG_GPDMA1_STOP)
#define __HAL_DBGMCU_UNFREEZE_GPDMA1() CLEAR_BIT(DBGMCU->AHB1FZR, DBGMCU_AHB1FZR_DBG_GPDMA1_STOP)
#endif /* DBGMCU_AHB1FZR_DBG_GPDMA1_STOP */
#if defined(DBGMCU_AHB1FZR_DBG_GPDMA2_STOP)
#define __HAL_DBGMCU_FREEZE_GPDMA2() SET_BIT(DBGMCU->AHB1FZR, DBGMCU_AHB1FZR_DBG_GPDMA2_STOP)
#define __HAL_DBGMCU_UNFREEZE_GPDMA2() CLEAR_BIT(DBGMCU->AHB1FZR, DBGMCU_AHB1FZR_DBG_GPDMA2_STOP)
#endif /* DBGMCU_AHB1FZR_DBG_GPDMA2_STOP */
#if defined(DBGMCU_AHB1FZR_DBG_GPDMA3_STOP)
#define __HAL_DBGMCU_FREEZE_GPDMA3() SET_BIT(DBGMCU->AHB1FZR, DBGMCU_AHB1FZR_DBG_GPDMA3_STOP)
#define __HAL_DBGMCU_UNFREEZE_GPDMA3() CLEAR_BIT(DBGMCU->AHB1FZR, DBGMCU_AHB1FZR_DBG_GPDMA3_STOP)
#endif /* DBGMCU_AHB1FZR_DBG_GPDMA3_STOP */
#if defined(DBGMCU_AHB1FZR_DBG_GPDMA4_STOP)
#define __HAL_DBGMCU_FREEZE_GPDMA4() SET_BIT(DBGMCU->AHB1FZR, DBGMCU_AHB1FZR_DBG_GPDMA4_STOP)
#define __HAL_DBGMCU_UNFREEZE_GPDMA4() CLEAR_BIT(DBGMCU->AHB1FZR, DBGMCU_AHB1FZR_DBG_GPDMA4_STOP)
#endif /* DBGMCU_AHB1FZR_DBG_GPDMA4_STOP */
#if defined(DBGMCU_AHB1FZR_DBG_GPDMA5_STOP)
#define __HAL_DBGMCU_FREEZE_GPDMA5() SET_BIT(DBGMCU->AHB1FZR, DBGMCU_AHB1FZR_DBG_GPDMA5_STOP)
#define __HAL_DBGMCU_UNFREEZE_GPDMA5() CLEAR_BIT(DBGMCU->AHB1FZR, DBGMCU_AHB1FZR_DBG_GPDMA5_STOP)
#endif /* DBGMCU_AHB1FZR_DBG_GPDMA5_STOP */
#if defined(DBGMCU_AHB1FZR_DBG_GPDMA6_STOP)
#define __HAL_DBGMCU_FREEZE_GPDMA6() SET_BIT(DBGMCU->AHB1FZR, DBGMCU_AHB1FZR_DBG_GPDMA6_STOP)
#define __HAL_DBGMCU_UNFREEZE_GPDMA6() CLEAR_BIT(DBGMCU->AHB1FZR, DBGMCU_AHB1FZR_DBG_GPDMA6_STOP)
#endif /* DBGMCU_AHB1FZR_DBG_GPDMA6_STOP */
#if defined(DBGMCU_AHB1FZR_DBG_GPDMA7_STOP)
#define __HAL_DBGMCU_FREEZE_GPDMA7() SET_BIT(DBGMCU->AHB1FZR, DBGMCU_AHB1FZR_DBG_GPDMA7_STOP)
#define __HAL_DBGMCU_UNFREEZE_GPDMA7() CLEAR_BIT(DBGMCU->AHB1FZR, DBGMCU_AHB1FZR_DBG_GPDMA7_STOP)
#endif /* DBGMCU_AHB1FZR_DBG_GPDMA7_STOP */
#if defined(DBGMCU_AHB1FZR_DBG_GPDMA8_STOP)
#define __HAL_DBGMCU_FREEZE_GPDMA8() SET_BIT(DBGMCU->AHB1FZR, DBGMCU_AHB1FZR_DBG_GPDMA8_STOP)
#define __HAL_DBGMCU_UNFREEZE_GPDMA8() CLEAR_BIT(DBGMCU->AHB1FZR, DBGMCU_AHB1FZR_DBG_GPDMA8_STOP)
#endif /* DBGMCU_AHB1FZR_DBG_GPDMA8_STOP */
#if defined(DBGMCU_AHB1FZR_DBG_GPDMA9_STOP)
#define __HAL_DBGMCU_FREEZE_GPDMA9() SET_BIT(DBGMCU->AHB1FZR, DBGMCU_AHB1FZR_DBG_GPDMA9_STOP)
#define __HAL_DBGMCU_UNFREEZE_GPDMA9() CLEAR_BIT(DBGMCU->AHB1FZR, DBGMCU_AHB1FZR_DBG_GPDMA9_STOP)
#endif /* DBGMCU_AHB1FZR_DBG_GPDMA9_STOP */
#if defined(DBGMCU_AHB1FZR_DBG_GPDMA10_STOP)
#define __HAL_DBGMCU_FREEZE_GPDMA10() SET_BIT(DBGMCU->AHB1FZR, DBGMCU_AHB1FZR_DBG_GPDMA10_STOP)
#define __HAL_DBGMCU_UNFREEZE_GPDMA10() CLEAR_BIT(DBGMCU->AHB1FZR, DBGMCU_AHB1FZR_DBG_GPDMA10_STOP)
#endif /* DBGMCU_AHB1FZR_DBG_GPDMA10_STOP */
#if defined(DBGMCU_AHB1FZR_DBG_GPDMA11_STOP)
#define __HAL_DBGMCU_FREEZE_GPDMA11() SET_BIT(DBGMCU->AHB1FZR, DBGMCU_AHB1FZR_DBG_GPDMA11_STOP)
#define __HAL_DBGMCU_UNFREEZE_GPDMA11() CLEAR_BIT(DBGMCU->AHB1FZR, DBGMCU_AHB1FZR_DBG_GPDMA11_STOP)
#endif /* DBGMCU_AHB1FZR_DBG_GPDMA11_STOP */
/**
* @}
*/
/** @defgroup SYSCFG_Exported_Macros SYSCFG Exported Macros
* @{
*/
/** @brief Floating Point Unit interrupt enable/disable macros
* @param __INTERRUPT__: This parameter can be a value of @ref SYSCFG_FPU_Interrupts
*/
#define __HAL_SYSCFG_FPU_INTERRUPT_ENABLE(__INTERRUPT__) do {assert_param(IS_SYSCFG_FPU_INTERRUPT((__INTERRUPT__)));\
SET_BIT(SYSCFG->FPUIMR, (__INTERRUPT__));\
}while(0)
#define __HAL_SYSCFG_FPU_INTERRUPT_DISABLE(__INTERRUPT__) do {assert_param(IS_SYSCFG_FPU_INTERRUPT((__INTERRUPT__)));\
CLEAR_BIT(SYSCFG->FPUIMR, (__INTERRUPT__));\
}while(0)
/** @brief SYSCFG Break ECC lock.
* Enable and lock the connection of Flash ECC double error connection to TIM1/15/16/17 Break input.
* @note The selected configuration is locked and can be unlocked only by system reset.
*/
#define __HAL_SYSCFG_BREAK_ECC_LOCK() SET_BIT(SYSCFG->CFGR2, SYSCFG_CFGR2_ECCL)
/** @brief SYSCFG Break Cortex-M33 Lockup lock.
* Enable and lock the connection of Cortex-M33 LOCKUP (Hardfault) output to TIM1/15/16/17 Break input.
* @note The selected configuration is locked and can be unlocked only by system reset.
*/
#define __HAL_SYSCFG_BREAK_LOCKUP_LOCK() SET_BIT(SYSCFG->CFGR2, SYSCFG_CFGR2_CLL)
/** @brief SYSCFG Break PVD lock.
* Enable and lock the PVD connection to Timer1/15/16/17 Break input, as well as the PVDE and PVDLS[2:0] in
* the PWR_SVMCR register.
* @note The selected configuration is locked and can be unlocked only by system reset.
*/
#define __HAL_SYSCFG_BREAK_PVD_LOCK() SET_BIT(SYSCFG->CFGR2, SYSCFG_CFGR2_PVDL)
/** @brief SYSCFG Break SRAM2 parity lock.
* Enable and lock the SRAM2 parity error signal connection to TIM1/15/16/17 Break input.
* @note The selected configuration is locked and can be unlocked by system reset.
*/
#define __HAL_SYSCFG_BREAK_SRAM2PARITY_LOCK() SET_BIT(SYSCFG->CFGR2, SYSCFG_CFGR2_SPL)
/** @brief Fast-mode Plus driving capability enable/disable macros
* @param __FASTMODEPLUS__: This parameter can be a value of :
* @arg @ref SYSCFG_FASTMODEPLUS_PB6 Fast-mode Plus driving capability activation on PB6
* @arg @ref SYSCFG_FASTMODEPLUS_PB7 Fast-mode Plus driving capability activation on PB7
* @arg @ref SYSCFG_FASTMODEPLUS_PB8 Fast-mode Plus driving capability activation on PB8
* @arg @ref SYSCFG_FASTMODEPLUS_PB9 Fast-mode Plus driving capability activation on PB9
*/
#define __HAL_SYSCFG_FASTMODEPLUS_ENABLE(__FASTMODEPLUS__) \
do {assert_param(IS_SYSCFG_FASTMODEPLUS((__FASTMODEPLUS__)));\
SET_BIT(SYSCFG->CFGR1, (__FASTMODEPLUS__));\
}while(0)
#define __HAL_SYSCFG_FASTMODEPLUS_DISABLE(__FASTMODEPLUS__) \
do {assert_param(IS_SYSCFG_FASTMODEPLUS((__FASTMODEPLUS__)));\
CLEAR_BIT(SYSCFG->CFGR1, (__FASTMODEPLUS__));\
}while(0)
/**
* @}
*/
/* Private macros ------------------------------------------------------------*/
/** @defgroup SYSCFG_Private_Macros SYSCFG Private Macros
* @{
*/
#define IS_SYSCFG_IR_MODULATION(__MODULATION__) (((__MODULATION__) == SYSCFG_IR_MOD_TIM16) || \
((__MODULATION__) == SYSCFG_IR_MOD_USART1) || \
((__MODULATION__) == SYSCFG_IR_MOD_UART4))
#define IS_SYSCFG_IR_OUTPUTPOL(__OUTPUTPOL__) (((__OUTPUTPOL__) == SYSCFG_IR_OUTPUTPOL_NONINVERTED) || \
((__OUTPUTPOL__) == SYSCFG_IR_OUTPUTPOL_INVERTED))
#define IS_SYSCFG_IO_COMPENSATION_CODE(__VALUE__) (((__VALUE__) == SYSCFG_IO_CELL_CODE) || \
((__VALUE__) == SYSCFG_IO_REGISTER_CODE))
#define IS_SYSCFG_IO_COMPENSATION_CELL_PMOS_VALUE(__VALUE__) (((__VALUE__) < 16U))
#define IS_SYSCFG_IO_COMPENSATION_CELL_NMOS_VALUE(__VALUE__) (((__VALUE__) < 16U))
#define IS_SYSCFG_FPU_INTERRUPT(__INTERRUPT__) ((((__INTERRUPT__) & SYSCFG_IT_FPU_ALL) != 0x00U) && \
(((__INTERRUPT__) & ~SYSCFG_IT_FPU_ALL) == 0x00U))
#define IS_SYSCFG_VREFBUF_VOLTAGE_SCALE(__SCALE__) (((__SCALE__) == SYSCFG_VREFBUF_VOLTAGE_SCALE0) || \
((__SCALE__) == SYSCFG_VREFBUF_VOLTAGE_SCALE1) || \
((__SCALE__) == SYSCFG_VREFBUF_VOLTAGE_SCALE2) || \
((__SCALE__) == SYSCFG_VREFBUF_VOLTAGE_SCALE3))
#define IS_SYSCFG_VREFBUF_HIGH_IMPEDANCE(__VALUE__) (((__VALUE__) == SYSCFG_VREFBUF_HIGH_IMPEDANCE_DISABLE) || \
((__VALUE__) == SYSCFG_VREFBUF_HIGH_IMPEDANCE_ENABLE))
#define IS_SYSCFG_VREFBUF_TRIMMING(__VALUE__) (((__VALUE__) > 0U) && ((__VALUE__) <= VREFBUF_CCR_TRIM))
#define IS_SYSCFG_FASTMODEPLUS(__PIN__) ((((__PIN__) & SYSCFG_FASTMODEPLUS_ALL) != 0x00U) && \
(((__PIN__) & ~SYSCFG_FASTMODEPLUS_ALL) == 0x00U))
#define IS_SYSCFG_COMPENSATION_CELL(__CELL__) (((__CELL__) == SYSCFG_IO_VDD_CELL) || \
((__CELL__) == SYSCFG_IO_VDDIO2_CELL))
#if defined (CPU_IN_SECURE_STATE)
#define IS_SYSCFG_ATTRIBUTES(__ATTRIBUTES__) (((__ATTRIBUTES__) == SYSCFG_SEC) ||\
((__ATTRIBUTES__) == SYSCFG_NSEC))
#define IS_SYSCFG_ITEMS_ATTRIBUTES(__ITEM__) ((((__ITEM__) & SYSCFG_ALL) != 0x00U) && \
(((__ITEM__) & ~SYSCFG_ALL) == 0x00U))
#endif /* CPU_IN_SECURE_STATE */
#define IS_SYSCFG_SINGLE_ITEMS_ATTRIBUTES(__ITEM__) (((__ITEM__) == (SYSCFG_CLK)) || \
((__ITEM__) == (SYSCFG_CLASSB)) || \
((__ITEM__) == (SYSCFG_FPU)))
#define IS_SYSCFG_LOCK_ITEMS(__ITEM__) ((((__ITEM__) & SYSCFG_LOCK_ALL) != 0x00U) && \
(((__ITEM__) & ~SYSCFG_LOCK_ALL) == 0x00U))
/**
* @}
*/
/** @defgroup HAL_Private_Macros HAL Private Macros
* @{
*/
#define IS_TICKFREQ(FREQ) (((FREQ) == HAL_TICK_FREQ_10HZ) || \
((FREQ) == HAL_TICK_FREQ_100HZ) || \
((FREQ) == HAL_TICK_FREQ_1KHZ))
/**
* @}
*/
/* Exported functions --------------------------------------------------------*/
/** @addtogroup HAL_Exported_Functions
* @{
*/
/** @addtogroup HAL_Exported_Functions_Group1
* @{
*/
/* Initialization and de-initialization functions ******************************/
HAL_StatusTypeDef HAL_Init(void);
HAL_StatusTypeDef HAL_DeInit(void);
void HAL_MspInit(void);
void HAL_MspDeInit(void);
HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority);
/**
* @}
*/
/** @addtogroup HAL_Exported_Functions_Group2
* @{
*/
/* Peripheral Control functions ************************************************/
void HAL_IncTick(void);
void HAL_Delay(uint32_t Delay);
uint32_t HAL_GetTick(void);
uint32_t HAL_GetTickPrio(void);
HAL_StatusTypeDef HAL_SetTickFreq(HAL_TickFreqTypeDef Freq);
HAL_TickFreqTypeDef HAL_GetTickFreq(void);
void HAL_SuspendTick(void);
void HAL_ResumeTick(void);
uint32_t HAL_GetHalVersion(void);
uint32_t HAL_GetREVID(void);
uint32_t HAL_GetDEVID(void);
uint32_t HAL_GetUIDw0(void);
uint32_t HAL_GetUIDw1(void);
uint32_t HAL_GetUIDw2(void);
/**
* @}
*/
/** @addtogroup HAL_Exported_Functions_Group3
* @{
*/
/* DBGMCU Peripheral Control functions *****************************************/
void HAL_DBGMCU_EnableDBGStopMode(void);
void HAL_DBGMCU_DisableDBGStopMode(void);
void HAL_DBGMCU_EnableDBGStandbyMode(void);
void HAL_DBGMCU_DisableDBGStandbyMode(void);
/**
* @}
*/
/** @addtogroup HAL_Exported_Functions_Group4
* @{
*/
/* SYSCFG Control functions ****************************************************/
void HAL_SYSCFG_VREFBUF_VoltageScalingConfig(uint32_t VoltageScaling);
void HAL_SYSCFG_VREFBUF_HighImpedanceConfig(uint32_t Mode);
void HAL_SYSCFG_VREFBUF_TrimmingConfig(uint32_t TrimmingValue);
HAL_StatusTypeDef HAL_SYSCFG_EnableVREFBUF(void);
void HAL_SYSCFG_DisableVREFBUF(void);
void HAL_SYSCFG_EnableIOAnalogBooster(void);
void HAL_SYSCFG_DisableIOAnalogBooster(void);
void HAL_SYSCFG_EnableIOAnalogSwitchVdd(void);
void HAL_SYSCFG_DisableIOAnalogSwitchVdd(void);
void HAL_SYSCFG_EnableCompensationCell(uint32_t Selection);
void HAL_SYSCFG_DisableCompensationCell(uint32_t Selection);
uint32_t HAL_SYSCFG_GetCompensationCellReadyStatus(uint32_t Selection);
void HAL_SYSCFG_ConfigCompensationCell(uint32_t Selection,
uint32_t Code,
uint32_t NmosValue,
uint32_t PmosValue);
HAL_StatusTypeDef HAL_SYSCFG_GetCompensationCell(uint32_t Selection,
uint32_t *pCode,
uint32_t *pNmosValue,
uint32_t *pPmosValue);
void HAL_SYSCFG_ConfigIR(uint32_t Modulation, uint32_t OutputPol);
HAL_StatusTypeDef HAL_SYSCFG_GetConfigIR(uint32_t *pModulation, uint32_t *pOutputPol);
/**
* @}
*/
/** @addtogroup HAL_Exported_Functions_Group5
* @{
*/
/* SYSCFG Lock functions ********************************************/
void HAL_SYSCFG_Lock(uint32_t Item);
HAL_StatusTypeDef HAL_SYSCFG_GetLock(uint32_t *pItem);
/**
* @}
*/
/** @addtogroup HAL_Exported_Functions_Group6
* @{
*/
/* SYSCFG Attributes functions ********************************************/
#if defined (CPU_IN_SECURE_STATE)
void HAL_SYSCFG_ConfigAttributes(uint32_t Item, uint32_t Attributes);
#endif /* CPU_IN_SECURE_STATE */
HAL_StatusTypeDef HAL_SYSCFG_GetConfigAttributes(uint32_t Item, uint32_t *pAttributes);
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /* __STM32U3xx_HAL_H */

428
Software/Station_SW/Drivers/STM32U3xx_HAL_Driver/Inc/stm32u3xx_hal_cortex.h Normal file
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@@ -0,0 +1,428 @@
/**
******************************************************************************
* @file stm32u3xx_hal_cortex.h
* @author MCD Application Team
* @brief Header file of CORTEX HAL module.
******************************************************************************
* @attention
*
* Copyright (c) 2023 STMicroelectronics.
* All rights reserved.
*
* This software is licensed under terms that can be found in the LICENSE file
* in the root directory of this software component.
* If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef STM32U3xx_HAL_CORTEX_H
#define STM32U3xx_HAL_CORTEX_H
#ifdef __cplusplus
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include "stm32u3xx_hal_def.h"
/** @addtogroup STM32U3xx_HAL_Driver
* @{
*/
/** @defgroup CORTEX CORTEX
* @brief CORTEX HAL module driver
* @{
*/
/* Exported types ------------------------------------------------------------*/
/** @defgroup CORTEX_Exported_Types CORTEX Exported Types
* @{
*/
/** @defgroup CORTEX_MPU_Region_Initialization_Structure_definition MPU Region Initialization Structure Definition
* @brief MPU Region initialization structure
* @{
*/
typedef struct
{
uint8_t Enable; /*!< Specifies the status of the region.
This parameter can be a value of @ref CORTEX_MPU_Region_Enable */
uint8_t Number; /*!< Specifies the number of the region to protect.
This parameter can be a value of @ref CORTEX_MPU_Region_Number */
uint32_t BaseAddress; /*!< Specifies the base address of the region to protect. */
uint32_t LimitAddress; /*!< Specifies the limit address of the region to protect. */
uint8_t AttributesIndex; /*!< Specifies the memory attributes index.
This parameter can be a value of @ref CORTEX_MPU_Attributes_Number */
uint8_t AccessPermission; /*!< Specifies the region access permission type.
This parameter can be a value of @ref CORTEX_MPU_Region_Permission_Attributes */
uint8_t DisableExec; /*!< Specifies the instruction access status.
This parameter can be a value of @ref CORTEX_MPU_Instruction_Access */
uint8_t IsShareable; /*!< Specifies the shareability status of the protected region.
This parameter can be a value of @ref CORTEX_MPU_Access_Shareable */
} MPU_Region_InitTypeDef;
/**
* @}
*/
/** @defgroup CORTEX_MPU_Attributes_Initialization_Structure_definition \
MPU Attributes Initialization Structure Definition
* @{
*/
typedef struct
{
uint8_t Number; /*!< Specifies the number of the memory attributes to configure.
This parameter can be a value of @ref CORTEX_MPU_Attributes_Number */
uint8_t Attributes; /*!< Specifies the memory attributes vue.
This parameter must be a number between Min_Data = 0x0 and Max_Data = 0xFFFF */
} MPU_Attributes_InitTypeDef;
/**
* @}
*/
/**
* @}
*/
/* Exported constants --------------------------------------------------------*/
/** @defgroup CORTEX_Exported_Constants CORTEX Exported Constants
* @{
*/
/** @defgroup CORTEX_Preemption_Priority_Group CORTEX Preemption Priority Group
* @{
*/
#define NVIC_PRIORITYGROUP_0 7U /*!< 0 bit for pre-emption priority,
4 bits for subpriority */
#define NVIC_PRIORITYGROUP_1 6U /*!< 1 bit for pre-emption priority,
3 bits for subpriority */
#define NVIC_PRIORITYGROUP_2 5U /*!< 2 bits for pre-emption priority,
2 bits for subpriority */
#define NVIC_PRIORITYGROUP_3 4U /*!< 3 bits for pre-emption priority,
1 bit for subpriority */
#define NVIC_PRIORITYGROUP_4 3U /*!< 4 bits for pre-emption priority,
0 bit for subpriority */
/**
* @}
*/
/** @defgroup CORTEX_SysTick_clock_source CORTEX SysTick clock source
* @{
*/
#define SYSTICK_CLKSOURCE_HCLK_DIV8 0U /*!< AHB clock divided by 8 selected as SysTick clock source */
#define SYSTICK_CLKSOURCE_LSI 1U /*!< LSI clock selected as SysTick clock source */
#define SYSTICK_CLKSOURCE_LSE 2U /*!< LSE clock selected as SysTick clock source */
#define SYSTICK_CLKSOURCE_HCLK 4U /*!< AHB clock selected as SysTick clock source */
/**
* @}
*/
/** @defgroup CORTEX_MPU_HFNMI_PRIVDEF_Control CORTEX MPU HFNMI and PRIVILEGED Access control
* @{
*/
#define MPU_HFNMI_PRIVDEF_NONE 0U
#define MPU_HARDFAULT_NMI MPU_CTRL_HFNMIENA_Msk
#define MPU_PRIVILEGED_DEFAULT MPU_CTRL_PRIVDEFENA_Msk
#define MPU_HFNMI_PRIVDEF (MPU_CTRL_HFNMIENA_Msk | MPU_CTRL_PRIVDEFENA_Msk)
/**
* @}
*/
/** @defgroup CORTEX_MPU_Region_Enable CORTEX MPU Region Enable
* @{
*/
#define MPU_REGION_ENABLE 1U
#define MPU_REGION_DISABLE 0U
/**
* @}
*/
/** @defgroup CORTEX_MPU_Instruction_Access CORTEX MPU Instruction Access
* @{
*/
#define MPU_INSTRUCTION_ACCESS_ENABLE 0U
#define MPU_INSTRUCTION_ACCESS_DISABLE 1U
/**
* @}
*/
/** @defgroup CORTEX_MPU_Access_Shareable CORTEX MPU Instruction Access Shareable
* @{
*/
#define MPU_ACCESS_NOT_SHAREABLE 0U
#define MPU_ACCESS_OUTER_SHAREABLE 2U
#define MPU_ACCESS_INNER_SHAREABLE 3U
/**
* @}
*/
/** @defgroup CORTEX_MPU_Region_Permission_Attributes CORTEX MPU Region Permission Attributes
* @{
*/
#define MPU_REGION_PRIV_RW 0U
#define MPU_REGION_ALL_RW 1U
#define MPU_REGION_PRIV_RO 2U
#define MPU_REGION_ALL_RO 3U
/**
* @}
*/
/** @defgroup CORTEX_MPU_Region_Number CORTEX MPU Region Number
* @{
*/
/* STM32U3xx supports 12 secure and 8 non secure MPU regions. */
#define MPU_REGION_NUMBER0 0U
#define MPU_REGION_NUMBER1 1U
#define MPU_REGION_NUMBER2 2U
#define MPU_REGION_NUMBER3 3U
#define MPU_REGION_NUMBER4 4U
#define MPU_REGION_NUMBER5 5U
#define MPU_REGION_NUMBER6 6U
#define MPU_REGION_NUMBER7 7U
#if defined (CPU_IN_SECURE_STATE)
#define MPU_REGION_NUMBER8 8U
#define MPU_REGION_NUMBER9 9U
#define MPU_REGION_NUMBER10 10U
#define MPU_REGION_NUMBER11 11U
#endif /* defined (CPU_IN_SECURE_STATE) */
/**
* @}
*/
/** @defgroup CORTEX_MPU_Attributes_Number CORTEX MPU Memory Attributes Number
* @{
*/
#define MPU_ATTRIBUTES_NUMBER0 0U
#define MPU_ATTRIBUTES_NUMBER1 1U
#define MPU_ATTRIBUTES_NUMBER2 2U
#define MPU_ATTRIBUTES_NUMBER3 3U
#define MPU_ATTRIBUTES_NUMBER4 4U
#define MPU_ATTRIBUTES_NUMBER5 5U
#define MPU_ATTRIBUTES_NUMBER6 6U
#define MPU_ATTRIBUTES_NUMBER7 7U
/**
* @}
*/
/** @defgroup CORTEX_MPU_Attributes CORTEX MPU Attributes
* @{
*/
/* Device memory attributes */
#define MPU_DEVICE_NGNRNE 0x0U /* Device, noGather, noReorder, noEarly acknowledge. */
#define MPU_DEVICE_NGNRE 0x4U /* Device, noGather, noReorder, Early acknowledge. */
#define MPU_DEVICE_NGRE 0x8U /* Device, noGather, Reorder, Early acknowledge. */
#define MPU_DEVICE_GRE 0xCU /* Device, Gather, Reorder, Early acknowledge. */
/* Normal Memory attributes */
/* Note that these attributes need to be set for both inner AND outer attributes.
These defines should be used with the INNER_OUTER macro if they are the same for inner and outer. */
/* - Non-cacheable memory attribute*/
#define MPU_NOT_CACHEABLE 0x4U /* Normal memory, non-cacheable. */
/* - Cacheable memory attributes*/
#define MPU_WRITE_THROUGH 0x0U /* Normal memory, write-through. */
#define MPU_WRITE_BACK 0x4U /* Normal memory, write-back. */
#define MPU_TRANSIENT 0x0U /* Normal memory, transient. */
#define MPU_NON_TRANSIENT 0x8U /* Normal memory, non-transient. */
#define MPU_NO_ALLOCATE 0x0U /* Normal memory, no allocate. */
#define MPU_W_ALLOCATE 0x1U /* Normal memory, write allocate. */
#define MPU_R_ALLOCATE 0x2U /* Normal memory, read allocate. */
#define MPU_RW_ALLOCATE 0x3U /* Normal memory, read/write allocate. */
/**
* @}
*/
/**
* @}
*/
/* Exported macros -----------------------------------------------------------*/
/** @defgroup CORTEX_Exported_Macros CORTEX Exported Macros
* @{
*/
/** @defgroup CORTEX_MPU_Normal_Memory_Attributes CORTEX MPU Normal Memory Attributes
* @{
*/
/* __ATTR__ being a combination of MPU Normal memory attributes */
#define OUTER(__ATTR__) ((__ATTR__) << 4U)
#define INNER_OUTER(__ATTR__) ((__ATTR__) | ((__ATTR__) << 4U))
/**
* @}
*/
/**
* @}
*/
/* Exported functions --------------------------------------------------------*/
/** @defgroup CORTEX_Exported_Functions CORTEX Exported Functions
* @{
*/
/** @defgroup CORTEX_Exported_Functions_Group1 Initialization and Configuration functions
* @brief Initialization and Configuration functions
* @{
*/
/* Initialization and Configuration functions *****************************/
void HAL_NVIC_SetPriorityGrouping(uint32_t PriorityGroup);
void HAL_NVIC_SetPriority(IRQn_Type IRQn, uint32_t PreemptPriority, uint32_t SubPriority);
void HAL_NVIC_EnableIRQ(IRQn_Type IRQn);
void HAL_NVIC_DisableIRQ(IRQn_Type IRQn);
void HAL_NVIC_SystemReset(void);
uint32_t HAL_SYSTICK_Config(uint32_t TicksNumb);
/**
* @}
*/
/** @defgroup CORTEX_Exported_Functions_Group2 Peripheral Control functions
* @brief Cortex control functions
* @{
*/
/* Peripheral Control functions ***********************************************/
uint32_t HAL_NVIC_GetPriorityGrouping(void);
void HAL_NVIC_GetPriority(IRQn_Type IRQn, uint32_t PriorityGroup,
uint32_t *pPreemptPriority, uint32_t *pSubPriority);
uint32_t HAL_NVIC_GetPendingIRQ(IRQn_Type IRQn);
void HAL_NVIC_SetPendingIRQ(IRQn_Type IRQn);
void HAL_NVIC_ClearPendingIRQ(IRQn_Type IRQn);
uint32_t HAL_NVIC_GetActive(IRQn_Type IRQn);
void HAL_SYSTICK_CLKSourceConfig(uint32_t CLKSource);
uint32_t HAL_SYSTICK_GetCLKSourceConfig(void);
void HAL_SYSTICK_IRQHandler(void);
void HAL_SYSTICK_Callback(void);
void HAL_CORTEX_ClearEvent(void);
void HAL_MPU_Enable(uint32_t MPU_Control);
void HAL_MPU_Disable(void);
void HAL_MPU_EnableRegion(uint32_t RegionNumber);
void HAL_MPU_DisableRegion(uint32_t RegionNumber);
void HAL_MPU_ConfigRegion(const MPU_Region_InitTypeDef *pMPU_RegionInit);
void HAL_MPU_ConfigMemoryAttributes(const MPU_Attributes_InitTypeDef *pMPU_AttributesInit);
#if defined (CPU_IN_SECURE_STATE)
void HAL_MPU_Enable_NS(uint32_t MPU_Control);
void HAL_MPU_Disable_NS(void);
void HAL_MPU_EnableRegion_NS(uint32_t RegionNumber);
void HAL_MPU_DisableRegion_NS(uint32_t RegionNumber);
void HAL_MPU_ConfigRegion_NS(const MPU_Region_InitTypeDef *pMPU_RegionInit);
void HAL_MPU_ConfigMemoryAttributes_NS(const MPU_Attributes_InitTypeDef *pMPU_AttributesInit);
#endif /* defined (CPU_IN_SECURE_STATE) */
/**
* @}
*/
/**
* @}
*/
/* Private types -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private constants ---------------------------------------------------------*/
/* Private macros ------------------------------------------------------------*/
/** @defgroup CORTEX_Private_Macros CORTEX Private Macros
* @{
*/
#define IS_NVIC_PRIORITY_GROUP(__GROUP__) (((__GROUP__) == NVIC_PRIORITYGROUP_0) || \
((__GROUP__) == NVIC_PRIORITYGROUP_1) || \
((__GROUP__) == NVIC_PRIORITYGROUP_2) || \
((__GROUP__) == NVIC_PRIORITYGROUP_3) || \
((__GROUP__) == NVIC_PRIORITYGROUP_4))
#define IS_NVIC_PREEMPTION_PRIORITY(__PRIO__, __PRIOGRP__) (((__PRIO__) < (1uL << __NVIC_PRIO_BITS)) && \
((__PRIO__) < (0x1uL << (0x07u - __PRIOGRP__))))
#define IS_NVIC_SUB_PRIORITY(__PRIO__, __PRIOGRP__) \
((__PRIOGRP__ < (0x07u - __NVIC_PRIO_BITS)) ?\
((__PRIO__) < (1u)): \
((__PRIO__) < (0x1uL << (__PRIOGRP__ - (0x07u - __NVIC_PRIO_BITS)))))
#define IS_NVIC_DEVICE_IRQ(__IRQ__) ((__IRQ__) > SysTick_IRQn)
#define IS_NVIC_PRIO_INTERRUPT(__IT__) (((__IT__) > HardFault_IRQn) &&\
((__IT__) != DebugMonitor_IRQn) && ((__IT__) != SVCall_IRQn))
#define IS_SYSTICK_CLK_SOURCE(__SOURCE__) (((__SOURCE__) == SYSTICK_CLKSOURCE_LSI) || \
((__SOURCE__) == SYSTICK_CLKSOURCE_LSE) || \
((__SOURCE__) == SYSTICK_CLKSOURCE_HCLK)|| \
((__SOURCE__) == SYSTICK_CLKSOURCE_HCLK_DIV8))
#define IS_MPU_REGION_ENABLE(__STATE__) (((__STATE__) == MPU_REGION_ENABLE) || \
((__STATE__) == MPU_REGION_DISABLE))
#define IS_MPU_INSTRUCTION_ACCESS(__STATE__) (((__STATE__) == MPU_INSTRUCTION_ACCESS_ENABLE) || \
((__STATE__) == MPU_INSTRUCTION_ACCESS_DISABLE))
#define IS_MPU_ACCESS_SHAREABLE(__STATE__) (((__STATE__) == MPU_ACCESS_OUTER_SHAREABLE) || \
((__STATE__) == MPU_ACCESS_INNER_SHAREABLE) || \
((__STATE__) == MPU_ACCESS_NOT_SHAREABLE))
#define IS_MPU_REGION_PERMISSION_ATTRIBUTE(__TYPE__) (((__TYPE__) == MPU_REGION_PRIV_RW) || \
((__TYPE__) == MPU_REGION_ALL_RW) || \
((__TYPE__) == MPU_REGION_PRIV_RO) || \
((__TYPE__) == MPU_REGION_ALL_RO))
#if defined (CPU_IN_SECURE_STATE)
#define IS_MPU_REGION_NUMBER(__NUMBER__) (((__NUMBER__) == MPU_REGION_NUMBER0) || \
((__NUMBER__) == MPU_REGION_NUMBER1) || \
((__NUMBER__) == MPU_REGION_NUMBER2) || \
((__NUMBER__) == MPU_REGION_NUMBER3) || \
((__NUMBER__) == MPU_REGION_NUMBER4) || \
((__NUMBER__) == MPU_REGION_NUMBER5) || \
((__NUMBER__) == MPU_REGION_NUMBER6) || \
((__NUMBER__) == MPU_REGION_NUMBER7) || \
((__NUMBER__) == MPU_REGION_NUMBER8) || \
((__NUMBER__) == MPU_REGION_NUMBER9) || \
((__NUMBER__) == MPU_REGION_NUMBER10)|| \
((__NUMBER__) == MPU_REGION_NUMBER11))
#define IS_MPU_NS_REGION_NUMBER(__NUMBER__) (((__NUMBER__) == MPU_REGION_NUMBER0) || \
((__NUMBER__) == MPU_REGION_NUMBER1) || \
((__NUMBER__) == MPU_REGION_NUMBER2) || \
((__NUMBER__) == MPU_REGION_NUMBER3) || \
((__NUMBER__) == MPU_REGION_NUMBER4) || \
((__NUMBER__) == MPU_REGION_NUMBER5) || \
((__NUMBER__) == MPU_REGION_NUMBER6) || \
((__NUMBER__) == MPU_REGION_NUMBER7))
#else
#define IS_MPU_REGION_NUMBER(__NUMBER__) (((__NUMBER__) == MPU_REGION_NUMBER0) || \
((__NUMBER__) == MPU_REGION_NUMBER1) || \
((__NUMBER__) == MPU_REGION_NUMBER2) || \
((__NUMBER__) == MPU_REGION_NUMBER3) || \
((__NUMBER__) == MPU_REGION_NUMBER4) || \
((__NUMBER__) == MPU_REGION_NUMBER5) || \
((__NUMBER__) == MPU_REGION_NUMBER6) || \
((__NUMBER__) == MPU_REGION_NUMBER7))
#endif /* defined (CPU_IN_SECURE_STATE)*/
#define IS_MPU_ATTRIBUTES_NUMBER(__NUMBER__) (((__NUMBER__) == MPU_ATTRIBUTES_NUMBER0) || \
((__NUMBER__) == MPU_ATTRIBUTES_NUMBER1) || \
((__NUMBER__) == MPU_ATTRIBUTES_NUMBER2) || \
((__NUMBER__) == MPU_ATTRIBUTES_NUMBER3) || \
((__NUMBER__) == MPU_ATTRIBUTES_NUMBER4) || \
((__NUMBER__) == MPU_ATTRIBUTES_NUMBER5) || \
((__NUMBER__) == MPU_ATTRIBUTES_NUMBER6) || \
((__NUMBER__) == MPU_ATTRIBUTES_NUMBER7))
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /* STM32U3xx_HAL_CORTEX_H */

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/**
******************************************************************************
* @file stm32u3xx_hal_def.h
* @author MCD Application Team
* @brief This file contains HAL common defines, enumeration, macros and
* structures definitions.
******************************************************************************
* @attention
*
* Copyright (c) 2023 STMicroelectronics.
* All rights reserved.
*
* This software is licensed under terms that can be found in the LICENSE file
* in the root directory of this software component.
* If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __STM32U3xx_HAL_DEF
#define __STM32U3xx_HAL_DEF
#ifdef __cplusplus
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include "stm32u3xx.h"
#include "Legacy/stm32_hal_legacy.h" /* Aliases file for old names compatibility */
#include <stddef.h>
#include <math.h>
/* To keep after #include "stm32u3xx.h" to have CPU_IN_SECURE_STATE available */
#if defined (CPU_IN_SECURE_STATE)
#include <arm_cmse.h>
#endif /* CPU_IN_SECURE_STATE */
/* Exported types ------------------------------------------------------------*/
/**
* @brief HAL Status structures definition
*/
typedef enum
{
HAL_OK = 0x00,
HAL_ERROR = 0x01,
HAL_BUSY = 0x02,
HAL_TIMEOUT = 0x03
} HAL_StatusTypeDef;
/**
* @brief HAL Lock structures definition
*/
typedef enum
{
HAL_UNLOCKED = 0x00,
HAL_LOCKED = 0x01
} HAL_LockTypeDef;
/* Exported macros -----------------------------------------------------------*/
#define HAL_MAX_DELAY 0xFFFFFFFFU
#define HAL_IS_BIT_SET(REG, BIT) (((REG) & (BIT)) == (BIT))
#define HAL_IS_BIT_CLR(REG, BIT) (((REG) & (BIT)) == 0U)
#define __HAL_LINKDMA(__HANDLE__, __PPP_DMA_FIELD__, __DMA_HANDLE__) \
do{ \
(__HANDLE__)->__PPP_DMA_FIELD__ = &(__DMA_HANDLE__); \
(__DMA_HANDLE__).Parent = (__HANDLE__); \
} while(0)
#if !defined(UNUSED)
#define UNUSED(X) ((void)X) /* To avoid gcc/g++ warnings */
#endif /* UNUSED */
/** @brief Reset the Handle's State field.
* @param __HANDLE__: specifies the Peripheral Handle.
* @note This macro can be used for the following purpose:
* - When the Handle is declared as local variable; before passing it as parameter
* to HAL_PPP_Init() for the first time, it is mandatory to use this macro
* to set to 0 the Handle's "State" field.
* Otherwise, "State" field may have any random value and the first time the function
* HAL_PPP_Init() is called, the low level hardware initialization will be missed
* (i.e. HAL_PPP_MspInit() will not be executed).
* - When there is a need to reconfigure the low level hardware: instead of calling
* HAL_PPP_DeInit() then HAL_PPP_Init(), user can make a call to this macro then HAL_PPP_Init().
* In this later function, when the Handle's "State" field is set to 0, it will execute the function
* HAL_PPP_MspInit() which will reconfigure the low level hardware.
* @retval None
*/
#define __HAL_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = 0)
#if (USE_RTOS == 1)
/* Reserved for future use */
#error " USE_RTOS should be 0 in the current HAL release "
#else
#define __HAL_LOCK(__HANDLE__) \
do{ \
if((__HANDLE__)->Lock == HAL_LOCKED) \
{ \
return HAL_BUSY; \
} \
else \
{ \
(__HANDLE__)->Lock = HAL_LOCKED; \
} \
}while (0)
#define __HAL_UNLOCK(__HANDLE__) \
do{ \
(__HANDLE__)->Lock = HAL_UNLOCKED; \
}while (0)
#endif /* USE_RTOS */
#if defined ( __GNUC__ )
#ifndef __weak
#define __weak __attribute__((weak))
#endif /* __weak */
#ifndef __packed
#define __packed __attribute__((__packed__))
#endif /* __packed */
#endif /* __GNUC__ */
#if defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
#ifndef __weak
#define __weak __attribute__((weak))
#endif /* __weak */
#ifndef __packed
#define __packed __attribute__((packed))
#endif /* __packed */
#endif /* __ARMCC_VERSION */
/* Macro to get buffer 32-bytes aligned (aligned to cache line width) */
#define ALIGN_32BYTES(buf) buf __attribute__((aligned(32)))
/* Legacy macros to get variable 4-bytes aligned */
#ifndef __ALIGN_BEGIN
#define __ALIGN_BEGIN
#endif /* __ALIGN_BEGIN */
#ifndef __ALIGN_END
#define __ALIGN_END __attribute__((aligned(4)))
#endif /* __ALIGN_END */
/**
* @brief __RAM_FUNC definition
*/
#if defined ( __CC_ARM ) || ((__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050))
/* ARM Compiler
------------
RAM functions are defined using the toolchain options.
Functions that are executed in RAM should reside in a separate source module.
Using the 'Options for File' dialog you can simply change the 'Code / Const'
area of a module to a memory space in physical RAM.
Available memory areas are declared in the 'Target' tab of the 'Options for Target'
dialog.
*/
#define __RAM_FUNC HAL_StatusTypeDef
#elif defined ( __ICCARM__ )
/* ICCARM Compiler
---------------
RAM functions are defined using a specific toolchain keyword "__ramfunc".
*/
#define __RAM_FUNC __ramfunc HAL_StatusTypeDef
#elif defined ( __GNUC__ )
/* GNU Compiler
------------
RAM functions are defined using a specific toolchain attribute
"__attribute__((section(".RamFunc")))".
*/
#define __RAM_FUNC HAL_StatusTypeDef __attribute__((section(".RamFunc")))
#endif /* __RAM_FUNC */
/**
* @brief __NOINLINE definition
*/
#if defined ( __CC_ARM ) || ((__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)) || defined ( __GNUC__ )
/* ARM & GNUCompiler
----------------
*/
#define __NOINLINE __attribute__ ( (noinline) )
#elif defined ( __ICCARM__ )
/* ICCARM Compiler
---------------
*/
#define __NOINLINE _Pragma("optimize = no_inline")
#endif /* __NOINLINE */
#ifdef __cplusplus
}
#endif
#endif /* ___STM32U3xx_HAL_DEF */

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/**
**********************************************************************************************************************
* @file stm32u3xx_hal_dma.h
* @author MCD Application Team
* @brief Header file of DMA HAL module.
**********************************************************************************************************************
* @attention
*
* Copyright (c) 2023 STMicroelectronics.
* All rights reserved.
*
* This software is licensed under terms that can be found in the LICENSE file
* in the root directory of this software component.
* If no LICENSE file comes with this software, it is provided AS-IS.
*
**********************************************************************************************************************
*/
/* Define to prevent recursive inclusion -----------------------------------------------------------------------------*/
#ifndef STM32U3xx_HAL_DMA_H
#define STM32U3xx_HAL_DMA_H
#ifdef __cplusplus
extern "C" {
#endif
/* Includes ----------------------------------------------------------------------------------------------------------*/
#include "stm32u3xx_hal_def.h"
/** @addtogroup STM32U3xx_HAL_Driver
* @{
*/
/** @addtogroup DMA
* @{
*/
/* Exported types ----------------------------------------------------------------------------------------------------*/
/** @defgroup DMA_Exported_Types DMA Exported Types
* @brief DMA Exported Types
* @{
*/
/**
* @brief DMA Transfer Configuration Structure definition.
*/
typedef struct
{
uint32_t Request; /*!< Specifies the DMA channel request.
This parameter can be a value of @ref DMA_Request_Selection */
uint32_t BlkHWRequest; /*!< Specifies the Block hardware request mode for DMA channel.
Block Hardware request feature can be used only with dedicated peripherals.
This parameter can be a value of @ref DMA_Block_Request */
uint32_t Direction; /*!< Specifies the transfer direction for DMA channel.
This parameter can be a value of @ref DMA_Transfer_Direction */
uint32_t SrcInc; /*!< Specifies the source increment mode for the DMA channel.
This parameter can be a value of @ref DMA_Source_Increment_Mode */
uint32_t DestInc; /*!< Specifies the destination increment mode for the DMA channel.
This parameter can be a value of @ref DMA_Destination_Increment_Mode */
uint32_t SrcDataWidth; /*!< Specifies the source data width for the DMA channel.
This parameter can be a value of @ref DMA_Source_Data_Width */
uint32_t DestDataWidth; /*!< Specifies the destination data width for the DMA channel.
This parameter can be a value of @ref DMA_Destination_Data_Width */
uint32_t Priority; /*!< Specifies the priority level for the DMA channel.
This parameter can be a value of @ref DMA_Priority_Level */
uint32_t SrcBurstLength; /*!< Specifies the source burst length (number of beats within a burst) for the DMA
channel.
This parameter can be a value between 1 and 64 */
uint32_t DestBurstLength; /*!< Specifies the destination burst length (number of beats within a burst) for the
DMA channel.
This parameter can be a value between 1 and 64 */
uint32_t TransferAllocatedPort; /*!< Specifies the transfer allocated ports.
This parameter can be a combination of @ref DMA_Transfer_Allocated_Port */
uint32_t TransferEventMode; /*!< Specifies the transfer event mode for the DMA channel.
This parameter can be a value of @ref DMA_Transfer_Event_Mode */
uint32_t Mode; /*!< Specifies the transfer mode for the DMA channel.
This parameter can be a value of @ref DMA_Transfer_Mode */
} DMA_InitTypeDef;
/**
* @brief DMA Linked-List Configuration Structure Definition.
*/
typedef struct
{
uint32_t Priority; /*!< Specifies the priority level for the DMA channel.
This parameter can be a value of @ref DMA_Priority_Level */
uint32_t LinkStepMode; /*!< Specifies the link step mode for the DMA channel.
This parameter can be a value of @ref DMAEx_Link_Step_Mode */
uint32_t LinkAllocatedPort; /*!< Specifies the linked-list allocated port for the DMA channel.
This parameter can be a value of @ref DMAEx_Link_Allocated_Port */
uint32_t TransferEventMode; /*!< Specifies the transfer event mode for the DMA channel.
This parameter can be a value of @ref DMA_Transfer_Event_Mode */
uint32_t LinkedListMode; /*!< Specifies linked-list transfer mode for the DMA channel.
This parameter can be a value of @ref DMAEx_LinkedList_Mode */
} DMA_InitLinkedListTypeDef;
/**
* @brief HAL DMA State Enumeration Definition.
*/
typedef enum
{
HAL_DMA_STATE_RESET = 0x00U, /*!< DMA not yet initialized or disabled */
HAL_DMA_STATE_READY = 0x01U, /*!< DMA initialized and ready for use */
HAL_DMA_STATE_BUSY = 0x02U, /*!< DMA process is ongoing */
HAL_DMA_STATE_ERROR = 0x03U, /*!< DMA error state */
HAL_DMA_STATE_ABORT = 0x04U, /*!< DMA Abort state */
HAL_DMA_STATE_SUSPEND = 0x05U, /*!< DMA Suspend state */
} HAL_DMA_StateTypeDef;
/**
* @brief HAL DMA Level Complete Enumeration Definition.
*/
typedef enum
{
HAL_DMA_FULL_TRANSFER = 0x00U, /*!< Full channel transfer */
HAL_DMA_HALF_TRANSFER = 0x01U, /*!< Half channel transfer */
} HAL_DMA_LevelCompleteTypeDef;
/**
* @brief HAL DMA Callbacks IDs Enumeration Definition.
*/
typedef enum
{
HAL_DMA_XFER_CPLT_CB_ID = 0x00U, /*!< Complete transfer callback ID */
HAL_DMA_XFER_HALFCPLT_CB_ID = 0x01U, /*!< Half complete transfer callback ID */
HAL_DMA_XFER_ERROR_CB_ID = 0x02U, /*!< Error transfer callback ID */
HAL_DMA_XFER_ABORT_CB_ID = 0x03U, /*!< Abort transfer callback ID */
HAL_DMA_XFER_SUSPEND_CB_ID = 0x04U, /*!< Suspend transfer callback ID */
HAL_DMA_XFER_ALL_CB_ID = 0x05U /*!< All callback ID */
} HAL_DMA_CallbackIDTypeDef;
/**
* @brief DMA handle Structure definition
*/
typedef struct __DMA_HandleTypeDef
{
DMA_Channel_TypeDef *Instance; /*!< Register the DMA channel base address */
DMA_InitTypeDef Init; /*!< DMA channel init parameters */
DMA_InitLinkedListTypeDef InitLinkedList; /*!< DMA channel linked-list init parameters */
HAL_LockTypeDef Lock; /*!< DMA locking object */
uint32_t Mode; /*!< DMA transfer mode */
__IO HAL_DMA_StateTypeDef State; /*!< DMA transfer state */
__IO uint32_t ErrorCode; /*!< DMA error code */
void *Parent; /*!< Parent object state */
void (* XferCpltCallback)(struct __DMA_HandleTypeDef *hdma); /*!< DMA transfer complete callback */
void (* XferHalfCpltCallback)(struct __DMA_HandleTypeDef *hdma); /*!< DMA half transfer complete callback */
void (* XferErrorCallback)(struct __DMA_HandleTypeDef *hdma); /*!< DMA transfer error callback */
void (* XferAbortCallback)(struct __DMA_HandleTypeDef *hdma); /*!< DMA transfer Abort callback */
void (* XferSuspendCallback)(struct __DMA_HandleTypeDef *hdma); /*!< DMA transfer Suspend callback */
struct __DMA_QListTypeDef *LinkedListQueue; /*!< DMA linked-list queue */
} DMA_HandleTypeDef;
/**
* @}
*/
/* Exported constants ------------------------------------------------------------------------------------------------*/
/** @defgroup DMA_Exported_Constants DMA Exported Constants
* @brief DMA Exported constants
* @{
*/
/** @defgroup DMA_Error_Codes DMA Error Codes
* @brief DMA Error Codes
* @{
*/
#define HAL_DMA_ERROR_NONE (0x0000U) /*!< No error */
#define HAL_DMA_ERROR_DTE (0x0001U) /*!< Data transfer error */
#define HAL_DMA_ERROR_ULE (0x0002U) /*!< Update linked-list item error */
#define HAL_DMA_ERROR_USE (0x0004U) /*!< User setting error */
#define HAL_DMA_ERROR_TO (0x0008U) /*!< Trigger overrun error */
#define HAL_DMA_ERROR_TIMEOUT (0x0010U) /*!< Timeout error */
#define HAL_DMA_ERROR_NO_XFER (0x0020U) /*!< No transfer ongoing error */
#define HAL_DMA_ERROR_BUSY (0x0040U) /*!< Busy error */
#define HAL_DMA_ERROR_INVALID_CALLBACK (0x0080U) /*!< Invalid callback error */
#define HAL_DMA_ERROR_NOT_SUPPORTED (0x0100U) /*!< Not supported mode */
/**
* @}
*/
/** @defgroup DMA_Interrupt_Enable_Definition DMA Interrupt Enable Definition
* @brief DMA Interrupt Enable Definition
* @{
*/
#define DMA_IT_TC DMA_CCR_TCIE /*!< Transfer complete interrupt */
#define DMA_IT_HT DMA_CCR_HTIE /*!< Half transfer complete interrupt */
#define DMA_IT_DTE DMA_CCR_DTEIE /*!< Data transfer error interrupt */
#define DMA_IT_ULE DMA_CCR_ULEIE /*!< Update linked-list item error interrupt */
#define DMA_IT_USE DMA_CCR_USEIE /*!< User eetting error interrupt */
#define DMA_IT_SUSP DMA_CCR_SUSPIE /*!< Completed suspension interrupt */
#define DMA_IT_TO DMA_CCR_TOIE /*!< Trigger overrun interrupt */
/**
* @}
*/
/** @defgroup DMA_Flag_Definition DMA Flag Definition
* @brief DMA Flag Definition
* @{
*/
#define DMA_FLAG_IDLE DMA_CSR_IDLEF /*!< Idle flag */
#define DMA_FLAG_TC DMA_CSR_TCF /*!< Transfer complete flag */
#define DMA_FLAG_HT DMA_CSR_HTF /*!< Half transfer complete flag */
#define DMA_FLAG_DTE DMA_CSR_DTEF /*!< Data transfer error flag */
#define DMA_FLAG_ULE DMA_CSR_ULEF /*!< Update linked-list item error flag */
#define DMA_FLAG_USE DMA_CSR_USEF /*!< User setting error flag */
#define DMA_FLAG_SUSP DMA_CSR_SUSPF /*!< Completed suspension flag */
#define DMA_FLAG_TO DMA_CSR_TOF /*!< Trigger overrun flag */
/**
* @}
*/
/** @defgroup DMA_Request_Selection DMA Request Selection
* @brief DMA Request Selection
* @{
*/
/* GPDMA1 Hardware Requests */
#define GPDMA1_REQUEST_ADC1 0U /*!< GPDMA1 HW request is ADC1 */
#define GPDMA1_REQUEST_ADC2 1U /*!< GPDMA1 HW request is ADC2 */
#define GPDMA1_REQUEST_DAC1_CH1 2U /*!< GPDMA1 HW request is DAC1_CH1 */
#define GPDMA1_REQUEST_DAC1_CH2 3U /*!< GPDMA1 HW request is DAC1_CH2 */
#define GPDMA1_REQUEST_TIM6_UP 4U /*!< GPDMA1 HW request is TIM6_UP */
#define GPDMA1_REQUEST_TIM7_UP 5U /*!< GPDMA1 HW request is TIM7_UP */
#define GPDMA1_REQUEST_SPI1_RX 6U /*!< GPDMA1 HW request is SPI1_RX */
#define GPDMA1_REQUEST_SPI1_TX 7U /*!< GPDMA1 HW request is SPI1_TX */
#define GPDMA1_REQUEST_SPI2_RX 8U /*!< GPDMA1 HW request is SPI2_RX */
#define GPDMA1_REQUEST_SPI2_TX 9U /*!< GPDMA1 HW request is SPI2_TX */
#define GPDMA1_REQUEST_SPI3_RX 10U /*!< GPDMA1 HW request is SPI3_RX */
#define GPDMA1_REQUEST_SPI3_TX 11U /*!< GPDMA1 HW request is SPI3_TX */
#define GPDMA1_REQUEST_I2C1_RX 12U /*!< GPDMA1 HW request is I2C1_RX */
#define GPDMA1_REQUEST_I2C1_TX 13U /*!< GPDMA1 HW request is I2C1_TX */
#define GPDMA1_REQUEST_I2C1_EVC 14U /*!< GPDMA1 HW request is I2C1_EVC */
#if defined (I2C2)
#define GPDMA1_REQUEST_I2C2_RX 15U /*!< GPDMA1 HW request is I2C2_RX */
#define GPDMA1_REQUEST_I2C2_TX 16U /*!< GPDMA1 HW request is I2C2_TX */
#define GPDMA1_REQUEST_I2C2_EVC 17U /*!< GPDMA1 HW request is I2C2_EVC */
#endif /* I2C2 */
#define GPDMA1_REQUEST_I2C3_RX 18U /*!< GPDMA1 HW request is I2C3_RX */
#define GPDMA1_REQUEST_I2C3_TX 19U /*!< GPDMA1 HW request is I2C3_TX */
#define GPDMA1_REQUEST_I2C3_EVC 20U /*!< GPDMA1 HW request is I2C3_EVC */
#if defined (I2C4)
#define GPDMA1_REQUEST_I2C4_RX 21U /*!< GPDMA1 HW request is I2C4_RX */
#define GPDMA1_REQUEST_I2C4_TX 22U /*!< GPDMA1 HW request is I2C4_TX */
#define GPDMA1_REQUEST_I2C4_EVC 23U /*!< GPDMA1 HW request is I2C4_EVC */
#endif /* I2C4 */
#define GPDMA1_REQUEST_USART1_RX 24U /*!< GPDMA1 HW request is USART1_RX */
#define GPDMA1_REQUEST_USART1_TX 25U /*!< GPDMA1 HW request is USART1_TX */
#if defined (USART2)
#define GPDMA1_REQUEST_USART2_RX 26U /*!< GPDMA1 HW request is USART2_RX */
#define GPDMA1_REQUEST_USART2_TX 27U /*!< GPDMA1 HW request is USART2_TX */
#endif /* USART2 */
#define GPDMA1_REQUEST_USART3_RX 28U /*!< GPDMA1 HW request is USART3_RX */
#define GPDMA1_REQUEST_USART3_TX 29U /*!< GPDMA1 HW request is USART3_TX */
#define GPDMA1_REQUEST_UART4_RX 30U /*!< GPDMA1 HW request is UART4_RX */
#define GPDMA1_REQUEST_UART4_TX 31U /*!< GPDMA1 HW request is UART4_TX */
#define GPDMA1_REQUEST_UART5_RX 32U /*!< GPDMA1 HW request is UART5_RX */
#define GPDMA1_REQUEST_UART5_TX 33U /*!< GPDMA1 HW request is UART5_TX */
#define GPDMA1_REQUEST_LPUART1_RX 34U /*!< GPDMA1 HW request is LPUART1_RX */
#define GPDMA1_REQUEST_LPUART1_TX 35U /*!< GPDMA1 HW request is LPUART1_TX */
#if defined (SAI1)
#define GPDMA1_REQUEST_SAI1_A 36U /*!< GPDMA1 HW request is SAI1_A */
#define GPDMA1_REQUEST_SAI1_B 37U /*!< GPDMA1 HW request is SAI1_B */
#endif /* SAI1 */
/* Reserved 38U */
/* Reserved 39U */
#define GPDMA1_REQUEST_OCTOSPI1 40U /*!< GPDMA1 HW request is OCTOSPI1 */
/* Reserved 41U */
#define GPDMA1_REQUEST_TIM1_CH1 42U /*!< GPDMA1 HW request is TIM1_CH1 */
#define GPDMA1_REQUEST_TIM1_CH2 43U /*!< GPDMA1 HW request is TIM1_CH2 */
#define GPDMA1_REQUEST_TIM1_CH3 44U /*!< GPDMA1 HW request is TIM1_CH3 */
#define GPDMA1_REQUEST_TIM1_CH4 45U /*!< GPDMA1 HW request is TIM1_CH4 */
#define GPDMA1_REQUEST_TIM1_UP 46U /*!< GPDMA1 HW request is TIM1_UP */
#define GPDMA1_REQUEST_TIM1_TRIG 47U /*!< GPDMA1 HW request is TIM1_TRIG */
#define GPDMA1_REQUEST_TIM1_COM 48U /*!< GPDMA1 HW request is TIM1_COM */
#define GPDMA1_REQUEST_I3C1_RX 49U /*!< GPDMA1 HW request is I3C1_RX */
#define GPDMA1_REQUEST_I3C1_TX 50U /*!< GPDMA1 HW request is I3C1_TX */
#define GPDMA1_REQUEST_I3C1_TC 51U /*!< GPDMA1 HW request is I3C1_TC */
#define GPDMA1_REQUEST_I3C1_RS 52U /*!< GPDMA1 HW request is I3C1_RS */
/* Reserved 53U */
/* Reserved 54U */
/* Reserved 55U */
#define GPDMA1_REQUEST_TIM2_CH1 56U /*!< GPDMA1 HW request is TIM2_CH1 */
#define GPDMA1_REQUEST_TIM2_CH2 57U /*!< GPDMA1 HW request is TIM2_CH2 */
#define GPDMA1_REQUEST_TIM2_CH3 58U /*!< GPDMA1 HW request is TIM2_CH3 */
#define GPDMA1_REQUEST_TIM2_CH4 59U /*!< GPDMA1 HW request is TIM2_CH4 */
#define GPDMA1_REQUEST_TIM2_UP 60U /*!< GPDMA1 HW request is TIM2_UP */
#define GPDMA1_REQUEST_TIM3_CH1 61U /*!< GPDMA1 HW request is TIM3_CH1 */
#define GPDMA1_REQUEST_TIM3_CH2 62U /*!< GPDMA1 HW request is TIM3_CH2 */
#define GPDMA1_REQUEST_TIM3_CH3 63U /*!< GPDMA1 HW request is TIM3_CH3 */
#define GPDMA1_REQUEST_TIM3_CH4 64U /*!< GPDMA1 HW request is TIM3_CH4 */
#define GPDMA1_REQUEST_TIM3_UP 65U /*!< GPDMA1 HW request is TIM3_UP */
#define GPDMA1_REQUEST_TIM3_TRIG 66U /*!< GPDMA1 HW request is TIM3_TRIG */
#define GPDMA1_REQUEST_TIM4_CH1 67U /*!< GPDMA1 HW request is TIM4_CH1 */
#define GPDMA1_REQUEST_TIM4_CH2 68U /*!< GPDMA1 HW request is TIM4_CH2 */
#define GPDMA1_REQUEST_TIM4_CH3 69U /*!< GPDMA1 HW request is TIM4_CH3 */
#define GPDMA1_REQUEST_TIM4_CH4 70U /*!< GPDMA1 HW request is TIM4_CH4 */
#define GPDMA1_REQUEST_TIM4_UP 71U /*!< GPDMA1 HW request is TIM4_UP */
#if defined (I3C2)
#define GPDMA1_REQUEST_I3C2_RX 72U /*!< GPDMA1 HW request is I3C2_RX */
#define GPDMA1_REQUEST_I3C2_TX 73U /*!< GPDMA1 HW request is I3C2_TX */
#define GPDMA1_REQUEST_I3C2_TC 74U /*!< GPDMA1 HW request is I3C2_TC */
#define GPDMA1_REQUEST_I3C2_RS 75U /*!< GPDMA1 HW request is I3C2_RS */
#endif /* I3C2 */
#if defined (SPI4)
#define GPDMA1_REQUEST_SPI4_RX 76U /*!< GPDMA1 HW request is SPI4_RX */
#define GPDMA1_REQUEST_SPI4_TX 77U /*!< GPDMA1 HW request is SPI4_TX */
#endif /* SPI4 */
#define GPDMA1_REQUEST_TIM15_CH1 78U /*!< GPDMA1 HW request is TIM15_CH1 */
#define GPDMA1_REQUEST_TIM15_UP 79U /*!< GPDMA1 HW request is TIM15_UP */
#define GPDMA1_REQUEST_TIM15_TRIG 80U /*!< GPDMA1 HW request is TIM15_TRIG */
#define GPDMA1_REQUEST_TIM15_COM 81U /*!< GPDMA1 HW request is TIM15_COM */
#define GPDMA1_REQUEST_TIM16_CH1 82U /*!< GPDMA1 HW request is TIM16_CH1 */
#define GPDMA1_REQUEST_TIM16_UP 83U /*!< GPDMA1 HW request is TIM16_UP */
#define GPDMA1_REQUEST_TIM17_CH1 84U /*!< GPDMA1 HW request is TIM17_CH1 */
#define GPDMA1_REQUEST_TIM17_UP 85U /*!< GPDMA1 HW request is TIM17_UP */
/* Reserved 86U */
#define GPDMA1_REQUEST_AES_IN 87U /*!< GPDMA1 HW request is AES_IN */
#define GPDMA1_REQUEST_AES_OUT 88U /*!< GPDMA1 HW request is AES_OUT */
#define GPDMA1_REQUEST_HASH_IN 89U /*!< GPDMA1 HW request is HASH_IN */
/* Reserved 90U */
#if defined (TIM8)
#define GPDMA1_REQUEST_TIM8_CH1 91U /*!< GPDMA1 HW request is TIM8_CH1 */
#define GPDMA1_REQUEST_TIM8_CH2 92U /*!< GPDMA1 HW request is TIM8_CH2 */
#define GPDMA1_REQUEST_TIM8_CH3 93U /*!< GPDMA1 HW request is TIM8_CH3 */
#define GPDMA1_REQUEST_TIM8_CH4 94U /*!< GPDMA1 HW request is TIM8_CH4 */
#define GPDMA1_REQUEST_TIM8_UP 95U /*!< GPDMA1 HW request is TIM8_UP */
#define GPDMA1_REQUEST_TIM8_TRIG 96U /*!< GPDMA1 HW request is TIM8_TRIG */
#define GPDMA1_REQUEST_TIM8_COM 97U /*!< GPDMA1 HW request is TIM8_COM */
#endif /* TIM8 */
#if defined (ADF1)
#define GPDMA1_REQUEST_ADF1_FLT0 98U /*!< GPDMA1 HW request is ADF1_FLT0 */
#endif /* ADF1 */
/* Reserved 99U */
/* Reserved 100U */
/* Reserved 101U */
/* Reserved 102U */
#define GPDMA1_REQUEST_SAES_IN 103U /*!< GPDMA1 HW request is SAES_IN */
#define GPDMA1_REQUEST_SAES_OUT 104U /*!< GPDMA1 HW request is SAES_OUT */
#define GPDMA1_REQUEST_LPTIM1_IC1 105U /*!< GPDMA1 HW request is LPTIM1_IC1 */
#define GPDMA1_REQUEST_LPTIM1_IC2 106U /*!< GPDMA1 HW request is LPTIM1_IC2 */
#define GPDMA1_REQUEST_LPTIM1_UE 107U /*!< GPDMA1 HW request is LPTIM1_UE */
#define GPDMA1_REQUEST_LPTIM2_IC1 108U /*!< GPDMA1 HW request is LPTIM2_IC1 */
#define GPDMA1_REQUEST_LPTIM2_IC2 109U /*!< GPDMA1 HW request is LPTIM2_IC2 */
#define GPDMA1_REQUEST_LPTIM2_UE 110U /*!< GPDMA1 HW request is LPTIM2_UE */
#define GPDMA1_REQUEST_LPTIM3_IC1 111U /*!< GPDMA1 HW request is LPTIM3_IC1 */
#define GPDMA1_REQUEST_LPTIM3_IC2 112U /*!< GPDMA1 HW request is LPTIM3_IC2 */
#define GPDMA1_REQUEST_LPTIM3_UE 113U /*!< GPDMA1 HW request is LPTIM3_UE */
/* Software request */
#define DMA_REQUEST_SW DMA_CTR2_SWREQ /*!< DMA SW request */
/**
* @}
*/
/** @defgroup DMA_Block_Request DMA Block Request
* @brief DMA Block Request
* @{
*/
#define DMA_BREQ_SINGLE_BURST 0x00000000U /*!< Hardware request protocol at a single / burst level */
#define DMA_BREQ_BLOCK DMA_CTR2_BREQ /*!< Hardware request protocol at a block level */
/**
* @}
*/
/** @defgroup DMA_Transfer_Direction DMA Transfer Direction
* @brief DMA transfer direction
* @{
*/
#define DMA_PERIPH_TO_MEMORY 0x00000000U /*!< Peripheral to memory direction */
#define DMA_MEMORY_TO_PERIPH DMA_CTR2_DREQ /*!< Memory to peripheral direction */
#define DMA_MEMORY_TO_MEMORY DMA_CTR2_SWREQ /*!< Memory to memory direction */
/**
* @}
*/
/** @defgroup DMA_Source_Increment_Mode DMA Source Increment Mode
* @brief DMA Source Increment Mode
* @{
*/
#define DMA_SINC_FIXED 0x00000000U /*!< Source fixed single / burst */
#define DMA_SINC_INCREMENTED DMA_CTR1_SINC /*!< Source incremented single / burst */
/**
* @}
*/
/** @defgroup DMA_Destination_Increment_Mode DMA Destination Increment Mode
* @brief DMA Destination Increment Mode
* @{
*/
#define DMA_DINC_FIXED 0x00000000U /*!< Destination fixed single / burst */
#define DMA_DINC_INCREMENTED DMA_CTR1_DINC /*!< Destination incremented single / burst */
/**
* @}
*/
/** @defgroup DMA_Source_Data_Width DMA Source Data Width
* @brief DMA Source Data Width
* @{
*/
#define DMA_SRC_DATAWIDTH_BYTE 0x00000000U /*!< Source data width : Byte */
#define DMA_SRC_DATAWIDTH_HALFWORD DMA_CTR1_SDW_LOG2_0 /*!< Source data width : HalfWord */
#define DMA_SRC_DATAWIDTH_WORD DMA_CTR1_SDW_LOG2_1 /*!< Source data width : Word */
/**
* @}
*/
/** @defgroup DMA_Destination_Data_Width DMA destination Data Width
* @brief DMA destination Data Width
* @{
*/
#define DMA_DEST_DATAWIDTH_BYTE 0x00000000U /*!< Destination data width : Byte */
#define DMA_DEST_DATAWIDTH_HALFWORD DMA_CTR1_DDW_LOG2_0 /*!< Destination data width : HalfWord */
#define DMA_DEST_DATAWIDTH_WORD DMA_CTR1_DDW_LOG2_1 /*!< Destination data width : Word */
/**
* @}
*/
/** @defgroup DMA_Priority_Level DMA Priority Level
* @brief DMA Priority Level
* @{
*/
#define DMA_LOW_PRIORITY_LOW_WEIGHT 0x00000000U /*!< Priority level : Low Priority, Low weight */
#define DMA_LOW_PRIORITY_MID_WEIGHT DMA_CCR_PRIO_0 /*!< Priority level : Low Priority, Mid weight */
#define DMA_LOW_PRIORITY_HIGH_WEIGHT DMA_CCR_PRIO_1 /*!< Priority level : Low Priority, High weight */
#define DMA_HIGH_PRIORITY DMA_CCR_PRIO /*!< Priority level : HIGH Priority */
/**
* @}
*/
/** @defgroup DMA_Transfer_Allocated_Port DMA Transfer Allocated Port
* @brief DMA Transfer Allocated Port
* @{
*/
#define DMA_SRC_ALLOCATED_PORT0 0x00000000U /*!< Source allocated Port 0 */
#define DMA_SRC_ALLOCATED_PORT1 DMA_CTR1_SAP /*!< Source allocated Port 1 */
#define DMA_DEST_ALLOCATED_PORT0 0x00000000U /*!< Destination allocated Port 0 */
#define DMA_DEST_ALLOCATED_PORT1 DMA_CTR1_DAP /*!< Destination allocated Port 1 */
/**
* @}
*/
/** @defgroup DMA_Transfer_Event_Mode DMA Transfer Event Mode
* @brief DMA Transfer Event Mode
* @{
*/
#define DMA_TCEM_BLOCK_TRANSFER 0x00000000U /*!< The TC event is generated at the end of each block and the
HT event is generated at the half of each block */
#define DMA_TCEM_REPEATED_BLOCK_TRANSFER DMA_CTR2_TCEM_0 /*!< The TC event is generated at the end of the repeated block
and the HT event is generated at the half of the repeated
block */
#define DMA_TCEM_EACH_LL_ITEM_TRANSFER DMA_CTR2_TCEM_1 /*!< The TC event is generated at the end of each linked-list
item and the HT event is generated at the half of each
linked-list item */
#define DMA_TCEM_LAST_LL_ITEM_TRANSFER DMA_CTR2_TCEM /*!< The TC event is generated at the end of the last
linked-list item and the HT event is generated at the half
of the last linked-list item */
/**
* @}
*/
/** @defgroup DMA_Transfer_Mode DMA Transfer Mode
* @brief DMA Transfer Mode
* @{
*/
#define DMA_NORMAL (0x00U) /*!< Normal DMA transfer */
#define DMA_PFCTRL DMA_CTR2_PFREQ /*!< HW request peripheral flow control mode */
/**
* @}
*/
/** @defgroup DMA_Channel_Attributes DMA Channel Attributes
* @brief DMA Channel Security and Privilege Attributes
* @note Secure and non-secure attributes are only available from the secure world when TZEN = 1
* @{
*/
#define DMA_CHANNEL_PRIV (DMA_CHANNEL_ATTR_PRIV_MASK | 0x01U) /*!< Channel is privileged */
#define DMA_CHANNEL_NPRIV (DMA_CHANNEL_ATTR_PRIV_MASK) /*!< Channel is unprivileged */
#define DMA_CHANNEL_SEC (DMA_CHANNEL_ATTR_SEC_MASK | 0x02U) /*!< Channel is secure */
#define DMA_CHANNEL_NSEC (DMA_CHANNEL_ATTR_SEC_MASK) /*!< Channel is non-secure */
#define DMA_CHANNEL_SRC_SEC (DMA_CHANNEL_ATTR_SEC_SRC_MASK | 0x04U) /*!< Channel source is secure */
#define DMA_CHANNEL_SRC_NSEC (DMA_CHANNEL_ATTR_SEC_SRC_MASK) /*!< Channel source is non-secure */
#define DMA_CHANNEL_DEST_SEC (DMA_CHANNEL_ATTR_SEC_DEST_MASK | 0x08U) /*!< Channel destination is secure */
#define DMA_CHANNEL_DEST_NSEC (DMA_CHANNEL_ATTR_SEC_DEST_MASK) /*!< Channel destination is non-secure */
#define DMA_CHANNEL_ATTRIBUTE_UNLOCKED (0x00U) /*!< Channel attribute is unlocked */
#define DMA_CHANNEL_ATTRIBUTE_LOCKED (0x01U) /*!< Channel attribute is locked */
/**
* @}
*/
/**
* @}
*/
/* Exported macro ----------------------------------------------------------------------------------------------------*/
/** @defgroup DMA_Exported_Macros DMA Exported Macros
* @brief DMA Exported Macros
* @{
*/
/** @brief Reset DMA handle state.
* @param __HANDLE__ : DMA handle.
* @retval None.
*/
#define __HAL_DMA_RESET_HANDLE_STATE(__HANDLE__) \
((__HANDLE__)->State = HAL_DMA_STATE_RESET)
/**
* @brief Enable the specified DMA Channel.
* @param __HANDLE__ : DMA handle.
* @retval None
*/
#define __HAL_DMA_ENABLE(__HANDLE__) \
((__HANDLE__)->Instance->CCR |= DMA_CCR_EN)
/**
* @brief Disable the specified DMA Channel.
* @param __HANDLE__ : DMA handle.
* @retval None
*/
#define __HAL_DMA_DISABLE(__HANDLE__) \
((__HANDLE__)->Instance->CCR |= (DMA_CCR_SUSP | DMA_CCR_RESET))
/**
* @brief Get the DMA channel pending flags.
* @param __HANDLE__ : DMA handle.
* @param __FLAG__ : Get the specified flag.
* This parameter can be any combination of the following values:
* @arg DMA_FLAG_TC : Transfer Complete flag.
* @arg DMA_FLAG_HT : Half Transfer Complete flag.
* @arg DMA_FLAG_DTE : Data Transfer Error flag.
* @arg DMA_FLAG_ULE : Update linked-list Error flag.
* @arg DMA_FLAG_USE : User Setting Error flag.
* @arg DMA_FLAG_TO : Trigger Overrun flag.
* @arg DMA_FLAG_SUSP : Completed Suspension flag.
* @arg DMA_FLAG_IDLEF : Idle flag.
* @retval The state of FLAG (SET or RESET).
*/
#define __HAL_DMA_GET_FLAG(__HANDLE__, __FLAG__) \
((__HANDLE__)->Instance->CSR & (__FLAG__))
/**
* @brief Clear the DMA Channel pending flags.
* @param __HANDLE__ : DMA handle.
* @param __FLAG__ : Specifies the flag to clear.
* This parameter can be any combination of the following values:
* @arg DMA_FLAG_TC : Transfer Complete flag.
* @arg DMA_FLAG_HT : Half Transfer Complete flag.
* @arg DMA_FLAG_DTE : Data Transfer Error flag.
* @arg DMA_FLAG_ULE : Update Linked-List Error flag.
* @arg DMA_FLAG_USE : User Setting Error flag.
* @arg DMA_FLAG_TO : Trigger Overrun flag.
* @arg DMA_FLAG_SUSP : Completed Suspension flag.
* @retval None
*/
#define __HAL_DMA_CLEAR_FLAG(__HANDLE__, __FLAG__) \
((__HANDLE__)->Instance->CFCR = (__FLAG__))
/**
* @brief Enable the specified DMA Channel interrupts.
* @param __HANDLE__ : DMA handle.
* @param __INTERRUPT__ : Specifies the DMA interrupt sources to be enabled.
* This parameter can be any combination of the following values:
* @arg DMA_IT_TC : Transfer Complete interrupt.
* @arg DMA_IT_HT : Half Transfer Complete interrupt.
* @arg DMA_IT_DTE : Data Transfer Error interrupt.
* @arg DMA_IT_ULE : Update Linked-List Error interrupt.
* @arg DMA_IT_USE : User Setting Error interrupt.
* @arg DMA_IT_TO : Trigger Overrun interrupt.
* @arg DMA_IT_SUSP : Completed Suspension interrupt.
* @retval None
*/
#define __HAL_DMA_ENABLE_IT(__HANDLE__, __INTERRUPT__) \
((__HANDLE__)->Instance->CCR |= (__INTERRUPT__))
/**
* @brief Disable the specified DMA Channel interrupts.
* @param __HANDLE__ : DMA handle.
* @param __INTERRUPT__ : specifies the DMA interrupt sources to be disabled.
* This parameter can be any combination of the following values:
* @arg DMA_IT_TC : Transfer Complete interrupt.
* @arg DMA_IT_HT : Half Transfer Complete interrupt.
* @arg DMA_IT_DTE : Data Transfer Error interrupt.
* @arg DMA_IT_ULE : Update Linked-List Error interrupt.
* @arg DMA_IT_USE : User Setting Error interrupt.
* @arg DMA_IT_TO : Trigger Overrun interrupt.
* @arg DMA_IT_SUSP : Completed Suspension interrupt.
* @retval None
*/
#define __HAL_DMA_DISABLE_IT(__HANDLE__, __INTERRUPT__) \
((__HANDLE__)->Instance->CCR &= ~(__INTERRUPT__))
/**
* @brief Checks whether the specified DMA Channel interrupt is enabled or not.
* @param __HANDLE__ : DMA handle.
* @param __INTERRUPT__ : specifies the DMA interrupt source to check.
* @arg DMA_IT_TC : Transfer Complete interrupt.
* @arg DMA_IT_HT : Half Transfer Complete interrupt.
* @arg DMA_IT_DTE : Data Transfer Error interrupt.
* @arg DMA_IT_ULE : Update Linked-List Error interrupt.
* @arg DMA_IT_USE : User Setting Error interrupt.
* @arg DMA_IT_TO : Trigger Overrun interrupt.
* @arg DMA_IT_SUSP : Completed Suspension interrupt.
* @retval The state of DMA_IT (SET or RESET).
*/
#define __HAL_DMA_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) \
(((__HANDLE__)->Instance->CCR & (__INTERRUPT__)))
/**
* @brief Writes the block number of bytes to be transferred from the source on the DMA Channel.
* @param __HANDLE__ : DMA handle.
* @param __COUNTER__ : Number of data bytes to be transferred from the source (from 0 to 65535).
*/
#define __HAL_DMA_SET_COUNTER(__HANDLE__, __COUNTER__) \
MODIFY_REG((__HANDLE__)->Instance->CBR1, DMA_CBR1_BNDT, (__COUNTER__))
/**
* @brief Returns the number of remaining data bytes in the current DMA Channel transfer.
* @param __HANDLE__ : DMA handle.
* @retval The number of remaining data units in the current DMA Stream transfer.
*/
#define __HAL_DMA_GET_COUNTER(__HANDLE__) \
(((__HANDLE__)->Instance->CBR1) & DMA_CBR1_BNDT)
/**
* @}
*/
/* Include DMA HAL Extension module */
#include "stm32u3xx_hal_dma_ex.h"
/* Exported functions ------------------------------------------------------------------------------------------------*/
/** @defgroup DMA_Exported_Functions DMA Exported Functions
* @brief DMA Exported Functions
* @{
*/
/** @defgroup DMA_Exported_Functions_Group1 Initialization and De-Initialization Functions
* @brief Initialization and De-Initialization Functions
* @{
*/
HAL_StatusTypeDef HAL_DMA_Init(DMA_HandleTypeDef *const hdma);
HAL_StatusTypeDef HAL_DMA_DeInit(DMA_HandleTypeDef *const hdma);
/**
* @}
*/
/** @defgroup DMA_Exported_Functions_Group2 I/O Operation Functions
* @brief I/O Operation Functions
* @{
*/
HAL_StatusTypeDef HAL_DMA_Start(DMA_HandleTypeDef *const hdma,
uint32_t SrcAddress,
uint32_t DstAddress,
uint32_t SrcDataSize);
HAL_StatusTypeDef HAL_DMA_Start_IT(DMA_HandleTypeDef *const hdma,
uint32_t SrcAddress,
uint32_t DstAddress,
uint32_t SrcDataSize);
HAL_StatusTypeDef HAL_DMA_Abort(DMA_HandleTypeDef *const hdma);
HAL_StatusTypeDef HAL_DMA_Abort_IT(DMA_HandleTypeDef *const hdma);
HAL_StatusTypeDef HAL_DMA_PollForTransfer(DMA_HandleTypeDef *const hdma,
HAL_DMA_LevelCompleteTypeDef CompleteLevel,
uint32_t Timeout);
void HAL_DMA_IRQHandler(DMA_HandleTypeDef *const hdma);
HAL_StatusTypeDef HAL_DMA_RegisterCallback(DMA_HandleTypeDef *const hdma,
HAL_DMA_CallbackIDTypeDef CallbackID,
void (*const pCallback)(DMA_HandleTypeDef *const _hdma));
HAL_StatusTypeDef HAL_DMA_UnRegisterCallback(DMA_HandleTypeDef *const hdma,
HAL_DMA_CallbackIDTypeDef CallbackID);
/**
* @}
*/
/** @defgroup DMA_Exported_Functions_Group3 State and Error Functions
* @brief State and Error Functions
* @{
*/
HAL_DMA_StateTypeDef HAL_DMA_GetState(DMA_HandleTypeDef const *const hdma);
uint32_t HAL_DMA_GetError(DMA_HandleTypeDef const *const hdma);
/**
* @}
*/
/** @defgroup DMA_Exported_Functions_Group4 DMA Attributes Functions
* @brief DMA Attributes Functions
* @{
*/
HAL_StatusTypeDef HAL_DMA_ConfigChannelAttributes(DMA_HandleTypeDef *const hdma,
uint32_t ChannelAttributes);
HAL_StatusTypeDef HAL_DMA_GetConfigChannelAttributes(DMA_HandleTypeDef const *const hdma,
uint32_t *const pChannelAttributes);
#if defined (CPU_IN_SECURE_STATE)
HAL_StatusTypeDef HAL_DMA_LockChannelAttributes(DMA_HandleTypeDef const *const hdma);
#endif /* CPU_IN_SECURE_STATE */
HAL_StatusTypeDef HAL_DMA_GetLockChannelAttributes(DMA_HandleTypeDef const *const hdma,
uint32_t *const pLockState);
/**
* @}
*/
/**
* @}
*/
/* Private constants -------------------------------------------------------------------------------------------------*/
/** @defgroup DMA_Private_Constants DMA Private Constants
* @brief DMA Private Constants
* @{
*/
#define HAL_TIMEOUT_DMA_ABORT (0x00000005U) /* DMA channel abort timeout 5 milli-second */
#define HAL_DMA_CHANNEL_START (0x00000050U) /* DMA channel offset */
#define HAL_DMA_CHANNEL_SIZE (0x00000080U) /* DMA channel size */
#define HAL_DMA_OFFSET_MASK (0x00000FFFU) /* DMA channel offset mask */
#define DMA_CHANNEL_ATTR_PRIV_MASK (0x00000010U) /* DMA channel privilege mask */
#define DMA_CHANNEL_ATTR_SEC_MASK (0x00000020U) /* DMA channel secure mask */
#define DMA_CHANNEL_ATTR_SEC_SRC_MASK (0x00000040U) /* DMA channel source secure mask */
#define DMA_CHANNEL_ATTR_SEC_DEST_MASK (0x00000080U) /* DMA channel destination secure mask */
#define DMA_CHANNEL_ATTR_VALUE_MASK (0x0000000FU) /* DMA channel attributes value mask */
#define DMA_CHANNEL_ATTR_ITEM_MASK (0x000000F0U) /* DMA channel attributes item mask */
#define DMA_CHANNEL_BURST_MIN (0x00000001U) /* DMA channel minimum burst size */
#define DMA_CHANNEL_BURST_MAX (0x00000040U) /* DMA channel maximum burst size */
/**
* @}
*/
/* Private macros ----------------------------------------------------------------------------------------------------*/
/** @defgroup DMA_Private_Macros DMA Private Macros
* @brief DMA Private Macros
* @{
*/
#define GET_DMA_INSTANCE(__HANDLE__) \
((DMA_TypeDef *)((uint32_t)((__HANDLE__)->Instance) & (~HAL_DMA_OFFSET_MASK)))
#define GET_DMA_CHANNEL(__HANDLE__) \
((((uint32_t)((__HANDLE__)->Instance) & HAL_DMA_OFFSET_MASK) - HAL_DMA_CHANNEL_START) / HAL_DMA_CHANNEL_SIZE)
#define IS_DMA_MODE(MODE) \
(((MODE) == DMA_NORMAL) || \
((MODE) == DMA_PFCTRL))
#define IS_DMA_DIRECTION(DIRECTION) \
(((DIRECTION) == DMA_PERIPH_TO_MEMORY) || \
((DIRECTION) == DMA_MEMORY_TO_PERIPH) || \
((DIRECTION) == DMA_MEMORY_TO_MEMORY))
#define IS_DMA_LEVEL_COMPLETE(LEVEL) \
(((LEVEL) == HAL_DMA_FULL_TRANSFER) || \
((LEVEL) == HAL_DMA_HALF_TRANSFER))
#define IS_DMA_SOURCE_INC(INC) \
(((INC) == DMA_SINC_FIXED) || \
((INC) == DMA_SINC_INCREMENTED))
#define IS_DMA_DESTINATION_INC(INC) \
(((INC) == DMA_DINC_FIXED) || \
((INC) == DMA_DINC_INCREMENTED))
#define IS_DMA_SOURCE_DATA_WIDTH(WIDTH) \
(((WIDTH) == DMA_SRC_DATAWIDTH_BYTE) || \
((WIDTH) == DMA_SRC_DATAWIDTH_HALFWORD) || \
((WIDTH) == DMA_SRC_DATAWIDTH_WORD))
#define IS_DMA_DESTINATION_DATA_WIDTH(WIDTH) \
(((WIDTH) == DMA_DEST_DATAWIDTH_BYTE) || \
((WIDTH) == DMA_DEST_DATAWIDTH_HALFWORD) || \
((WIDTH) == DMA_DEST_DATAWIDTH_WORD))
#define IS_DMA_BURST_LENGTH(LENGTH) \
(((LENGTH) >= DMA_CHANNEL_BURST_MIN) && \
((LENGTH) <= DMA_CHANNEL_BURST_MAX))
#define IS_DMA_PRIORITY(PRIORITY) \
(((PRIORITY) == DMA_LOW_PRIORITY_LOW_WEIGHT) || \
((PRIORITY) == DMA_LOW_PRIORITY_MID_WEIGHT) || \
((PRIORITY) == DMA_LOW_PRIORITY_HIGH_WEIGHT) || \
((PRIORITY) == DMA_HIGH_PRIORITY))
#define IS_DMA_TRANSFER_ALLOCATED_PORT(ALLOCATED_PORT) \
(((ALLOCATED_PORT) & (~(DMA_CTR1_SAP | DMA_CTR1_DAP))) == 0U)
#define IS_DMA_REQUEST(REQUEST) \
(((REQUEST) == DMA_REQUEST_SW) || \
((REQUEST) <= GPDMA1_REQUEST_LPTIM3_UE))
#define IS_DMA_BLOCK_HW_REQUEST(MODE) \
(((MODE) == DMA_BREQ_SINGLE_BURST) || \
((MODE) == DMA_BREQ_BLOCK))
#define IS_DMA_TCEM_EVENT_MODE(MODE) \
(((MODE) == DMA_TCEM_BLOCK_TRANSFER) || \
((MODE) == DMA_TCEM_REPEATED_BLOCK_TRANSFER) || \
((MODE) == DMA_TCEM_EACH_LL_ITEM_TRANSFER) || \
((MODE) == DMA_TCEM_LAST_LL_ITEM_TRANSFER))
#define IS_DMA_BLOCK_SIZE(SIZE) \
(((SIZE) > 0U) && ((SIZE) <= DMA_CBR1_BNDT))
#if defined (CPU_IN_SECURE_STATE)
#define IS_DMA_ATTRIBUTES(ATTRIBUTE) \
(((ATTRIBUTE) != 0U) && (((ATTRIBUTE) & (~(DMA_CHANNEL_ATTR_VALUE_MASK | DMA_CHANNEL_ATTR_ITEM_MASK))) == 0U) && \
(((((ATTRIBUTE) & DMA_CHANNEL_ATTR_ITEM_MASK) >> 4U) | ((ATTRIBUTE) & DMA_CHANNEL_ATTR_VALUE_MASK)) == \
(((ATTRIBUTE) & DMA_CHANNEL_ATTR_ITEM_MASK) >> 4U)))
#else
#define IS_DMA_ATTRIBUTES(ATTRIBUTE) \
(((ATTRIBUTE) == DMA_CHANNEL_PRIV) || \
((ATTRIBUTE) == DMA_CHANNEL_NPRIV))
#endif /* CPU_IN_SECURE_STATE */
#if defined (CPU_IN_SECURE_STATE)
#define IS_DMA_GLOBAL_ACTIVE_FLAG_S(INSTANCE, GLOBAL_FLAG) \
(((INSTANCE)->SMISR & (GLOBAL_FLAG)))
#endif /* CPU_IN_SECURE_STATE */
#define IS_DMA_GLOBAL_ACTIVE_FLAG_NS(INSTANCE, GLOBAL_FLAG) \
(((INSTANCE)->MISR & (GLOBAL_FLAG)))
/**
* @}
*/
/* Private functions -------------------------------------------------------------------------------------------------*/
/** @defgroup DMA_Private_Functions DMA Private Functions
* @brief DMA Private Functions
* @{
*/
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /* STM32U3xx_HAL_DMA_H */

670
Software/Station_SW/Drivers/STM32U3xx_HAL_Driver/Inc/stm32u3xx_hal_dma_ex.h Normal file
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@@ -0,0 +1,670 @@
/**
**********************************************************************************************************************
* @file stm32u3xx_hal_dma_ex.h
* @author MCD Application Team
* @brief Header file of DMA HAL extension module.
**********************************************************************************************************************
* @attention
*
* Copyright (c) 2023 STMicroelectronics.
* All rights reserved.
*
* This software is licensed under terms that can be found in the LICENSE file
* in the root directory of this software component.
* If no LICENSE file comes with this software, it is provided AS-IS.
*
**********************************************************************************************************************
*/
/* Define to prevent recursive inclusion -----------------------------------------------------------------------------*/
#ifndef STM32U3xx_HAL_DMA_EX_H
#define STM32U3xx_HAL_DMA_EX_H
#ifdef __cplusplus
extern "C" {
#endif
/* Includes ----------------------------------------------------------------------------------------------------------*/
#include "stm32u3xx_hal_def.h"
/** @addtogroup STM32U3xx_HAL_Driver
* @{
*/
/** @addtogroup DMAEx
* @{
*/
/* Exported types ----------------------------------------------------------------------------------------------------*/
/** @defgroup DMAEx_Exported_Types DMAEx Exported Types
* @brief DMAEx Exported types
* @{
*/
/**
* @brief DMAEx Data Handling Configuration Structure Definition.
*/
typedef struct
{
uint32_t DataExchange; /*!< Specifies the DMA channel data exchange mode.
This parameter can be a value of @ref DMAEx_Data_Exchange */
uint32_t DataAlignment; /*!< Specifies the DMA channel data padding and alignment mode
This parameter can be a value of @ref DMAEx_Data_Alignment */
} DMA_DataHandlingConfTypeDef;
/**
* @brief DMAEx Trigger Configuration Structure Definition.
*/
typedef struct
{
uint32_t TriggerMode; /*!< Specifies the DMA channel trigger mode.
This parameter can be a value of @ref DMAEx_Trigger_Mode */
uint32_t TriggerPolarity; /*!< Specifies the DMA channel trigger event polarity.
This parameter can be a value of @ref DMAEx_Trigger_Polarity */
uint32_t TriggerSelection; /*!< Specifies the DMA channel trigger event selection.
This parameter can be a value of @ref DMAEx_Trigger_Selection */
} DMA_TriggerConfTypeDef;
/**
* @brief DMAEx Repeated Block Configuration Structure Definition.
*/
typedef struct
{
uint32_t RepeatCount; /*!< Specifies the DMA channel repeat count (the number of repetitions of block).
This parameter can be a value between 1 and 2048 */
int32_t SrcAddrOffset; /*!< Specifies the DMA channel single/burst source address offset :
This parameter can be a value between -8191 and 8191.
* If source address offset > 0 => Increment the source address by offset from where
the last single/burst transfer ends.
* If source address offset < 0 => Decrement the source address by offset from where
the last single/burst transfer ends.
* If source address offset == 0 => The next single/burst source address starts from
where the last transfer ends */
int32_t DestAddrOffset; /*!< Specifies the DMA channel single/burst destination address offset signed value :
This parameter can be a value between -8191 and 8191.
* If destination address offset > 0 => Increment the destination address by offset
from where the last single/burst transfer ends.
* If destination address offset < 0 => Decrement the destination address by offset
from where the last single/burst transfer ends.
* If destination address offset == 0 => The next single/burst destination address
starts from where the last transfer ends. */
int32_t BlkSrcAddrOffset; /*!< Specifies the DMA channel block source address offset signed value :
This parameter can be a value between -65535 and 65535.
* If block source address offset > 0 => Increment the block source address by offset
from where the last block ends.
* If block source address offset < 0 => Decrement the next block source address by
offset from where the last block ends.
* If block source address offset == 0 => the next block source address starts from
where the last block ends */
int32_t BlkDestAddrOffset; /*!< Specifies the DMA channel block destination address offset signed value :
This parameter can be a value between -65535 and 65535.
* If block destination address offset > 0 => Increment the block destination address
by offset from where the last block ends.
* If block destination address offset < 0 => Decrement the next block destination
address by offset from where the last block ends.
* If block destination address offset == 0 => the next block destination address
starts from where the last block ends */
} DMA_RepeatBlockConfTypeDef;
/**
* @brief DMAEx Queue State Enumeration Definition.
*/
typedef enum
{
HAL_DMA_QUEUE_STATE_RESET = 0x00U, /*!< DMA queue empty */
HAL_DMA_QUEUE_STATE_READY = 0x01U, /*!< DMA queue ready for use */
HAL_DMA_QUEUE_STATE_BUSY = 0x02U /*!< DMA queue execution on going */
} HAL_DMA_QStateTypeDef;
/**
* @brief DMAEx Linked-List Node Configuration Structure Definition.
*/
typedef struct
{
uint32_t NodeType; /*!< Specifies the DMA channel node type.
This parameter can be a value of @ref DMAEx_Node_Type */
DMA_InitTypeDef Init; /*!< Specifies the DMA channel basic configuration */
DMA_DataHandlingConfTypeDef DataHandlingConfig; /*!< Specifies the DMA channel data handling channel configuration */
DMA_TriggerConfTypeDef TriggerConfig; /*!< Specifies the DMA channel trigger configuration */
DMA_RepeatBlockConfTypeDef RepeatBlockConfig; /*!< Specifies the DMA channel repeated block configuration */
uint32_t SrcAddress; /*!< Specifies the source memory address */
uint32_t DstAddress; /*!< Specifies the destination memory address */
uint32_t DataSize; /*!< Specifies the source data size in bytes */
#if defined (CPU_IN_SECURE_STATE)
uint32_t SrcSecure; /*!< Specifies the source security attribute */
uint32_t DestSecure; /*!< Specifies the destination security attribute */
#endif /* CPU_IN_SECURE_STATE */
} DMA_NodeConfTypeDef;
/**
* @brief DMAEx Linked-List Node Structure Definition.
*/
typedef struct
{
uint32_t LinkRegisters[8U]; /*!< Physical Node register description */
uint32_t NodeInfo; /*!< Node information */
} DMA_NodeTypeDef;
/**
* @brief DMAEx Linked-List Queue Structure Definition.
*/
typedef struct __DMA_QListTypeDef
{
DMA_NodeTypeDef *Head; /*!< Specifies the queue head node */
DMA_NodeTypeDef *FirstCircularNode; /*!< Specifies the queue first circular node */
uint32_t NodeNumber; /*!< Specifies the queue node number */
__IO HAL_DMA_QStateTypeDef State; /*!< Specifies the queue state */
__IO uint32_t ErrorCode; /*!< Specifies the queue error code */
__IO uint32_t Type; /*!< Specifies whether the queue is static or dynamic */
} DMA_QListTypeDef;
/**
* @}
*/
/* Exported constants ------------------------------------------------------------------------------------------------*/
/** @defgroup DMAEx_Exported_Constants DMAEx Exported Constants
* @brief DMAEx Exported Constants
* @{
*/
/** @defgroup Queue_Error_Codes Queue Error Codes
* @brief Queue Error Codes
* @{
*/
#define HAL_DMA_QUEUE_ERROR_NONE (0x00U) /*!< No error */
#define HAL_DMA_QUEUE_ERROR_BUSY (0x01U) /*!< Error busy */
#define HAL_DMA_QUEUE_ERROR_EMPTY (0x02U) /*!< Error unallowed operation for empty queue */
#define HAL_DMA_QUEUE_ERROR_UNSUPPORTED (0x03U) /*!< Error unsupported feature */
#define HAL_DMA_QUEUE_ERROR_INVALIDTYPE (0x04U) /*!< Error incompatible node type or circular initialization
and queue circular types are incompatible */
#define HAL_DMA_QUEUE_ERROR_OUTOFRANGE (0x05U) /*!< Error out of range node memory */
#define HAL_DMA_QUEUE_ERROR_NOTFOUND (0x06U) /*!< Error node not found in queue */
/**
* @}
*/
/** @defgroup DMAEx_LinkedList_Mode DMAEx LinkedList Mode
* @brief DMAEx LinkedList Mode
* @{
*/
#define DMA_LINKEDLIST_NORMAL DMA_LINKEDLIST /*!< Linear linked-list DMA channel transfer */
#define DMA_LINKEDLIST_CIRCULAR (DMA_LINKEDLIST | (0x01U)) /*!< Circular linked-list DMA channel transfer */
/**
* @}
*/
/** @defgroup DMAEx_Data_Alignment DMAEx Data Alignment
* @brief DMAEx Data Alignment
* @{
*/
#define DMA_DATA_RIGHTALIGN_ZEROPADDED 0x00000000U /*!< If source data width < destination data width
=> Right aligned padded with 0 up to destination data
width */
#define DMA_DATA_RIGHTALIGN_LEFTTRUNC 0x00000000U /*!< If source data width > destination data width
=> Right aligned left Truncated down to destination
data width */
#define DMA_DATA_RIGHTALIGN_SIGNEXT DMA_CTR1_PAM_0 /*!< If source data width < destination data width
=> Right Aligned padded with sign extended up to
destination data width */
#define DMA_DATA_LEFTALIGN_RIGHTTRUNC DMA_CTR1_PAM_0 /*!< If source data width > destination data width
=> Left Aligned Right Truncated down to the
destination data width */
#define DMA_DATA_PACK DMA_CTR1_PAM_1 /*!< If source data width < destination data width
=> Packed at the destination data width */
#define DMA_DATA_UNPACK DMA_CTR1_PAM_1 /*!< If source data width > destination data width
=> Unpacked at the destination data width */
/**
* @}
*/
/** @defgroup DMAEx_Data_Exchange DMAEx Data Exchange
* @brief DMAEx Data Exchange
* @{
*/
#define DMA_EXCHANGE_NONE 0x00000000U /*!< No data exchange */
#define DMA_EXCHANGE_DEST_BYTE DMA_CTR1_DBX /*!< Destination Byte exchange when destination data width is > Byte */
#define DMA_EXCHANGE_DEST_HALFWORD DMA_CTR1_DHX /*!< Destination Half-Word exchange when destination data width is > Half-Word */
#define DMA_EXCHANGE_SRC_BYTE DMA_CTR1_SBX /*!< Source Byte endianness exchange when source data width is word */
/**
* @}
*/
/** @defgroup DMAEx_Trigger_Polarity DMAEx Trigger Polarity
* @brief DMAEx Trigger Polarity
* @{
*/
#define DMA_TRIG_POLARITY_MASKED 0x00000000U /*!< No trigger of the selected DMA request. Masked trigger event */
#define DMA_TRIG_POLARITY_RISING DMA_CTR2_TRIGPOL_0 /*!< Trigger of the selected DMA request on the rising edge of the selected trigger event input */
#define DMA_TRIG_POLARITY_FALLING DMA_CTR2_TRIGPOL_1 /*!< Trigger of the selected DMA request on the falling edge of the selected trigger event input */
/**
* @}
*/
/** @defgroup DMAEx_Trigger_Mode DMAEx Trigger Mode
* @brief DMAEx Trigger Mode
* @{
*/
#define DMA_TRIGM_BLOCK_TRANSFER 0x00000000U /*!< A block transfer is conditioned by (at least) one hit trigger */
#define DMA_TRIGM_REPEATED_BLOCK_TRANSFER DMA_CTR2_TRIGM_0 /*!< A repeated block transfer is conditioned by (at least) one hit trigger */
#define DMA_TRIGM_LLI_LINK_TRANSFER DMA_CTR2_TRIGM_1 /*!< A LLI link transfer is conditioned by (at least) one hit trigger */
#define DMA_TRIGM_SINGLE_BURST_TRANSFER DMA_CTR2_TRIGM /*!< A single/burst transfer is conditioned by (at least) one hit trigger */
/**
* @}
*/
/** @defgroup DMAEx_Trigger_Selection DMAEx Trigger Selection
* @brief DMAEx Trigger Selection
* @{
*/
/* GPDMA1 triggers */
#define GPDMA1_TRIGGER_EXTI_LINE0 0U /*!< GPDMA1 HW Trigger signal is EXTI_LINE0 */
#define GPDMA1_TRIGGER_EXTI_LINE1 1U /*!< GPDMA1 HW Trigger signal is EXTI_LINE1 */
#define GPDMA1_TRIGGER_EXTI_LINE2 2U /*!< GPDMA1 HW Trigger signal is EXTI_LINE2 */
#define GPDMA1_TRIGGER_EXTI_LINE3 3U /*!< GPDMA1 HW Trigger signal is EXTI_LINE3 */
#define GPDMA1_TRIGGER_EXTI_LINE4 4U /*!< GPDMA1 HW Trigger signal is EXTI_LINE4 */
#define GPDMA1_TRIGGER_EXTI_LINE5 5U /*!< GPDMA1 HW Trigger signal is EXTI_LINE5 */
#define GPDMA1_TRIGGER_EXTI_LINE6 6U /*!< GPDMA1 HW Trigger signal is EXTI_LINE6 */
#define GPDMA1_TRIGGER_EXTI_LINE7 7U /*!< GPDMA1 HW Trigger signal is EXTI_LINE7 */
#define GPDMA1_TRIGGER_TAMP_TRG1 8U /*!< GPDMA1 HW Trigger signal is TAMP_TRG1 */
#define GPDMA1_TRIGGER_TAMP_TRG2 9U /*!< GPDMA1 HW Trigger signal is TAMP_TRG2 */
#define GPDMA1_TRIGGER_TAMP_TRG3 10U /*!< GPDMA1 HW Trigger signal is TAMP_TRG3 */
#define GPDMA1_TRIGGER_LPTIM1_CH1 11U /*!< GPDMA1 HW Trigger signal is LPTIM1_CH1 */
#define GPDMA1_TRIGGER_LPTIM1_CH2 12U /*!< GPDMA1 HW Trigger signal is LPTIM1_CH2 */
#define GPDMA1_TRIGGER_LPTIM2_CH1 13U /*!< GPDMA1 HW Trigger signal is LPTIM2_CH1 */
#define GPDMA1_TRIGGER_LPTIM2_CH2 14U /*!< GPDMA1 HW Trigger signal is LPTIM2_CH2 */
#define GPDMA1_TRIGGER_LPTIM4_OUT 15U /*!< GPDMA1 HW Trigger signal is LPTIM4_OUT */
#define GPDMA1_TRIGGER_COMP1_OUT 16U /*!< GPDMA1 HW Trigger signal is COMP1_OUT */
#define GPDMA1_TRIGGER_COMP2_OUT 17U /*!< GPDMA1 HW Trigger signal is COMP2_OUT */
#define GPDMA1_TRIGGER_RTC_ALRA_TRG 18U /*!< GPDMA1 HW Trigger signal is RTC_ALRA_TRG */
#define GPDMA1_TRIGGER_RTC_ALRB_TRG 19U /*!< GPDMA1 HW Trigger signal is RTC_ALRB_TRG */
#define GPDMA1_TRIGGER_RTC_WUT_TRG 20U /*!< GPDMA1 HW Trigger signal is RTC_WUT_TRG */
/* Reserved 21U */
#define GPDMA1_TRIGGER_GPDMA1_CH0_TCF 22U /*!< GPDMA1 HW Trigger signal is GPDMA1_CH0_TCF */
#define GPDMA1_TRIGGER_GPDMA1_CH1_TCF 23U /*!< GPDMA1 HW Trigger signal is GPDMA1_CH1_TCF */
#define GPDMA1_TRIGGER_GPDMA1_CH2_TCF 24U /*!< GPDMA1 HW Trigger signal is GPDMA1_CH2_TCF */
#define GPDMA1_TRIGGER_GPDMA1_CH3_TCF 25U /*!< GPDMA1 HW Trigger signal is GPDMA1_CH3_TCF */
#define GPDMA1_TRIGGER_GPDMA1_CH4_TCF 26U /*!< GPDMA1 HW Trigger signal is GPDMA1_CH4_TCF */
#define GPDMA1_TRIGGER_GPDMA1_CH5_TCF 27U /*!< GPDMA1 HW Trigger signal is GPDMA1_CH5_TCF */
#define GPDMA1_TRIGGER_GPDMA1_CH6_TCF 28U /*!< GPDMA1 HW Trigger signal is GPDMA1_CH6_TCF */
#define GPDMA1_TRIGGER_GPDMA1_CH7_TCF 29U /*!< GPDMA1 HW Trigger signal is GPDMA1_CH7_TCF */
#define GPDMA1_TRIGGER_GPDMA1_CH8_TCF 30U /*!< GPDMA1 HW Trigger signal is GPDMA1_CH8_TCF */
#define GPDMA1_TRIGGER_GPDMA1_CH9_TCF 31U /*!< GPDMA1 HW Trigger signal is GPDMA1_CH9_TCF */
#define GPDMA1_TRIGGER_GPDMA1_CH10_TCF 32U /*!< GPDMA1 HW Trigger signal is GPDMA1_CH10_TCF */
#define GPDMA1_TRIGGER_GPDMA1_CH11_TCF 33U /*!< GPDMA1 HW Trigger signal is GPDMA1_CH11_TCF */
#if defined (HSP1)
#define GPDMA1_TRIGGER_HSP_TRG_OUT0 34U /*!< GPDMA1 HW Trigger signal is HSP_TRG_OUT0 */
#define GPDMA1_TRIGGER_HSP_TRG_OUT1 35U /*!< GPDMA1 HW Trigger signal is HSP_TRG_OUT1 */
#define GPDMA1_TRIGGER_HSP_TRG_OUT2 36U /*!< GPDMA1 HW Trigger signal is HSP_TRG_OUT2 */
#define GPDMA1_TRIGGER_HSP_TRG_OUT3 37U /*!< GPDMA1 HW Trigger signal is HSP_TRG_OUT3 */
#define GPDMA1_TRIGGER_HSP_GPO0 38U /*!< GPDMA1 HW Trigger signal is HSP_GPO0 */
#define GPDMA1_TRIGGER_HSP_GPO1 39U /*!< GPDMA1 HW Trigger signal is HSP_GPO1 */
#define GPDMA1_TRIGGER_HSP_GPO2 40U /*!< GPDMA1 HW Trigger signal is HSP_GPO2 */
#define GPDMA1_TRIGGER_HSP_GPO3 41U /*!< GPDMA1 HW Trigger signal is HSP_GPO3 */
#endif /* HSP1 */
#define GPDMA1_TRIGGER_TIM2_TRGO 42U /*!< GPDMA1 HW Trigger signal is TIM2_TRGO */
#define GPDMA1_TRIGGER_TIM15_TRGO 43U /*!< GPDMA1 HW Trigger signal is TIM15_TRGO */
#if defined (TIM8)
#define GPDMA1_TRIGGER_TIM8_TRGO 44U /*!< GPDMA1 HW Trigger signal is TIM8_TRGO */
#endif /* TIM8 */
#if defined (TIM12)
#define GPDMA1_TRIGGER_TIM12_TRGO 45U /*!< GPDMA1 HW Trigger signal is TIM12_TRGO */
#endif /* TIM12 */
/* Reserved 46U */
/* Reserved 47U */
/* Reserved 48U */
/* Reserved 49U */
/* Reserved 50U */
/* Reserved 51U */
/* Reserved 52U */
/* Reserved 53U */
/* Reserved 54U */
/* Reserved 55U */
/* Reserved 56U */
#define GPDMA1_TRIGGER_ADC2_AWD1 57U /*!< GPDMA1 HW Trigger signal is ADC2_AWD1 */
#define GPDMA1_TRIGGER_ADC1_AWD1 58U /*!< GPDMA1 HW Trigger signal is ADC1_AWD1 */
/**
* @}
*/
/** @defgroup DMAEx_Node_Type DMAEx Node Type
* @brief DMAEx Node Type
* @{
*/
#define DMA_GPDMA_LINEAR_NODE (DMA_CHANNEL_TYPE_GPDMA | DMA_CHANNEL_TYPE_LINEAR_ADDR) /*!< Defines the GPDMA linear addressing node type */
#define DMA_GPDMA_2D_NODE (DMA_CHANNEL_TYPE_GPDMA | DMA_CHANNEL_TYPE_2D_ADDR) /*!< Defines the GPDMA 2 dimension addressing node type */
/**
* @}
*/
/** @defgroup DMAEx_Link_Allocated_Port DMAEx Linked-List Allocated Port
* @brief DMAEx Linked-List Allocated Port
* @{
*/
#define DMA_LINK_ALLOCATED_PORT0 0x00000000U /*!< Link allocated port 0 */
#define DMA_LINK_ALLOCATED_PORT1 DMA_CCR_LAP /*!< Link allocated port 1 */
/**
* @}
*/
/** @defgroup DMAEx_Link_Step_Mode DMAEx Link Step Mode
* @brief DMAEx Link Step Mode
* @{
*/
#define DMA_LSM_FULL_EXECUTION 0x00000000U /*!< Channel is executed for the full linked-list */
#define DMA_LSM_1LINK_EXECUTION DMA_CCR_LSM /*!< Channel is executed once for the current LLI */
/**
* @}
*/
/**
* @}
*/
/* Exported functions ------------------------------------------------------------------------------------------------*/
/** @defgroup DMAEx_Exported_Functions DMAEx Exported Functions
* @brief DMAEx Exported functions
* @{
*/
/** @defgroup DMAEx_Exported_Functions_Group1 Linked-List Initialization and De-Initialization Functions
* @brief Linked-List Initialization and De-Initialization Functions
* @{
*/
HAL_StatusTypeDef HAL_DMAEx_List_Init(DMA_HandleTypeDef *const hdma);
HAL_StatusTypeDef HAL_DMAEx_List_DeInit(DMA_HandleTypeDef *const hdma);
/**
* @}
*/
/** @defgroup DMAEx_Exported_Functions_Group2 Linked-List IO Operation Functions
* @brief Linked-List IO Operation Functions
* @{
*/
HAL_StatusTypeDef HAL_DMAEx_List_Start(DMA_HandleTypeDef *const hdma);
HAL_StatusTypeDef HAL_DMAEx_List_Start_IT(DMA_HandleTypeDef *const hdma);
/**
* @}
*/
/** @defgroup DMAEx_Exported_Functions_Group3 Linked-List Management Functions
* @brief Linked-List Management Functions
* @{
*/
HAL_StatusTypeDef HAL_DMAEx_List_BuildNode(DMA_NodeConfTypeDef const *const pNodeConfig,
DMA_NodeTypeDef *const pNode);
HAL_StatusTypeDef HAL_DMAEx_List_GetNodeConfig(DMA_NodeConfTypeDef *const pNodeConfig,
DMA_NodeTypeDef const *const pNode);
HAL_StatusTypeDef HAL_DMAEx_List_InsertNode(DMA_QListTypeDef *const pQList,
DMA_NodeTypeDef *const pPrevNode,
DMA_NodeTypeDef *const pNewNode);
HAL_StatusTypeDef HAL_DMAEx_List_InsertNode_Head(DMA_QListTypeDef *const pQList,
DMA_NodeTypeDef *const pNewNode);
HAL_StatusTypeDef HAL_DMAEx_List_InsertNode_Tail(DMA_QListTypeDef *const pQList,
DMA_NodeTypeDef *const pNewNode);
HAL_StatusTypeDef HAL_DMAEx_List_RemoveNode(DMA_QListTypeDef *const pQList,
DMA_NodeTypeDef *const pNode);
HAL_StatusTypeDef HAL_DMAEx_List_RemoveNode_Head(DMA_QListTypeDef *const pQList);
HAL_StatusTypeDef HAL_DMAEx_List_RemoveNode_Tail(DMA_QListTypeDef *const pQList);
HAL_StatusTypeDef HAL_DMAEx_List_ReplaceNode(DMA_QListTypeDef *const pQList,
DMA_NodeTypeDef *const pOldNode,
DMA_NodeTypeDef *const pNewNode);
HAL_StatusTypeDef HAL_DMAEx_List_ReplaceNode_Head(DMA_QListTypeDef *const pQList,
DMA_NodeTypeDef *const pNewNode);
HAL_StatusTypeDef HAL_DMAEx_List_ReplaceNode_Tail(DMA_QListTypeDef *const pQList,
DMA_NodeTypeDef *const pNewNode);
HAL_StatusTypeDef HAL_DMAEx_List_ResetQ(DMA_QListTypeDef *const pQList);
HAL_StatusTypeDef HAL_DMAEx_List_InsertQ(DMA_QListTypeDef *const pSrcQList,
DMA_NodeTypeDef const *const pPrevNode,
DMA_QListTypeDef *const pDestQList);
HAL_StatusTypeDef HAL_DMAEx_List_InsertQ_Head(DMA_QListTypeDef *const pSrcQList,
DMA_QListTypeDef *const pDestQList);
HAL_StatusTypeDef HAL_DMAEx_List_InsertQ_Tail(DMA_QListTypeDef *const pSrcQList,
DMA_QListTypeDef *const pDestQList);
HAL_StatusTypeDef HAL_DMAEx_List_SetCircularModeConfig(DMA_QListTypeDef *const pQList,
DMA_NodeTypeDef *const pFirstCircularNode);
HAL_StatusTypeDef HAL_DMAEx_List_SetCircularMode(DMA_QListTypeDef *const pQList);
HAL_StatusTypeDef HAL_DMAEx_List_ClearCircularMode(DMA_QListTypeDef *const pQList);
HAL_StatusTypeDef HAL_DMAEx_List_ConvertQToDynamic(DMA_QListTypeDef *const pQList);
HAL_StatusTypeDef HAL_DMAEx_List_ConvertQToStatic(DMA_QListTypeDef *const pQList);
HAL_StatusTypeDef HAL_DMAEx_List_LinkQ(DMA_HandleTypeDef *const hdma,
DMA_QListTypeDef *const pQList);
HAL_StatusTypeDef HAL_DMAEx_List_UnLinkQ(DMA_HandleTypeDef *const hdma);
/**
* @}
*/
/** @defgroup DMAEx_Exported_Functions_Group4 Data Handling, Repeated Block and Trigger Configuration Functions
* @brief Data Handling, Repeated Block and Trigger Configuration Functions
* @{
*/
HAL_StatusTypeDef HAL_DMAEx_ConfigDataHandling(DMA_HandleTypeDef *const hdma,
DMA_DataHandlingConfTypeDef const *const pConfigDataHandling);
HAL_StatusTypeDef HAL_DMAEx_ConfigTrigger(DMA_HandleTypeDef *const hdma,
DMA_TriggerConfTypeDef const *const pConfigTrigger);
HAL_StatusTypeDef HAL_DMAEx_ConfigRepeatBlock(DMA_HandleTypeDef *const hdma,
DMA_RepeatBlockConfTypeDef const *const pConfigRepeatBlock);
/**
* @}
*/
/** @defgroup DMAEx_Exported_Functions_Group5 Suspend and Resume Operation Functions
* @brief Suspend and Resume Operation Functions
* @{
*/
HAL_StatusTypeDef HAL_DMAEx_Suspend(DMA_HandleTypeDef *const hdma);
HAL_StatusTypeDef HAL_DMAEx_Suspend_IT(DMA_HandleTypeDef *const hdma);
HAL_StatusTypeDef HAL_DMAEx_Resume(DMA_HandleTypeDef *const hdma);
/**
* @}
*/
/** @defgroup DMAEx_Exported_Functions_Group6 FIFO Status Function
* @brief FIFO Status Function
* @{
*/
uint32_t HAL_DMAEx_GetFifoLevel(DMA_HandleTypeDef const *const hdma);
/**
* @}
*/
/**
* @}
*/
/* Private types -----------------------------------------------------------------------------------------------------*/
/** @defgroup DMAEx_Private_Types DMAEx Private Types
* @brief DMAEx Private Types
* @{
*/
/**
* @brief DMA Node in Queue Information Structure Definition.
*/
typedef struct
{
uint32_t cllr_offset; /* CLLR register offset */
uint32_t previousnode_addr; /* Previous node address */
uint32_t currentnode_pos; /* Current node position */
uint32_t currentnode_addr; /* Current node address */
uint32_t nextnode_addr; /* Next node address */
} DMA_NodeInQInfoTypeDef;
/**
* @}
*/
/* Private constants -------------------------------------------------------------------------------------------------*/
/** @defgroup DMAEx_Private_Constants DMAEx Private Constants
* @brief DMAEx Private Constants
* @{
*/
#define DMA_LINKEDLIST (0x0080U) /* DMA channel linked-list mode */
#define DMA_CHANNEL_TYPE_LINEAR_ADDR (0x0001U) /* DMA channel linear addressing mode */
#define DMA_CHANNEL_TYPE_2D_ADDR (0x0002U) /* DMA channel 2D addressing mode */
#define DMA_CHANNEL_TYPE_GPDMA (0x0020U) /* GPDMA channel node */
#define NODE_TYPE_MASK (0x00FFU) /* DMA channel node type */
#define NODE_CLLR_IDX (0x0700U) /* DMA channel node CLLR index mask */
#define NODE_CLLR_IDX_POS (0x0008U) /* DMA channel node CLLR index position */
#define NODE_MAXIMUM_SIZE (0x0008U) /* Amount of registers of the node */
#define NODE_STATIC_FORMAT (0x0000U) /* DMA channel node static format */
#define NODE_DYNAMIC_FORMAT (0x0001U) /* DMA channel node dynamic format */
#define UPDATE_CLLR_POSITION (0x0000U) /* DMA channel update CLLR position */
#define UPDATE_CLLR_VALUE (0x0001U) /* DMA channel update CLLR value */
#define LASTNODE_ISNOT_CIRCULAR (0x0000U) /* Last node is not first circular node */
#define LASTNODE_IS_CIRCULAR (0x0001U) /* Last node is first circular node */
#define QUEUE_TYPE_STATIC (0x0000U) /* DMA channel static queue */
#define QUEUE_TYPE_DYNAMIC (0x0001U) /* DMA channel dynamic queue */
#define NODE_CTR1_DEFAULT_OFFSET (0x0000U) /* CTR1 default offset */
#define NODE_CTR2_DEFAULT_OFFSET (0x0001U) /* CTR2 default offset */
#define NODE_CBR1_DEFAULT_OFFSET (0x0002U) /* CBR1 default offset */
#define NODE_CSAR_DEFAULT_OFFSET (0x0003U) /* CSAR default offset */
#define NODE_CDAR_DEFAULT_OFFSET (0x0004U) /* CDAR default offset */
#define NODE_CTR3_DEFAULT_OFFSET (0x0005U) /* CTR3 2D addressing default offset */
#define NODE_CBR2_DEFAULT_OFFSET (0x0006U) /* CBR2 2D addressing default offset */
#define NODE_CLLR_2D_DEFAULT_OFFSET (0x0007U) /* CLLR 2D addressing default offset */
#define NODE_CLLR_LINEAR_DEFAULT_OFFSET (0x0005U) /* CLLR linear addressing default offset */
#define DMA_BURST_ADDR_OFFSET_MIN (-8192L) /* DMA burst minimum address offset */
#define DMA_BURST_ADDR_OFFSET_MAX (8192L) /* DMA burst maximum address offset */
#define DMA_BLOCK_ADDR_OFFSET_MIN (-65536L) /* DMA block minimum address offset */
#define DMA_BLOCK_ADDR_OFFSET_MAX (65536L) /* DMA block maximum address offset */
/**
* @}
*/
/* Private macros ----------------------------------------------------------------------------------------------------*/
/** @defgroup DMAEx_Private_Macros DMAEx Private Macros
* @brief DMAEx Private Macros
* @{
*/
#define IS_DMA_DATA_ALIGNMENT(ALIGNMENT) \
(((ALIGNMENT) == DMA_DATA_RIGHTALIGN_ZEROPADDED) || \
((ALIGNMENT) == DMA_DATA_RIGHTALIGN_SIGNEXT) || \
((ALIGNMENT) == DMA_DATA_PACK))
#define IS_DMA_DATA_EXCHANGE(EXCHANGE) \
(((EXCHANGE) & (~(DMA_EXCHANGE_SRC_BYTE | DMA_EXCHANGE_DEST_BYTE | DMA_EXCHANGE_DEST_HALFWORD))) == 0U)
#define IS_DMA_REPEAT_COUNT(COUNT) \
(((COUNT) > 0U) && ((COUNT) <= (DMA_CBR1_BRC >> DMA_CBR1_BRC_Pos)))
#define IS_DMA_BURST_ADDR_OFFSET(BURST_ADDR_OFFSET) \
(((BURST_ADDR_OFFSET) > DMA_BURST_ADDR_OFFSET_MIN) && \
((BURST_ADDR_OFFSET) < DMA_BURST_ADDR_OFFSET_MAX))
#define IS_DMA_BLOCK_ADDR_OFFSET(BLOCK_ADDR_OFFSET) \
(((BLOCK_ADDR_OFFSET) > DMA_BLOCK_ADDR_OFFSET_MIN) && \
((BLOCK_ADDR_OFFSET) < DMA_BLOCK_ADDR_OFFSET_MAX))
#define IS_DMA_LINK_ALLOCATED_PORT(LINK_ALLOCATED_PORT) \
(((LINK_ALLOCATED_PORT) & (~(DMA_CCR_LAP))) == 0U)
#define IS_DMA_LINK_STEP_MODE(MODE) \
(((MODE) == DMA_LSM_FULL_EXECUTION) || \
((MODE) == DMA_LSM_1LINK_EXECUTION))
#define IS_DMA_TRIGGER_MODE(MODE) \
(((MODE) == DMA_TRIGM_BLOCK_TRANSFER) || \
((MODE) == DMA_TRIGM_REPEATED_BLOCK_TRANSFER) || \
((MODE) == DMA_TRIGM_LLI_LINK_TRANSFER) || \
((MODE) == DMA_TRIGM_SINGLE_BURST_TRANSFER))
#define IS_DMA_TCEM_LINKEDLIST_EVENT_MODE(MODE) \
(((MODE) == DMA_TCEM_BLOCK_TRANSFER) || \
((MODE) == DMA_TCEM_REPEATED_BLOCK_TRANSFER) || \
((MODE) == DMA_TCEM_EACH_LL_ITEM_TRANSFER) || \
((MODE) == DMA_TCEM_LAST_LL_ITEM_TRANSFER))
#define IS_DMA_LINKEDLIST_MODE(MODE) \
(((MODE) == DMA_LINKEDLIST_NORMAL) || \
((MODE) == DMA_LINKEDLIST_CIRCULAR))
#define IS_DMA_TRIGGER_POLARITY(POLARITY) \
(((POLARITY) == DMA_TRIG_POLARITY_MASKED) || \
((POLARITY) == DMA_TRIG_POLARITY_RISING) || \
((POLARITY) == DMA_TRIG_POLARITY_FALLING))
#define IS_DMA_TRIGGER_SELECTION(TRIGGER) \
((TRIGGER) <= GPDMA1_TRIGGER_ADC1_AWD1)
#define IS_DMA_NODE_TYPE(TYPE) \
(((TYPE) == DMA_GPDMA_LINEAR_NODE) || \
((TYPE) == DMA_GPDMA_2D_NODE))
/**
* @}
*/
/* Private functions -------------------------------------------------------------------------------------------------*/
/** @defgroup DMAEx_Private_Functions DMAEx Private Functions
* @brief DMAEx Private Functions
* @{
*/
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
#ifdef __cplusplus
}
#endif /* __cplusplus */
#endif /* STM32U3xx_HAL_DMA_EX_H */

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/**
******************************************************************************
* @file stm32u3xx_hal_exti.h
* @author MCD Application Team
* @brief Header file of EXTI HAL module.
******************************************************************************
* @attention
*
* Copyright (c) 2023 STMicroelectronics.
* All rights reserved.
*
* This software is licensed under terms that can be found in the LICENSE file
* in the root directory of this software component.
* If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef STM32U3xx_HAL_EXTI_H
#define STM32U3xx_HAL_EXTI_H
#ifdef __cplusplus
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include "stm32u3xx_hal_def.h"
/** @addtogroup STM32U3xx_HAL_Driver
* @{
*/
/** @defgroup EXTI EXTI
* @brief EXTI HAL module driver
* @{
*/
/* Exported types ------------------------------------------------------------*/
/** @defgroup EXTI_Exported_Types EXTI Exported Types
* @{
*/
typedef enum
{
HAL_EXTI_COMMON_CB_ID = 0x00U,
HAL_EXTI_RISING_CB_ID = 0x01U,
HAL_EXTI_FALLING_CB_ID = 0x02U,
} EXTI_CallbackIDTypeDef;
/**
* @brief EXTI Handle structure definition
*/
typedef struct
{
uint32_t Line; /*!< Exti line number */
void (* RisingCallback)(void); /*!< Exti rising callback */
void (* FallingCallback)(void); /*!< Exti falling callback */
} EXTI_HandleTypeDef;
/**
* @brief EXTI Configuration structure definition
*/
typedef struct
{
uint32_t Line; /*!< The Exti line to be configured. This parameter
can be a value of @ref EXTI_Line */
uint32_t Mode; /*!< The Exit Mode to be configured for a core.
This parameter can be a combination of @ref EXTI_Mode */
uint32_t Trigger; /*!< The Exti Trigger to be configured. This parameter
can be a value of @ref EXTI_Trigger */
uint32_t GPIOSel; /*!< The Exti GPIO multiplexer selection to be configured.
This parameter is only possible for line 0 to 15. It
can be a value of @ref EXTI_GPIOSel */
} EXTI_ConfigTypeDef;
/**
* @}
*/
/* Exported constants --------------------------------------------------------*/
/** @defgroup EXTI_Exported_Constants EXTI Exported Constants
* @{
*/
/** @defgroup EXTI_Line EXTI Line
* @{
*/
#define EXTI_LINE_0 (EXTI_GPIO | EXTI_REG1 | 0x00U)
#define EXTI_LINE_1 (EXTI_GPIO | EXTI_REG1 | 0x01U)
#define EXTI_LINE_2 (EXTI_GPIO | EXTI_REG1 | 0x02U)
#define EXTI_LINE_3 (EXTI_GPIO | EXTI_REG1 | 0x03U)
#define EXTI_LINE_4 (EXTI_GPIO | EXTI_REG1 | 0x04U)
#define EXTI_LINE_5 (EXTI_GPIO | EXTI_REG1 | 0x05U)
#define EXTI_LINE_6 (EXTI_GPIO | EXTI_REG1 | 0x06U)
#define EXTI_LINE_7 (EXTI_GPIO | EXTI_REG1 | 0x07U)
#define EXTI_LINE_8 (EXTI_GPIO | EXTI_REG1 | 0x08U)
#define EXTI_LINE_9 (EXTI_GPIO | EXTI_REG1 | 0x09U)
#define EXTI_LINE_10 (EXTI_GPIO | EXTI_REG1 | 0x0AU)
#define EXTI_LINE_11 (EXTI_GPIO | EXTI_REG1 | 0x0BU)
#define EXTI_LINE_12 (EXTI_GPIO | EXTI_REG1 | 0x0CU)
#define EXTI_LINE_13 (EXTI_GPIO | EXTI_REG1 | 0x0DU)
#define EXTI_LINE_14 (EXTI_GPIO | EXTI_REG1 | 0x0EU)
#define EXTI_LINE_15 (EXTI_GPIO | EXTI_REG1 | 0x0FU)
#define EXTI_LINE_16 (EXTI_CONFIG | EXTI_REG1 | 0x10U)
#define EXTI_LINE_17 (EXTI_CONFIG | EXTI_REG1 | 0x11U)
#define EXTI_LINE_18 (EXTI_CONFIG | EXTI_REG1 | 0x12U)
#define EXTI_LINE_19 (EXTI_CONFIG | EXTI_REG1 | 0x13U)
#define EXTI_LINE_20 (EXTI_CONFIG | EXTI_REG1 | 0x14U)
#define EXTI_LINE_21 (EXTI_CONFIG | EXTI_REG1 | 0x15U)
#define EXTI_LINE_22 (EXTI_CONFIG | EXTI_REG1 | 0x16U)
/**
* @}
*/
/** @defgroup EXTI_Mode EXTI Mode
* @{
*/
#define EXTI_MODE_NONE 0x00000000U
#define EXTI_MODE_INTERRUPT 0x00000001U
#define EXTI_MODE_EVENT 0x00000002U
/**
* @}
*/
/** @defgroup EXTI_Trigger EXTI Trigger
* @{
*/
#define EXTI_TRIGGER_NONE 0x00000000U
#define EXTI_TRIGGER_RISING 0x00000001U
#define EXTI_TRIGGER_FALLING 0x00000002U
#define EXTI_TRIGGER_RISING_FALLING (EXTI_TRIGGER_RISING | EXTI_TRIGGER_FALLING)
/**
* @}
*/
/** @defgroup EXTI_GPIOSel EXTI GPIOSel
* @brief
* @{
*/
#define EXTI_GPIOA 0x00000000U
#define EXTI_GPIOB 0x00000001U
#define EXTI_GPIOC 0x00000002U
#define EXTI_GPIOD 0x00000003U
#define EXTI_GPIOE 0x00000004U
#define EXTI_GPIOG 0x00000006U
#define EXTI_GPIOH 0x00000007U
/**
* @}
*/
/** @defgroup EXTI_Line_attributes EXTI line attributes
* @brief EXTI line secure or non-secure and privileged or non-privileged attributes
* @note secure and non-secure attributes are only available from secure state when the system
* implement the security (TZEN=1)
* @{
*/
#define EXTI_LINE_SEC (EXTI_LINE_ATTR_SEC_MASK | 0x00000001U) /*!< Secure line attribute */
#define EXTI_LINE_NSEC (EXTI_LINE_ATTR_SEC_MASK | 0x00000000U) /*!< Non-secure line attribute */
#define EXTI_LINE_PRIV (EXTI_LINE_ATTR_PRIV_MASK | 0x00000002U) /*!< Privileged line attribute */
#define EXTI_LINE_NPRIV (EXTI_LINE_ATTR_PRIV_MASK | 0x00000000U) /*!< Non-privileged line attribute */
/**
* @}
*/
/**
* @}
*/
/* Exported macro ------------------------------------------------------------*/
/* Private constants --------------------------------------------------------*/
/** @defgroup EXTI_Private_Constants EXTI Private Constants
* @{
*/
/**
* @brief EXTI Line property definition
*/
#define EXTI_PROPERTY_SHIFT 24U
#define EXTI_DIRECT (0x01U << EXTI_PROPERTY_SHIFT)
#define EXTI_CONFIG (0x02U << EXTI_PROPERTY_SHIFT)
#define EXTI_GPIO ((0x04U << EXTI_PROPERTY_SHIFT) | EXTI_CONFIG)
#define EXTI_RESERVED (0x08U << EXTI_PROPERTY_SHIFT)
#define EXTI_PROPERTY_MASK (EXTI_DIRECT | EXTI_CONFIG | EXTI_GPIO)
/**
* @brief EXTI Register and bit usage
*/
#define EXTI_REG_SHIFT 16U
#define EXTI_REG1 (0x00U << EXTI_REG_SHIFT)
#define EXTI_REG_MASK EXTI_REG1
#define EXTI_PIN_MASK 0x0000001FU
/**
* @brief EXTI Mask for interrupt & event mode
*/
#define EXTI_MODE_MASK (EXTI_MODE_EVENT | EXTI_MODE_INTERRUPT)
/**
* @brief EXTI Mask for trigger possibilities
*/
#define EXTI_TRIGGER_MASK (EXTI_TRIGGER_RISING | EXTI_TRIGGER_FALLING)
/**
* @brief EXTI Line number
*/
#define EXTI_LINE_NB 23U
/**
* @brief EXTI Mask for secure & privilege attributes
*/
#define EXTI_LINE_ATTR_SEC_MASK 0x100U
#define EXTI_LINE_ATTR_PRIV_MASK 0x200U
/**
* @}
*/
/* Private macros ------------------------------------------------------------*/
/** @defgroup EXTI_Private_Macros EXTI Private Macros
* @{
*/
#define IS_EXTI_LINE(__LINE__) \
((((__LINE__) & ~(EXTI_PROPERTY_MASK | EXTI_REG_MASK | EXTI_PIN_MASK)) == 0x00U) && \
((((__LINE__) & EXTI_PROPERTY_MASK) == EXTI_DIRECT) || \
(((__LINE__) & EXTI_PROPERTY_MASK) == EXTI_CONFIG) || \
(((__LINE__) & EXTI_PROPERTY_MASK) == EXTI_GPIO)) && \
(((__LINE__) & (EXTI_REG_MASK | EXTI_PIN_MASK)) < \
(((EXTI_LINE_NB / 32U) << EXTI_REG_SHIFT) | (EXTI_LINE_NB % 32U))))
#define IS_EXTI_MODE(__LINE__) ((((__LINE__) & EXTI_MODE_MASK) != 0x00U) && \
(((__LINE__) & ~EXTI_MODE_MASK) == 0x00U))
#define IS_EXTI_TRIGGER(__LINE__) (((__LINE__) & ~EXTI_TRIGGER_MASK) == 0x00U)
#define IS_EXTI_PENDING_EDGE(__LINE__) (((__LINE__) == EXTI_TRIGGER_RISING) || \
((__LINE__) == EXTI_TRIGGER_FALLING))
#define IS_EXTI_CONFIG_LINE(__LINE__) (((__LINE__) & EXTI_CONFIG) != 0x00U)
#define IS_EXTI_GPIO_PORT(__PORT__) (((__PORT__) == EXTI_GPIOA) || \
((__PORT__) == EXTI_GPIOB) || \
((__PORT__) == EXTI_GPIOC) || \
((__PORT__) == EXTI_GPIOD) || \
((__PORT__) == EXTI_GPIOE) || \
((__PORT__) == EXTI_GPIOG) || \
((__PORT__) == EXTI_GPIOH))
#define IS_EXTI_GPIO_PIN(__PIN__) ((__PIN__) < 16U)
#if defined (CPU_IN_SECURE_STATE)
#define IS_EXTI_LINE_ATTRIBUTES(__ATTRIBUTES__) \
(((((__ATTRIBUTES__) & EXTI_LINE_SEC) == EXTI_LINE_SEC) || \
(((__ATTRIBUTES__) & EXTI_LINE_NSEC) == EXTI_LINE_NSEC) || \
(((__ATTRIBUTES__) & EXTI_LINE_PRIV) == EXTI_LINE_PRIV) || \
(((__ATTRIBUTES__) & EXTI_LINE_NPRIV) == EXTI_LINE_NPRIV)) && \
(((__ATTRIBUTES__) & ~(EXTI_LINE_SEC|EXTI_LINE_NSEC|EXTI_LINE_PRIV|EXTI_LINE_NPRIV)) == 0U))
#else
#define IS_EXTI_LINE_ATTRIBUTES(__ATTRIBUTES__) (((((__ATTRIBUTES__) & EXTI_LINE_PRIV) == EXTI_LINE_PRIV) || \
(((__ATTRIBUTES__) & EXTI_LINE_NPRIV) == EXTI_LINE_NPRIV)) && \
(((__ATTRIBUTES__) & ~(EXTI_LINE_PRIV|EXTI_LINE_NPRIV)) == 0U))
#endif /* CPU_IN_SECURE_STATE */
/**
* @}
*/
/* Exported functions --------------------------------------------------------*/
/** @defgroup EXTI_Exported_Functions EXTI Exported Functions
* @brief EXTI Exported Functions
* @{
*/
/** @defgroup EXTI_Exported_Functions_Group1 Configuration functions
* @brief Configuration functions
* @{
*/
/* Configuration functions ****************************************************/
HAL_StatusTypeDef HAL_EXTI_SetConfigLine(EXTI_HandleTypeDef *hexti, EXTI_ConfigTypeDef *pExtiConfig);
HAL_StatusTypeDef HAL_EXTI_GetConfigLine(const EXTI_HandleTypeDef *hexti, EXTI_ConfigTypeDef *pExtiConfig);
HAL_StatusTypeDef HAL_EXTI_ClearConfigLine(const EXTI_HandleTypeDef *hexti);
HAL_StatusTypeDef HAL_EXTI_RegisterCallback(EXTI_HandleTypeDef *hexti, EXTI_CallbackIDTypeDef CallbackID,
void (*pPendingCbfn)(void));
HAL_StatusTypeDef HAL_EXTI_GetHandle(EXTI_HandleTypeDef *hexti, uint32_t ExtiLine);
/**
* @}
*/
/** @defgroup EXTI_Exported_Functions_Group2 IO operation functions
* @brief IO operation functions
* @{
*/
/* IO operation functions *****************************************************/
void HAL_EXTI_IRQHandler(const EXTI_HandleTypeDef *hexti);
uint32_t HAL_EXTI_GetPending(const EXTI_HandleTypeDef *hexti, uint32_t Edge);
void HAL_EXTI_ClearPending(const EXTI_HandleTypeDef *hexti, uint32_t Edge);
void HAL_EXTI_GenerateSWI(const EXTI_HandleTypeDef *hexti);
/**
* @}
*/
/** @addtogroup EXTI_Exported_Functions_Group3 EXTI line attributes management functions
* @{
*/
/* EXTI line attributes management functions **********************************/
void HAL_EXTI_ConfigLineAttributes(uint32_t ExtiLine, uint32_t LineAttributes);
HAL_StatusTypeDef HAL_EXTI_GetConfigLineAttributes(uint32_t ExtiLine, uint32_t *pLineAttributes);
#if defined (CPU_IN_SECURE_STATE)
void HAL_EXTI_LockAttributes(void);
uint32_t HAL_EXTI_GetLockAttributes(void);
#endif /* CPU_IN_SECURE_STATE */
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /* STM32U3xx_HAL_EXTI_H */

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/**
******************************************************************************
* @file stm32u3xx_hal_flash_ex.h
* @author MCD Application Team
* @brief Header file of FLASH HAL Extended module.
******************************************************************************
* @attention
*
* Copyright (c) 2023 STMicroelectronics.
* All rights reserved.
*
* This software is licensed under terms that can be found in the LICENSE file
* in the root directory of this software component.
* If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef STM32U3xx_HAL_FLASH_EX_H
#define STM32U3xx_HAL_FLASH_EX_H
#ifdef __cplusplus
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include "stm32u3xx_hal_def.h"
/** @addtogroup STM32U3xx_HAL_Driver
* @{
*/
/** @addtogroup FLASHEx
* @{
*/
/* Private constants ---------------------------------------------------------*/
/** @defgroup FLASHEx_Private_Constants FLASH Extended Private Constants
* @{
*/
#if defined(FLASH_PRIVBB1R5_PRIV0)
#define FLASH_BLOCKBASED_NB_REG (8U) /*!< Number of block-based registers available */
#elif defined(FLASH_PRIVBB1R3_PRIV0)
#define FLASH_BLOCKBASED_NB_REG (4U) /*!< Number of block-based registers available */
#else
#define FLASH_BLOCKBASED_NB_REG (2U) /*!< Number of block-based registers available */
#endif /* defined(STM32U3C5xx) || defined(STM32U3B5xx) */
/**
* @}
*/
/* Exported types ------------------------------------------------------------*/
/** @defgroup FLASHEx_Exported_Types FLASH Exported Types
* @{
*/
/**
* @brief FLASHEx Block-based attributes structure definition
*/
typedef struct
{
uint32_t Bank;
/*!< Selection of the associated bank of Block-based Area.
This parameter must be a value of @ref FLASH_Banks */
uint32_t BBAttributesType;
/*!< Block-Based Attributes type.
This parameter must be a value of @ref FLASHEx_BB_Attributes */
uint32_t BBAttributes_array[FLASH_BLOCKBASED_NB_REG];
/*!< Each bit specifies the block-based attribute configuration of a page:
0 means page non-protected, 1 means page protected.
Protection (secure or privilege) depends on BBAttributesType value */
} FLASH_BBAttributesTypeDef;
#if defined (CPU_IN_SECURE_STATE)
/**
* @brief FLASHEx Extended secure hide area structure definition
*/
typedef struct
{
uint32_t Bank; /*!< Selection of the associated bank of extended secure hide area.
This parameter must be a value of @ref FLASH_Banks */
uint32_t NbPages; /*!< Number of pages of the extended secure hide area.
This parameter must be a value between 0 and (WM end page - WM start page) if no HDP,
or between 0 and (WM end page - HDP end page) if HDP enabled */
} FLASH_HDPExtensionTypeDef;
#endif /* CPU_IN_SECURE_STATE */
/**
* @brief FLASHEx Operation structure definition
*/
typedef struct
{
uint32_t OperationType; /*!< Flash operation Type.
This parameter must be a value of @ref FLASHEx_Operation_Type */
uint32_t FlashArea; /*!< Flash operation memory area.
This parameter must be a value of @ref FLASH_Operation_Area */
uint32_t Address; /*!< Flash operation Address offset.
This parameter is given by bank, and must be a value between 0x0 and 0xFFFF0 */
} FLASH_OperationTypeDef;
/**
* @brief FLASHEx ECC information structure definition
*/
typedef struct
{
uint32_t Area; /*!< Area from which an ECC was detected.
This parameter can be a value of @ref FLASHEx_ECC_Area */
uint32_t Address; /*!< Flash address from which en ECC error was detected.
This parameter must be a value between begin address and end address of the Flash */
uint32_t MasterID; /*!< Master that initiated transfer on which error was detected
This parameter can be a value of @ref FLASHEx_ECC_Master */
} FLASH_EccInfoTypeDef;
/**
* @}
*/
/* Exported constants --------------------------------------------------------*/
/** @defgroup FLASHEx_Exported_Constants FLASH Extended Exported Constants
* @{
*/
/** @defgroup FLASHEx_PRIV_MODE_CFG FLASH privilege mode configuration
* @{
*/
#define FLASH_NSPRIV_GRANTED 0x00000000U \
/*!< access to non-secure Flash registers is granted to privileged or unprivileged access */
#define FLASH_NSPRIV_DENIED FLASH_PRIVCFGR_PRIV \
/*!< access to non-secure Flash registers is denied to non-privilege access */
#define FLASH_SPRIV_GRANTED 0x00000000U \
/*!< access to secure Flash registers is granted to privileged or unprivileged access */
#define FLASH_SPRIV_DENIED FLASH_PRIVCFGR_SPRIV \
/*!< access to secure Flash registers is denied to non-privilege access */
/**
* @}
*/
#if defined (CPU_IN_SECURE_STATE)
/** @defgroup FLASHEx_SEC_INVERSION_CFG FLASH security inversion configuration
* @{
*/
#define FLASH_INV_DISABLE 0x00000000U /*!< Security state of Flash is not inverted */
#define FLASH_INV_ENABLE FLASH_SCR_INV /*!< Security state of Flash is inverted */
/**
* @}
*/
#endif /* CPU_IN_SECURE_STATE */
/** @defgroup FLASHEx_LPM_CFG FLASH LPM configuration
* @{
*/
#define FLASH_LPM_DISABLE 0x00000000U /*!< Flash is in normal read mode */
#define FLASH_LPM_ENABLE FLASH_ACR_LPM /*!< Flash is in low-power read mode */
/**
* @}
*/
/** @defgroup FLASHEx_BB_Attributes FLASH Block-Based Attributes
* @{
*/
#define FLASH_BB_SEC 0x00000001U /*!< Flash Block-Based Security Attributes */
#define FLASH_BB_PRIV 0x00000002U /*!< Flash Block-Based Privilege Attributes */
/**
* @}
*/
/** @defgroup FLASHEx_Operation_Type FLASH Operation Type
* @{
*/
#define FLASH_OPERATION_TYPE_NONE 00000000U /*!< No Flash operation */
#define FLASH_OPERATION_TYPE_DOUBLEWORD FLASH_OPSR_CODE_OP_0 /*!< Single write operation */
#define FLASH_OPERATION_TYPE_BURST FLASH_OPSR_CODE_OP_1 /*!< Burst write operation */
#define FLASH_OPERATION_TYPE_PAGEERASE (FLASH_OPSR_CODE_OP_1 | FLASH_OPSR_CODE_OP_0) /*!< Page erase operation */
#define FLASH_OPERATION_TYPE_BANKERASE FLASH_OPSR_CODE_OP_2 /*!< Bank erase operation */
#define FLASH_OPERATION_TYPE_MASSERASE (FLASH_OPSR_CODE_OP_2 | FLASH_OPSR_CODE_OP_0) /*!< Mass erase operation */
#define FLASH_OPERATION_TYPE_OPTIONCHANGE (FLASH_OPSR_CODE_OP_2 | FLASH_OPSR_CODE_OP_1) /*!< Option change operation */
/**
* @}
*/
/** @defgroup FLASH_Operation_Area FLASH Operation Area
* @{
*/
#define FLASH_OPERATION_AREA_BANK_1 00000000U /*!< Operation in Bank 1 */
#define FLASH_OPERATION_AREA_BANK_2 FLASH_OPSR_BK_OP /*!< Operation in Bank 2 */
#define FLASH_OPERATION_AREA_SYSF FLASH_OPSR_SYSF_OP /*!< Operation in System Flash memory */
/**
* @}
*/
/** @defgroup FLASH_ExtHDP_Protection FLASH Extended HDP Area protection type
* @{
*/
#define FLASH_EXTHDP_NO_PROTECTION 0xA3U /*!< Access to bits configuration and area allowed */
#define FLASH_EXTHDP_ONLY_ACCESS_PROTECTED 0x5CU /*!< Access to area denied and bits configuration allowed */
#define FLASH_EXTHDP_ALL_PROTECTED 0x00U /*!< Access to bits configuration and area denied */
/**
* @}
*/
/** @defgroup FLASHEx_ECC_Area FLASH ECC Area
* @{
*/
#define FLASH_ECC_AREA_USER_BANK1 0x00000000U /*!< FLASH bank 1 area */
#define FLASH_ECC_AREA_USER_BANK2 FLASH_ECCCR_BK_ECC /*!< FLASH bank 2 area */
#define FLASH_ECC_AREA_SYSTEM FLASH_ECCCR_SYSF_ECC /*!< System FLASH area */
/**
* @}
*/
/** @defgroup FLASHEx_ECC_Master FLASH ECC Master
* @{
*/
#define FLASH_ECC_MASTER_CPU1 0x00000000U /*!< ECC error occurs on a CPU1 transaction */
/**
* @}
*/
/**
* @}
*/
/* Exported macro ------------------------------------------------------------*/
/* Exported functions --------------------------------------------------------*/
/** @addtogroup FLASHEx_Exported_Functions
* @{
*/
/* Extended Program operation functions *************************************/
/** @addtogroup FLASHEx_Exported_Functions_Group1
* @{
*/
HAL_StatusTypeDef HAL_FLASHEx_Erase(FLASH_EraseInitTypeDef *pEraseInit, uint32_t *PageError);
HAL_StatusTypeDef HAL_FLASHEx_Erase_IT(FLASH_EraseInitTypeDef *pEraseInit);
HAL_StatusTypeDef HAL_FLASHEx_OBProgram(FLASH_OBProgramInitTypeDef *pOBInit);
void HAL_FLASHEx_OBGetConfig(FLASH_OBProgramInitTypeDef *pOBInit);
HAL_StatusTypeDef HAL_FLASHEx_ConfigBBAttributes(FLASH_BBAttributesTypeDef *pBBAttributes);
void HAL_FLASHEx_GetConfigBBAttributes(FLASH_BBAttributesTypeDef *pBBAttributes);
#if defined (CPU_IN_SECURE_STATE)
void HAL_FLASHEx_EnableSecHideProtection(uint32_t Banks);
HAL_StatusTypeDef HAL_FLASHEx_ConfigHDPExtension(FLASH_HDPExtensionTypeDef *pHDPExtension);
void HAL_FLASHEx_GetConfigHDPExtension(FLASH_HDPExtensionTypeDef *pHDPExtension);
void HAL_FLASHEx_EnableHDPExtensionProtection(uint32_t Banks, uint32_t ProtectionType);
#endif /* CPU_IN_SECURE_STATE */
void HAL_FLASHEx_GetRDPKeyCRC(uint32_t RDPKeyType, uint32_t *CRCKeyValue);
/**
* @}
*/
/** @addtogroup FLASHEx_Exported_Functions_Group2
* @{
*/
void HAL_FLASHEx_ConfigPrivMode(uint32_t PrivMode);
uint32_t HAL_FLASHEx_GetPrivMode(void);
#if defined (CPU_IN_SECURE_STATE)
HAL_StatusTypeDef HAL_FLASHEx_ConfigSecInversion(uint32_t SecInvState);
uint32_t HAL_FLASHEx_GetSecInversion(void);
#endif /* CPU_IN_SECURE_STATE */
HAL_StatusTypeDef HAL_FLASHEx_EnablePowerDown(uint32_t Banks);
HAL_StatusTypeDef HAL_FLASHEx_ConfigLowPowerRead(uint32_t ConfigLPM);
uint32_t HAL_FLASHEx_GetLowPowerRead(void);
void HAL_FLASHEx_GetOperation(FLASH_OperationTypeDef *pFlashOperation);
/**
* @}
*/
/** @addtogroup FLASHEx_Exported_Functions_Group3
* @{
*/
void HAL_FLASHEx_EnableEccCorrectionInterrupt(void);
void HAL_FLASHEx_DisableEccCorrectionInterrupt(void);
void HAL_FLASHEx_GetEccInfo(FLASH_EccInfoTypeDef *pData);
void HAL_FLASHEx_ECCD_IRQHandler(void);
__weak void HAL_FLASHEx_EccDetectionCallback(void);
__weak void HAL_FLASHEx_EccCorrectionCallback(void);
/**
* @}
*/
/**
* @}
*/
/* Private function ----------------------------------------------------------*/
/** @addtogroup FLASHEx_Private_Functions FLASH Extended Private Functions
* @{
*/
void FLASH_PageErase(uint32_t Page, uint32_t Banks);
/**
* @}
*/
/* Private macros ------------------------------------------------------------*/
/** @defgroup FLASHEx_Private_Macros FLASH Private Macros
* @{
*/
#define IS_FLASH_BB_EXCLUSIVE(CFG) (((CFG) == FLASH_BB_SEC) || \
((CFG) == FLASH_BB_PRIV))
#define IS_FLASH_CFGPRIVMODE(CFG) (((CFG) & 0xFFFFFFFCU) == 0U)
#if defined (CPU_IN_SECURE_STATE)
#define IS_FLASH_CFGSECINV(CFG) (((CFG) == FLASH_INV_DISABLE) || \
((CFG) == FLASH_INV_ENABLE))
#endif /* CPU_IN_SECURE_STATE */
#define IS_FLASH_CFGLPM(CFG) (((CFG) == FLASH_LPM_DISABLE) || \
((CFG) == FLASH_LPM_ENABLE))
#define IS_FLASH_EXTHDP_PROTECTION(CFG) (((CFG) == FLASH_EXTHDP_ONLY_ACCESS_PROTECTED) || \
((CFG) == FLASH_EXTHDP_ALL_PROTECTED))
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /* STM32U3xx_HAL_FLASH_EX_H */

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/**
******************************************************************************
* @file stm32u3xx_hal_gpio.h
* @author MCD Application Team
* @brief Header file of GPIO HAL module.
******************************************************************************
* @attention
*
* Copyright (c) 2023 STMicroelectronics.
* All rights reserved.
*
* This software is licensed under terms that can be found in the LICENSE file
* in the root directory of this software component.
* If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef STM32U3xx_HAL_GPIO_H
#define STM32U3xx_HAL_GPIO_H
#ifdef __cplusplus
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include "stm32u3xx_hal_def.h"
/** @addtogroup STM32U3xx_HAL_Driver
* @{
*/
/** @defgroup GPIO GPIO
* @brief GPIO HAL module driver
* @{
*/
/* Exported types ------------------------------------------------------------*/
/** @defgroup GPIO_Exported_Types GPIO Exported Types
* @{
*/
/**
* @brief GPIO Init structure definition
*/
typedef struct
{
uint32_t Pin; /*!< Specifies the GPIO pins to be configured.
This parameter can be any value of @ref GPIO_pins */
uint32_t Mode; /*!< Specifies the operating mode for the selected pins.
This parameter can be a value of @ref GPIO_mode */
uint32_t Pull; /*!< Specifies the Pull-up or Pull-Down activation for the selected pins.
This parameter can be a value of @ref GPIO_pull */
uint32_t Speed; /*!< Specifies the speed for the selected pins.
This parameter can be a value of @ref GPIO_speed */
uint32_t Alternate; /*!< Peripheral to be connected to the selected pins
This parameter can be a value of @ref GPIOEx_Alternate_function_selection */
} GPIO_InitTypeDef;
/**
* @brief GPIO Bit SET and Bit RESET enumeration
*/
typedef enum
{
GPIO_PIN_RESET = 0U,
GPIO_PIN_SET
} GPIO_PinState;
/**
* @}
*/
/* Exported constants --------------------------------------------------------*/
/** @defgroup GPIO_Exported_Constants GPIO Exported Constants
* @{
*/
/** @defgroup GPIO_pins GPIO pins
* @{
*/
#define GPIO_PIN_0 ((uint16_t)0x0001) /* Pin 0 selected */
#define GPIO_PIN_1 ((uint16_t)0x0002) /* Pin 1 selected */
#define GPIO_PIN_2 ((uint16_t)0x0004) /* Pin 2 selected */
#define GPIO_PIN_3 ((uint16_t)0x0008) /* Pin 3 selected */
#define GPIO_PIN_4 ((uint16_t)0x0010) /* Pin 4 selected */
#define GPIO_PIN_5 ((uint16_t)0x0020) /* Pin 5 selected */
#define GPIO_PIN_6 ((uint16_t)0x0040) /* Pin 6 selected */
#define GPIO_PIN_7 ((uint16_t)0x0080) /* Pin 7 selected */
#define GPIO_PIN_8 ((uint16_t)0x0100) /* Pin 8 selected */
#define GPIO_PIN_9 ((uint16_t)0x0200) /* Pin 9 selected */
#define GPIO_PIN_10 ((uint16_t)0x0400) /* Pin 10 selected */
#define GPIO_PIN_11 ((uint16_t)0x0800) /* Pin 11 selected */
#define GPIO_PIN_12 ((uint16_t)0x1000) /* Pin 12 selected */
#define GPIO_PIN_13 ((uint16_t)0x2000) /* Pin 13 selected */
#define GPIO_PIN_14 ((uint16_t)0x4000) /* Pin 14 selected */
#define GPIO_PIN_15 ((uint16_t)0x8000) /* Pin 15 selected */
#define GPIO_PIN_ALL ((uint16_t)0xFFFF) /* All pins selected */
#define GPIO_PIN_MASK (0x0000FFFFU) /* PIN mask for assert test */
/**
* @}
*/
/** @defgroup GPIO_mode GPIO mode
* @brief GPIO Configuration Mode
* Elements values convention: 0x00WX00YZ
* - W : EXTI trigger detection on 3 bits
* - X : EXTI mode (IT or Event) on 2 bits
* - Y : Output type (Push Pull or Open Drain) on 1 bit
* - Z : GPIO mode (Input, Output, Alternate or Analog) on 2 bits
* @{
*/
#define GPIO_MODE_INPUT MODE_INPUT /*!< Input Floating Mode */
#define GPIO_MODE_OUTPUT_PP (MODE_OUTPUT | OUTPUT_PP) /*!< Output Push Pull Mode */
#define GPIO_MODE_OUTPUT_OD (MODE_OUTPUT | OUTPUT_OD) /*!< Output Open Drain Mode */
#define GPIO_MODE_AF_PP (MODE_AF | OUTPUT_PP) /*!< Alternate Function Push Pull Mode */
#define GPIO_MODE_AF_OD (MODE_AF | OUTPUT_OD) /*!< Alternate Function Open Drain Mode */
#define GPIO_MODE_ANALOG MODE_ANALOG /*!< Analog Mode */
#define GPIO_MODE_IT_RISING (MODE_INPUT | EXTI_IT | TRIGGER_RISING) /*!< External Interrupt Mode with Rising edge trigger detection */
#define GPIO_MODE_IT_FALLING (MODE_INPUT | EXTI_IT | TRIGGER_FALLING) /*!< External Interrupt Mode with Falling edge trigger detection */
#define GPIO_MODE_IT_RISING_FALLING (MODE_INPUT | EXTI_IT | TRIGGER_RISING | TRIGGER_FALLING) /*!< External Interrupt Mode with Rising/Falling edge trigger detection */
#define GPIO_MODE_EVT_RISING (MODE_INPUT | EXTI_EVT | TRIGGER_RISING) /*!< External Event Mode with Rising edge trigger detection */
#define GPIO_MODE_EVT_FALLING (MODE_INPUT | EXTI_EVT | TRIGGER_FALLING) /*!< External Event Mode with Falling edge trigger detection */
#define GPIO_MODE_EVT_RISING_FALLING (MODE_INPUT | EXTI_EVT | TRIGGER_RISING | TRIGGER_FALLING) /*!< External Event Mode with Rising/Falling edge trigger detection */
/**
* @}
*/
/** @defgroup GPIO_speed GPIO speed
* @brief GPIO Output Maximum frequency
* @{
*/
#define GPIO_SPEED_FREQ_LOW 0x00000000U /*!< Low speed */
#define GPIO_SPEED_FREQ_MEDIUM 0x00000001U /*!< Medium speed */
#define GPIO_SPEED_FREQ_HIGH 0x00000002U /*!< High speed */
#define GPIO_SPEED_FREQ_VERY_HIGH 0x00000003U /*!< Very high speed */
/**
* @}
*/
/** @defgroup GPIO_pull GPIO pull
* @brief GPIO Pull-Up or Pull-Down Activation
* @{
*/
#define GPIO_NOPULL 0x00000000U /*!< No Pull-up or Pull-down activation */
#define GPIO_PULLUP 0x00000001U /*!< Pull-up activation */
#define GPIO_PULLDOWN 0x00000002U /*!< Pull-down activation */
/**
* @}
*/
/** @defgroup GPIO_attributes GPIO attributes
* @brief GPIO pin secure or non-secure attributes
* @{
*/
#define GPIO_PIN_SEC (0x00000001U) /*!< Secure pin attribute */
#define GPIO_PIN_NSEC (0x00000000U) /*!< Non-secure pin attribute */
/**
* @}
*/
/**
* @}
*/
/* Exported macro ------------------------------------------------------------*/
/** @defgroup GPIO_Exported_Macros GPIO Exported Macros
* @{
*/
/**
* @brief Check whether the specified EXTI line is rising edge asserted or not.
* @param __EXTI_LINE__ specifies the EXTI line to check.
* This parameter can be GPIO_PIN_x where x can be(0..15)
* @retval The new state of __EXTI_LINE__ (SET or RESET).
*/
#define __HAL_GPIO_EXTI_GET_RISING_IT(__EXTI_LINE__) (EXTI->RPR1 & (__EXTI_LINE__))
/**
* @brief Clear the EXTI line rising pending bits.
* @param __EXTI_LINE__ specifies the EXTI lines to clear.
* This parameter can be any combination of GPIO_PIN_x where x can be (0..15)
* @retval None
*/
#define __HAL_GPIO_EXTI_CLEAR_RISING_IT(__EXTI_LINE__) (EXTI->RPR1 = (__EXTI_LINE__))
/**
* @brief Check whether the specified EXTI line is falling edge asserted or not.
* @param __EXTI_LINE__ specifies the EXTI line to check.
* This parameter can be GPIO_PIN_x where x can be(0..15)
* @retval The new state of __EXTI_LINE__ (SET or RESET).
*/
#define __HAL_GPIO_EXTI_GET_FALLING_IT(__EXTI_LINE__) (EXTI->FPR1 & (__EXTI_LINE__))
/**
* @brief Clear the EXTI line falling pending bits.
* @param __EXTI_LINE__ specifies the EXTI lines to clear.
* This parameter can be any combination of GPIO_PIN_x where x can be (0..15)
* @retval None
*/
#define __HAL_GPIO_EXTI_CLEAR_FALLING_IT(__EXTI_LINE__) (EXTI->FPR1 = (__EXTI_LINE__))
/**
* @brief Check whether the specified EXTI line is asserted or not.
* @param __EXTI_LINE__ specifies the EXTI line to check.
* This parameter can be GPIO_PIN_x where x can be(0..15)
* @retval The new state of __EXTI_LINE__ (SET or RESET).
*/
#define __HAL_GPIO_EXTI_GET_IT(__EXTI_LINE__) (__HAL_GPIO_EXTI_GET_RISING_IT(__EXTI_LINE__) || \
__HAL_GPIO_EXTI_GET_FALLING_IT(__EXTI_LINE__))
/**
* @brief Clear the EXTI's line pending bits.
* @param __EXTI_LINE__ specifies the EXTI lines to clear.
* This parameter can be any combination of GPIO_PIN_x where x can be (0..15)
* @retval None
*/
#define __HAL_GPIO_EXTI_CLEAR_IT(__EXTI_LINE__) \
do { \
__HAL_GPIO_EXTI_CLEAR_RISING_IT(__EXTI_LINE__); \
__HAL_GPIO_EXTI_CLEAR_FALLING_IT(__EXTI_LINE__); \
} while(0)
/**
* @brief Generate a Software interrupt on selected EXTI line(s).
* @param __EXTI_LINE__ specifies the EXTI line to be set.
* This parameter can be any combination of GPIO_PIN_x where x can be (0..15)
* @retval None
*/
#define __HAL_GPIO_EXTI_GENERATE_SWIT(__EXTI_LINE__) (EXTI->SWIER1 = (__EXTI_LINE__))
/**
* @}
*/
/* Private macros ------------------------------------------------------------*/
/** @defgroup GPIO_Private_Constants GPIO Private Constants
* @{
*/
#define GPIO_MODE_Pos 0u
#define GPIO_MODE (0x3uL << GPIO_MODE_Pos)
#define MODE_INPUT (0x0uL << GPIO_MODE_Pos)
#define MODE_OUTPUT (0x1uL << GPIO_MODE_Pos)
#define MODE_AF (0x2uL << GPIO_MODE_Pos)
#define MODE_ANALOG (0x3uL << GPIO_MODE_Pos)
#define OUTPUT_TYPE_Pos 4u
#define OUTPUT_TYPE (0x1uL << OUTPUT_TYPE_Pos)
#define OUTPUT_PP (0x0uL << OUTPUT_TYPE_Pos)
#define OUTPUT_OD (0x1uL << OUTPUT_TYPE_Pos)
#define EXTI_MODE_Pos 16u
#define EXTI_MODE (0x3uL << EXTI_MODE_Pos)
#define EXTI_IT (0x1uL << EXTI_MODE_Pos)
#define EXTI_EVT (0x2uL << EXTI_MODE_Pos)
#define TRIGGER_MODE_Pos 20u
#define TRIGGER_MODE (0x7uL << TRIGGER_MODE_Pos)
#define TRIGGER_RISING (0x1uL << TRIGGER_MODE_Pos)
#define TRIGGER_FALLING (0x2uL << TRIGGER_MODE_Pos)
/**
* @}
*/
/** @defgroup GPIO_Private_Macros GPIO Private Macros
* @{
*/
#define IS_GPIO_PIN_ACTION(ACTION) (((ACTION) == GPIO_PIN_RESET) || ((ACTION) == GPIO_PIN_SET))
#define IS_GPIO_PIN(__PIN__) ((((uint32_t)(__PIN__) & GPIO_PIN_MASK) != 0x00u) &&\
(((uint32_t)(__PIN__) & ~GPIO_PIN_MASK) == 0x00u))
#define IS_GPIO_SINGLE_PIN(__PIN__) (((__PIN__) == GPIO_PIN_0) || \
((__PIN__) == GPIO_PIN_1) || \
((__PIN__) == GPIO_PIN_2) || \
((__PIN__) == GPIO_PIN_3) || \
((__PIN__) == GPIO_PIN_4) || \
((__PIN__) == GPIO_PIN_5) || \
((__PIN__) == GPIO_PIN_6) || \
((__PIN__) == GPIO_PIN_7) || \
((__PIN__) == GPIO_PIN_8) || \
((__PIN__) == GPIO_PIN_9) || \
((__PIN__) == GPIO_PIN_10) || \
((__PIN__) == GPIO_PIN_11) || \
((__PIN__) == GPIO_PIN_12) || \
((__PIN__) == GPIO_PIN_13) || \
((__PIN__) == GPIO_PIN_14) || \
((__PIN__) == GPIO_PIN_15))
#define IS_GPIO_COMMON_PIN(__RESETMASK__, __SETMASK__) (((uint32_t)(__RESETMASK__) & (uint32_t)(__SETMASK__)) == 0x00u)
#define IS_GPIO_MODE(__MODE__) (((__MODE__) == GPIO_MODE_INPUT) || \
((__MODE__) == GPIO_MODE_OUTPUT_PP) || \
((__MODE__) == GPIO_MODE_OUTPUT_OD) || \
((__MODE__) == GPIO_MODE_AF_PP) || \
((__MODE__) == GPIO_MODE_AF_OD) || \
((__MODE__) == GPIO_MODE_IT_RISING) || \
((__MODE__) == GPIO_MODE_IT_FALLING) || \
((__MODE__) == GPIO_MODE_IT_RISING_FALLING) || \
((__MODE__) == GPIO_MODE_EVT_RISING) || \
((__MODE__) == GPIO_MODE_EVT_FALLING) || \
((__MODE__) == GPIO_MODE_EVT_RISING_FALLING) || \
((__MODE__) == GPIO_MODE_ANALOG))
#define IS_GPIO_SPEED(__SPEED__) (((__SPEED__) == GPIO_SPEED_FREQ_LOW) || \
((__SPEED__) == GPIO_SPEED_FREQ_MEDIUM) || \
((__SPEED__) == GPIO_SPEED_FREQ_HIGH) || \
((__SPEED__) == GPIO_SPEED_FREQ_VERY_HIGH))
#define IS_GPIO_PULL(__PULL__) (((__PULL__) == GPIO_NOPULL) || \
((__PULL__) == GPIO_PULLUP) || \
((__PULL__) == GPIO_PULLDOWN))
#if defined (CPU_IN_SECURE_STATE)
#define IS_GPIO_PIN_ATTRIBUTES(__ATTRIBUTES__) (((__ATTRIBUTES__) == GPIO_PIN_SEC) || \
((__ATTRIBUTES__) == GPIO_PIN_NSEC))
#endif /* CPU_IN_SECURE_STATE */
/* Include GPIO HAL Extended module */
#include "stm32u3xx_hal_gpio_ex.h"
/* Exported functions --------------------------------------------------------*/
/** @defgroup GPIO_Exported_Functions GPIO Exported Functions
* @brief GPIO Exported Functions
* @{
*/
/** @defgroup GPIO_Exported_Functions_Group1 Initialization/de-initialization functions
* @brief Initialization and Configuration functions
* @{
*/
/* Initialization and de-initialization functions *****************************/
void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, const GPIO_InitTypeDef *GPIO_Init);
void HAL_GPIO_DeInit(GPIO_TypeDef *GPIOx, uint32_t GPIO_Pin);
/**
* @}
*/
/** @defgroup GPIO_Exported_Functions_Group2 IO operation functions
* @brief IO operation functions
* @{
*/
/* IO operation functions *****************************************************/
GPIO_PinState HAL_GPIO_ReadPin(const GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin);
void HAL_GPIO_WritePin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin, GPIO_PinState PinState);
void HAL_GPIO_WriteMultipleStatePin(GPIO_TypeDef *GPIOx, uint16_t PinReset, uint16_t PinSet);
void HAL_GPIO_TogglePin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin);
HAL_StatusTypeDef HAL_GPIO_LockPin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin);
void HAL_GPIO_EnableHighSpeedLowVoltage(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin);
void HAL_GPIO_DisableHighSpeedLowVoltage(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin);
void HAL_GPIO_EXTI_IRQHandler(uint16_t GPIO_Pin);
void HAL_GPIO_EXTI_Rising_Callback(uint16_t GPIO_Pin);
void HAL_GPIO_EXTI_Falling_Callback(uint16_t GPIO_Pin);
/**
* @}
*/
/** @defgroup GPIO_Exported_Functions_Group3 IO attributes management functions
* @{
*/
/* IO attributes management functions *****************************************/
#if defined (CPU_IN_SECURE_STATE)
void HAL_GPIO_ConfigPinAttributes(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin, uint32_t PinAttributes);
#endif /* CPU_IN_SECURE_STATE */
HAL_StatusTypeDef HAL_GPIO_GetConfigPinAttributes(const GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin,
uint32_t *pPinAttributes);
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /* STM32U3xx_HAL_GPIO_H */

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/**
******************************************************************************
* @file stm32u3xx_hal_gpio_ex.h
* @author MCD Application Team
* @brief Header file of GPIO HAL Extended module.
******************************************************************************
* @attention
*
* Copyright (c) 2023 STMicroelectronics.
* All rights reserved.
*
* This software is licensed under terms that can be found in the LICENSE file
* in the root directory of this software component.
* If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef STM32U3xx_HAL_GPIO_EX_H
#define STM32U3xx_HAL_GPIO_EX_H
#ifdef __cplusplus
extern "C" {
#endif /* __cplusplus */
/* Includes ------------------------------------------------------------------*/
#include "stm32u3xx_hal_def.h"
/** @addtogroup STM32U3xx_HAL_Driver
* @{
*/
/** @defgroup GPIOEx GPIOEx
* @brief GPIO Extended HAL module driver
* @{
*/
/* Exported constants --------------------------------------------------------*/
/** @defgroup GPIOEx_Exported_Constants GPIOEx Exported Constants
* @{
*/
/** @defgroup GPIOEx_Alternate_function_selection GPIOEx Alternate function selection
* @{
*/
#if defined(STM32U356xx) || defined(STM32U366xx) || defined(STM32U385xx) || defined(STM32U375xx) || defined(STM32U3B5xx) || defined(STM32U3C5xx)
/**
* @brief AF 0 selection
*/
#define GPIO_AF0_CRS ((uint8_t)0x00) /*!< CRS Alternate Function mapping */
#define GPIO_AF0_LPTIM1 ((uint8_t)0x00) /*!< LPTIM1 Alternate Function mapping */
#define GPIO_AF0_MCO ((uint8_t)0x00) /*!< MCO Alternate Function mapping */
#define GPIO_AF0_PWR ((uint8_t)0x00) /*!< PWR Alternate Function mapping */
#define GPIO_AF0_RTC ((uint8_t)0x00) /*!< RTC Alternate Function mapping */
#define GPIO_AF0_SWJ ((uint8_t)0x00) /*!< SWD and JTAG Alternate Function mapping */
#define GPIO_AF0_TRACE ((uint8_t)0x00) /*!< TRACE Alternate Function mapping */
/**
* @brief AF 1 selection
*/
#define GPIO_AF1_IR ((uint8_t)0x01) /*!< IR Alternate Function mapping */
#define GPIO_AF1_LPTIM1 ((uint8_t)0x01) /*!< LPTIM1 Alternate Function mapping */
#define GPIO_AF1_TIM1 ((uint8_t)0x01) /*!< TIM1 Alternate Function mapping */
#define GPIO_AF1_TIM2 ((uint8_t)0x01) /*!< TIM2 Alternate Function mapping */
#if defined(STM32U3B5xx) || defined(STM32U3C5xx)
#define GPIO_AF1_TIM8 ((uint8_t)0x01) /*!< TIM8 Alternate Function mapping */
#endif /* defined(STM32U3B5xx) || defined(STM32U3C5xx) */
/**
* @brief AF 2 selection
*/
#define GPIO_AF2_LPTIM1 ((uint8_t)0x02) /*!< LPTIM1 Alternate Function mapping */
#define GPIO_AF2_LPTIM2 ((uint8_t)0x02) /*!< LPTIM2 Alternate Function mapping */
#define GPIO_AF2_LPTIM3 ((uint8_t)0x02) /*!< LPTIM3 Alternate Function mapping */
#define GPIO_AF2_TIM1 ((uint8_t)0x02) /*!< TIM1 Alternate Function mapping */
#define GPIO_AF2_TIM2 ((uint8_t)0x02) /*!< TIM2 Alternate Function mapping */
#define GPIO_AF2_TIM3 ((uint8_t)0x02) /*!< TIM3 Alternate Function mapping */
#define GPIO_AF2_TIM4 ((uint8_t)0x02) /*!< TIM4 Alternate Function mapping */
#if defined(STM32U3B5xx) || defined(STM32U3C5xx)
#define GPIO_AF2_TIM12 ((uint8_t)0x02) /*!< TIM12 Alternate Function mapping */
#endif /* defined(STM32U3B5xx) || defined(STM32U3C5xx) */
/**
* @brief AF 3 selection
*/
#define GPIO_AF3_ADF1 ((uint8_t)0x03) /*!< ADF1 Alternate Function mapping */
#define GPIO_AF3_I2C1 ((uint8_t)0x03) /*!< I2C1 Alternate Function mapping */
#if !(defined(STM32U356xx) || defined(STM32U366xx))
#define GPIO_AF3_I2C2 ((uint8_t)0x03) /*!< I2C2 Alternate Function mapping */
#endif /* !(defined(STM32U356xx) || defined(STM32U366xx)) */
#define GPIO_AF3_I3C1 ((uint8_t)0x03) /*!< I3C1 Alternate Function mapping */
#if !(defined(STM32U356xx) || defined(STM32U366xx))
#define GPIO_AF3_I3C2 ((uint8_t)0x03) /*!< I3C2 Alternate Function mapping */
#endif /* !(defined(STM32U356xx) || defined(STM32U366xx)) */
#define GPIO_AF3_OCTOSPI1 ((uint8_t)0x03) /*!< OCTOSPI1 Alternate Function mapping */
#if !(defined(STM32U356xx) || defined(STM32U366xx))
#define GPIO_AF3_SAI1 ((uint8_t)0x03) /*!< SAI1 Alternate Function mapping */
#endif /* !(defined(STM32U356xx) || defined(STM32U366xx)) */
#define GPIO_AF3_SPI2 ((uint8_t)0x03) /*!< SPI2 Alternate Function mapping */
#define GPIO_AF3_TIM1 ((uint8_t)0x03) /*!< TIM1 Alternate Function mapping */
#if defined(STM32U3B5xx) || defined(STM32U3C5xx)
#define GPIO_AF3_TIM8 ((uint8_t)0x03) /*!< TIM8 Alternate Function mapping */
#endif /* defined(STM32U3B5xx) || defined(STM32U3C5xx) */
/**
* @brief AF 4 selection
*/
#define GPIO_AF4_I2C1 ((uint8_t)0x04) /*!< I2C1 Alternate Function mapping */
#if !(defined(STM32U356xx) || defined(STM32U366xx))
#define GPIO_AF4_I2C2 ((uint8_t)0x04) /*!< I2C2 Alternate Function mapping */
#endif /* !(defined(STM32U356xx) || defined(STM32U366xx)) */
#define GPIO_AF4_I2C3 ((uint8_t)0x04) /*!< I2C3 Alternate Function mapping */
#define GPIO_AF4_LPTIM3 ((uint8_t)0x04) /*!< LPTIM3 Alternate Function mapping */
#if defined(STM32U3B5xx) || defined(STM32U3C5xx)
#define GPIO_AF4_USART2 ((uint8_t)0x04) /*!< USART2 Alternate Function mapping */
#endif /* defined(STM32U3B5xx) || defined(STM32U3C5xx) */
/**
* @brief AF 5 selection
*/
#define GPIO_AF5_I2C3 ((uint8_t)0x05) /*!< I2C3 Alternate Function mapping */
#define GPIO_AF5_I3C1 ((uint8_t)0x05) /*!< I3C1 Alternate Function mapping */
#define GPIO_AF5_I3C2 ((uint8_t)0x05) /*!< I3C2 Alternate Function mapping */
#define GPIO_AF5_OCTOSPI1 ((uint8_t)0x05) /*!< OCTOSPI1 Alternate Function mapping */
#define GPIO_AF5_SPI1 ((uint8_t)0x05) /*!< SPI1 Alternate Function mapping */
#define GPIO_AF5_SPI2 ((uint8_t)0x05) /*!< SPI2 Alternate Function mapping */
#define GPIO_AF5_SPI3 ((uint8_t)0x05) /*!< SPI3 Alternate Function mapping */
#if defined(STM32U3B5xx) || defined(STM32U3C5xx)
#define GPIO_AF5_I2C4 ((uint8_t)0x05) /*!< I2C4 Alternate Function mapping */
#define GPIO_AF5_SPI4 ((uint8_t)0x05) /*!< SPI4 Alternate Function mapping */
#endif /* defined(STM32U3B5xx) || defined(STM32U3C5xx) */
/**
* @brief AF 6 selection
*/
#define GPIO_AF6_I3C1 ((uint8_t)0x06) /*!< I3C1 Alternate Function mapping */
#if !(defined(STM32U356xx) || defined(STM32U366xx))
#define GPIO_AF6_I3C2 ((uint8_t)0x06) /*!< I3C2 Alternate Function mapping */
#endif /* !(defined(STM32U356xx) || defined(STM32U366xx)) */
#define GPIO_AF6_SPI3 ((uint8_t)0x06) /*!< SPI3 Alternate Function mapping */
#if defined(STM32U3B5xx) || defined(STM32U3C5xx)
#define GPIO_AF6_SPI4 ((uint8_t)0x06) /*!< SPI4 Alternate Function mapping */
#endif /* defined(STM32U3B5xx) || defined(STM32U3C5xx) */
/**
* @brief AF 7 selection
*/
#define GPIO_AF7_USART1 ((uint8_t)0x07) /*!< USART1 Alternate Function mapping */
#if defined(STM32U3B5xx) || defined(STM32U3C5xx)
#define GPIO_AF7_USART2 ((uint8_t)0x07) /*!< USART2 Alternate Function mapping */
#endif /* defined(STM32U3B5xx) || defined(STM32U3C5xx) */
#define GPIO_AF7_USART3 ((uint8_t)0x07) /*!< USART3 Alternate Function mapping */
/**
* @brief AF 8 selection
*/
#define GPIO_AF8_LPUART1 ((uint8_t)0x08) /*!< LPUART1 Alternate Function mapping */
#define GPIO_AF8_UART4 ((uint8_t)0x08) /*!< UART4 Alternate Function mapping */
#define GPIO_AF8_UART5 ((uint8_t)0x08) /*!< UART5 Alternate Function mapping */
#if !(defined(STM32U356xx) || defined(STM32U366xx))
#define GPIO_AF8_SDMMC1 ((uint8_t)0x08) /*!< SDMMC1 Alternate Function mapping */
#endif /* !(defined(STM32U356xx) || defined(STM32U366xx)) */
/**
* @brief AF 9 selection
*/
#if !(defined(STM32U356xx) || defined(STM32U366xx))
#define GPIO_AF9_FDCAN1 ((uint8_t)0x09) /*!< FDCAN1 Alternate Function mapping */
#endif /* !(defined(STM32U356xx) || defined(STM32U366xx)) */
#define GPIO_AF9_TSC ((uint8_t)0x09) /*!< TSC Alternate Function mapping */
/**
* @brief AF 10 selection
*/
#define GPIO_AF10_CRS ((uint8_t)0x0A) /*!< CRS Alternate Function mapping */
#define GPIO_AF10_OCTOSPI1 ((uint8_t)0x0A) /*!< OCTOSPI1 Alternate Function mapping */
#define GPIO_AF10_USB ((uint8_t)0x0A) /*!< USB Alternate Function mapping */
/**
* @brief AF 11 selection
*/
#define GPIO_AF11_MCO2 ((uint8_t)0x0B) /*!< MCO2 Alternate Function mapping */
#if defined(STM32U3B5xx) || defined(STM32U3C5xx)
#define GPIO_AF11_I2C4 ((uint8_t)0x0B) /*!< I2C4 Alternate Function mapping */
#define GPIO_AF11_FDCAN2 ((uint8_t)0x0B) /*!< FDCAN2 Alternate Function mapping */
#endif /* defined(STM32U3B5xx) || defined(STM32U3C5xx) */
#if defined(STM32U356xx) || defined(STM32U366xx)
#define GPIO_AF11_LCD ((uint8_t)0x0B) /*!< LCD Alternate Function mapping */
#endif /* defined(STM32U356xx) || defined(STM32U366xx) */
/**
* @brief AF 12 selection
*/
#define GPIO_AF12_COMP1 ((uint8_t)0x0C) /*!< COMP1 Alternate Function mapping */
#define GPIO_AF12_COMP2 ((uint8_t)0x0C) /*!< COMP2 Alternate Function mapping */
#if !(defined(STM32U356xx) || defined(STM32U366xx))
#define GPIO_AF12_SDMMC1 ((uint8_t)0x0C) /*!< SDMMC1 Alternate Function mapping */
#endif /* !(defined(STM32U356xx) || defined(STM32U366xx)) */
#define GPIO_AF12_TRACE ((uint8_t)0x0C) /*!< TRACE Alternate Function mapping */
#if defined(STM32U3B5xx) || defined(STM32U3C5xx)
#define GPIO_AF12_I2C4 ((uint8_t)0x0C) /*!< I2C4 Alternate Function mapping */
#endif /* defined(STM32U3B5xx) || defined(STM32U3C5xx) */
/**
* @brief AF 13 selection
*/
#define GPIO_AF13_AUDIOCLK ((uint8_t)0x0D) /*!< AUDIOCLOCK Alternate Function mapping */
#define GPIO_AF13_LPTIM2 ((uint8_t)0x0D) /*!< LPTIM2 Alternate Function mapping */
#define GPIO_AF13_LPTIM4 ((uint8_t)0x0D) /*!< LPTIM4 Alternate Function mapping */
#if !(defined(STM32U356xx) || defined(STM32U366xx))
#define GPIO_AF13_SAI1 ((uint8_t)0x0D) /*!< SAI1 Alternate Function mapping */
#endif /* !(defined(STM32U356xx) || defined(STM32U366xx)) */
#if defined(STM32U3B5xx) || defined(STM32U3C5xx)
#define GPIO_AF13_TIM8 ((uint8_t)0x0D) /*!< TIM8 Alternate Function mapping */
#endif /* defined(STM32U3B5xx) || defined(STM32U3C5xx) */
/**
* @brief AF 14 selection
*/
#define GPIO_AF14_LPTIM2 ((uint8_t)0x0E) /*!< LPTIM2 Alternate Function mapping */
#define GPIO_AF14_LPTIM3 ((uint8_t)0x0E) /*!< LPTIM3 Alternate Function mapping */
#define GPIO_AF14_TIM2 ((uint8_t)0x0E) /*!< TIM2 Alternate Function mapping */
#define GPIO_AF14_TIM15 ((uint8_t)0x0E) /*!< TIM15 Alternate Function mapping */
#define GPIO_AF14_TIM16 ((uint8_t)0x0E) /*!< TIM16 Alternate Function mapping */
#define GPIO_AF14_TIM17 ((uint8_t)0x0E) /*!< TIM17 Alternate Function mapping */
/**
* @brief AF 15 selection
*/
#define GPIO_AF15_EVENTOUT ((uint8_t)0x0F) /*!< EVENTOUT Alternate Function mapping */
#define IS_GPIO_AF(AF) ((AF) <= (uint8_t)0x0F)
#endif /* defined(STM32U385xx) || defined(STM32U375xx) || defined(STM32U3B5xx) || defined(STM32U3C5xx) */
/**
* @}
*/
/**
* @}
*/
/* Exported macro ------------------------------------------------------------*/
/** @defgroup GPIOEx_Exported_Macros GPIOEx Exported Macros
* @{
*/
/** @defgroup GPIOEx_Get_Port_Index GPIOEx Get Port Index
* @{
*/
#if defined(GPIOF)
#define GPIO_GET_INDEX(__GPIOx__) (((__GPIOx__) == (GPIOA))? 0UL :\
((__GPIOx__) == (GPIOB))? 1UL :\
((__GPIOx__) == (GPIOC))? 2UL :\
((__GPIOx__) == (GPIOD))? 3UL :\
((__GPIOx__) == (GPIOE))? 4UL :\
((__GPIOx__) == (GPIOF))? 5UL :\
((__GPIOx__) == (GPIOG))? 6UL :\
((__GPIOx__) == (GPIOH))? 7UL : 16UL)
#elif defined(GPIOG)
#define GPIO_GET_INDEX(__GPIOx__) (((__GPIOx__) == (GPIOA))? 0UL :\
((__GPIOx__) == (GPIOB))? 1UL :\
((__GPIOx__) == (GPIOC))? 2UL :\
((__GPIOx__) == (GPIOD))? 3UL :\
((__GPIOx__) == (GPIOE))? 4UL :\
((__GPIOx__) == (GPIOG))? 6UL :\
((__GPIOx__) == (GPIOH))? 7UL : 16UL)
#else
#define GPIO_GET_INDEX(__GPIOx__) (((__GPIOx__) == (GPIOA))? 0UL :\
((__GPIOx__) == (GPIOB))? 1UL :\
((__GPIOx__) == (GPIOC))? 2UL :\
((__GPIOx__) == (GPIOD))? 3UL :\
((__GPIOx__) == (GPIOE))? 4UL :\
((__GPIOx__) == (GPIOH))? 7UL : 16UL)
#endif /* GPIOF */
/**
* @}
*/
/**
* @}
*/
/* Exported functions --------------------------------------------------------*/
/**
* @}
*/
/**
* @}
*/
#ifdef __cplusplus
}
#endif /* __cplusplus */
#endif /* STM32U3xx_HAL_GPIO_EX_H */

545
Software/Station_SW/Drivers/STM32U3xx_HAL_Driver/Inc/stm32u3xx_hal_gtzc.h Normal file
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@@ -0,0 +1,545 @@
/**
******************************************************************************
* @file stm32u3xx_hal_gtzc.h
* @author MCD Application Team
* @brief Header file of GTZC HAL module.
******************************************************************************
* @attention
*
* Copyright (c) 2023 STMicroelectronics.
* All rights reserved.
*
* This software is licensed under terms that can be found in the LICENSE file
* in the root directory of this software component.
* If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef STM32U3xx_HAL_GTZC_H
#define STM32U3xx_HAL_GTZC_H
#ifdef __cplusplus
extern "C" {
#endif /* __cplusplus */
/* Includes ------------------------------------------------------------------*/
#include "stm32u3xx_hal_def.h"
/** @addtogroup STM32U3xx_HAL_Driver
* @{
*/
#if defined(GTZC_TZSC1) && defined(HAL_GTZC_MODULE_ENABLED)
/** @addtogroup GTZC
* @{
*/
/* Exported types ------------------------------------------------------------*/
/** @defgroup GTZC_Exported_Types GTZC Exported Types
* @{
*/
/*!< Values needed for MPCBB_Attribute_ConfigTypeDef structure sizing */
#define GTZC_MCPBB_NB_VCTR_REG_MAX (12U)
/*!< Maximum number of super-blocks (32 consecutive blocks, block size is 512 bytes) */
#define GTZC_MCPBB_NB_LCK_VCTR_REG_MAX (1U)
/*!< Maximum number of lock configuration registers to manage super-blocks */
typedef struct
{
uint32_t MPCBB_SecConfig_array[GTZC_MCPBB_NB_VCTR_REG_MAX];
/*!< Each element specifies secure access mode for a super-block.
Each bit corresponds to a block inside the super-block.
0 means non-secure, 1 means secure */
uint32_t MPCBB_PrivConfig_array[GTZC_MCPBB_NB_VCTR_REG_MAX];
/*!< Each element specifies privilege access mode for a super-block.
Each bit corresponds to a block inside the super-block.
0 means non-privilege, 1 means privilege */
uint32_t MPCBB_LockConfig_array[GTZC_MCPBB_NB_LCK_VCTR_REG_MAX];
/*!< Each bit specifies the lock configuration of a super-block (32 blocks).
0 means unlocked, 1 means locked */
} MPCBB_Attribute_ConfigTypeDef;
typedef struct
{
uint32_t SecureRWIllegalMode; /*!< Secure read/write illegal access
field. It can be a value of @ref GTZC_MPCBB_SecureRWIllegalMode */
uint32_t InvertSecureState; /*!< Default security state field (can be inverted or not).
It can be a value of @ref GTZC_MPCBB_InvertSecureState */
MPCBB_Attribute_ConfigTypeDef AttributeConfig; /*!< MPCBB attribute configuration sub-structure */
} MPCBB_ConfigTypeDef;
/**
* @}
*/
/* Private constants ---------------------------------------------------------*/
/** @defgroup GTZC_Private_Constants GTZC Private Constants
* @{
*/
/** @defgroup GTZC_Private_PeriphId_composition GTZC Peripheral identifier composition
* @{
*/
/* composition definition for Peripheral identifier parameter (PeriphId) used in
* HAL_GTZC_TZSC_ConfigPeriphAttributes() and HAL_GTZC_TZSC_GetConfigPeriphAttributes()
* functions and also in all HAL_GTZC_TZIC relative functions.
* Bitmap Definition
* bits[31:28] Field "register". Define the register index a peripheral belongs to.
* Each bit is dedicated to a single register.
* bit[5] Field "all peripherals". If this bit is set then the PeriphId targets
* all peripherals within all registers.
* bits[4:0] Field "bit position". Define the bit position within the
* register dedicated to the peripheral, value from 0 to 31.
*/
#define GTZC_PERIPH_REG_SHIFT (28U)
#define GTZC_PERIPH_REG (0xF0000000U)
#define GTZC_PERIPH_REG1 (0x00000000U)
#define GTZC_PERIPH_REG2 (0x10000000U)
#define GTZC_PERIPH_REG3 (0x20000000U)
#define GTZC_PERIPH_REG4 (0x30000000U)
#define GTZC_PERIPH_BIT_POSITION (0x0000001FU)
/**
* @}
*/
/** @defgroup GTZC_Private_Attributes_Msk GTZC Attributes Masks
* @{
*/
#define GTZC_ATTR_SEC_MASK 0x100U
#define GTZC_ATTR_PRIV_MASK 0x200U
/**
* @}
*/
/**
* @}
*/
/* Exported constants --------------------------------------------------------*/
/** @defgroup GTZC_Exported_Constants GTZC Exported Constants
* @{
*/
/** @defgroup GTZC_MPCBB_SecureRWIllegalMode GTZC MPCBB SRWILADIS values
* @{
*/
#define GTZC_MPCBB_SRWILADIS_ENABLE (0U)
#define GTZC_MPCBB_SRWILADIS_DISABLE (GTZC_MPCBB_CR_SRWILADIS_Msk)
/**
* @}
*/
/** @defgroup GTZC_MPCBB_InvertSecureState GTZC MPCBB INVSECSTATE values
* @{
*/
#define GTZC_MPCBB_INVSECSTATE_NOT_INVERTED (0U)
#define GTZC_MPCBB_INVSECSTATE_INVERTED (GTZC_MPCBB_CR_INVSECSTATE_Msk)
/**
* @}
*/
/** @defgroup GTZC_TZSC_TZIC_PeriphId GTZC TZSC and TZIC Peripheral identifier values
* @{
*/
/* GTZC */
#define GTZC_PERIPH_TIM2 (GTZC_PERIPH_REG1 | GTZC_CFGR1_TIM2_Pos)
#define GTZC_PERIPH_TIM3 (GTZC_PERIPH_REG1 | GTZC_CFGR1_TIM3_Pos)
#define GTZC_PERIPH_TIM4 (GTZC_PERIPH_REG1 | GTZC_CFGR1_TIM4_Pos)
#define GTZC_PERIPH_TIM6 (GTZC_PERIPH_REG1 | GTZC_CFGR1_TIM6_Pos)
#define GTZC_PERIPH_TIM7 (GTZC_PERIPH_REG1 | GTZC_CFGR1_TIM7_Pos)
#define GTZC_PERIPH_WWDG (GTZC_PERIPH_REG1 | GTZC_CFGR1_WWDG_Pos)
#define GTZC_PERIPH_IWDG (GTZC_PERIPH_REG1 | GTZC_CFGR1_IWDG_Pos)
#define GTZC_PERIPH_SPI2 (GTZC_PERIPH_REG1 | GTZC_CFGR1_SPI2_Pos)
#if defined(USART2)
#define GTZC_PERIPH_USART2 (GTZC_PERIPH_REG1 | GTZC_CFGR1_USART2_Pos)
#endif /* USART2 */
#define GTZC_PERIPH_USART3 (GTZC_PERIPH_REG1 | GTZC_CFGR1_USART3_Pos)
#define GTZC_PERIPH_UART4 (GTZC_PERIPH_REG1 | GTZC_CFGR1_UART4_Pos)
#define GTZC_PERIPH_UART5 (GTZC_PERIPH_REG1 | GTZC_CFGR1_UART5_Pos)
#define GTZC_PERIPH_I2C1 (GTZC_PERIPH_REG1 | GTZC_CFGR1_I2C1_Pos)
#if defined(I2C2)
#define GTZC_PERIPH_I2C2 (GTZC_PERIPH_REG1 | GTZC_CFGR1_I2C2_Pos)
#endif /* I2C2 */
#define GTZC_PERIPH_CRS (GTZC_PERIPH_REG1 | GTZC_CFGR1_CRS_Pos)
#if defined(I2C4)
#define GTZC_PERIPH_I2C4 (GTZC_PERIPH_REG1 | GTZC_CFGR1_I2C4_Pos)
#endif /* I2C4 */
#define GTZC_PERIPH_LPTIM2 (GTZC_PERIPH_REG1 | GTZC_CFGR1_LPTIM2_Pos)
#if defined(FDCAN1)
#define GTZC_PERIPH_FDCAN1 (GTZC_PERIPH_REG1 | GTZC_CFGR1_FDCAN1_Pos)
#endif /* FDCAN1 */
#if defined(FDCAN2)
#define GTZC_PERIPH_FDCAN2 (GTZC_PERIPH_REG1 | GTZC_CFGR1_FDCAN2_Pos)
#endif /* FDCAN2 */
#define GTZC_PERIPH_SPI3 (GTZC_PERIPH_REG1 | GTZC_CFGR1_SPI3_Pos)
#define GTZC_PERIPH_I3C1 (GTZC_PERIPH_REG1 | GTZC_CFGR1_I3C1_Pos)
#define GTZC_PERIPH_OPAMP (GTZC_PERIPH_REG1 | GTZC_CFGR1_OPAMP_Pos)
#define GTZC_PERIPH_VREFBUF (GTZC_PERIPH_REG1 | GTZC_CFGR1_VREFBUF_Pos)
#if defined(SPI4)
#define GTZC_PERIPH_SPI4 (GTZC_PERIPH_REG1 | GTZC_CFGR1_SPI4_Pos)
#endif /* SPI4 */
#define GTZC_PERIPH_TIM1 (GTZC_PERIPH_REG2 | GTZC_CFGR2_TIM1_Pos)
#define GTZC_PERIPH_SPI1 (GTZC_PERIPH_REG2 | GTZC_CFGR2_SPI1_Pos)
#if defined(TIM8)
#define GTZC_PERIPH_TIM8 (GTZC_PERIPH_REG2 | GTZC_CFGR2_TIM8_Pos)
#endif /* TIM8 */
#define GTZC_PERIPH_USART1 (GTZC_PERIPH_REG2 | GTZC_CFGR2_USART1_Pos)
#define GTZC_PERIPH_TIM15 (GTZC_PERIPH_REG2 | GTZC_CFGR2_TIM15_Pos)
#define GTZC_PERIPH_TIM16 (GTZC_PERIPH_REG2 | GTZC_CFGR2_TIM16_Pos)
#define GTZC_PERIPH_TIM17 (GTZC_PERIPH_REG2 | GTZC_CFGR2_TIM17_Pos)
#if defined(SAI1)
#define GTZC_PERIPH_SAI1 (GTZC_PERIPH_REG2 | GTZC_CFGR2_SAI1_Pos)
#endif /* SAI1 */
#if defined(TIM12)
#define GTZC_PERIPH_TIM12 (GTZC_PERIPH_REG2 | GTZC_CFGR2_TIM12_Pos)
#endif /* TIM12 */
#define GTZC_PERIPH_USB (GTZC_PERIPH_REG2 | GTZC_CFGR2_USB_Pos)
#if defined(I3C2)
#define GTZC_PERIPH_I3C2 (GTZC_PERIPH_REG2 | GTZC_CFGR2_I3C2_Pos)
#endif /* I3C2 */
#define GTZC_PERIPH_LPUART1 (GTZC_PERIPH_REG2 | GTZC_CFGR2_LPUART1_Pos)
#define GTZC_PERIPH_I2C3 (GTZC_PERIPH_REG2 | GTZC_CFGR2_I2C3_Pos)
#define GTZC_PERIPH_LPTIM1 (GTZC_PERIPH_REG2 | GTZC_CFGR2_LPTIM1_Pos)
#define GTZC_PERIPH_LPTIM3 (GTZC_PERIPH_REG2 | GTZC_CFGR2_LPTIM3_Pos)
#define GTZC_PERIPH_LPTIM4 (GTZC_PERIPH_REG2 | GTZC_CFGR2_LPTIM4_Pos)
#define GTZC_PERIPH_COMP (GTZC_PERIPH_REG2 | GTZC_CFGR2_COMP_Pos)
#if defined(LCD)
#define GTZC_PERIPH_LCD (GTZC_PERIPH_REG2 | GTZC_CFGR2_LCD_Pos)
#endif /* LCD */
#define GTZC_PERIPH_CRC (GTZC_PERIPH_REG3 | GTZC_CFGR3_CRC_Pos)
#define GTZC_PERIPH_TSC (GTZC_PERIPH_REG3 | GTZC_CFGR3_TSC_Pos)
#define GTZC_PERIPH_ICACHE_REG (GTZC_PERIPH_REG3 | GTZC_CFGR3_ICACHE_REG_Pos)
#define GTZC_PERIPH_ADC12 (GTZC_PERIPH_REG3 | GTZC_CFGR3_ADC12_Pos)
#if defined(AES)
#define GTZC_PERIPH_AES (GTZC_PERIPH_REG3 | GTZC_CFGR3_AES_Pos)
#endif /* AES */
#define GTZC_PERIPH_HASH (GTZC_PERIPH_REG3 | GTZC_CFGR3_HASH_Pos)
#define GTZC_PERIPH_RNG (GTZC_PERIPH_REG3 | GTZC_CFGR3_RNG_Pos)
#if defined(PKA)
#define GTZC_PERIPH_PKA (GTZC_PERIPH_REG3 | GTZC_CFGR3_PKA_Pos)
#endif /* PKA */
#if defined(SAES)
#define GTZC_PERIPH_SAES (GTZC_PERIPH_REG3 | GTZC_CFGR3_SAES_Pos)
#endif /* SAES */
#if defined(CCB)
#define GTZC_PERIPH_CCB (GTZC_PERIPH_REG3 | GTZC_CFGR3_CCB_Pos)
#endif /* CCB */
#define GTZC_PERIPH_SDMMC1 (GTZC_PERIPH_REG3 | GTZC_CFGR3_SDMMC1_Pos)
#define GTZC_PERIPH_OCTOSPI1_REG (GTZC_PERIPH_REG3 | GTZC_CFGR3_OCTOSPI1_REG_Pos)
#define GTZC_PERIPH_RAMCFG (GTZC_PERIPH_REG3 | GTZC_CFGR3_RAMCFG_Pos)
#define GTZC_PERIPH_DAC1 (GTZC_PERIPH_REG3 | GTZC_CFGR3_DAC1_Pos)
#define GTZC_PERIPH_ADF1 (GTZC_PERIPH_REG3 | GTZC_CFGR3_ADF1_Pos)
#if defined(HSP1)
#define GTZC_PERIPH_HSP1 (GTZC_PERIPH_REG3 | GTZC_CFGR3_HSP1_Pos)
#endif /* HSP1 */
#define GTZC_PERIPH_GPDMA1 (GTZC_PERIPH_REG4 | GTZC_CFGR4_GPDMA1_Pos)
#define GTZC_PERIPH_FLASH_REG (GTZC_PERIPH_REG4 | GTZC_CFGR4_FLASH_REG_Pos)
#define GTZC_PERIPH_FLASH (GTZC_PERIPH_REG4 | GTZC_CFGR4_FLASH_Pos)
#define GTZC_PERIPH_PWR (GTZC_PERIPH_REG4 | GTZC_CFGR4_PWR_Pos)
#define GTZC_PERIPH_RCC (GTZC_PERIPH_REG4 | GTZC_CFGR4_RCC_Pos)
#define GTZC_PERIPH_SYSCFG (GTZC_PERIPH_REG4 | GTZC_CFGR4_SYSCFG_Pos)
#define GTZC_PERIPH_EXTI (GTZC_PERIPH_REG4 | GTZC_CFGR4_EXTI_Pos)
#define GTZC_PERIPH_RTC (GTZC_PERIPH_REG4 | GTZC_CFGR4_RTC_Pos)
#define GTZC_PERIPH_TAMP (GTZC_PERIPH_REG4 | GTZC_CFGR4_TAMP_Pos)
#define GTZC_PERIPH_TZSC (GTZC_PERIPH_REG4 | GTZC_CFGR4_TZSC_Pos)
#define GTZC_PERIPH_TZIC (GTZC_PERIPH_REG4 | GTZC_CFGR4_TZIC_Pos)
#define GTZC_PERIPH_SRAM1 (GTZC_PERIPH_REG4 | GTZC_CFGR4_SRAM1_Pos)
#define GTZC_PERIPH_MPCBB1_REG (GTZC_PERIPH_REG4 | GTZC_CFGR4_MPCBB1_REG_Pos)
#define GTZC_PERIPH_SRAM2 (GTZC_PERIPH_REG4 | GTZC_CFGR4_SRAM2_Pos)
#define GTZC_PERIPH_MPCBB2_REG (GTZC_PERIPH_REG4 | GTZC_CFGR4_MPCBB2_REG_Pos)
#if defined(SRAM3_BASE)
#define GTZC_PERIPH_SRAM3 (GTZC_PERIPH_REG4 | GTZC_CFGR4_SRAM2_Pos)
#define GTZC_PERIPH_MPCBB3_REG (GTZC_PERIPH_REG4 | GTZC_CFGR4_MPCBB2_REG_Pos)
#endif /* SRAM3_BASE */
#if defined(SRAM4_BASE)
#define GTZC_PERIPH_SRAM4 (GTZC_PERIPH_REG4 | GTZC_CFGR4_SRAM2_Pos)
#define GTZC_PERIPH_MPCBB4_REG (GTZC_PERIPH_REG4 | GTZC_CFGR4_MPCBB2_REG_Pos)
#endif /* SRAM4_BASE */
#define GTZC_PERIPH_ALL (0x00000020U)
/* Note that two maximum values are also defined here:
* - max number of securable AHB/APB peripherals or masters
* (used in TZSC sub-block)
* - max number of securable and TrustZone-aware AHB/APB peripherals or masters
* (used in TZIC sub-block)
*/
#if defined(HSP1)
#define GTZC_TZSC_PERIPH_NUMBER (HAL_GTZC_GET_ARRAY_INDEX(GTZC_PERIPH_HSP1) + 1U)
#elif defined(ADF1)
#define GTZC_TZSC_PERIPH_NUMBER (HAL_GTZC_GET_ARRAY_INDEX(GTZC_PERIPH_ADF1) + 1U)
#else
#define GTZC_TZSC_PERIPH_NUMBER (HAL_GTZC_GET_ARRAY_INDEX(GTZC_PERIPH_DAC1) + 1U)
#endif /* HSP1 */
#if defined(SRAM4_BASE)
#define GTZC_TZIC_PERIPH_NUMBER (HAL_GTZC_GET_ARRAY_INDEX(GTZC_PERIPH_MPCBB4_REG) + 1U)
#else
#define GTZC_TZIC_PERIPH_NUMBER (HAL_GTZC_GET_ARRAY_INDEX(GTZC_PERIPH_MPCBB2_REG) + 1U)
#endif /* SRAM4_BASE */
/**
* @}
*/
/** @defgroup GTZC_TZSC_PeriphAttributes GTZC TZSC peripheral attribute values
* @{
*/
/* user-oriented definitions for attribute parameter (PeriphAttributes) used in
* HAL_GTZC_TZSC_ConfigPeriphAttributes() and HAL_GTZC_TZSC_GetConfigPeriphAttributes()
* functions
*/
#define GTZC_TZSC_PERIPH_SEC (GTZC_ATTR_SEC_MASK | 0x00000001U) /*!< Secure attribute */
#define GTZC_TZSC_PERIPH_NSEC (GTZC_ATTR_SEC_MASK | 0x00000000U) /*!< Non-secure attribute */
#define GTZC_TZSC_PERIPH_PRIV (GTZC_ATTR_PRIV_MASK | 0x00000002U) /*!< Privilege attribute */
#define GTZC_TZSC_PERIPH_NPRIV (GTZC_ATTR_PRIV_MASK | 0x00000000U) /*!< Non-privilege attribute */
/**
* @}
*/
/** @defgroup GTZC_TZSC_Lock GTZC TZSC lock values
* @{
*/
/* user-oriented definitions for HAL_GTZC_TZSC_GetLock() returned value */
#define GTZC_TZSC_LOCK_OFF (0U)
#define GTZC_TZSC_LOCK_ON GTZC_TZSC_CR_LCK_Msk
/**
* @}
*/
/** @defgroup GTZC_MPCBB_Group GTZC MPCBB values
* @{
*/
/* user-oriented definitions for MPCBB */
#define GTZC_MPCBB_BLOCK_SIZE 0x200U /* 512 Bytes */
#define GTZC_MPCBB_SUPERBLOCK_SIZE (GTZC_MPCBB_BLOCK_SIZE * 32U) /* 16 KBytes */
#define GTZC_MCPBB_SUPERBLOCK_UNLOCKED (0U)
#define GTZC_MCPBB_SUPERBLOCK_LOCKED (1U)
#define GTZC_MCPBB_BLOCK_NSEC (GTZC_ATTR_SEC_MASK | 0U)
#define GTZC_MCPBB_BLOCK_SEC (GTZC_ATTR_SEC_MASK | 1U)
#define GTZC_MCPBB_BLOCK_NPRIV (GTZC_ATTR_PRIV_MASK | 0U)
#define GTZC_MCPBB_BLOCK_PRIV (GTZC_ATTR_PRIV_MASK | 2U)
/* user-oriented definitions for HAL_GTZC_MPCBB_GetLock() returned value */
#define GTZC_MCPBB_LOCK_OFF (0U)
#define GTZC_MCPBB_LOCK_ON (1U)
/**
* @}
*/
/** @defgroup GTZC_TZIC_Flag GTZC TZIC flag values
* @{
*/
/* user-oriented definitions for HAL_GTZC_TZIC_GetFlag() flag parameter */
#define GTZC_TZIC_NO_ILA_EVENT (0U)
#define GTZC_TZIC_ILA_EVENT_PENDING (1U)
/**
* @}
*/
/**
* @}
*/
/* Private macros ------------------------------------------------------------*/
/** @defgroup GTZC_Private_Macros GTZC Private Macros
* @{
*/
/* retrieve information to access register for a specific PeriphId */
#define GTZC_GET_REG_INDEX(periph_id)\
(((periph_id) & GTZC_PERIPH_REG) >> GTZC_PERIPH_REG_SHIFT)
#define GTZC_GET_REG_INDEX_IN_INSTANCE(periph_id)\
((((periph_id) & GTZC_PERIPH_REG) <= GTZC_PERIPH_REG4) ? \
(((periph_id) & GTZC_PERIPH_REG) >> GTZC_PERIPH_REG_SHIFT) : \
((((periph_id) & GTZC_PERIPH_REG) >> GTZC_PERIPH_REG_SHIFT) - 4U))
#define GTZC_GET_PERIPH_POS(periph_id) ((periph_id) & GTZC_PERIPH_BIT_POSITION)
#if defined(CPU_IN_SECURE_STATE)
#define IS_GTZC_BASE_ADDRESS(mem, address)\
( ( (uint32_t)(address) == (uint32_t)GTZC_BASE_ADDRESS_NS(mem) ) || \
( (uint32_t)(address) == (uint32_t)GTZC_BASE_ADDRESS_S(mem) ) )
#else
#define IS_GTZC_BASE_ADDRESS(mem, address)\
( (uint32_t)(address) == (uint32_t)GTZC_BASE_ADDRESS_NS(mem) )
#endif /* CPU_IN_SECURE_STATE */
/* MISRA C:2012 Rule-20.10 deviation granted to use the definition of */
/* GTZC_MEM_SIZE(), GTZC_BASE_ADDRESS_S() and GTZC_BASE_ADDRESS_NS() */
#define GTZC_MEM_SIZE(mem)\
( mem ## _SIZE )
#define GTZC_BASE_ADDRESS_S(mem)\
( mem ## _BASE_S )
#define GTZC_BASE_ADDRESS_NS(mem)\
( mem ## _BASE_NS )
/**
* @}
*/
/* Exported macros -----------------------------------------------------------*/
/** @defgroup GTZC_Exported_Macros GTZC Exported Macros
* @{
*/
/* user-oriented macro to get array index of a specific PeriphId
* in case of GTZC_PERIPH_ALL usage in the two following functions:
* HAL_GTZC_TZSC_ConfigPeriphAttributes() and HAL_GTZC_TZSC_GetConfigPeriphAttributes()
*/
#define HAL_GTZC_GET_ARRAY_INDEX(periph_id) \
((GTZC_GET_REG_INDEX((periph_id)) * 32U) + GTZC_GET_PERIPH_POS((periph_id)))
#define HAL_GTZC_TZSC_GET_ARRAY_INDEX(periph_id) \
(((GTZC_GET_REG_INDEX(periph_id) * 32U) + GTZC_GET_PERIPH_POS(periph_id)))
#define HAL_GTZC_TZIC_GET_ARRAY_INDEX(periph_id) \
((GTZC_GET_REG_INDEX((periph_id)) * 32U) + GTZC_GET_PERIPH_POS((periph_id)))
/**
* @}
*/
/* Exported functions --------------------------------------------------------*/
/** @addtogroup GTZC_Exported_Functions
* @{
*/
/** @addtogroup GTZC_Exported_Functions_Group1
* @brief TZSC Initialization and Configuration functions
* @{
*/
HAL_StatusTypeDef HAL_GTZC_TZSC_ConfigPeriphAttributes(uint32_t PeriphId,
uint32_t PeriphAttributes);
HAL_StatusTypeDef HAL_GTZC_TZSC_GetConfigPeriphAttributes(uint32_t PeriphId,
uint32_t *PeriphAttributes);
/**
* @}
*/
#if defined(CPU_IN_SECURE_STATE)
/** @addtogroup GTZC_Exported_Functions_Group3
* @brief TZSC and TZSC-MPCWM Lock functions
* @{
*/
void HAL_GTZC_TZSC_Lock(GTZC_TZSC_TypeDef *TZSC_Instance);
uint32_t HAL_GTZC_TZSC_GetLock(const GTZC_TZSC_TypeDef *TZSC_Instance);
/**
* @}
*/
#endif /* CPU_IN_SECURE_STATE */
/** @addtogroup GTZC_Exported_Functions_Group4
* @brief MPCBB Initialization and Configuration functions
* @{
*/
HAL_StatusTypeDef HAL_GTZC_MPCBB_ConfigMem(uint32_t MemBaseAddress,
const MPCBB_ConfigTypeDef *pMPCBB_desc);
HAL_StatusTypeDef HAL_GTZC_MPCBB_GetConfigMem(uint32_t MemBaseAddress,
MPCBB_ConfigTypeDef *pMPCBB_desc);
HAL_StatusTypeDef HAL_GTZC_MPCBB_ConfigMemAttributes(uint32_t MemAddress,
uint32_t NbBlocks,
const uint32_t *pMemAttributes);
HAL_StatusTypeDef HAL_GTZC_MPCBB_GetConfigMemAttributes(uint32_t MemAddress,
uint32_t NbBlocks,
uint32_t *pMemAttributes);
#if defined(CPU_IN_SECURE_STATE)
HAL_StatusTypeDef HAL_GTZC_MPCBB_LockConfig(uint32_t MemAddress,
uint32_t NbSuperBlocks,
const uint32_t *pLockAttributes);
HAL_StatusTypeDef HAL_GTZC_MPCBB_GetLockConfig(uint32_t MemAddress,
uint32_t NbSuperBlocks,
uint32_t *pLockAttributes);
HAL_StatusTypeDef HAL_GTZC_MPCBB_Lock(uint32_t MemBaseAddress);
HAL_StatusTypeDef HAL_GTZC_MPCBB_GetLock(uint32_t MemBaseAddress,
uint32_t *pLockState);
#endif /* CPU_IN_SECURE_STATE */
/**
* @}
*/
#if defined(CPU_IN_SECURE_STATE)
/** @addtogroup GTZC_Exported_Functions_Group5
* @brief TZIC functions
* @{
*/
HAL_StatusTypeDef HAL_GTZC_TZIC_DisableIT(uint32_t PeriphId);
HAL_StatusTypeDef HAL_GTZC_TZIC_EnableIT(uint32_t PeriphId);
HAL_StatusTypeDef HAL_GTZC_TZIC_GetFlag(uint32_t PeriphId, uint32_t *pFlag);
HAL_StatusTypeDef HAL_GTZC_TZIC_ClearFlag(uint32_t PeriphId);
/**
* @}
*/
/** @addtogroup GTZC_Exported_Functions_Group6
* @brief IRQ related Functions
* @{
*/
void HAL_GTZC_IRQHandler(void);
void HAL_GTZC_TZIC_Callback(uint32_t PeriphId);
/**
* @}
*/
#endif /* CPU_IN_SECURE_STATE */
/**
* @}
*/
/**
* @}
*/
#endif /* defined(GTZC_TZSC1) && defined(HAL_GTZC_MODULE_ENABLED) */
/**
* @}
*/
#ifdef __cplusplus
}
#endif /* __cplusplus */
#endif /* STM32U3xx_HAL_GTZC_H */

846
Software/Station_SW/Drivers/STM32U3xx_HAL_Driver/Inc/stm32u3xx_hal_i2c.h Normal file
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@@ -0,0 +1,846 @@
/**
******************************************************************************
* @file stm32u3xx_hal_i2c.h
* @author MCD Application Team
* @brief Header file of I2C HAL module.
******************************************************************************
* @attention
*
* Copyright (c) 2023 STMicroelectronics.
* All rights reserved.
*
* This software is licensed under terms that can be found in the LICENSE file
* in the root directory of this software component.
* If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef STM32U3xx_HAL_I2C_H
#define STM32U3xx_HAL_I2C_H
#ifdef __cplusplus
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include "stm32u3xx_hal_def.h"
/** @addtogroup STM32U3xx_HAL_Driver
* @{
*/
/** @addtogroup I2C
* @{
*/
/* Exported types ------------------------------------------------------------*/
/** @defgroup I2C_Exported_Types I2C Exported Types
* @{
*/
/** @defgroup I2C_Configuration_Structure_definition I2C Configuration Structure definition
* @brief I2C Configuration Structure definition
* @{
*/
typedef struct
{
uint32_t Timing; /*!< Specifies the I2C_TIMINGR_register value.
This parameter calculated by referring to I2C initialization section
in Reference manual */
uint32_t OwnAddress1; /*!< Specifies the first device own address.
This parameter can be a 7-bit or 10-bit address. */
uint32_t AddressingMode; /*!< Specifies if 7-bit or 10-bit addressing mode is selected.
This parameter can be a value of @ref I2C_ADDRESSING_MODE */
uint32_t DualAddressMode; /*!< Specifies if dual addressing mode is selected.
This parameter can be a value of @ref I2C_DUAL_ADDRESSING_MODE */
uint32_t OwnAddress2; /*!< Specifies the second device own address if dual addressing mode is selected
This parameter can be a 7-bit address. */
uint32_t OwnAddress2Masks; /*!< Specifies the acknowledge mask address second device own address if dual addressing
mode is selected.
This parameter can be a value of @ref I2C_OWN_ADDRESS2_MASKS */
uint32_t GeneralCallMode; /*!< Specifies if general call mode is selected.
This parameter can be a value of @ref I2C_GENERAL_CALL_ADDRESSING_MODE */
uint32_t NoStretchMode; /*!< Specifies if nostretch mode is selected.
This parameter can be a value of @ref I2C_NOSTRETCH_MODE */
} I2C_InitTypeDef;
/**
* @}
*/
/** @defgroup HAL_state_structure_definition HAL state structure definition
* @brief HAL State structure definition
* @note HAL I2C State value coding follow below described bitmap :\n
* b7-b6 Error information\n
* 00 : No Error\n
* 01 : Abort (Abort user request on going)\n
* 10 : Timeout\n
* 11 : Error\n
* b5 Peripheral initialization status\n
* 0 : Reset (peripheral not initialized)\n
* 1 : Init done (peripheral initialized and ready to use. HAL I2C Init function called)\n
* b4 (not used)\n
* x : Should be set to 0\n
* b3\n
* 0 : Ready or Busy (No Listen mode ongoing)\n
* 1 : Listen (peripheral in Address Listen Mode)\n
* b2 Intrinsic process state\n
* 0 : Ready\n
* 1 : Busy (peripheral busy with some configuration or internal operations)\n
* b1 Rx state\n
* 0 : Ready (no Rx operation ongoing)\n
* 1 : Busy (Rx operation ongoing)\n
* b0 Tx state\n
* 0 : Ready (no Tx operation ongoing)\n
* 1 : Busy (Tx operation ongoing)
* @{
*/
typedef enum
{
HAL_I2C_STATE_RESET = 0x00U, /*!< Peripheral is not yet Initialized */
HAL_I2C_STATE_READY = 0x20U, /*!< Peripheral Initialized and ready for use */
HAL_I2C_STATE_BUSY = 0x24U, /*!< An internal process is ongoing */
HAL_I2C_STATE_BUSY_TX = 0x21U, /*!< Data Transmission process is ongoing */
HAL_I2C_STATE_BUSY_RX = 0x22U, /*!< Data Reception process is ongoing */
HAL_I2C_STATE_LISTEN = 0x28U, /*!< Address Listen Mode is ongoing */
HAL_I2C_STATE_BUSY_TX_LISTEN = 0x29U, /*!< Address Listen Mode and Data Transmission
process is ongoing */
HAL_I2C_STATE_BUSY_RX_LISTEN = 0x2AU, /*!< Address Listen Mode and Data Reception
process is ongoing */
HAL_I2C_STATE_ABORT = 0x60U, /*!< Abort user request ongoing */
} HAL_I2C_StateTypeDef;
/**
* @}
*/
/** @defgroup HAL_mode_structure_definition HAL mode structure definition
* @brief HAL Mode structure definition
* @note HAL I2C Mode value coding follow below described bitmap :\n
* b7 (not used)\n
* x : Should be set to 0\n
* b6\n
* 0 : None\n
* 1 : Memory (HAL I2C communication is in Memory Mode)\n
* b5\n
* 0 : None\n
* 1 : Slave (HAL I2C communication is in Slave Mode)\n
* b4\n
* 0 : None\n
* 1 : Master (HAL I2C communication is in Master Mode)\n
* b3-b2-b1-b0 (not used)\n
* xxxx : Should be set to 0000
* @{
*/
typedef enum
{
HAL_I2C_MODE_NONE = 0x00U, /*!< No I2C communication on going */
HAL_I2C_MODE_MASTER = 0x10U, /*!< I2C communication is in Master Mode */
HAL_I2C_MODE_SLAVE = 0x20U, /*!< I2C communication is in Slave Mode */
HAL_I2C_MODE_MEM = 0x40U /*!< I2C communication is in Memory Mode */
} HAL_I2C_ModeTypeDef;
/**
* @}
*/
/** @defgroup I2C_Error_Code_definition I2C Error Code definition
* @brief I2C Error Code definition
* @{
*/
#define HAL_I2C_ERROR_NONE (0x00000000U) /*!< No error */
#define HAL_I2C_ERROR_BERR (0x00000001U) /*!< BERR error */
#define HAL_I2C_ERROR_ARLO (0x00000002U) /*!< ARLO error */
#define HAL_I2C_ERROR_AF (0x00000004U) /*!< ACKF error */
#define HAL_I2C_ERROR_OVR (0x00000008U) /*!< OVR error */
#define HAL_I2C_ERROR_DMA (0x00000010U) /*!< DMA transfer error */
#define HAL_I2C_ERROR_TIMEOUT (0x00000020U) /*!< Timeout error */
#define HAL_I2C_ERROR_SIZE (0x00000040U) /*!< Size Management error */
#define HAL_I2C_ERROR_DMA_PARAM (0x00000080U) /*!< DMA Parameter Error */
#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
#define HAL_I2C_ERROR_INVALID_CALLBACK (0x00000100U) /*!< Invalid Callback error */
#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
#define HAL_I2C_ERROR_INVALID_PARAM (0x00000200U) /*!< Invalid Parameters error */
/**
* @}
*/
/** @defgroup I2C_handle_Structure_definition I2C handle Structure definition
* @brief I2C handle Structure definition
* @{
*/
typedef struct __I2C_HandleTypeDef
{
I2C_TypeDef *Instance; /*!< I2C registers base address */
I2C_InitTypeDef Init; /*!< I2C communication parameters */
uint8_t *pBuffPtr; /*!< Pointer to I2C transfer buffer */
uint16_t XferSize; /*!< I2C transfer size */
__IO uint16_t XferCount; /*!< I2C transfer counter */
__IO uint32_t XferOptions; /*!< I2C sequantial transfer options, this parameter can
be a value of @ref I2C_XFEROPTIONS */
__IO uint32_t PreviousState; /*!< I2C communication Previous state */
HAL_StatusTypeDef(*XferISR)(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, uint32_t ITSources);
/*!< I2C transfer IRQ handler function pointer */
#if defined(HAL_DMA_MODULE_ENABLED)
DMA_HandleTypeDef *hdmatx; /*!< I2C Tx DMA handle parameters */
DMA_HandleTypeDef *hdmarx; /*!< I2C Rx DMA handle parameters */
#endif /*HAL_DMA_MODULE_ENABLED*/
HAL_LockTypeDef Lock; /*!< I2C locking object */
__IO HAL_I2C_StateTypeDef State; /*!< I2C communication state */
__IO HAL_I2C_ModeTypeDef Mode; /*!< I2C communication mode */
__IO uint32_t ErrorCode; /*!< I2C Error code */
__IO uint32_t AddrEventCount; /*!< I2C Address Event counter */
__IO uint32_t Devaddress; /*!< I2C Target device address */
__IO uint32_t Memaddress; /*!< I2C Target memory address */
#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
void (* MasterTxCpltCallback)(struct __I2C_HandleTypeDef *hi2c);
/*!< I2C Master Tx Transfer completed callback */
void (* MasterRxCpltCallback)(struct __I2C_HandleTypeDef *hi2c);
/*!< I2C Master Rx Transfer completed callback */
void (* SlaveTxCpltCallback)(struct __I2C_HandleTypeDef *hi2c);
/*!< I2C Slave Tx Transfer completed callback */
void (* SlaveRxCpltCallback)(struct __I2C_HandleTypeDef *hi2c);
/*!< I2C Slave Rx Transfer completed callback */
void (* ListenCpltCallback)(struct __I2C_HandleTypeDef *hi2c);
/*!< I2C Listen Complete callback */
void (* MemTxCpltCallback)(struct __I2C_HandleTypeDef *hi2c);
/*!< I2C Memory Tx Transfer completed callback */
void (* MemRxCpltCallback)(struct __I2C_HandleTypeDef *hi2c);
/*!< I2C Memory Rx Transfer completed callback */
void (* ErrorCallback)(struct __I2C_HandleTypeDef *hi2c);
/*!< I2C Error callback */
void (* AbortCpltCallback)(struct __I2C_HandleTypeDef *hi2c);
/*!< I2C Abort callback */
void (* AddrCallback)(struct __I2C_HandleTypeDef *hi2c, uint8_t TransferDirection, uint16_t AddrMatchCode);
/*!< I2C Slave Address Match callback */
void (* MspInitCallback)(struct __I2C_HandleTypeDef *hi2c);
/*!< I2C Msp Init callback */
void (* MspDeInitCallback)(struct __I2C_HandleTypeDef *hi2c);
/*!< I2C Msp DeInit callback */
#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
} I2C_HandleTypeDef;
#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
/**
* @brief HAL I2C Callback ID enumeration definition
*/
typedef enum
{
HAL_I2C_MASTER_TX_COMPLETE_CB_ID = 0x00U, /*!< I2C Master Tx Transfer completed callback ID */
HAL_I2C_MASTER_RX_COMPLETE_CB_ID = 0x01U, /*!< I2C Master Rx Transfer completed callback ID */
HAL_I2C_SLAVE_TX_COMPLETE_CB_ID = 0x02U, /*!< I2C Slave Tx Transfer completed callback ID */
HAL_I2C_SLAVE_RX_COMPLETE_CB_ID = 0x03U, /*!< I2C Slave Rx Transfer completed callback ID */
HAL_I2C_LISTEN_COMPLETE_CB_ID = 0x04U, /*!< I2C Listen Complete callback ID */
HAL_I2C_MEM_TX_COMPLETE_CB_ID = 0x05U, /*!< I2C Memory Tx Transfer callback ID */
HAL_I2C_MEM_RX_COMPLETE_CB_ID = 0x06U, /*!< I2C Memory Rx Transfer completed callback ID */
HAL_I2C_ERROR_CB_ID = 0x07U, /*!< I2C Error callback ID */
HAL_I2C_ABORT_CB_ID = 0x08U, /*!< I2C Abort callback ID */
HAL_I2C_MSPINIT_CB_ID = 0x09U, /*!< I2C Msp Init callback ID */
HAL_I2C_MSPDEINIT_CB_ID = 0x0AU /*!< I2C Msp DeInit callback ID */
} HAL_I2C_CallbackIDTypeDef;
/**
* @brief HAL I2C Callback pointer definition
*/
typedef void (*pI2C_CallbackTypeDef)(I2C_HandleTypeDef *hi2c);
/*!< pointer to an I2C callback function */
typedef void (*pI2C_AddrCallbackTypeDef)(I2C_HandleTypeDef *hi2c, uint8_t TransferDirection,
uint16_t AddrMatchCode);
/*!< pointer to an I2C Address Match callback function */
#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
/**
* @}
*/
/**
* @}
*/
/* Exported constants --------------------------------------------------------*/
/** @defgroup I2C_Exported_Constants I2C Exported Constants
* @{
*/
/** @defgroup I2C_XFEROPTIONS I2C Sequential Transfer Options
* @{
*/
#define I2C_FIRST_FRAME ((uint32_t)I2C_SOFTEND_MODE)
#define I2C_FIRST_AND_NEXT_FRAME ((uint32_t)(I2C_RELOAD_MODE | I2C_SOFTEND_MODE))
#define I2C_NEXT_FRAME ((uint32_t)(I2C_RELOAD_MODE | I2C_SOFTEND_MODE))
#define I2C_FIRST_AND_LAST_FRAME ((uint32_t)I2C_AUTOEND_MODE)
#define I2C_LAST_FRAME ((uint32_t)I2C_AUTOEND_MODE)
#define I2C_LAST_FRAME_NO_STOP ((uint32_t)I2C_SOFTEND_MODE)
/* List of XferOptions in usage of :
* 1- Restart condition in all use cases (direction change or not)
*/
#define I2C_OTHER_FRAME (0x000000AAU)
#define I2C_OTHER_AND_LAST_FRAME (0x0000AA00U)
/**
* @}
*/
/** @defgroup I2C_ADDRESSING_MODE I2C Addressing Mode
* @{
*/
#define I2C_ADDRESSINGMODE_7BIT (0x00000001U)
#define I2C_ADDRESSINGMODE_10BIT (0x00000002U)
/**
* @}
*/
/** @defgroup I2C_DUAL_ADDRESSING_MODE I2C Dual Addressing Mode
* @{
*/
#define I2C_DUALADDRESS_DISABLE (0x00000000U)
#define I2C_DUALADDRESS_ENABLE I2C_OAR2_OA2EN
/**
* @}
*/
/** @defgroup I2C_OWN_ADDRESS2_MASKS I2C Own Address2 Masks
* @{
*/
#define I2C_OA2_NOMASK ((uint8_t)0x00U)
#define I2C_OA2_MASK01 ((uint8_t)0x01U)
#define I2C_OA2_MASK02 ((uint8_t)0x02U)
#define I2C_OA2_MASK03 ((uint8_t)0x03U)
#define I2C_OA2_MASK04 ((uint8_t)0x04U)
#define I2C_OA2_MASK05 ((uint8_t)0x05U)
#define I2C_OA2_MASK06 ((uint8_t)0x06U)
#define I2C_OA2_MASK07 ((uint8_t)0x07U)
/**
* @}
*/
/** @defgroup I2C_GENERAL_CALL_ADDRESSING_MODE I2C General Call Addressing Mode
* @{
*/
#define I2C_GENERALCALL_DISABLE (0x00000000U)
#define I2C_GENERALCALL_ENABLE I2C_CR1_GCEN
/**
* @}
*/
/** @defgroup I2C_NOSTRETCH_MODE I2C No-Stretch Mode
* @{
*/
#define I2C_NOSTRETCH_DISABLE (0x00000000U)
#define I2C_NOSTRETCH_ENABLE I2C_CR1_NOSTRETCH
/**
* @}
*/
/** @defgroup I2C_MEMORY_ADDRESS_SIZE I2C Memory Address Size
* @{
*/
#define I2C_MEMADD_SIZE_8BIT (0x00000001U)
#define I2C_MEMADD_SIZE_16BIT (0x00000002U)
/**
* @}
*/
/** @defgroup I2C_XFERDIRECTION I2C Transfer Direction Master Point of View
* @{
*/
#define I2C_DIRECTION_TRANSMIT (0x00000000U)
#define I2C_DIRECTION_RECEIVE (0x00000001U)
/**
* @}
*/
/** @defgroup I2C_RELOAD_END_MODE I2C Reload End Mode
* @{
*/
#define I2C_RELOAD_MODE I2C_CR2_RELOAD
#define I2C_AUTOEND_MODE I2C_CR2_AUTOEND
#define I2C_SOFTEND_MODE (0x00000000U)
/**
* @}
*/
/** @defgroup I2C_START_STOP_MODE I2C Start or Stop Mode
* @{
*/
#define I2C_NO_STARTSTOP (0x00000000U)
#define I2C_GENERATE_NO_START_READ (uint32_t)(0x80000000U | I2C_CR2_RD_WRN)
#define I2C_GENERATE_NO_START_WRITE (uint32_t)(0x80000000U)
#define I2C_GENERATE_STOP (uint32_t)(0x80000000U | I2C_CR2_STOP)
#define I2C_GENERATE_START_READ (uint32_t)(0x80000000U | I2C_CR2_START | I2C_CR2_RD_WRN)
#define I2C_GENERATE_START_WRITE (uint32_t)(0x80000000U | I2C_CR2_START)
/**
* @}
*/
/** @defgroup I2C_Interrupt_configuration_definition I2C Interrupt configuration definition
* @brief I2C Interrupt definition
* Elements values convention: 0xXXXXXXXX
* - XXXXXXXX : Interrupt control mask
* @{
*/
#define I2C_IT_ERRI I2C_CR1_ERRIE
#define I2C_IT_TCI I2C_CR1_TCIE
#define I2C_IT_STOPI I2C_CR1_STOPIE
#define I2C_IT_NACKI I2C_CR1_NACKIE
#define I2C_IT_ADDRI I2C_CR1_ADDRIE
#define I2C_IT_RXI I2C_CR1_RXIE
#define I2C_IT_TXI I2C_CR1_TXIE
/**
* @}
*/
/** @defgroup I2C_Flag_definition I2C Flag definition
* @{
*/
#define I2C_FLAG_TXE I2C_ISR_TXE
#define I2C_FLAG_TXIS I2C_ISR_TXIS
#define I2C_FLAG_RXNE I2C_ISR_RXNE
#define I2C_FLAG_ADDR I2C_ISR_ADDR
#define I2C_FLAG_AF I2C_ISR_NACKF
#define I2C_FLAG_STOPF I2C_ISR_STOPF
#define I2C_FLAG_TC I2C_ISR_TC
#define I2C_FLAG_TCR I2C_ISR_TCR
#define I2C_FLAG_BERR I2C_ISR_BERR
#define I2C_FLAG_ARLO I2C_ISR_ARLO
#define I2C_FLAG_OVR I2C_ISR_OVR
#define I2C_FLAG_PECERR I2C_ISR_PECERR
#define I2C_FLAG_TIMEOUT I2C_ISR_TIMEOUT
#define I2C_FLAG_ALERT I2C_ISR_ALERT
#define I2C_FLAG_BUSY I2C_ISR_BUSY
#define I2C_FLAG_DIR I2C_ISR_DIR
/**
* @}
*/
/**
* @}
*/
/* Exported macros -----------------------------------------------------------*/
/** @defgroup I2C_Exported_Macros I2C Exported Macros
* @{
*/
/** @brief Reset I2C handle state.
* @param __HANDLE__ specifies the I2C Handle.
* @retval None
*/
#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
#define __HAL_I2C_RESET_HANDLE_STATE(__HANDLE__) do{ \
(__HANDLE__)->State = HAL_I2C_STATE_RESET; \
(__HANDLE__)->MspInitCallback = NULL; \
(__HANDLE__)->MspDeInitCallback = NULL; \
} while(0)
#else
#define __HAL_I2C_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_I2C_STATE_RESET)
#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
/** @brief Enable the specified I2C interrupt.
* @param __HANDLE__ specifies the I2C Handle.
* @param __INTERRUPT__ specifies the interrupt source to enable.
* This parameter can be one of the following values:
* @arg @ref I2C_IT_ERRI Errors interrupt enable
* @arg @ref I2C_IT_TCI Transfer complete interrupt enable
* @arg @ref I2C_IT_STOPI STOP detection interrupt enable
* @arg @ref I2C_IT_NACKI NACK received interrupt enable
* @arg @ref I2C_IT_ADDRI Address match interrupt enable
* @arg @ref I2C_IT_RXI RX interrupt enable
* @arg @ref I2C_IT_TXI TX interrupt enable
*
* @retval None
*/
#define __HAL_I2C_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR1 |= (__INTERRUPT__))
/** @brief Disable the specified I2C interrupt.
* @param __HANDLE__ specifies the I2C Handle.
* @param __INTERRUPT__ specifies the interrupt source to disable.
* This parameter can be one of the following values:
* @arg @ref I2C_IT_ERRI Errors interrupt enable
* @arg @ref I2C_IT_TCI Transfer complete interrupt enable
* @arg @ref I2C_IT_STOPI STOP detection interrupt enable
* @arg @ref I2C_IT_NACKI NACK received interrupt enable
* @arg @ref I2C_IT_ADDRI Address match interrupt enable
* @arg @ref I2C_IT_RXI RX interrupt enable
* @arg @ref I2C_IT_TXI TX interrupt enable
*
* @retval None
*/
#define __HAL_I2C_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR1 &= (~(__INTERRUPT__)))
/** @brief Check whether the specified I2C interrupt source is enabled or not.
* @param __HANDLE__ specifies the I2C Handle.
* @param __INTERRUPT__ specifies the I2C interrupt source to check.
* This parameter can be one of the following values:
* @arg @ref I2C_IT_ERRI Errors interrupt enable
* @arg @ref I2C_IT_TCI Transfer complete interrupt enable
* @arg @ref I2C_IT_STOPI STOP detection interrupt enable
* @arg @ref I2C_IT_NACKI NACK received interrupt enable
* @arg @ref I2C_IT_ADDRI Address match interrupt enable
* @arg @ref I2C_IT_RXI RX interrupt enable
* @arg @ref I2C_IT_TXI TX interrupt enable
*
* @retval The new state of __INTERRUPT__ (SET or RESET).
*/
#define __HAL_I2C_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->CR1 & \
(__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
/** @brief Check whether the specified I2C flag is set or not.
* @param __HANDLE__ specifies the I2C Handle.
* @param __FLAG__ specifies the flag to check.
* This parameter can be one of the following values:
* @arg @ref I2C_FLAG_TXE Transmit data register empty
* @arg @ref I2C_FLAG_TXIS Transmit interrupt status
* @arg @ref I2C_FLAG_RXNE Receive data register not empty
* @arg @ref I2C_FLAG_ADDR Address matched (slave mode)
* @arg @ref I2C_FLAG_AF Acknowledge failure received flag
* @arg @ref I2C_FLAG_STOPF STOP detection flag
* @arg @ref I2C_FLAG_TC Transfer complete (master mode)
* @arg @ref I2C_FLAG_TCR Transfer complete reload
* @arg @ref I2C_FLAG_BERR Bus error
* @arg @ref I2C_FLAG_ARLO Arbitration lost
* @arg @ref I2C_FLAG_OVR Overrun/Underrun
* @arg @ref I2C_FLAG_PECERR PEC error in reception
* @arg @ref I2C_FLAG_TIMEOUT Timeout or Tlow detection flag
* @arg @ref I2C_FLAG_ALERT SMBus alert
* @arg @ref I2C_FLAG_BUSY Bus busy
* @arg @ref I2C_FLAG_DIR Transfer direction (slave mode)
*
* @retval The new state of __FLAG__ (SET or RESET).
*/
#define I2C_FLAG_MASK (0x0001FFFFU)
#define __HAL_I2C_GET_FLAG(__HANDLE__, __FLAG__) (((((__HANDLE__)->Instance->ISR) & \
(__FLAG__)) == (__FLAG__)) ? SET : RESET)
/** @brief Clear the I2C pending flags which are cleared by writing 1 in a specific bit.
* @param __HANDLE__ specifies the I2C Handle.
* @param __FLAG__ specifies the flag to clear.
* This parameter can be any combination of the following values:
* @arg @ref I2C_FLAG_TXE Transmit data register empty
* @arg @ref I2C_FLAG_ADDR Address matched (slave mode)
* @arg @ref I2C_FLAG_AF Acknowledge failure received flag
* @arg @ref I2C_FLAG_STOPF STOP detection flag
* @arg @ref I2C_FLAG_BERR Bus error
* @arg @ref I2C_FLAG_ARLO Arbitration lost
* @arg @ref I2C_FLAG_OVR Overrun/Underrun
* @arg @ref I2C_FLAG_PECERR PEC error in reception
* @arg @ref I2C_FLAG_TIMEOUT Timeout or Tlow detection flag
* @arg @ref I2C_FLAG_ALERT SMBus alert
*
* @retval None
*/
#define __HAL_I2C_CLEAR_FLAG(__HANDLE__, __FLAG__) (((__FLAG__) == I2C_FLAG_TXE) ? \
((__HANDLE__)->Instance->ISR |= (__FLAG__)) : \
((__HANDLE__)->Instance->ICR = (__FLAG__)))
/** @brief Enable the specified I2C peripheral.
* @param __HANDLE__ specifies the I2C Handle.
* @retval None
*/
#define __HAL_I2C_ENABLE(__HANDLE__) (SET_BIT((__HANDLE__)->Instance->CR1, I2C_CR1_PE))
/** @brief Disable the specified I2C peripheral.
* @param __HANDLE__ specifies the I2C Handle.
* @retval None
*/
#define __HAL_I2C_DISABLE(__HANDLE__) (CLEAR_BIT((__HANDLE__)->Instance->CR1, I2C_CR1_PE))
/** @brief Generate a Non-Acknowledge I2C peripheral in Slave mode.
* @param __HANDLE__ specifies the I2C Handle.
* @retval None
*/
#define __HAL_I2C_GENERATE_NACK(__HANDLE__) (SET_BIT((__HANDLE__)->Instance->CR2, I2C_CR2_NACK))
/**
* @}
*/
/* Include I2C HAL Extended module */
#include "stm32u3xx_hal_i2c_ex.h"
/* Exported functions --------------------------------------------------------*/
/** @addtogroup I2C_Exported_Functions
* @{
*/
/** @addtogroup I2C_Exported_Functions_Group1 Initialization and de-initialization functions
* @{
*/
/* Initialization and de-initialization functions******************************/
HAL_StatusTypeDef HAL_I2C_Init(I2C_HandleTypeDef *hi2c);
HAL_StatusTypeDef HAL_I2C_DeInit(I2C_HandleTypeDef *hi2c);
void HAL_I2C_MspInit(I2C_HandleTypeDef *hi2c);
void HAL_I2C_MspDeInit(I2C_HandleTypeDef *hi2c);
/* Callbacks Register/UnRegister functions ***********************************/
#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
HAL_StatusTypeDef HAL_I2C_RegisterCallback(I2C_HandleTypeDef *hi2c, HAL_I2C_CallbackIDTypeDef CallbackID,
pI2C_CallbackTypeDef pCallback);
HAL_StatusTypeDef HAL_I2C_UnRegisterCallback(I2C_HandleTypeDef *hi2c, HAL_I2C_CallbackIDTypeDef CallbackID);
HAL_StatusTypeDef HAL_I2C_RegisterAddrCallback(I2C_HandleTypeDef *hi2c, pI2C_AddrCallbackTypeDef pCallback);
HAL_StatusTypeDef HAL_I2C_UnRegisterAddrCallback(I2C_HandleTypeDef *hi2c);
#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
/**
* @}
*/
/** @addtogroup I2C_Exported_Functions_Group2 Input and Output operation functions
* @{
*/
/* IO operation functions ****************************************************/
/******* Blocking mode: Polling */
HAL_StatusTypeDef HAL_I2C_Master_Transmit(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData,
uint16_t Size, uint32_t Timeout);
HAL_StatusTypeDef HAL_I2C_Master_Receive(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData,
uint16_t Size, uint32_t Timeout);
HAL_StatusTypeDef HAL_I2C_Slave_Transmit(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size,
uint32_t Timeout);
HAL_StatusTypeDef HAL_I2C_Slave_Receive(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size,
uint32_t Timeout);
HAL_StatusTypeDef HAL_I2C_Mem_Write(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress,
uint16_t MemAddSize, uint8_t *pData, uint16_t Size, uint32_t Timeout);
HAL_StatusTypeDef HAL_I2C_Mem_Read(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress,
uint16_t MemAddSize, uint8_t *pData, uint16_t Size, uint32_t Timeout);
HAL_StatusTypeDef HAL_I2C_IsDeviceReady(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint32_t Trials,
uint32_t Timeout);
/******* Non-Blocking mode: Interrupt */
HAL_StatusTypeDef HAL_I2C_Master_Transmit_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData,
uint16_t Size);
HAL_StatusTypeDef HAL_I2C_Master_Receive_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData,
uint16_t Size);
HAL_StatusTypeDef HAL_I2C_Slave_Transmit_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size);
HAL_StatusTypeDef HAL_I2C_Slave_Receive_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size);
HAL_StatusTypeDef HAL_I2C_Mem_Write_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress,
uint16_t MemAddSize, uint8_t *pData, uint16_t Size);
HAL_StatusTypeDef HAL_I2C_Mem_Read_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress,
uint16_t MemAddSize, uint8_t *pData, uint16_t Size);
HAL_StatusTypeDef HAL_I2C_Master_Seq_Transmit_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData,
uint16_t Size, uint32_t XferOptions);
HAL_StatusTypeDef HAL_I2C_Master_Seq_Receive_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData,
uint16_t Size, uint32_t XferOptions);
HAL_StatusTypeDef HAL_I2C_Slave_Seq_Transmit_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size,
uint32_t XferOptions);
HAL_StatusTypeDef HAL_I2C_Slave_Seq_Receive_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size,
uint32_t XferOptions);
HAL_StatusTypeDef HAL_I2C_EnableListen_IT(I2C_HandleTypeDef *hi2c);
HAL_StatusTypeDef HAL_I2C_DisableListen_IT(I2C_HandleTypeDef *hi2c);
HAL_StatusTypeDef HAL_I2C_Master_Abort_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress);
#if defined(HAL_DMA_MODULE_ENABLED)
/******* Non-Blocking mode: DMA */
HAL_StatusTypeDef HAL_I2C_Master_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData,
uint16_t Size);
HAL_StatusTypeDef HAL_I2C_Master_Receive_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData,
uint16_t Size);
HAL_StatusTypeDef HAL_I2C_Slave_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size);
HAL_StatusTypeDef HAL_I2C_Slave_Receive_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size);
HAL_StatusTypeDef HAL_I2C_Mem_Write_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress,
uint16_t MemAddSize, uint8_t *pData, uint16_t Size);
HAL_StatusTypeDef HAL_I2C_Mem_Read_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress,
uint16_t MemAddSize, uint8_t *pData, uint16_t Size);
HAL_StatusTypeDef HAL_I2C_Master_Seq_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData,
uint16_t Size, uint32_t XferOptions);
HAL_StatusTypeDef HAL_I2C_Master_Seq_Receive_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData,
uint16_t Size, uint32_t XferOptions);
HAL_StatusTypeDef HAL_I2C_Slave_Seq_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size,
uint32_t XferOptions);
HAL_StatusTypeDef HAL_I2C_Slave_Seq_Receive_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size,
uint32_t XferOptions);
#endif /*HAL_DMA_MODULE_ENABLED*/
/**
* @}
*/
/** @addtogroup I2C_IRQ_Handler_and_Callbacks IRQ Handler and Callbacks
* @{
*/
/******* I2C IRQHandler and Callbacks used in non blocking modes (Interrupt and DMA) */
void HAL_I2C_EV_IRQHandler(I2C_HandleTypeDef *hi2c);
void HAL_I2C_ER_IRQHandler(I2C_HandleTypeDef *hi2c);
void HAL_I2C_MasterTxCpltCallback(I2C_HandleTypeDef *hi2c);
void HAL_I2C_MasterRxCpltCallback(I2C_HandleTypeDef *hi2c);
void HAL_I2C_SlaveTxCpltCallback(I2C_HandleTypeDef *hi2c);
void HAL_I2C_SlaveRxCpltCallback(I2C_HandleTypeDef *hi2c);
void HAL_I2C_AddrCallback(I2C_HandleTypeDef *hi2c, uint8_t TransferDirection, uint16_t AddrMatchCode);
void HAL_I2C_ListenCpltCallback(I2C_HandleTypeDef *hi2c);
void HAL_I2C_MemTxCpltCallback(I2C_HandleTypeDef *hi2c);
void HAL_I2C_MemRxCpltCallback(I2C_HandleTypeDef *hi2c);
void HAL_I2C_ErrorCallback(I2C_HandleTypeDef *hi2c);
void HAL_I2C_AbortCpltCallback(I2C_HandleTypeDef *hi2c);
/**
* @}
*/
/** @addtogroup I2C_Exported_Functions_Group3 Peripheral State, Mode and Error functions
* @{
*/
/* Peripheral State, Mode and Error functions *********************************/
HAL_I2C_StateTypeDef HAL_I2C_GetState(const I2C_HandleTypeDef *hi2c);
HAL_I2C_ModeTypeDef HAL_I2C_GetMode(const I2C_HandleTypeDef *hi2c);
uint32_t HAL_I2C_GetError(const I2C_HandleTypeDef *hi2c);
/**
* @}
*/
/**
* @}
*/
/* Private constants ---------------------------------------------------------*/
/** @defgroup I2C_Private_Constants I2C Private Constants
* @{
*/
/**
* @}
*/
/* Private macros ------------------------------------------------------------*/
/** @defgroup I2C_Private_Macro I2C Private Macros
* @{
*/
#define IS_I2C_ADDRESSING_MODE(MODE) (((MODE) == I2C_ADDRESSINGMODE_7BIT) || \
((MODE) == I2C_ADDRESSINGMODE_10BIT))
#define IS_I2C_DUAL_ADDRESS(ADDRESS) (((ADDRESS) == I2C_DUALADDRESS_DISABLE) || \
((ADDRESS) == I2C_DUALADDRESS_ENABLE))
#define IS_I2C_OWN_ADDRESS2_MASK(MASK) (((MASK) == I2C_OA2_NOMASK) || \
((MASK) == I2C_OA2_MASK01) || \
((MASK) == I2C_OA2_MASK02) || \
((MASK) == I2C_OA2_MASK03) || \
((MASK) == I2C_OA2_MASK04) || \
((MASK) == I2C_OA2_MASK05) || \
((MASK) == I2C_OA2_MASK06) || \
((MASK) == I2C_OA2_MASK07))
#define IS_I2C_GENERAL_CALL(CALL) (((CALL) == I2C_GENERALCALL_DISABLE) || \
((CALL) == I2C_GENERALCALL_ENABLE))
#define IS_I2C_NO_STRETCH(STRETCH) (((STRETCH) == I2C_NOSTRETCH_DISABLE) || \
((STRETCH) == I2C_NOSTRETCH_ENABLE))
#define IS_I2C_MEMADD_SIZE(SIZE) (((SIZE) == I2C_MEMADD_SIZE_8BIT) || \
((SIZE) == I2C_MEMADD_SIZE_16BIT))
#define IS_TRANSFER_MODE(MODE) (((MODE) == I2C_RELOAD_MODE) || \
((MODE) == I2C_AUTOEND_MODE) || \
((MODE) == I2C_SOFTEND_MODE))
#define IS_TRANSFER_REQUEST(REQUEST) (((REQUEST) == I2C_GENERATE_STOP) || \
((REQUEST) == I2C_GENERATE_START_READ) || \
((REQUEST) == I2C_GENERATE_START_WRITE) || \
((REQUEST) == I2C_GENERATE_NO_START_READ) || \
((REQUEST) == I2C_GENERATE_NO_START_WRITE)|| \
((REQUEST) == I2C_NO_STARTSTOP))
#define IS_I2C_TRANSFER_OPTIONS_REQUEST(REQUEST) (((REQUEST) == I2C_FIRST_FRAME) || \
((REQUEST) == I2C_FIRST_AND_NEXT_FRAME) || \
((REQUEST) == I2C_NEXT_FRAME) || \
((REQUEST) == I2C_FIRST_AND_LAST_FRAME) || \
((REQUEST) == I2C_LAST_FRAME) || \
((REQUEST) == I2C_LAST_FRAME_NO_STOP) || \
IS_I2C_TRANSFER_OTHER_OPTIONS_REQUEST(REQUEST))
#define IS_I2C_TRANSFER_OTHER_OPTIONS_REQUEST(REQUEST) (((REQUEST) == I2C_OTHER_FRAME) || \
((REQUEST) == I2C_OTHER_AND_LAST_FRAME))
#define I2C_RESET_CR2(__HANDLE__) ((__HANDLE__)->Instance->CR2 &= \
(uint32_t)~((uint32_t)(I2C_CR2_SADD | I2C_CR2_HEAD10R | \
I2C_CR2_NBYTES | I2C_CR2_RELOAD | \
I2C_CR2_RD_WRN)))
#define I2C_GET_ADDR_MATCH(__HANDLE__) ((uint16_t)(((__HANDLE__)->Instance->ISR & I2C_ISR_ADDCODE) \
>> 16U))
#define I2C_GET_DIR(__HANDLE__) ((uint8_t)(((__HANDLE__)->Instance->ISR & I2C_ISR_DIR) \
>> 16U))
#define I2C_GET_STOP_MODE(__HANDLE__) ((__HANDLE__)->Instance->CR2 & I2C_CR2_AUTOEND)
#define I2C_GET_OWN_ADDRESS1(__HANDLE__) ((uint16_t)((__HANDLE__)->Instance->OAR1 & I2C_OAR1_OA1))
#define I2C_GET_OWN_ADDRESS2(__HANDLE__) ((uint16_t)((__HANDLE__)->Instance->OAR2 & I2C_OAR2_OA2))
#define IS_I2C_OWN_ADDRESS1(ADDRESS1) ((ADDRESS1) <= 0x000003FFU)
#define IS_I2C_OWN_ADDRESS2(ADDRESS2) ((ADDRESS2) <= (uint16_t)0x00FFU)
#define I2C_MEM_ADD_MSB(__ADDRESS__) ((uint8_t)((uint16_t)(((uint16_t)((__ADDRESS__) & \
(uint16_t)(0xFF00U))) >> 8U)))
#define I2C_MEM_ADD_LSB(__ADDRESS__) ((uint8_t)((uint16_t)((__ADDRESS__) & (uint16_t)(0x00FFU))))
#define I2C_GENERATE_START(__ADDMODE__,__ADDRESS__) (((__ADDMODE__) == I2C_ADDRESSINGMODE_7BIT) ? \
(uint32_t)((((uint32_t)(__ADDRESS__) & (I2C_CR2_SADD)) | \
(I2C_CR2_START) | (I2C_CR2_AUTOEND)) & \
(~I2C_CR2_RD_WRN)) : \
(uint32_t)((((uint32_t)(__ADDRESS__) & (I2C_CR2_SADD)) | \
(I2C_CR2_ADD10) | (I2C_CR2_START) | \
(I2C_CR2_AUTOEND)) & (~I2C_CR2_RD_WRN)))
#define I2C_CHECK_FLAG(__ISR__, __FLAG__) ((((__ISR__) & ((__FLAG__) & I2C_FLAG_MASK)) == \
((__FLAG__) & I2C_FLAG_MASK)) ? SET : RESET)
#define I2C_CHECK_IT_SOURCE(__CR1__, __IT__) ((((__CR1__) & (__IT__)) == (__IT__)) ? SET : RESET)
/**
* @}
*/
/* Private Functions ---------------------------------------------------------*/
/** @defgroup I2C_Private_Functions I2C Private Functions
* @{
*/
/* Private functions are defined in stm32u3xx_hal_i2c.c file */
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /* STM32U3xx_HAL_I2C_H */

312
Software/Station_SW/Drivers/STM32U3xx_HAL_Driver/Inc/stm32u3xx_hal_i2c_ex.h Normal file
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@@ -0,0 +1,312 @@
/**
******************************************************************************
* @file stm32u3xx_hal_i2c_ex.h
* @author MCD Application Team
* @brief Header file of I2C HAL Extended module.
******************************************************************************
* @attention
*
* Copyright (c) 2023 STMicroelectronics.
* All rights reserved.
*
* This software is licensed under terms that can be found in the LICENSE file
* in the root directory of this software component.
* If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef STM32U3xx_HAL_I2C_EX_H
#define STM32U3xx_HAL_I2C_EX_H
#ifdef __cplusplus
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include "stm32u3xx_hal_def.h"
/** @addtogroup STM32U3xx_HAL_Driver
* @{
*/
/** @addtogroup I2CEx
* @{
*/
/* Exported types ------------------------------------------------------------*/
/** @defgroup I2C_Exported_Types I2C Exported Types
* @{
*/
/** @defgroup I2C_Autonomous_Mode_Configuration_Structure_definition Autonomous Mode Configuration Structure definition
* @brief I2C Autonomous Mode Configuration structure definition
* @{
*/
typedef struct
{
uint32_t TriggerState; /*!< Specifies the trigger state. This parameter can be a value
of @ref I2CEx_AutonomousMode_FunctionalState */
uint32_t TriggerSelection; /*!< Specifies the autonomous mode trigger signal selection. This parameter
can be a value of @ref I2CEx_AutonomousMode_TriggerSelection */
uint32_t TriggerPolarity; /*!< Specifies the autonomous mode trigger signal polarity sensitivity. This parameter
can be a value of @ref I2CEx_AutonomousMode_TriggerPolarity */
} I2C_AutonomousModeConfTypeDef;
/**
* @}
*/
/**
* @}
*/
/* Exported constants --------------------------------------------------------*/
/** @defgroup I2CEx_Exported_Constants I2C Extended Exported Constants
* @{
*/
/** @defgroup I2CEx_Analog_Filter I2C Extended Analog Filter
* @{
*/
#define I2C_ANALOGFILTER_ENABLE 0x00000000U
#define I2C_ANALOGFILTER_DISABLE I2C_CR1_ANFOFF
/**
* @}
*/
/** @defgroup I2CEx_FastModePlus I2C Extended Fast Mode Plus
* @{
*/
#define I2C_FASTMODEPLUS_ENABLE 0x00000000U /*!< Enable Fast Mode Plus */
#define I2C_FASTMODEPLUS_DISABLE 0x00000001U /*!< Disable Fast Mode Plus */
/**
* @}
*/
/** @defgroup I2CEx_AutonomousMode_FunctionalState I2C Extended Autonomous Mode State
* @{
*/
#define I2C_AUTO_MODE_DISABLE (0x00000000U) /*!< Autonomous mode disable */
#define I2C_AUTO_MODE_ENABLE I2C_AUTOCR_TRIGEN /*!< Autonomous mode enable */
/**
* @}
*/
/** @defgroup I2CEx_AutonomousMode_TriggerSelection I2C Extended Autonomous Mode Trigger Selection
* @{
*/
#define I2C_TRIG_GRP1 (0x10000000U) /*!< Trigger Group for I2C1, I2C2 */
#define I2C_TRIG_GRP2 (0x20000000U) /*!< Trigger Group for I2C3 */
#define I2C_GRP1_GPDMA_CH0_TCF_TRG (uint32_t)(I2C_TRIG_GRP1 | (0x00000000U))
/*!< HW Trigger signal is GPDMA_CH0_TRG */
#define I2C_GRP1_GPDMA_CH1_TCF_TRG (uint32_t)(I2C_TRIG_GRP1 | (0x1U << I2C_AUTOCR_TRIGSEL_Pos))
/*!< HW Trigger signal is GPDMA_CH1_TRG */
#define I2C_GRP1_GPDMA_CH2_TCF_TRG (uint32_t)(I2C_TRIG_GRP1 | (0x2U << I2C_AUTOCR_TRIGSEL_Pos))
/*!< HW Trigger signal is GPDMA_CH2_TRG */
#define I2C_GRP1_GPDMA_CH3_TCF_TRG (uint32_t)(I2C_TRIG_GRP1 | (0x3U << I2C_AUTOCR_TRIGSEL_Pos))
/*!< HW Trigger signal is GPDMA_CH3_TRG */
#define I2C_GRP1_EXTI5_TRG (uint32_t)(I2C_TRIG_GRP1 | (0x4U << I2C_AUTOCR_TRIGSEL_Pos))
/*!< HW Trigger signal is EXTI5_TRG */
#define I2C_GRP1_EXTI9_TRG (uint32_t)(I2C_TRIG_GRP1 | (0x5U << I2C_AUTOCR_TRIGSEL_Pos))
/*!< HW Trigger signal is EXTI9_TRG */
#define I2C_GRP1_LPTIM1_CH1_TRG (uint32_t)(I2C_TRIG_GRP1 | (0x6U << I2C_AUTOCR_TRIGSEL_Pos))
/*!< HW Trigger signal is LPTIM1_CH1_TRG */
#define I2C_GRP1_LPTIM2_CH1_TRG (uint32_t)(I2C_TRIG_GRP1 | (0x7U << I2C_AUTOCR_TRIGSEL_Pos))
/*!< HW Trigger signal is LPTIM2_CH1_TRG */
#define I2C_GRP1_COMP1_TRG (uint32_t)(I2C_TRIG_GRP1 | (0x8U << I2C_AUTOCR_TRIGSEL_Pos))
/*!< HW Trigger signal is COMP1_TRG */
#define I2C_GRP1_COMP2_TRG (uint32_t)(I2C_TRIG_GRP1 | (0x9U << I2C_AUTOCR_TRIGSEL_Pos))
/*!< HW Trigger signal is COMP2_TRG */
#define I2C_GRP1_RTC_ALRA_TRG (uint32_t)(I2C_TRIG_GRP1 | (0xAU << I2C_AUTOCR_TRIGSEL_Pos))
/*!< HW Trigger signal is RTC_ALRA_TRG */
#define I2C_GRP1_RTC_WUT_TRG (uint32_t)(I2C_TRIG_GRP1 | (0xBU << I2C_AUTOCR_TRIGSEL_Pos))
/*!< HW Trigger signal is RTC_WUT_TRG */
#define I2C_GRP2_GPDMA_CH0_TCF_TRG (uint32_t)(I2C_TRIG_GRP2 | (0x00000000U))
/*!< HW Trigger signal is GPDMA_CH0_TRG */
#define I2C_GRP2_GPDMA_CH1_TCF_TRG (uint32_t)(I2C_TRIG_GRP2 | (0x1U << I2C_AUTOCR_TRIGSEL_Pos))
/*!< HW Trigger signal is GPDMA_CH1_TRG */
#define I2C_GRP2_GPDMA_CH2_TCF_TRG (uint32_t)(I2C_TRIG_GRP2 | (0x2U << I2C_AUTOCR_TRIGSEL_Pos))
/*!< HW Trigger signal is GPDMA_CH2_TRG */
#define I2C_GRP2_GPDMA_CH3_TCF_TRG (uint32_t)(I2C_TRIG_GRP2 | (0x3U << I2C_AUTOCR_TRIGSEL_Pos))
/*!< HW Trigger signal is GPDMA_CH3_TRG */
#define I2C_GRP2_EXTI5_TRG (uint32_t)(I2C_TRIG_GRP2 | (0x4U << I2C_AUTOCR_TRIGSEL_Pos))
/*!< HW Trigger signal is EXTI5_TRG */
#define I2C_GRP2_EXTI8_TRG (uint32_t)(I2C_TRIG_GRP2 | (0x5U << I2C_AUTOCR_TRIGSEL_Pos))
/*!< HW Trigger signal is EXTI8_TRG */
#define I2C_GRP2_LPTIM1_CH1_TRG (uint32_t)(I2C_TRIG_GRP2 | (0x6U << I2C_AUTOCR_TRIGSEL_Pos))
/*!< HW Trigger signal is LPTIM1_CH1_TRG */
#define I2C_GRP2_LPTIM3_CH1_TRG (uint32_t)(I2C_TRIG_GRP2 | (0x7U << I2C_AUTOCR_TRIGSEL_Pos))
/*!< HW Trigger signal is LPTIM3_CH1_TRG */
#define I2C_GRP2_COMP1_TRG (uint32_t)(I2C_TRIG_GRP2 | (0x8U << I2C_AUTOCR_TRIGSEL_Pos))
/*!< HW Trigger signal is COMP1_TRG */
#define I2C_GRP2_COMP2_TRG (uint32_t)(I2C_TRIG_GRP2 | (0x9U << I2C_AUTOCR_TRIGSEL_Pos))
/*!< HW Trigger signal is COMP2_TRG */
#define I2C_GRP2_RTC_ALRA_TRG (uint32_t)(I2C_TRIG_GRP2 | (0xAU << I2C_AUTOCR_TRIGSEL_Pos))
/*!< HW Trigger signal is RTC_ALRA_TRG */
#define I2C_GRP2_RTC_WUT_TRG (uint32_t)(I2C_TRIG_GRP2 | (0xBU << I2C_AUTOCR_TRIGSEL_Pos))
/*!< HW Trigger signal is RTC_WUT_TRG */
/**
* @}
*/
/** @defgroup I2CEx_AutonomousMode_TriggerPolarity Extended Autonomous Mode Trigger Polarity
* @{
*/
#define I2C_TRIG_POLARITY_RISING (0x00000000U) /*!< I2C HW Trigger signal on rising edge */
#define I2C_TRIG_POLARITY_FALLING I2C_AUTOCR_TRIGPOL /*!< I2C HW Trigger signal on falling edge */
/**
* @}
*/
/**
* @}
*/
/* Exported macro ------------------------------------------------------------*/
/** @defgroup I2CEx_Exported_Macros I2C Extended Exported Macros
* @{
*/
/**
* @}
*/
/* Exported functions --------------------------------------------------------*/
/** @addtogroup I2CEx_Exported_Functions I2C Extended Exported Functions
* @{
*/
/** @addtogroup I2CEx_Exported_Functions_Group1 Filter Mode Functions
* @{
*/
/* Peripheral Control functions ************************************************/
HAL_StatusTypeDef HAL_I2CEx_ConfigAnalogFilter(I2C_HandleTypeDef *hi2c, uint32_t AnalogFilter);
HAL_StatusTypeDef HAL_I2CEx_ConfigDigitalFilter(I2C_HandleTypeDef *hi2c, uint32_t DigitalFilter);
/**
* @}
*/
/** @addtogroup I2CEx_Exported_Functions_Group2 WakeUp Mode Functions
* @{
*/
HAL_StatusTypeDef HAL_I2CEx_EnableWakeUp(I2C_HandleTypeDef *hi2c);
HAL_StatusTypeDef HAL_I2CEx_DisableWakeUp(I2C_HandleTypeDef *hi2c);
/**
* @}
*/
/** @addtogroup I2CEx_Exported_Functions_Group3 Fast Mode Plus Functions
* @{
*/
HAL_StatusTypeDef HAL_I2CEx_ConfigFastModePlus(I2C_HandleTypeDef *hi2c, uint32_t FastModePlus);
/**
* @}
*/
/** @addtogroup I2CEx_Exported_Functions_Group4 Autonomous Mode Functions
* @{
*/
HAL_StatusTypeDef HAL_I2CEx_SetConfigAutonomousMode(I2C_HandleTypeDef *hi2c,
const I2C_AutonomousModeConfTypeDef *sConfig);
HAL_StatusTypeDef HAL_I2CEx_GetConfigAutonomousMode(const I2C_HandleTypeDef *hi2c,
I2C_AutonomousModeConfTypeDef *sConfig);
HAL_StatusTypeDef HAL_I2CEx_ClearConfigAutonomousMode(I2C_HandleTypeDef *hi2c);
/**
* @}
*/
/**
* @}
*/
/* Private constants ---------------------------------------------------------*/
/** @defgroup I2CEx_Private_Constants I2C Extended Private Constants
* @{
*/
/**
* @}
*/
/* Private macros ------------------------------------------------------------*/
/** @defgroup I2CEx_Private_Macro I2C Extended Private Macros
* @{
*/
#define IS_I2C_ANALOG_FILTER(FILTER) (((FILTER) == I2C_ANALOGFILTER_ENABLE) || \
((FILTER) == I2C_ANALOGFILTER_DISABLE))
#define IS_I2C_DIGITAL_FILTER(FILTER) ((FILTER) <= 0x0000000FU)
#define IS_I2C_FASTMODEPLUS(__CONFIG__) (((__CONFIG__) == (I2C_FASTMODEPLUS_ENABLE)) || \
((__CONFIG__) == (I2C_FASTMODEPLUS_DISABLE)))
#define IS_I2C_AUTO_MODE(__MODE__) (((__MODE__) == I2C_AUTO_MODE_DISABLE) || \
((__MODE__) == I2C_AUTO_MODE_ENABLE))
#define IS_I2C_TRIG_SOURCE(__INSTANCE__, __SOURCE__) (((__INSTANCE__) == I2C3) ? \
IS_I2C_GRP2_TRIG_SOURCE(__SOURCE__) : \
IS_I2C_GRP1_TRIG_SOURCE(__SOURCE__))
#define IS_I2C_GRP1_TRIG_SOURCE(__SOURCE__) (((__SOURCE__) == I2C_GRP1_GPDMA_CH0_TCF_TRG ) || \
((__SOURCE__) == I2C_GRP1_GPDMA_CH1_TCF_TRG ) || \
((__SOURCE__) == I2C_GRP1_GPDMA_CH2_TCF_TRG ) || \
((__SOURCE__) == I2C_GRP1_GPDMA_CH3_TCF_TRG ) || \
((__SOURCE__) == I2C_GRP1_EXTI5_TRG ) || \
((__SOURCE__) == I2C_GRP1_EXTI9_TRG ) || \
((__SOURCE__) == I2C_GRP1_LPTIM1_CH1_TRG ) || \
((__SOURCE__) == I2C_GRP1_LPTIM2_CH1_TRG ) || \
((__SOURCE__) == I2C_GRP1_COMP1_TRG ) || \
((__SOURCE__) == I2C_GRP1_COMP2_TRG ) || \
((__SOURCE__) == I2C_GRP1_RTC_ALRA_TRG ) || \
((__SOURCE__) == I2C_GRP1_RTC_WUT_TRG ))
#define IS_I2C_GRP2_TRIG_SOURCE(__SOURCE__) (((__SOURCE__) == I2C_GRP2_GPDMA_CH0_TCF_TRG ) || \
((__SOURCE__) == I2C_GRP2_GPDMA_CH1_TCF_TRG ) || \
((__SOURCE__) == I2C_GRP2_GPDMA_CH2_TCF_TRG ) || \
((__SOURCE__) == I2C_GRP2_GPDMA_CH3_TCF_TRG ) || \
((__SOURCE__) == I2C_GRP2_EXTI5_TRG ) || \
((__SOURCE__) == I2C_GRP2_EXTI8_TRG ) || \
((__SOURCE__) == I2C_GRP2_LPTIM1_CH1_TRG ) || \
((__SOURCE__) == I2C_GRP2_LPTIM3_CH1_TRG ) || \
((__SOURCE__) == I2C_GRP2_COMP1_TRG ) || \
((__SOURCE__) == I2C_GRP2_COMP2_TRG ) || \
((__SOURCE__) == I2C_GRP2_RTC_ALRA_TRG ) || \
((__SOURCE__) == I2C_GRP2_RTC_WUT_TRG ))
#define IS_I2C_TRIG_INPUT_INSTANCE(__INSTANCE__) (IS_I2C_GRP1_INSTANCE(__INSTANCE__) || \
IS_I2C_GRP2_INSTANCE(__INSTANCE__))
#define IS_I2C_AUTO_MODE_TRG_POL(__POLARITY__) (((__POLARITY__) == I2C_TRIG_POLARITY_RISING) || \
((__POLARITY__) == I2C_TRIG_POLARITY_FALLING))
/**
* @}
*/
/* Private Functions ---------------------------------------------------------*/
/** @defgroup I2CEx_Private_Functions I2C Extended Private Functions
* @{
*/
/* Private functions are defined in stm32u3xx_hal_i2c_ex.c file */
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /* STM32U3xx_HAL_I2C_EX_H */

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Software/Station_SW/Drivers/STM32U3xx_HAL_Driver/Inc/stm32u3xx_hal_icache.h Normal file
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/**
******************************************************************************
* @file stm32u3xx_hal_icache.h
* @author MCD Application Team
* @brief Header file of ICACHE HAL module.
******************************************************************************
* @attention
*
* Copyright (c) 2023 STMicroelectronics.
* All rights reserved.
*
* This software is licensed under terms that can be found in the LICENSE file
* in the root directory of this software component.
* If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
/* Define to prevent recursive inclusion ------------------------------------*/
#ifndef STM32U3xx_HAL_ICACHE_H
#define STM32U3xx_HAL_ICACHE_H
#ifdef __cplusplus
extern "C" {
#endif
/* Includes -----------------------------------------------------------------*/
#include "stm32u3xx_hal_def.h"
#if defined(ICACHE)
/** @addtogroup STM32U3xx_HAL_Driver
* @{
*/
/** @addtogroup ICACHE
* @{
*/
/* Exported types -----------------------------------------------------------*/
/** @defgroup ICACHE_Exported_Types ICACHE Exported Types
* @{
*/
/**
* @brief HAL ICACHE region configuration structure definition
*/
typedef struct
{
uint32_t BaseAddress; /*!< Configures the Base address of Region i to be remapped */
uint32_t RemapAddress; /*!< Configures the Remap address of Region i to be remapped */
uint32_t Size; /*!< Configures the Region size.
This parameter can be a value of @ref ICACHE_Region_Size */
uint32_t TrafficRoute; /*!< Selects the traffic route.
This parameter can be a value of @ref ICACHE_Traffic_Route */
uint32_t OutputBurstType; /*!< Selects the output burst type.
This parameter can be a value of @ref ICACHE_Output_Burst_Type */
} ICACHE_RegionConfigTypeDef;
/**
* @}
*/
/* Exported constants -------------------------------------------------------*/
/** @defgroup ICACHE_Exported_Constants ICACHE Exported Constants
* @{
*/
/** @defgroup ICACHE_WaysSelection Ways selection
* @{
*/
#define ICACHE_1WAY 0U /*!< 1-way cache (direct mapped cache) */
#define ICACHE_2WAYS ICACHE_CR_WAYSEL /*!< 2-ways set associative cache (default) */
/**
* @}
*/
/** @defgroup ICACHE_Monitor_Type Monitor type
* @{
*/
#define ICACHE_MONITOR_HIT_MISS (ICACHE_CR_HITMEN | ICACHE_CR_MISSMEN) /*!< Hit & Miss monitoring */
#define ICACHE_MONITOR_HIT ICACHE_CR_HITMEN /*!< Hit monitoring */
#define ICACHE_MONITOR_MISS ICACHE_CR_MISSMEN /*!< Miss monitoring */
/**
* @}
*/
/** @defgroup ICACHE_Region Remapped Region number
* @{
*/
#define ICACHE_REGION_0 0U /*!< Region 0 */
#define ICACHE_REGION_1 1U /*!< Region 1 */
#define ICACHE_REGION_2 2U /*!< Region 2 */
#define ICACHE_REGION_3 3U /*!< Region 3 */
/**
* @}
*/
/** @defgroup ICACHE_Region_Size Remapped Region size
* @{
*/
#define ICACHE_REGIONSIZE_2MB 1U /*!< Region size 2MB */
#define ICACHE_REGIONSIZE_4MB 2U /*!< Region size 4MB */
#define ICACHE_REGIONSIZE_8MB 3U /*!< Region size 8MB */
#define ICACHE_REGIONSIZE_16MB 4U /*!< Region size 16MB */
#define ICACHE_REGIONSIZE_32MB 5U /*!< Region size 32MB */
#define ICACHE_REGIONSIZE_64MB 6U /*!< Region size 64MB */
#define ICACHE_REGIONSIZE_128MB 7U /*!< Region size 128MB */
/**
* @}
*/
/** @defgroup ICACHE_Traffic_Route Remapped Traffic route
* @{
*/
#define ICACHE_MASTER1_PORT 0U /*!< Master1 port */
#define ICACHE_MASTER2_PORT ICACHE_CRRx_MSTSEL /*!< Master2 port */
/**
* @}
*/
/** @defgroup ICACHE_Output_Burst_Type Remapped Output burst type
* @{
*/
#define ICACHE_OUTPUT_BURST_WRAP 0U /*!< WRAP */
#define ICACHE_OUTPUT_BURST_INCR ICACHE_CRRx_HBURST /*!< INCR */
/**
* @}
*/
/** @defgroup ICACHE_Interrupts Interrupts
* @{
*/
#define ICACHE_IT_BUSYEND ICACHE_IER_BSYENDIE /*!< Busy end interrupt */
#define ICACHE_IT_ERROR ICACHE_IER_ERRIE /*!< Cache error interrupt */
/**
* @}
*/
/** @defgroup ICACHE_Flags Flags
* @{
*/
#define ICACHE_FLAG_BUSY ICACHE_SR_BUSYF /*!< Busy flag */
#define ICACHE_FLAG_BUSYEND ICACHE_SR_BSYENDF /*!< Busy end flag */
#define ICACHE_FLAG_ERROR ICACHE_SR_ERRF /*!< Cache error flag */
/**
* @}
*/
/**
* @}
*/
/* Exported macros ----------------------------------------------------------*/
/** @defgroup ICACHE_Exported_Macros ICACHE Exported Macros
* @{
*/
/** @defgroup ICACHE_Flags_Interrupts_Management Flags and Interrupts Management
* @brief macros to manage the specified ICACHE flags and interrupts.
* @{
*/
/** @brief Enable ICACHE interrupts.
* @param __INTERRUPT__ specifies the ICACHE interrupt sources to be enabled.
* This parameter can be any combination of the following values:
* @arg @ref ICACHE_IT_BUSYEND Busy end interrupt
* @arg @ref ICACHE_IT_ERROR Cache error interrupt
*/
#define __HAL_ICACHE_ENABLE_IT(__INTERRUPT__) SET_BIT(ICACHE->IER, (__INTERRUPT__))
/** @brief Disable ICACHE interrupts.
* @param __INTERRUPT__ specifies the ICACHE interrupt sources to be disabled.
* This parameter can be any combination of the following values:
* @arg @ref ICACHE_IT_BUSYEND Busy end interrupt
* @arg @ref ICACHE_IT_ERROR Cache error interrupt
*/
#define __HAL_ICACHE_DISABLE_IT(__INTERRUPT__) CLEAR_BIT(ICACHE->IER, (__INTERRUPT__))
/** @brief Check whether the specified ICACHE interrupt source is enabled or not.
* @param __INTERRUPT__ specifies the ICACHE interrupt source to check.
* This parameter can be any combination of the following values:
* @arg @ref ICACHE_IT_BUSYEND Busy end interrupt
* @arg @ref ICACHE_IT_ERROR Cache error interrupt
* @retval The state of __INTERRUPT__ (0 or 1).
*/
#define __HAL_ICACHE_GET_IT_SOURCE(__INTERRUPT__) \
((READ_BIT(ICACHE->IER, (__INTERRUPT__)) == (__INTERRUPT__)) ? 1U : 0U)
/** @brief Check whether the selected ICACHE flag is set or not.
* @param __FLAG__ specifies the flag to check.
* This parameter can be one of the following values:
* @arg @ref ICACHE_FLAG_BUSY Busy flag
* @arg @ref ICACHE_FLAG_BUSYEND Busy end flag
* @arg @ref ICACHE_FLAG_ERROR Cache error flag
* @retval The state of __FLAG__ (0 or 1).
*/
#define __HAL_ICACHE_GET_FLAG(__FLAG__) ((READ_BIT(ICACHE->SR, (__FLAG__)) != 0U) ? 1U : 0U)
/** @brief Clear the selected ICACHE flags.
* @param __FLAG__ specifies the ICACHE flags to clear.
* This parameter can be any combination of the following values:
* @arg @ref ICACHE_FLAG_BUSYEND Busy end flag
* @arg @ref ICACHE_FLAG_ERROR Cache error flag
*/
#define __HAL_ICACHE_CLEAR_FLAG(__FLAG__) WRITE_REG(ICACHE->FCR, (__FLAG__))
/**
* @}
*/
/**
* @}
*/
/* Exported functions -------------------------------------------------------*/
/** @addtogroup ICACHE_Exported_Functions
* @{
*/
/** @addtogroup ICACHE_Exported_Functions_Group1
* @brief Initialization and control functions
* @{
*/
/* Peripheral Control functions **********************************************/
HAL_StatusTypeDef HAL_ICACHE_Enable(void);
HAL_StatusTypeDef HAL_ICACHE_Disable(void);
uint32_t HAL_ICACHE_IsEnabled(void);
HAL_StatusTypeDef HAL_ICACHE_ConfigAssociativityMode(uint32_t AssociativityMode);
HAL_StatusTypeDef HAL_ICACHE_DeInit(void);
/******* Invalidate in blocking mode (Polling) */
HAL_StatusTypeDef HAL_ICACHE_Invalidate(void);
/******* Invalidate in non-blocking mode (Interrupt) */
HAL_StatusTypeDef HAL_ICACHE_Invalidate_IT(void);
/******* Wait for Invalidate complete in blocking mode (Polling) */
HAL_StatusTypeDef HAL_ICACHE_WaitForInvalidateComplete(void);
/******* Performance instruction cache monitoring functions */
HAL_StatusTypeDef HAL_ICACHE_Monitor_Start(uint32_t MonitorType);
HAL_StatusTypeDef HAL_ICACHE_Monitor_Stop(uint32_t MonitorType);
HAL_StatusTypeDef HAL_ICACHE_Monitor_Reset(uint32_t MonitorType);
uint32_t HAL_ICACHE_Monitor_GetHitValue(void);
uint32_t HAL_ICACHE_Monitor_GetMissValue(void);
/**
* @}
*/
/** @addtogroup ICACHE_Exported_Functions_Group2
* @brief IRQ and callback functions
* @{
*/
/******* IRQHandler and Callbacks used in non-blocking mode (Interrupt) */
void HAL_ICACHE_IRQHandler(void);
void HAL_ICACHE_InvalidateCompleteCallback(void);
void HAL_ICACHE_ErrorCallback(void);
/**
* @}
*/
/** @addtogroup ICACHE_Exported_Functions_Group3
* @brief Memory remapped regions functions
* @{
*/
/******* Memory remapped regions functions */
HAL_StatusTypeDef HAL_ICACHE_EnableRemapRegion(uint32_t Region, const ICACHE_RegionConfigTypeDef *const pRegionConfig);
HAL_StatusTypeDef HAL_ICACHE_DisableRemapRegion(uint32_t Region);
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
#endif /* ICACHE */
#ifdef __cplusplus
}
#endif
#endif /* STM32U3xx_HAL_ICACHE_H */

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Software/Station_SW/Drivers/STM32U3xx_HAL_Driver/Inc/stm32u3xx_hal_pwr_ex.h Normal file
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/**
******************************************************************************
* @file stm32u3xx_hal_pwr_ex.h
* @author GPM Application Team
* @brief Header file of PWR HAL Extended module.
******************************************************************************
* @attention
*
* Copyright (c) 2023 STMicroelectronics.
* All rights reserved.
*
* This software is licensed under terms that can be found in the LICENSE file
* in the root directory of this software component.
* If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef STM32U3xx_HAL_PWR_EX_H
#define STM32U3xx_HAL_PWR_EX_H
#ifdef __cplusplus
extern "C" {
#endif /* __cplusplus */
/* Includes ------------------------------------------------------------------*/
#include "stm32u3xx_hal_def.h"
/** @addtogroup STM32U3xx_HAL_Driver
* @{
*/
/** @addtogroup PWREx
* @{
*/
/* Exported types ------------------------------------------------------------*/
/** @defgroup PWREx_Exported_Types PWR Extended Exported Types
* @{
*/
/**
* @}
*/
/* Exported constants --------------------------------------------------------*/
/** @defgroup PWREx_Exported_Constants PWR Extended Exported Constants
* @{
*/
/** @defgroup PWREx_RAM_PowerDown PWR Extended SRAM Power Down
* @{
*/
#define PWR_SRAM1_POWERDOWN PWR_CR1_SRAM1PD /*!< SRAM1 power down */
#define PWR_SRAM2_POWERDOWN PWR_CR1_SRAM2PD /*!< SRAM2 power down */
#if defined(RAMCFG_SRAM3)
#define PWR_SRAM3_POWERDOWN PWR_CR1_SRAM3PD /*!< SRAM3 power down */
#define PWR_SRAM4_POWERDOWN PWR_CR1_SRAM4PD /*!< SRAM4 power down */
#endif /* RAMCFG_SRAM3 */
/**
* @}
*/
/** @defgroup PWREx_RAM_Contents_Stop_Retention PWR Extended SRAM Contents Stop Retention
* @{
*/
/* SRAM1 pages retention defines */
#define PWR_SRAM1_PAGE1_STOP_RETENTION PWR_CR2_SRAM1PDS1 /*!< SRAM1 page 1 retention in Stop modes (Stop 0, 1, 2, 3) */
#define PWR_SRAM1_PAGE2_STOP_RETENTION PWR_CR2_SRAM1PDS2 /*!< SRAM1 page 2 retention in Stop modes (Stop 0, 1, 2, 3) */
#define PWR_SRAM1_PAGE3_STOP_RETENTION PWR_CR2_SRAM1PDS3 /*!< SRAM1 page 3 retention in Stop modes (Stop 0, 1, 2, 3) */
#define PWR_SRAM1_PAGE4_STOP_RETENTION PWR_CR2_SRAM1PDS4 /*!< SRAM1 page 4 retention in Stop modes (Stop 0, 1, 2, 3) */
#define PWR_SRAM1_PAGE5_STOP_RETENTION PWR_CR2_SRAM1PDS5 /*!< SRAM1 page 5 retention in Stop modes (Stop 0, 1, 2, 3) */
#if defined(PWR_CR2_SRAM1PDS6)
#define PWR_SRAM1_PAGE6_STOP_RETENTION PWR_CR2_SRAM1PDS6 /*!< SRAM1 page 6 retention in Stop modes (Stop 0, 1, 2, 3) */
#define PWR_SRAM1_PAGE7_STOP_RETENTION PWR_CR2_SRAM1PDS7 /*!< SRAM1 page 7 retention in Stop modes (Stop 0, 1, 2, 3) */
#define PWR_SRAM1_FULL_STOP_RETENTION (PWR_CR2_SRAM1PDS1 | PWR_CR2_SRAM1PDS2 | PWR_CR2_SRAM1PDS3 | PWR_CR2_SRAM1PDS4 |\
PWR_CR2_SRAM1PDS5 | PWR_CR2_SRAM1PDS6 | PWR_CR2_SRAM1PDS7)
/*!< SRAM1 full retention in Stop modes (Stop 0, 1, 2, 3) */
#else
#define PWR_SRAM1_FULL_STOP_RETENTION (PWR_CR2_SRAM1PDS1 | PWR_CR2_SRAM1PDS2 | PWR_CR2_SRAM1PDS3 | PWR_CR2_SRAM1PDS4 |\
PWR_CR2_SRAM1PDS5)
/*!< SRAM1 full retention in Stop modes (Stop 0, 1, 2, 3) */
#endif /* PWR_CR2_SRAM1PDS6 */
/* SRAM2 pages retention defines */
#define PWR_SRAM2_PAGE1_STOP_RETENTION PWR_CR2_SRAM2PDS1 /*!< SRAM2 page 1 retention in Stop modes (Stop 0, 1, 2, 3) */
#define PWR_SRAM2_PAGE2_STOP_RETENTION PWR_CR2_SRAM2PDS2 /*!< SRAM2 page 2 retention in Stop modes (Stop 0, 1, 2, 3) */
#define PWR_SRAM2_PAGE3_STOP_RETENTION PWR_CR2_SRAM2PDS3 /*!< SRAM2 page 3 retention in Stop modes (Stop 0, 1, 2, 3) */
#define PWR_SRAM2_FULL_STOP_RETENTION (PWR_CR2_SRAM2PDS1 | PWR_CR2_SRAM2PDS2 | PWR_CR2_SRAM2PDS3)
/*!< SRAM2 full retention in Stop modes (Stop 0, 1, 2, 3) */
#if defined(RAMCFG_SRAM3)
/* SRAM3 pages retention defines */
#define PWR_SRAM3_PAGE1_STOP_RETENTION PWR_CR2_SRAM3PDS1 /*!< SRAM3 page 1 retention in Stop modes (Stop 0, 1, 2, 3) */
#define PWR_SRAM3_PAGE2_STOP_RETENTION PWR_CR2_SRAM3PDS2 /*!< SRAM3 page 2 retention in Stop modes (Stop 0, 1, 2, 3) */
#define PWR_SRAM3_PAGE3_STOP_RETENTION PWR_CR2_SRAM3PDS3 /*!< SRAM3 page 3 retention in Stop modes (Stop 0, 1, 2, 3) */
#define PWR_SRAM3_PAGE4_STOP_RETENTION PWR_CR2_SRAM3PDS4 /*!< SRAM3 page 4 retention in Stop modes (Stop 0, 1, 2, 3) */
#define PWR_SRAM3_PAGE5_STOP_RETENTION PWR_CR2_SRAM3PDS5 /*!< SRAM3 page 5 retention in Stop modes (Stop 0, 1, 2, 3) */
#define PWR_SRAM3_FULL_STOP_RETENTION (PWR_CR2_SRAM1PDS1 | PWR_CR2_SRAM1PDS2 | PWR_CR2_SRAM1PDS3 | PWR_CR2_SRAM1PDS4 |\
PWR_CR2_SRAM1PDS5)
/*!< SRAM3 full retention in Stop modes (Stop 0, 1, 2, 3) */
/* SRAM4 pages retention defines */
#define PWR_SRAM4_FULL_STOP_RETENTION PWR_CR2_SRAM4PDS /*!< SRAM4 full retention in Stop modes (Stop 0, 1, 2, 3) */
#endif /* defined(RAMCFG_SRAM3) */
/* I-Cache SRAM retention defines */
#define PWR_ICACHE_STOP_RETENTION PWR_CR2_ICRAMPDS /*!< ICACHE SRAM retention in Stop modes (Stop 0, 1, 2, 3) */
/* FDCAN & USB SRAM retention defines */
#define PWR_FDCAN_USB_STOP_RETENTION PWR_CR2_PRAMPDS /*!< FDCAN & USB SRAM retention in Stop modes
(Stop 0, 1, 2, 3) */
/* PKA SRAM retention defines */
#define PWR_PKA_STOP_RETENTION PWR_CR2_PKARAMPDS /*!< PKA SRAM retention in Stop modes (Stop 0, 1, 2, 3) */
/**
* @}
*/
/** @defgroup PWREx_RAM_Contents_Standby_Retention PWR Extended SRAM Contents Standby Retention
* @{
*/
#define PWR_SRAM2_PAGE1_STANDBY_RETENTION PWR_CR1_RRSB1 /*!< SRAM2 page 1 retention in Standby mode */
#define PWR_SRAM2_PAGE2_STANDBY_RETENTION PWR_CR1_RRSB2 /*!< SRAM2 page 2 retention in Standby mode */
#define PWR_SRAM2_PAGE3_STANDBY_RETENTION PWR_CR1_RRSB3 /*!< SRAM2 page 3 retention in Standby mode */
#define PWR_SRAM2_FULL_STANDBY_RETENTION (PWR_CR1_RRSB1 |PWR_CR1_RRSB2 |PWR_CR1_RRSB3 )
/*!< SRAM2 full retention in Standby mode */
/**
* @}
*/
/** @defgroup PWREx_Supply_Configuration PWR Extended Supply Configuration
* @{
*/
#define PWR_LDO_SUPPLY (0U) /*!< LDO supply */
#define PWR_SMPS_SUPPLY PWR_CR3_REGSEL /*!< SMPS supply */
/**
* @}
*/
/** @defgroup PWREx_Regulator_Voltage_Scale PWR Extended Regulator Voltage Scale
* @{
*/
#define PWR_REGULATOR_VOLTAGE_SCALE1 PWR_VOSR_R1EN /*!< Voltage scaling range 1 */
#define PWR_REGULATOR_VOLTAGE_SCALE2 PWR_VOSR_R2EN /*!< Voltage scaling range 2 */
/**
* @}
*/
/** @defgroup PWREx_VBAT_Battery_Charging_Selection PWR Extended Battery Charging Resistor Selection
* @{
*/
#define PWR_BATTERY_CHARGING_RESISTOR_5 (0U) /*!< VBAT charging through a 5 kOhms resistor */
#define PWR_BATTERY_CHARGING_RESISTOR_1_5 PWR_BDCR_VBRS /*!< VBAT charging through a 1.5 kOhms resistor */
/**
* @}
*/
/** @defgroup PWREx_GPIO_Port PWR Extended GPIO Port
* @{
*/
#define PWR_GPIO_A (0U) /*!< GPIO port A */
#define PWR_GPIO_B (1U) /*!< GPIO port B */
#define PWR_GPIO_C (2U) /*!< GPIO port C */
#define PWR_GPIO_D (3U) /*!< GPIO port D */
#define PWR_GPIO_E (4U) /*!< GPIO port E */
#if defined(RAMCFG_SRAM3)
#define PWR_GPIO_F (5U) /*!< GPIO port F */
#endif /* RAMCFG_SRAM3 */
#if defined(PWR_PDCRG_PD15)
#define PWR_GPIO_G (6U) /*!< GPIO port G */
#endif /* PWR_PDCRG_PD15 */
#define PWR_GPIO_H (7U) /*!< GPIO port H */
/**
* @}
*/
/** @defgroup PWREx_GPIO_Pin_Mask PWR Extended GPIO Pin Mask
* @{
*/
#define PWR_GPIO_BIT_0 (0x00001U) /*!< GPIO port I/O pin 0 */
#define PWR_GPIO_BIT_1 (0x00002U) /*!< GPIO port I/O pin 1 */
#define PWR_GPIO_BIT_2 (0x00004U) /*!< GPIO port I/O pin 2 */
#define PWR_GPIO_BIT_3 (0x00008U) /*!< GPIO port I/O pin 3 */
#define PWR_GPIO_BIT_4 (0x00010U) /*!< GPIO port I/O pin 4 */
#define PWR_GPIO_BIT_5 (0x00020U) /*!< GPIO port I/O pin 5 */
#define PWR_GPIO_BIT_6 (0x00040U) /*!< GPIO port I/O pin 6 */
#define PWR_GPIO_BIT_7 (0x00080U) /*!< GPIO port I/O pin 7 */
#define PWR_GPIO_BIT_8 (0x00100U) /*!< GPIO port I/O pin 8 */
#define PWR_GPIO_BIT_9 (0x00200U) /*!< GPIO port I/O pin 9 */
#define PWR_GPIO_BIT_10 (0x00400U) /*!< GPIO port I/O pin 10 */
#define PWR_GPIO_BIT_11 (0x00800U) /*!< GPIO port I/O pin 11 */
#define PWR_GPIO_BIT_12 (0x01000U) /*!< GPIO port I/O pin 12 */
#define PWR_GPIO_BIT_13 (0x02000U) /*!< GPIO port I/O pin 13 */
#define PWR_GPIO_BIT_14 (0x04000U) /*!< GPIO port I/O pin 14 */
#define PWR_GPIO_BIT_15 (0x08000U) /*!< GPIO port I/O pin 15 */
#define PWR_GPIO_PIN_MASK (0x0FFFFU)
/**
* @}
*/
/** @defgroup PWREx_I3C_PULLUP_GPIO PWR Extended I3C Pull-up Configuration
* @{
*/
#define PWR_I3CPU_PA1 PWR_I3CPUCR1_PA1_I3CPU /*!< I3C pull-up on PA1 */
#define PWR_I3CPU_PA6 PWR_I3CPUCR1_PA6_I3CPU /*!< I3C pull-up on PA6 */
#define PWR_I3CPU_PA7 PWR_I3CPUCR1_PA7_I3CPU /*!< I3C pull-up on PA7 */
#define PWR_I3CPU_PB2 PWR_I3CPUCR1_PB2_I3CPU /*!< I3C pull-up on PB2 */
#define PWR_I3CPU_PB6 PWR_I3CPUCR1_PB6_I3CPU /*!< I3C pull-up on PB6 */
#if defined(RAMCFG_SRAM3)
#define PWR_I3CPU_PB7 PWR_I3CPUCR1_PB7_I3CPU /*!< I3C pull-up on PB7 */
#endif /* RAMCFG_SRAM3 */
#if defined(PWR_I3CPUCR1_PB8_I3CPU)
#define PWR_I3CPU_PB8 PWR_I3CPUCR1_PB8_I3CPU /*!< I3C pull-up on PB8 */
#define PWR_I3CPU_PB9 PWR_I3CPUCR1_PB9_I3CPU /*!< I3C pull-up on PB9 */
#endif /* PWR_I3CPUCR1_PB8_I3CPU */
#define PWR_I3CPU_PB10 PWR_I3CPUCR1_PB10_I3CPU /*!< I3C pull-up on PB10 */
#define PWR_I3CPU_PB12 PWR_I3CPUCR1_PB12_I3CPU /*!< I3C pull-up on PB12 */
#define PWR_I3CPU_PB13 PWR_I3CPUCR1_PB13_I3CPU /*!< I3C pull-up on PB13 */
#if defined(PWR_I3CPUCR1_PB8_I3CPU)
#define PWR_I3CPU_PB14 PWR_I3CPUCR1_PB14_I3CPU /*!< I3C pull-up on PB14 */
#define PWR_I3CPU_PC0 (PWR_I3CPUCR2_PC0_I3CPU << PWR_I3CUPCR2_OFFSET) /*!< I3C pull-up on PC0 */
#endif /* PWR_I3CPUCR1_PB8_I3CPU */
#define PWR_I3CPU_PC1 (PWR_I3CPUCR2_PC1_I3CPU << PWR_I3CUPCR2_OFFSET) /*!< I3C pull-up on PC1 */
#define PWR_I3CPU_PD12 (PWR_I3CPUCR2_PD12_I3CPU << PWR_I3CUPCR2_OFFSET) /*!< I3C pull-up on PD12 */
#define PWR_I3CPU_PD13 (PWR_I3CPUCR2_PD13_I3CPU << PWR_I3CUPCR2_OFFSET) /*!< I3C pull-up on PD13 */
#if defined(PWR_I3CPUCR1_PB8_I3CPU)
#define PWR_I3CPU_PG7 (PWR_I3CPUCR2_PG7_I3CPU << PWR_I3CUPCR2_OFFSET) /*!< I3C pull-up on PG7 */
#define PWR_I3CPU_PG8 (PWR_I3CPUCR2_PG8_I3CPU << PWR_I3CUPCR2_OFFSET) /*!< I3C pull-up on PG8 */
#define PWR_I3CPU_PG13 (PWR_I3CPUCR2_PG13_I3CPU << PWR_I3CUPCR2_OFFSET) /*!< I3C pull-up on PG13 */
#define PWR_I3CPU_PG14 (PWR_I3CPUCR2_PG14_I3CPU << PWR_I3CUPCR2_OFFSET) /*!< I3C pull-up on PG14 */
#endif /* PWR_I3CPUCR1_PB8_I3CPU */
#define PWR_I3CPU_PH3 (PWR_I3CPUCR2_PH3_I3CPU << PWR_I3CUPCR2_OFFSET) /*!< I3C pull-up on PH3 */
#if defined(RAMCFG_SRAM3)
#define PWR_I3CPUCR_ALL (PWR_I3CPU_PA1 | PWR_I3CPU_PA6 | PWR_I3CPU_PA7 | PWR_I3CPU_PB2 |\
PWR_I3CPU_PB6 | PWR_I3CPU_PB7 | PWR_I3CPU_PB8 | PWR_I3CPU_PB9 |\
PWR_I3CPU_PB10 | PWR_I3CPU_PB12 | PWR_I3CPU_PB13 | PWR_I3CPU_PB14 |\
PWR_I3CPU_PC0 | PWR_I3CPU_PC1 | PWR_I3CPU_PD12 | PWR_I3CPU_PD13 |\
PWR_I3CPU_PG7 | PWR_I3CPU_PG8 | PWR_I3CPU_PG13 | PWR_I3CPU_PG14 |\
PWR_I3CPU_PH3)
#elif defined(PWR_I3CPUCR1_PB8_I3CPU)
#define PWR_I3CPUCR_ALL (PWR_I3CPU_PA1 | PWR_I3CPU_PA6 | PWR_I3CPU_PA7 | PWR_I3CPU_PB2 |\
PWR_I3CPU_PB6 | PWR_I3CPU_PB8 | PWR_I3CPU_PB9 | PWR_I3CPU_PB10 |\
PWR_I3CPU_PB12 | PWR_I3CPU_PB13 | PWR_I3CPU_PB14 | PWR_I3CPU_PC0 |\
PWR_I3CPU_PC1 | PWR_I3CPU_PD12 | PWR_I3CPU_PD13 | PWR_I3CPU_PG7 |\
PWR_I3CPU_PG8 | PWR_I3CPU_PG13 | PWR_I3CPU_PG14 | PWR_I3CPU_PH3)
#else
#define PWR_I3CPUCR_ALL (PWR_I3CPU_PA1 | PWR_I3CPU_PA6 | PWR_I3CPU_PA7 | PWR_I3CPU_PB2 |\
PWR_I3CPU_PB6 | PWR_I3CPU_PB10 | PWR_I3CPU_PB12 | PWR_I3CPU_PB13 |\
PWR_I3CPU_PC1 | PWR_I3CPU_PD12 | PWR_I3CPU_PD13 | PWR_I3CPU_PH3)
#endif /* defined(RAMCFG_SRAM3)*/
/*!< I3C pull-up all */
/**
* @}
*/
/**
* @}
*/
/* Exported macros -----------------------------------------------------------*/
/** @defgroup PWREx_Exported_Macros PWR Extended Exported Macros
* @{
*/
/**
* @}
*/
/* Private constants ---------------------------------------------------------*/
/** @addtogroup PWREx_Private_Constants PWR Extended Private Constants
* @{
*/
/* All available RAM retention in Standby mode define */
#define PWR_ALL_RAM_STANDBY_RETENTION_MASK (PWR_SRAM2_FULL_STANDBY_RETENTION)
/* Offset for I3C Pull-Up Configuration */
#define PWR_I3CUPCR2_OFFSET (16U)
/**
* @}
*/
/* Private macros --------------------------------------------------------*/
/** @addtogroup PWREx_Private_Macros PWR Extended Private Macros
* @{
*/
/* Supply selection check macro */
#define IS_PWR_SUPPLY(__PWR_SOURCE__) (((__PWR_SOURCE__) == PWR_LDO_SUPPLY) ||\
((__PWR_SOURCE__) == PWR_SMPS_SUPPLY))
/* Voltage scaling range check macro */
#define IS_PWR_VOLTAGE_SCALING_RANGE(__RANGE__) (((__RANGE__) == PWR_REGULATOR_VOLTAGE_SCALE1) ||\
((__RANGE__) == PWR_REGULATOR_VOLTAGE_SCALE2))
/* Battery charging resistor selection check macro */
#define IS_PWR_BATTERY_RESISTOR_SELECT(__RESISTOR__) (((__RESISTOR__) == PWR_BATTERY_CHARGING_RESISTOR_5) ||\
((__RESISTOR__) == PWR_BATTERY_CHARGING_RESISTOR_1_5))
/* GPIO port check macro */
#if defined(RAMCFG_SRAM3)
#define IS_PWR_GPIO_PORT(__GPIO_PORT__) (((__GPIO_PORT__) == PWR_GPIO_A) ||\
((__GPIO_PORT__) == PWR_GPIO_B) ||\
((__GPIO_PORT__) == PWR_GPIO_C) ||\
((__GPIO_PORT__) == PWR_GPIO_D) ||\
((__GPIO_PORT__) == PWR_GPIO_E) ||\
((__GPIO_PORT__) == PWR_GPIO_F) ||\
((__GPIO_PORT__) == PWR_GPIO_G) ||\
((__GPIO_PORT__) == PWR_GPIO_H))
#else
#if defined(PWR_GPIO_G)
#define IS_PWR_GPIO_PORT(__GPIO_PORT__) (((__GPIO_PORT__) == PWR_GPIO_A) ||\
((__GPIO_PORT__) == PWR_GPIO_B) ||\
((__GPIO_PORT__) == PWR_GPIO_C) ||\
((__GPIO_PORT__) == PWR_GPIO_D) ||\
((__GPIO_PORT__) == PWR_GPIO_E) ||\
((__GPIO_PORT__) == PWR_GPIO_G) ||\
((__GPIO_PORT__) == PWR_GPIO_H))
#else
#define IS_PWR_GPIO_PORT(__GPIO_PORT__) (((__GPIO_PORT__) == PWR_GPIO_A) ||\
((__GPIO_PORT__) == PWR_GPIO_B) ||\
((__GPIO_PORT__) == PWR_GPIO_C) ||\
((__GPIO_PORT__) == PWR_GPIO_D) ||\
((__GPIO_PORT__) == PWR_GPIO_E) ||\
((__GPIO_PORT__) == PWR_GPIO_H))
#endif /* PWR_GPIO_G */
#endif /* defined(RAMCFG_SRAM3) */
/* GPIO pin mask check macro */
#define IS_PWR_GPIO_PIN_MASK(__BIT_MASK__) ((((__BIT_MASK__) & PWR_GPIO_PIN_MASK) != 0U) &&\
((__BIT_MASK__) <= PWR_GPIO_PIN_MASK))
/* RAMs power down check macro */
#if defined(RAMCFG_SRAM3)
#define IS_PWR_RAM_POWERDOWN(__RAM__) (((__RAM__) == PWR_SRAM1_POWERDOWN) ||\
((__RAM__) == PWR_SRAM2_POWERDOWN) ||\
((__RAM__) == PWR_SRAM3_POWERDOWN) ||\
((__RAM__) == PWR_SRAM4_POWERDOWN))
#else
#define IS_PWR_RAM_POWERDOWN(__RAM__) (((__RAM__) == PWR_SRAM1_POWERDOWN) ||\
((__RAM__) == PWR_SRAM2_POWERDOWN))
#endif /* RAMCFG_SRAM3 */
/* RAMs retention in Stop mode check macro */
#if defined(RAMCFG_SRAM3)
#define IS_PWR_RAM_STOP_RETENTION(__RAM__) (((__RAM__) == PWR_SRAM1_PAGE1_STOP_RETENTION) ||\
((__RAM__) == PWR_SRAM1_PAGE2_STOP_RETENTION) ||\
((__RAM__) == PWR_SRAM1_PAGE3_STOP_RETENTION) ||\
((__RAM__) == PWR_SRAM1_PAGE4_STOP_RETENTION) ||\
((__RAM__) == PWR_SRAM1_PAGE5_STOP_RETENTION) ||\
((__RAM__) == PWR_SRAM1_PAGE6_STOP_RETENTION) ||\
((__RAM__) == PWR_SRAM1_PAGE7_STOP_RETENTION) ||\
((__RAM__) == PWR_SRAM1_FULL_STOP_RETENTION) ||\
((__RAM__) == PWR_SRAM2_PAGE1_STOP_RETENTION) ||\
((__RAM__) == PWR_SRAM2_PAGE2_STOP_RETENTION) ||\
((__RAM__) == PWR_SRAM2_PAGE3_STOP_RETENTION) ||\
((__RAM__) == PWR_SRAM2_FULL_STOP_RETENTION) ||\
((__RAM__) == PWR_SRAM3_PAGE1_STOP_RETENTION) ||\
((__RAM__) == PWR_SRAM3_PAGE2_STOP_RETENTION) ||\
((__RAM__) == PWR_SRAM3_PAGE3_STOP_RETENTION) ||\
((__RAM__) == PWR_SRAM3_PAGE4_STOP_RETENTION) ||\
((__RAM__) == PWR_SRAM3_PAGE5_STOP_RETENTION) ||\
((__RAM__) == PWR_SRAM3_FULL_STOP_RETENTION) ||\
((__RAM__) == PWR_SRAM4_FULL_STOP_RETENTION) ||\
((__RAM__) == PWR_ICACHE_STOP_RETENTION) ||\
((__RAM__) == PWR_FDCAN_USB_STOP_RETENTION) ||\
((__RAM__) == PWR_PKA_STOP_RETENTION))
#elif defined(PWR_SRAM1_PAGE6_STOP_RETENTION)
#define IS_PWR_RAM_STOP_RETENTION(__RAM__) (((__RAM__) == PWR_SRAM1_PAGE1_STOP_RETENTION) ||\
((__RAM__) == PWR_SRAM1_PAGE2_STOP_RETENTION) ||\
((__RAM__) == PWR_SRAM1_PAGE3_STOP_RETENTION) ||\
((__RAM__) == PWR_SRAM1_PAGE4_STOP_RETENTION) ||\
((__RAM__) == PWR_SRAM1_PAGE5_STOP_RETENTION) ||\
((__RAM__) == PWR_SRAM1_PAGE6_STOP_RETENTION) ||\
((__RAM__) == PWR_SRAM1_PAGE7_STOP_RETENTION) ||\
((__RAM__) == PWR_SRAM1_FULL_STOP_RETENTION) ||\
((__RAM__) == PWR_SRAM2_PAGE1_STOP_RETENTION) ||\
((__RAM__) == PWR_SRAM2_PAGE2_STOP_RETENTION) ||\
((__RAM__) == PWR_SRAM2_PAGE3_STOP_RETENTION) ||\
((__RAM__) == PWR_SRAM2_FULL_STOP_RETENTION) ||\
((__RAM__) == PWR_ICACHE_STOP_RETENTION) ||\
((__RAM__) == PWR_FDCAN_USB_STOP_RETENTION) ||\
((__RAM__) == PWR_PKA_STOP_RETENTION))
#else
#define IS_PWR_RAM_STOP_RETENTION(__RAM__) (((__RAM__) == PWR_SRAM1_PAGE1_STOP_RETENTION) ||\
((__RAM__) == PWR_SRAM1_PAGE2_STOP_RETENTION) ||\
((__RAM__) == PWR_SRAM1_PAGE3_STOP_RETENTION) ||\
((__RAM__) == PWR_SRAM1_PAGE4_STOP_RETENTION) ||\
((__RAM__) == PWR_SRAM1_PAGE5_STOP_RETENTION) ||\
((__RAM__) == PWR_SRAM1_FULL_STOP_RETENTION) ||\
((__RAM__) == PWR_SRAM2_PAGE1_STOP_RETENTION) ||\
((__RAM__) == PWR_SRAM2_PAGE2_STOP_RETENTION) ||\
((__RAM__) == PWR_SRAM2_PAGE3_STOP_RETENTION) ||\
((__RAM__) == PWR_SRAM2_FULL_STOP_RETENTION) ||\
((__RAM__) == PWR_ICACHE_STOP_RETENTION) ||\
((__RAM__) == PWR_FDCAN_USB_STOP_RETENTION) ||\
((__RAM__) == PWR_PKA_STOP_RETENTION))
#endif /* RAMCFG_SRAM3 */
/* SRAM2 retention in Standby mode check macro */
#define IS_PWR_SRAM2_STANDBY_RETENTION(__PAGE__) (((__PAGE__) == PWR_SRAM2_PAGE1_STANDBY_RETENTION) ||\
((__PAGE__) == PWR_SRAM2_PAGE2_STANDBY_RETENTION) ||\
((__PAGE__) == PWR_SRAM2_PAGE3_STANDBY_RETENTION) ||\
((__PAGE__) == PWR_SRAM2_FULL_STANDBY_RETENTION))
/* I3C Pull-up configuration check macro */
#if defined(PWR_I3CPU_PB7)
#define IS_PWR_I3C_PULLUP_GPIO(__GPIO__) (((__GPIO__) == PWR_I3CPU_PA1) ||\
((__GPIO__) == PWR_I3CPU_PA6) ||\
((__GPIO__) == PWR_I3CPU_PA7) ||\
((__GPIO__) == PWR_I3CPU_PB2) ||\
((__GPIO__) == PWR_I3CPU_PB6) ||\
((__GPIO__) == PWR_I3CPU_PB7) ||\
((__GPIO__) == PWR_I3CPU_PB8) ||\
((__GPIO__) == PWR_I3CPU_PB9) ||\
((__GPIO__) == PWR_I3CPU_PB10) ||\
((__GPIO__) == PWR_I3CPU_PB12) ||\
((__GPIO__) == PWR_I3CPU_PB13) ||\
((__GPIO__) == PWR_I3CPU_PB14) ||\
((__GPIO__) == PWR_I3CPU_PC0) ||\
((__GPIO__) == PWR_I3CPU_PC1) ||\
((__GPIO__) == PWR_I3CPU_PD12) ||\
((__GPIO__) == PWR_I3CPU_PD13) ||\
((__GPIO__) == PWR_I3CPU_PG7) ||\
((__GPIO__) == PWR_I3CPU_PG8) ||\
((__GPIO__) == PWR_I3CPU_PG13) ||\
((__GPIO__) == PWR_I3CPU_PG14) ||\
((__GPIO__) == PWR_I3CPU_PH3) ||\
((__GPIO__) == PWR_I3CPUCR_ALL))
#elif defined(PWR_I3CPU_PB8)
#define IS_PWR_I3C_PULLUP_GPIO(__GPIO__) (((__GPIO__) == PWR_I3CPU_PA1) ||\
((__GPIO__) == PWR_I3CPU_PA6) ||\
((__GPIO__) == PWR_I3CPU_PA7) ||\
((__GPIO__) == PWR_I3CPU_PB2) ||\
((__GPIO__) == PWR_I3CPU_PB6) ||\
((__GPIO__) == PWR_I3CPU_PB8) ||\
((__GPIO__) == PWR_I3CPU_PB9) ||\
((__GPIO__) == PWR_I3CPU_PB10) ||\
((__GPIO__) == PWR_I3CPU_PB12) ||\
((__GPIO__) == PWR_I3CPU_PB13) ||\
((__GPIO__) == PWR_I3CPU_PB14) ||\
((__GPIO__) == PWR_I3CPU_PC0) ||\
((__GPIO__) == PWR_I3CPU_PC1) ||\
((__GPIO__) == PWR_I3CPU_PD12) ||\
((__GPIO__) == PWR_I3CPU_PD13) ||\
((__GPIO__) == PWR_I3CPU_PG7) ||\
((__GPIO__) == PWR_I3CPU_PG8) ||\
((__GPIO__) == PWR_I3CPU_PG13) ||\
((__GPIO__) == PWR_I3CPU_PG14) ||\
((__GPIO__) == PWR_I3CPU_PH3) ||\
((__GPIO__) == PWR_I3CPUCR_ALL))
#else
#define IS_PWR_I3C_PULLUP_GPIO(__GPIO__) (((__GPIO__) == PWR_I3CPU_PA1) ||\
((__GPIO__) == PWR_I3CPU_PA6) ||\
((__GPIO__) == PWR_I3CPU_PA7) ||\
((__GPIO__) == PWR_I3CPU_PB2) ||\
((__GPIO__) == PWR_I3CPU_PB6) ||\
((__GPIO__) == PWR_I3CPU_PB10) ||\
((__GPIO__) == PWR_I3CPU_PB12) ||\
((__GPIO__) == PWR_I3CPU_PB13) ||\
((__GPIO__) == PWR_I3CPU_PC1) ||\
((__GPIO__) == PWR_I3CPU_PD12) ||\
((__GPIO__) == PWR_I3CPU_PD13) ||\
((__GPIO__) == PWR_I3CPU_PH3) ||\
((__GPIO__) == PWR_I3CPUCR_ALL))
#endif /* defined(PWR_I3CPU_PB7) */
/**
* @}
*/
/** @addtogroup PWREx_Exported_Functions PWR Extended Exported Functions
* @{
*/
/** @addtogroup PWREx_Exported_Functions_Group1 Power Supply Control Functions
* @{
*/
HAL_StatusTypeDef HAL_PWREx_ControlVoltageScaling(uint32_t VoltageScaling);
uint32_t HAL_PWREx_GetVoltageRange(void);
void HAL_PWREx_EnableVddUSB(void);
void HAL_PWREx_DisableVddUSB(void);
#if defined(PWR_SVMCR_IO2SV)
void HAL_PWREx_EnableVddIO2(void);
void HAL_PWREx_DisableVddIO2(void);
#endif /* PWR_SVMCR_IO2SV */
void HAL_PWREx_EnableVddA(void);
void HAL_PWREx_DisableVddA(void);
HAL_StatusTypeDef HAL_PWREx_EnableEpodBooster(void);
HAL_StatusTypeDef HAL_PWREx_DisableEpodBooster(void);
HAL_StatusTypeDef HAL_PWREx_ConfigSupply(uint32_t SupplySource);
uint32_t HAL_PWREx_GetSupplyConfig(void);
void HAL_PWREx_EnableFastSoftStart(void);
void HAL_PWREx_DisableFastSoftStart(void);
void HAL_PWREx_EnableBatteryCharging(uint32_t ResistorValue);
void HAL_PWREx_DisableBatteryCharging(void);
/**
* @}
*/
/** @addtogroup PWREx_Exported_Functions_Group2 Low Power Control Functions
* @{
*/
void HAL_PWREx_EnterSHUTDOWNMode(void);
void HAL_PWREx_EnableUltraLowPowerMode(void);
void HAL_PWREx_DisableUltraLowPowerMode(void);
/**
* @}
*/
/** @addtogroup PWREx_Exported_Functions_Group3 Memories Retention Functions
* @{
*/
void HAL_PWREx_EnableRAMsPowerDown(uint32_t RAMSelection);
void HAL_PWREx_EnableRAMsContentStopRetention(uint32_t RAMSelection);
void HAL_PWREx_DisableRAMsContentStopRetention(uint32_t RAMSelection);
void HAL_PWREx_EnableSRAM2ContentStandbyRetention(uint32_t SRAM2Pages);
void HAL_PWREx_DisableSRAM2ContentStandbyRetention(uint32_t SRAM2Pages);
void HAL_PWREx_EnableFlashFastWakeUp(void);
void HAL_PWREx_DisableFlashFastWakeUp(void);
void HAL_PWREx_EnableSRAMFastWakeUp(void);
void HAL_PWREx_DisableSRAMFastWakeUp(void);
/**
* @}
*/
/** @addtogroup PWREx_Exported_Functions_Group4 I/O Pull-Up Pull-Down Configuration Functions
* @{
*/
void HAL_PWREx_EnablePullUpPullDownConfig(void);
void HAL_PWREx_DisablePullUpPullDownConfig(void);
HAL_StatusTypeDef HAL_PWREx_EnableGPIOPullUp(uint32_t GPIO_Port, uint32_t GPIO_Pin);
HAL_StatusTypeDef HAL_PWREx_DisableGPIOPullUp(uint32_t GPIO_Port, uint32_t GPIO_Pin);
HAL_StatusTypeDef HAL_PWREx_EnableGPIOPullDown(uint32_t GPIO_Port, uint32_t GPIO_Pin);
HAL_StatusTypeDef HAL_PWREx_DisableGPIOPullDown(uint32_t GPIO_Port, uint32_t GPIO_Pin);
/**
* @}
*/
/** @addtogroup PWREx_Exported_Functions_Group5 I3C Pull-Up Configuration Functions
* @{
*/
HAL_StatusTypeDef HAL_PWREx_EnableI3CPullUp(uint32_t Gpio);
HAL_StatusTypeDef HAL_PWREx_DisableI3CPullUp(uint32_t Gpio);
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
#ifdef __cplusplus
}
#endif /* __cplusplus */
#endif /* STM32U3xx_HAL_PWR_EX_H */

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/**
******************************************************************************
* @file stm32u3xx_hal_spi_ex.h
* @author MCD Application Team
* @brief Header file of SPI HAL Extended module.
******************************************************************************
* @attention
*
* Copyright (c) 2023 STMicroelectronics.
* All rights reserved.
*
* This software is licensed under terms that can be found in the LICENSE file
* in the root directory of this software component.
* If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef STM32U3xx_HAL_SPI_EX_H
#define STM32U3xx_HAL_SPI_EX_H
#ifdef __cplusplus
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include "stm32u3xx_hal_def.h"
/** @addtogroup STM32U3xx_HAL_Driver
* @{
*/
/** @addtogroup SPIEx
* @{
*/
/* Exported types ------------------------------------------------------------*/
/** @defgroup SPIEx_Exported_Types SPIEx Exported Types
* @{
*/
/**
* @brief SPI Autonomous Mode Configuration structure definition
*/
typedef struct
{
uint32_t TriggerState; /*!< Specifies the trigger state. This parameter can be a value
of @ref FunctionalState */
uint32_t TriggerSelection; /*!< Specifies the autonomous mode trigger signal selection. This parameter
can be a value of @ref SPI_AutonomousMode_TriggerSelection */
uint32_t TriggerPolarity; /*!< Specifies the autonomous mode trigger signal polarity sensitivity. This parameter
can be a value of @ref SPI_AutonomousMode_TriggerPolarity */
} SPI_AutonomousModeConfTypeDef;
/**
* @}
*/
/* Exported constants --------------------------------------------------------*/
/** @defgroup SPIEx_Exported_Constants SPIEx Exported Constants
* @{
*/
/** @defgroup FunctionalState SPI Autonomous Mode State
* @{
*/
#define SPI_AUTO_MODE_DISABLE (0x00000000UL)
#define SPI_AUTO_MODE_ENABLE SPI_AUTOCR_TRIGEN
/**
* @}
*/
/** @defgroup SPI_AutonomousMode_TriggerSelection Autonomous Mode Trigger Selection
* @{
*/
#define SPI_TRIG_GRP1 (0x10000000U) /* Trigger Group for SPI1 and SPI2 */
#define SPI_TRIG_GRP2 (0x20000000U) /* Trigger Group for SPI3 */
/* HW Trigger signal is GPDMA_CH0_TRG */
#define SPI_GRP1_GPDMA_CH0_TCF_TRG (uint32_t)(SPI_TRIG_GRP1 | (0x00000000U))
/* HW Trigger signal is GPDMA_CH1_TRG */
#define SPI_GRP1_GPDMA_CH1_TCF_TRG (uint32_t)(SPI_TRIG_GRP1 | (0x1U << SPI_AUTOCR_TRIGSEL_Pos))
/* HW Trigger signal is GPDMA_CH2_TRG */
#define SPI_GRP1_GPDMA_CH2_TCF_TRG (uint32_t)(SPI_TRIG_GRP1 | (0x2U << SPI_AUTOCR_TRIGSEL_Pos))
/* HW Trigger signal is GPDMA_CH3_TRG */
#define SPI_GRP1_GPDMA_CH3_TCF_TRG (uint32_t)(SPI_TRIG_GRP1 | (0x3U << SPI_AUTOCR_TRIGSEL_Pos))
/* HW Trigger signal is EXTI4_TRG */
#define SPI_GRP1_EXTI4_TRG (uint32_t)(SPI_TRIG_GRP1 | (0x4U << SPI_AUTOCR_TRIGSEL_Pos))
/* HW Trigger signal is EXTI9_TRG */
#define SPI_GRP1_EXTI9_TRG (uint32_t)(SPI_TRIG_GRP1 | (0x5U << SPI_AUTOCR_TRIGSEL_Pos))
/* HW Trigger signal is LPTIM1_CH1_TRG */
#define SPI_GRP1_LPTIM1_CH1_TRG (uint32_t)(SPI_TRIG_GRP1 | (0x6U << SPI_AUTOCR_TRIGSEL_Pos))
/* HW Trigger signal is LPTIM2_CH1_TRG */
#define SPI_GRP1_LPTIM2_CH1_TRG (uint32_t)(SPI_TRIG_GRP1 | (0x7U << SPI_AUTOCR_TRIGSEL_Pos))
/* HW Trigger signal is COMP1_TRG */
#define SPI_GRP1_COMP1_TRG (uint32_t)(SPI_TRIG_GRP1 | (0x8U << SPI_AUTOCR_TRIGSEL_Pos))
/* HW Trigger signal is COMP2_TRG */
#define SPI_GRP1_COMP2_TRG (uint32_t)(SPI_TRIG_GRP1 | (0x9U << SPI_AUTOCR_TRIGSEL_Pos))
/* HW Trigger signal is RTC_ALRA_TRG */
#define SPI_GRP1_RTC_ALRA_TRG (uint32_t)(SPI_TRIG_GRP1 | (0xAU << SPI_AUTOCR_TRIGSEL_Pos))
/* HW Trigger signal is RTC_WUT_TRG */
#define SPI_GRP1_RTC_WUT_TRG (uint32_t)(SPI_TRIG_GRP1 | (0xBU << SPI_AUTOCR_TRIGSEL_Pos))
/* HW Trigger signal is LPDMA_CH0_TRG */
#define SPI_GRP2_GPDMA_CH0_TCF_TRG (uint32_t)(SPI_TRIG_GRP2 | (0x00000000U))
/* HW Trigger signal is LPDMA_CH1_TRG */
#define SPI_GRP2_GPDMA_CH1_TCF_TRG (uint32_t)(SPI_TRIG_GRP2 | (0x1U << SPI_AUTOCR_TRIGSEL_Pos))
/* HW Trigger signal is LPDMA_CH2_TRG */
#define SPI_GRP2_GPDMA_CH2_TCF_TRG (uint32_t)(SPI_TRIG_GRP2 | (0x2U << SPI_AUTOCR_TRIGSEL_Pos))
/* HW Trigger signal is LPDMA_CH3_TRG */
#define SPI_GRP2_GPDMA_CH3_TCF_TRG (uint32_t)(SPI_TRIG_GRP2 | (0x3U << SPI_AUTOCR_TRIGSEL_Pos))
/* HW Trigger signal is EXTI4_TRG */
#define SPI_GRP2_EXTI4_TRG (uint32_t)(SPI_TRIG_GRP2 | (0x4U << SPI_AUTOCR_TRIGSEL_Pos))
/* HW Trigger signal is EXTI8_TRG */
#define SPI_GRP2_EXTI8_TRG (uint32_t)(SPI_TRIG_GRP2 | (0x5U << SPI_AUTOCR_TRIGSEL_Pos))
/* HW Trigger signal is LPTIM1_CH1_TRG */
#define SPI_GRP2_LPTIM1_CH1_TRG (uint32_t)(SPI_TRIG_GRP2 | (0x6U << SPI_AUTOCR_TRIGSEL_Pos))
/* HW Trigger signal is LPTIM3_CH1_TRG */
#define SPI_GRP2_LPTIM3_CH1_TRG (uint32_t)(SPI_TRIG_GRP2 | (0x7U << SPI_AUTOCR_TRIGSEL_Pos))
/* HW Trigger signal is COMP1_TRG */
#define SPI_GRP2_COMP1_TRG (uint32_t)(SPI_TRIG_GRP2 | (0x8U << SPI_AUTOCR_TRIGSEL_Pos))
/* HW Trigger signal is COMP2_TRG */
#define SPI_GRP2_COMP2_TRG (uint32_t)(SPI_TRIG_GRP2 | (0x9U << SPI_AUTOCR_TRIGSEL_Pos))
/* HW Trigger signal is RTC_ALRA_TRG */
#define SPI_GRP2_RTC_ALRA_TRG (uint32_t)(SPI_TRIG_GRP2 | (0xAU << SPI_AUTOCR_TRIGSEL_Pos))
/* HW Trigger signal is RTC_WUT_TRG */
#define SPI_GRP2_RTC_WUT_TRG (uint32_t)(SPI_TRIG_GRP2 | (0xBU << SPI_AUTOCR_TRIGSEL_Pos))
/**
* @}
*/
/** @defgroup SPI_AutonomousMode_TriggerPolarity Autonomous Mode Trigger Polarity
* @{
*/
#define SPI_TRIG_POLARITY_RISING (0x00000000UL) /* SPI HW Trigger signal on rising edge */
#define SPI_TRIG_POLARITY_FALLING SPI_AUTOCR_TRIGPOL /* SPI HW Trigger signal on falling edge */
/**
* @}
*/
/**
* @}
*/
/* Exported macros -----------------------------------------------------------*/
/** @defgroup SPIEx_Exported_Macros SPIEx Extended Exported Macros
* @{
*/
#define IS_SPI_AUTO_MODE(__MODE__) (((__MODE__) == SPI_AUTO_MODE_DISABLE) || \
((__MODE__) == SPI_AUTO_MODE_ENABLE))
#define IS_SPI_AUTONOMOUS_INSTANCE(__INSTANCE__) (IS_SPI_GRP1_INSTANCE(__INSTANCE__) || \
IS_SPI_GRP2_INSTANCE(__INSTANCE__))
#define IS_SPI_TRIG_SOURCE(__INSTANCE__, __SOURCE__) ((IS_SPI_GRP2_INSTANCE(__INSTANCE__)) ? \
IS_SPI_GRP2_TRIG_SOURCE(__SOURCE__) : \
IS_SPI_GRP1_TRIG_SOURCE(__SOURCE__))
#define IS_SPI_GRP1_TRIG_SOURCE(__SOURCE__) (((__SOURCE__) == SPI_GRP1_GPDMA_CH0_TCF_TRG ) || \
((__SOURCE__) == SPI_GRP1_GPDMA_CH1_TCF_TRG ) || \
((__SOURCE__) == SPI_GRP1_GPDMA_CH2_TCF_TRG ) || \
((__SOURCE__) == SPI_GRP1_GPDMA_CH3_TCF_TRG ) || \
((__SOURCE__) == SPI_GRP1_EXTI4_TRG ) || \
((__SOURCE__) == SPI_GRP1_EXTI9_TRG ) || \
((__SOURCE__) == SPI_GRP1_LPTIM1_CH1_TRG ) || \
((__SOURCE__) == SPI_GRP1_LPTIM2_CH1_TRG ) || \
((__SOURCE__) == SPI_GRP1_COMP1_TRG ) || \
((__SOURCE__) == SPI_GRP1_COMP2_TRG ) || \
((__SOURCE__) == SPI_GRP1_RTC_ALRA_TRG ) || \
((__SOURCE__) == SPI_GRP1_RTC_WUT_TRG ))
#define IS_SPI_GRP2_TRIG_SOURCE(__SOURCE__) (((__SOURCE__) == SPI_GRP2_GPDMA_CH0_TCF_TRG ) || \
((__SOURCE__) == SPI_GRP2_GPDMA_CH1_TCF_TRG ) || \
((__SOURCE__) == SPI_GRP2_GPDMA_CH2_TCF_TRG ) || \
((__SOURCE__) == SPI_GRP2_GPDMA_CH3_TCF_TRG ) || \
((__SOURCE__) == SPI_GRP2_EXTI4_TRG ) || \
((__SOURCE__) == SPI_GRP2_EXTI8_TRG ) || \
((__SOURCE__) == SPI_GRP2_LPTIM1_CH1_TRG ) || \
((__SOURCE__) == SPI_GRP2_LPTIM3_CH1_TRG ) || \
((__SOURCE__) == SPI_GRP2_COMP1_TRG ) || \
((__SOURCE__) == SPI_GRP2_COMP2_TRG ) || \
((__SOURCE__) == SPI_GRP2_RTC_ALRA_TRG ) || \
((__SOURCE__) == SPI_GRP2_RTC_WUT_TRG ))
#define IS_SPI_AUTO_MODE_TRG_POL(__POLARITY__) (((__POLARITY__) == SPI_TRIG_POLARITY_RISING) || \
((__POLARITY__) == SPI_TRIG_POLARITY_FALLING))
/**
* @}
*/
/* Exported functions --------------------------------------------------------*/
/** @addtogroup SPIEx_Exported_Functions
* @{
*/
/* Initialization and de-initialization functions ****************************/
/* IO operation functions *****************************************************/
/** @addtogroup SPIEx_Exported_Functions_Group1
* @{
*/
HAL_StatusTypeDef HAL_SPIEx_FlushRxFifo(const SPI_HandleTypeDef *hspi);
HAL_StatusTypeDef HAL_SPIEx_EnableLockConfiguration(SPI_HandleTypeDef *hspi);
HAL_StatusTypeDef HAL_SPIEx_ConfigureUnderrun(SPI_HandleTypeDef *hspi, uint32_t UnderrunDetection,
uint32_t UnderrunBehaviour);
/**
* @}
*/
/** @addtogroup SPI_Autonomous_Mode_Functions Autonomous Mode Functions
* @{
*/
HAL_StatusTypeDef HAL_SPIEx_SetConfigAutonomousMode(SPI_HandleTypeDef *hspi,
const SPI_AutonomousModeConfTypeDef *sConfig);
HAL_StatusTypeDef HAL_SPIEx_GetConfigAutonomousMode(const SPI_HandleTypeDef *hspi,
SPI_AutonomousModeConfTypeDef *sConfig);
HAL_StatusTypeDef HAL_SPIEx_ClearConfigAutonomousMode(SPI_HandleTypeDef *hspi);
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /* STM32U3xx_HAL_SPI_EX_H */

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/**
******************************************************************************
* @file stm32u3xx_hal_uart_ex.h
* @author MCD Application Team
* @brief Header file of UART HAL Extended module.
******************************************************************************
* @attention
*
* Copyright (c) 2023 STMicroelectronics.
* All rights reserved.
*
* This software is licensed under terms that can be found in the LICENSE file
* in the root directory of this software component.
* If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef STM32U3xx_HAL_UART_EX_H
#define STM32U3xx_HAL_UART_EX_H
#ifdef __cplusplus
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include "stm32u3xx_hal_def.h"
/** @addtogroup STM32U3xx_HAL_Driver
* @{
*/
/** @addtogroup UARTEx
* @{
*/
/* Exported types ------------------------------------------------------------*/
/** @defgroup UARTEx_Exported_Types UARTEx Exported Types
* @{
*/
/**
* @brief UART wake up from stop mode parameters
*/
typedef struct
{
uint32_t WakeUpEvent; /*!< Specifies which event will activate the Wakeup from Stop mode flag (WUF).
This parameter can be a value of @ref UART_WakeUp_from_Stop_Selection.
If set to UART_WAKEUP_ON_ADDRESS, the two other fields below must
be filled up. */
uint16_t AddressLength; /*!< Specifies whether the address is 4 or 7-bit long.
This parameter can be a value of @ref UARTEx_WakeUp_Address_Length. */
uint8_t Address; /*!< UART/USART node address (7-bit long max). */
} UART_WakeUpTypeDef;
/**
* @brief UART Autonomous mode parameters
*/
typedef struct
{
uint32_t AutonomousModeState; /*!< Specifies the autonomous mode state.This parameter can be a value of
@ref UARTEx_Autonomous_mode.*/
uint32_t TriggerSelection; /*!< Specifies which trigger will activate the Transmission automatically.
This parameter can be a value of @ref UARTEx_Autonomous_Trigger_selection
or @ref UARTEx_Low_Power_Autonomous_Trigger_selection.*/
uint32_t TriggerPolarity; /*!< Specifies the autonomous mode trigger signal polarity.
This parameter can be a value of @ref UARTEx_Autonomous_Trigger_Polarity */
uint32_t DataSize; /*!< Specifies the transmitted data size in byte */
uint32_t IdleFrame; /*!< Specifies whether the IDLE frame transmission is enabled or disabled.
This parameter can be a value of @ref UARTEx_Autonomous_IDLE_FRAME. */
} UART_AutonomousModeConfTypeDef;
/**
* @}
*/
/* Exported constants --------------------------------------------------------*/
/** @defgroup UARTEx_Exported_Constants UARTEx Exported Constants
* @{
*/
/** @defgroup UARTEx_Word_Length UARTEx Word Length
* @{
*/
#define UART_WORDLENGTH_7B USART_CR1_M1 /*!< 7-bit long UART frame */
#define UART_WORDLENGTH_8B 0x00000000U /*!< 8-bit long UART frame */
#define UART_WORDLENGTH_9B USART_CR1_M0 /*!< 9-bit long UART frame */
/**
* @}
*/
/** @defgroup UARTEx_WakeUp_Address_Length UARTEx WakeUp Address Length
* @{
*/
#define UART_ADDRESS_DETECT_4B 0x00000000U /*!< 4-bit long wake-up address */
#define UART_ADDRESS_DETECT_7B USART_CR2_ADDM7 /*!< 7-bit long wake-up address */
/**
* @}
*/
/** @defgroup UARTEx_FIFO_mode UARTEx FIFO mode
* @brief UART FIFO mode
* @{
*/
#define UART_FIFOMODE_DISABLE 0x00000000U /*!< FIFO mode disable */
#define UART_FIFOMODE_ENABLE USART_CR1_FIFOEN /*!< FIFO mode enable */
/**
* @}
*/
/** @defgroup UARTEx_TXFIFO_threshold_level UARTEx TXFIFO threshold level
* @brief UART TXFIFO threshold level
* @{
*/
#define UART_TXFIFO_THRESHOLD_1_8 0x00000000U /*!< TX FIFO reaches 1/8 of its depth */
#define UART_TXFIFO_THRESHOLD_1_4 USART_CR3_TXFTCFG_0 /*!< TX FIFO reaches 1/4 of its depth */
#define UART_TXFIFO_THRESHOLD_1_2 USART_CR3_TXFTCFG_1 /*!< TX FIFO reaches 1/2 of its depth */
#define UART_TXFIFO_THRESHOLD_3_4 (USART_CR3_TXFTCFG_0|USART_CR3_TXFTCFG_1) /*!< TX FIFO reaches 3/4 of its depth */
#define UART_TXFIFO_THRESHOLD_7_8 USART_CR3_TXFTCFG_2 /*!< TX FIFO reaches 7/8 of its depth */
#define UART_TXFIFO_THRESHOLD_8_8 (USART_CR3_TXFTCFG_2|USART_CR3_TXFTCFG_0) /*!< TX FIFO becomes empty */
/**
* @}
*/
/** @defgroup UARTEx_RXFIFO_threshold_level UARTEx RXFIFO threshold level
* @brief UART RXFIFO threshold level
* @{
*/
#define UART_RXFIFO_THRESHOLD_1_8 0x00000000U /*!< RX FIFO reaches 1/8 of its depth */
#define UART_RXFIFO_THRESHOLD_1_4 USART_CR3_RXFTCFG_0 /*!< RX FIFO reaches 1/4 of its depth */
#define UART_RXFIFO_THRESHOLD_1_2 USART_CR3_RXFTCFG_1 /*!< RX FIFO reaches 1/2 of its depth */
#define UART_RXFIFO_THRESHOLD_3_4 (USART_CR3_RXFTCFG_0|USART_CR3_RXFTCFG_1) /*!< RX FIFO reaches 3/4 of its depth */
#define UART_RXFIFO_THRESHOLD_7_8 USART_CR3_RXFTCFG_2 /*!< RX FIFO reaches 7/8 of its depth */
#define UART_RXFIFO_THRESHOLD_8_8 (USART_CR3_RXFTCFG_2|USART_CR3_RXFTCFG_0) /*!< RX FIFO becomes full */
/**
* @}
*/
/** @defgroup UARTEx_Autonomous_mode UARTEx Autonomous Mode
* @brief UART Autonomous mode
* @{
*/
#define UART_AUTONOMOUS_MODE_DISABLE 0x00000000U /*!< Autonomous mode disable */
#define UART_AUTONOMOUS_MODE_ENABLE USART_AUTOCR_TRIGEN /*!< Autonomous mode enable */
/**
* @}
*/
/** @defgroup UARTEx_Autonomous_Trigger_Polarity UARTEx Autonomous Trigger Polarity
* @brief UART Trigger polarity edge selection
* @{
*/
#define UART_TRIG_POLARITY_RISING 0x00000000U /*!< UART triggered on rising edge */
#define UART_TRIG_POLARITY_FALLING USART_AUTOCR_TRIGPOL /*!< UART triggered on falling edge */
/**
* @}
*/
/** @defgroup UARTEx_Autonomous_IDLE_FRAME UARTEx Autonomous IDLE Frame
* @brief UART IDLE frame transmission
* @{
*/
#define UART_IDLE_FRAME_ENABLE 0x00000000U /*!< IDLE Frame sent after enabling the transmitter */
#define UART_IDLE_FRAME_DISABLE USART_AUTOCR_IDLEDIS /*!< IDLE Frame not sent after enabling the transmitter */
/**
* @}
*/
/** @defgroup UARTEx_Autonomous_Trigger_selection UARTEx Autonomous trigger selection
* @brief UART Autonomous Trigger selection
* @{
*/
#define UART_GPDMA1_CH0_TCF_TRG 0U /*!< UART GPDMA1 channel0 Internal Trigger */
#define UART_GPDMA1_CH1_TCF_TRG 1U /*!< UART GPDMA1 channel1 Internal Trigger */
#define UART_GPDMA1_CH2_TCF_TRG 2U /*!< UART GPDMA1 channel2 Internal Trigger */
#define UART_GPDMA1_CH3_TCF_TRG 3U /*!< UART GPDMA1 channel3 Internal Trigger */
#define UART_EXTI_LINE6_TRG 4U /*!< UART EXTI line 6 Internal Trigger */
#define UART_EXTI_LINE9_TRG 5U /*!< UART EXTI line 9 Internal Trigger */
#define UART_LPTIM1_OUT_TRG 6U /*!< UART LPTIM1 out Internal Trigger */
#define UART_LPTIM2_OUT_TRG 7U /*!< UART LPTIM2 out Internal Trigger */
#define UART_COMP1_OUT_TRG 8U /*!< UART COMP1 out Internal Trigger */
#define UART_COMP2_OUT_TRG 9U /*!< UART COMP2 out Internal Trigger */
#define UART_RTC_ALRA_TRG 10U /*!< UART RTC alarm Internal Trigger */
#define UART_RTC_WUT_TRG 11U /*!< UART RTC wakeup Internal Trigger */
/**
* @}
*/
/** @defgroup UARTEx_Low_Power_Autonomous_Trigger_selection UARTEx Low Power Autonomous trigger selection
* @brief LPUART Autonomous Trigger selection
* @{
*/
#define LPUART_GPDMA1_CH0_TCF_TRG 0U /*!< LPUART GPDMA1 channel0 Internal Trigger */
#define LPUART_GPDMA1_CH1_TCF_TRG 1U /*!< LPUART GPDMA1 channel1 Internal Trigger */
#define LPUART_GPDMA1_CH2_TCF_TRG 2U /*!< LPUART GPDMA1 channel2 Internal Trigger */
#define LPUART_GPDMA1_CH3_TCF_TRG 3U /*!< LPUART GPDMA1 channel3 Internal Trigger */
#define LPUART_EXTI_LINE6_TRG 4U /*!< LPUART EXTI line 6 Internal Trigger */
#define LPUART_EXTI_LINE8_TRG 5U /*!< LPUART EXTI line 8 Internal Trigger */
#define LPUART_LPTIM1_OUT_TRG 6U /*!< LPUART LPTIM1 out Internal Trigger */
#define LPUART_LPTIM3_OUT_TRG 7U /*!< LPUART LPTIM3 out Internal Trigger */
#define LPUART_COMP1_OUT_TRG 8U /*!< LPUART COMP1 out Internal Trigger */
#define LPUART_COMP2_OUT_TRG 9U /*!< LPUART COMP2 out Internal Trigger */
#define LPUART_RTC_ALRA_TRG 10U /*!< LPUART RTC alarm Internal Trigger */
#define LPUART_RTC_WUT_TRG 11U /*!< LPUART RTC wakeup Internal Trigger */
/**
* @}
*/
/**
* @}
*/
/* Exported macros -----------------------------------------------------------*/
/* Exported functions --------------------------------------------------------*/
/** @addtogroup UARTEx_Exported_Functions
* @{
*/
/** @addtogroup UARTEx_Exported_Functions_Group1
* @{
*/
/* Initialization and de-initialization functions ****************************/
HAL_StatusTypeDef HAL_RS485Ex_Init(UART_HandleTypeDef *huart, uint32_t Polarity, uint32_t AssertionTime,
uint32_t DeassertionTime);
/**
* @}
*/
/** @addtogroup UARTEx_Exported_Functions_Group2
* @{
*/
void HAL_UARTEx_RxFifoFullCallback(UART_HandleTypeDef *huart);
void HAL_UARTEx_TxFifoEmptyCallback(UART_HandleTypeDef *huart);
/**
* @}
*/
/** @addtogroup UARTEx_Exported_Functions_Group3
* @{
*/
/* Peripheral Control functions **********************************************/
HAL_StatusTypeDef HAL_UARTEx_StopModeWakeUpSourceConfig(UART_HandleTypeDef *huart, UART_WakeUpTypeDef WakeUpSelection);
HAL_StatusTypeDef HAL_UARTEx_EnableStopMode(UART_HandleTypeDef *huart);
HAL_StatusTypeDef HAL_UARTEx_DisableStopMode(UART_HandleTypeDef *huart);
HAL_StatusTypeDef HAL_MultiProcessorEx_AddressLength_Set(UART_HandleTypeDef *huart, uint32_t AddressLength);
HAL_StatusTypeDef HAL_UARTEx_EnableFifoMode(UART_HandleTypeDef *huart);
HAL_StatusTypeDef HAL_UARTEx_DisableFifoMode(UART_HandleTypeDef *huart);
HAL_StatusTypeDef HAL_UARTEx_SetTxFifoThreshold(UART_HandleTypeDef *huart, uint32_t Threshold);
HAL_StatusTypeDef HAL_UARTEx_SetRxFifoThreshold(UART_HandleTypeDef *huart, uint32_t Threshold);
HAL_StatusTypeDef HAL_UARTEx_ReceiveToIdle(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size, uint16_t *RxLen,
uint32_t Timeout);
HAL_StatusTypeDef HAL_UARTEx_ReceiveToIdle_IT(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size);
#if defined(HAL_DMA_MODULE_ENABLED)
HAL_StatusTypeDef HAL_UARTEx_ReceiveToIdle_DMA(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size);
#endif /* HAL_DMA_MODULE_ENABLED */
HAL_UART_RxEventTypeTypeDef HAL_UARTEx_GetRxEventType(const UART_HandleTypeDef *huart);
/* Autonomous Mode Control functions **********************************************/
HAL_StatusTypeDef HAL_UARTEx_SetConfigAutonomousMode(UART_HandleTypeDef *huart,
const UART_AutonomousModeConfTypeDef *sConfig);
HAL_StatusTypeDef HAL_UARTEx_GetConfigAutonomousMode(const UART_HandleTypeDef *huart,
UART_AutonomousModeConfTypeDef *sConfig);
HAL_StatusTypeDef HAL_UARTEx_ClearConfigAutonomousMode(UART_HandleTypeDef *huart);
/**
* @}
*/
/**
* @}
*/
/* Private macros ------------------------------------------------------------*/
/** @defgroup UARTEx_Private_Macros UARTEx Private Macros
* @{
*/
/** @brief Report the UART clock source.
* @param __HANDLE__ specifies the UART Handle.
* @param __CLOCKSOURCE__ output variable.
* @retval UART clocking source, written in __CLOCKSOURCE__.
*/
#define UART_GETCLOCKSOURCE(__HANDLE__,__CLOCKSOURCE__) \
do { \
if((__HANDLE__)->Instance == USART1) \
{ \
(__CLOCKSOURCE__) = (uint32_t)RCC_PERIPHCLK_USART1; \
} \
else if((__HANDLE__)->Instance == USART3) \
{ \
(__CLOCKSOURCE__) = (uint32_t)RCC_PERIPHCLK_USART3; \
} \
else if((__HANDLE__)->Instance == UART4) \
{ \
(__CLOCKSOURCE__) = (uint32_t)RCC_PERIPHCLK_UART4; \
} \
else if((__HANDLE__)->Instance == UART5) \
{ \
(__CLOCKSOURCE__) = (uint32_t)RCC_PERIPHCLK_UART5; \
} \
else if((__HANDLE__)->Instance == LPUART1) \
{ \
(__CLOCKSOURCE__) = (uint32_t)RCC_PERIPHCLK_LPUART1; \
} \
else \
{ \
(__CLOCKSOURCE__) = 0U; \
} \
} while(0U)
/** @brief Report the UART mask to apply to retrieve the received data
* according to the word length and to the parity bits activation.
* @note If PCE = 1, the parity bit is not included in the data extracted
* by the reception API().
* This masking operation is not carried out in the case of
* DMA transfers.
* @param __HANDLE__ specifies the UART Handle.
* @retval None, the mask to apply to UART RDR register is stored in (__HANDLE__)->Mask field.
*/
#define UART_MASK_COMPUTATION(__HANDLE__) \
do { \
if ((__HANDLE__)->Init.WordLength == UART_WORDLENGTH_9B) \
{ \
if ((__HANDLE__)->Init.Parity == UART_PARITY_NONE) \
{ \
(__HANDLE__)->Mask = 0x01FFU ; \
} \
else \
{ \
(__HANDLE__)->Mask = 0x00FFU ; \
} \
} \
else if ((__HANDLE__)->Init.WordLength == UART_WORDLENGTH_8B) \
{ \
if ((__HANDLE__)->Init.Parity == UART_PARITY_NONE) \
{ \
(__HANDLE__)->Mask = 0x00FFU ; \
} \
else \
{ \
(__HANDLE__)->Mask = 0x007FU ; \
} \
} \
else if ((__HANDLE__)->Init.WordLength == UART_WORDLENGTH_7B) \
{ \
if ((__HANDLE__)->Init.Parity == UART_PARITY_NONE) \
{ \
(__HANDLE__)->Mask = 0x007FU ; \
} \
else \
{ \
(__HANDLE__)->Mask = 0x003FU ; \
} \
} \
else \
{ \
(__HANDLE__)->Mask = 0x0000U; \
} \
} while(0U)
/**
* @brief Ensure that UART frame length is valid.
* @param __LENGTH__ UART frame length.
* @retval SET (__LENGTH__ is valid) or RESET (__LENGTH__ is invalid)
*/
#define IS_UART_WORD_LENGTH(__LENGTH__) (((__LENGTH__) == UART_WORDLENGTH_7B) || \
((__LENGTH__) == UART_WORDLENGTH_8B) || \
((__LENGTH__) == UART_WORDLENGTH_9B))
/**
* @brief Ensure that UART wake-up address length is valid.
* @param __ADDRESS__ UART wake-up address length.
* @retval SET (__ADDRESS__ is valid) or RESET (__ADDRESS__ is invalid)
*/
#define IS_UART_ADDRESSLENGTH_DETECT(__ADDRESS__) (((__ADDRESS__) == UART_ADDRESS_DETECT_4B) || \
((__ADDRESS__) == UART_ADDRESS_DETECT_7B))
/**
* @brief Ensure that UART TXFIFO threshold level is valid.
* @param __THRESHOLD__ UART TXFIFO threshold level.
* @retval SET (__THRESHOLD__ is valid) or RESET (__THRESHOLD__ is invalid)
*/
#define IS_UART_TXFIFO_THRESHOLD(__THRESHOLD__) (((__THRESHOLD__) == UART_TXFIFO_THRESHOLD_1_8) || \
((__THRESHOLD__) == UART_TXFIFO_THRESHOLD_1_4) || \
((__THRESHOLD__) == UART_TXFIFO_THRESHOLD_1_2) || \
((__THRESHOLD__) == UART_TXFIFO_THRESHOLD_3_4) || \
((__THRESHOLD__) == UART_TXFIFO_THRESHOLD_7_8) || \
((__THRESHOLD__) == UART_TXFIFO_THRESHOLD_8_8))
/**
* @brief Ensure that UART RXFIFO threshold level is valid.
* @param __THRESHOLD__ UART RXFIFO threshold level.
* @retval SET (__THRESHOLD__ is valid) or RESET (__THRESHOLD__ is invalid)
*/
#define IS_UART_RXFIFO_THRESHOLD(__THRESHOLD__) (((__THRESHOLD__) == UART_RXFIFO_THRESHOLD_1_8) || \
((__THRESHOLD__) == UART_RXFIFO_THRESHOLD_1_4) || \
((__THRESHOLD__) == UART_RXFIFO_THRESHOLD_1_2) || \
((__THRESHOLD__) == UART_RXFIFO_THRESHOLD_3_4) || \
((__THRESHOLD__) == UART_RXFIFO_THRESHOLD_7_8) || \
((__THRESHOLD__) == UART_RXFIFO_THRESHOLD_8_8))
/**
* @brief Ensure that UART Trigger polarity state is valid.
* @param __POLARITY__ UART Trigger polarity.
* @retval SET (__POLARITY__ is valid) or RESET (__POLARITY__ is invalid)
*/
#define IS_UART_TRIGGER_POLARITY(__POLARITY__) (((__POLARITY__) == UART_TRIG_POLARITY_RISING) ||\
((__POLARITY__) == UART_TRIG_POLARITY_FALLING))
/**
* @brief Ensure that UART IDLE Frame Transmit state is valid.
* @param __IDLE__ UART IDLE Frame Transmit state.
* @retval SET (__IDLE__ is valid) or RESET (__IDLE__ is invalid)
*/
#define IS_UART_IDLE_FRAME_TRANSMIT(__IDLE__) (((__IDLE__) == UART_IDLE_FRAME_ENABLE) ||\
((__IDLE__) == UART_IDLE_FRAME_DISABLE))
/**
* @brief Ensure that UART Trigger source selection is valid.
* @param __SOURCE__ UART Trigger source selection.
* @retval SET (__SOURCE__ is valid) or RESET (__SOURCE__ is invalid)
*/
#define IS_UART_TRIGGER_SELECTION(__SOURCE__) ((__SOURCE__) <= 11U)
/**
* @brief Ensure that LPUART Trigger source selection is valid.
* @param __SOURCE__ LPUART Trigger source selection.
* @retval SET (__SOURCE__ is valid) or RESET (__SOURCE__ is invalid)
*/
#define IS_LPUART_TRIGGER_SELECTION(__SOURCE__) ((__SOURCE__) <= 11U)
/**
* @brief Ensure that the number of transferred data is valid.
* @param __SOURCE__ UART TX data size.
* @retval SET (__SOURCE__ is valid) or RESET (__SOURCE__ is invalid)
*/
#define IS_UART_TX_DATA_SIZE(__SOURCE__) ((__SOURCE__) <= 0xFFFFU)
/**
* @}
*/
/* Private functions ---------------------------------------------------------*/
/**
* @}
*/
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /* STM32U3xx_HAL_UART_EX_H */

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/**
******************************************************************************
* @file stm32u3xx_ll_crs.h
* @author MCD Application Team
* @brief Header file of CRS LL module.
******************************************************************************
* @attention
*
* Copyright (c) 2023 STMicroelectronics.
* All rights reserved.
*
* This software is licensed under terms that can be found in the LICENSE file
* in the root directory of this software component.
* If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef STM32U3xx_LL_CRS_H
#define STM32U3xx_LL_CRS_H
#ifdef __cplusplus
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include "stm32u3xx.h"
/** @addtogroup STM32U3xx_LL_Driver
* @{
*/
#if defined(CRS)
/** @defgroup CRS_LL CRS
* @{
*/
/* Private types -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private constants ---------------------------------------------------------*/
/* Private macros ------------------------------------------------------------*/
/* Exported types ------------------------------------------------------------*/
/* Exported constants --------------------------------------------------------*/
/** @defgroup CRS_LL_Exported_Constants CRS Exported Constants
* @{
*/
/** @defgroup CRS_LL_EC_GET_FLAG Get Flags Defines
* @brief Flags defines which can be used with LL_CRS_ReadReg function
* @{
*/
#define LL_CRS_ISR_SYNCOKF CRS_ISR_SYNCOKF
#define LL_CRS_ISR_SYNCWARNF CRS_ISR_SYNCWARNF
#define LL_CRS_ISR_ERRF CRS_ISR_ERRF
#define LL_CRS_ISR_ESYNCF CRS_ISR_ESYNCF
#define LL_CRS_ISR_SYNCERR CRS_ISR_SYNCERR
#define LL_CRS_ISR_SYNCMISS CRS_ISR_SYNCMISS
#define LL_CRS_ISR_TRIMOVF CRS_ISR_TRIMOVF
/**
* @}
*/
/** @defgroup CRS_LL_EC_IT IT Defines
* @brief IT defines which can be used with LL_CRS_ReadReg and LL_CRS_WriteReg functions
* @{
*/
#define LL_CRS_CR_SYNCOKIE CRS_CR_SYNCOKIE
#define LL_CRS_CR_SYNCWARNIE CRS_CR_SYNCWARNIE
#define LL_CRS_CR_ERRIE CRS_CR_ERRIE
#define LL_CRS_CR_ESYNCIE CRS_CR_ESYNCIE
/**
* @}
*/
/** @defgroup CRS_LL_EC_SYNC_DIV Synchronization Signal Divider
* @{
*/
#define LL_CRS_SYNC_DIV_1 0U /*!< Synchro Signal not divided (default) */
#define LL_CRS_SYNC_DIV_2 CRS_CFGR_SYNCDIV_0 /*!< Synchro Signal divided by 2 */
#define LL_CRS_SYNC_DIV_4 CRS_CFGR_SYNCDIV_1 /*!< Synchro Signal divided by 4 */
#define LL_CRS_SYNC_DIV_8 (CRS_CFGR_SYNCDIV_1 | CRS_CFGR_SYNCDIV_0) /*!< Synchro Signal divided by 8 */
#define LL_CRS_SYNC_DIV_16 CRS_CFGR_SYNCDIV_2 /*!< Synchro Signal divided by 16 */
#define LL_CRS_SYNC_DIV_32 (CRS_CFGR_SYNCDIV_2 | CRS_CFGR_SYNCDIV_0) /*!< Synchro Signal divided by 32 */
#define LL_CRS_SYNC_DIV_64 (CRS_CFGR_SYNCDIV_2 | CRS_CFGR_SYNCDIV_1) /*!< Synchro Signal divided by 64 */
#define LL_CRS_SYNC_DIV_128 CRS_CFGR_SYNCDIV /*!< Synchro Signal divided by 128 */
/**
* @}
*/
/** @defgroup CRS_LL_EC_SYNC_SOURCE Synchronization Signal Source
* @{
*/
#define LL_CRS_SYNC_SOURCE_GPIO 0U /*!< Synchro Signal source GPIO */
#define LL_CRS_SYNC_SOURCE_LSE CRS_CFGR_SYNCSRC_0 /*!< Synchro Signal source LSE */
#define LL_CRS_SYNC_SOURCE_USB CRS_CFGR_SYNCSRC_1 /*!< Synchro Signal source USB SOF (default) */
/**
* @}
*/
/** @defgroup CRS_LL_EC_SYNC_POLARITY Synchronization Signal Polarity
* @{
*/
#define LL_CRS_SYNC_POLARITY_RISING 0U /*!< Synchro Active on rising edge (default) */
#define LL_CRS_SYNC_POLARITY_FALLING CRS_CFGR_SYNCPOL /*!< Synchro Active on falling edge */
/**
* @}
*/
/** @defgroup CRS_LL_EC_FREQERRORDIR Frequency Error Direction
* @{
*/
#define LL_CRS_FREQ_ERROR_DIR_UP 0U /*!< Upcounting direction, the actual frequency is above the target */
#define LL_CRS_FREQ_ERROR_DIR_DOWN CRS_ISR_FEDIR /*!< Downcounting direction, the actual frequency is below the target */
/**
* @}
*/
/** @defgroup CRS_LL_EC_DEFAULTVALUES Default Values
* @{
*/
/**
* @brief Reset value of the RELOAD field
* @note The reset value of the RELOAD field corresponds to a target frequency of 48 MHz
* and a synchronization signal frequency of 1 kHz (SOF signal from USB)
*/
#define LL_CRS_RELOADVALUE_DEFAULT 0x0000BB7FU
/**
* @brief Reset value of Frequency error limit.
*/
#define LL_CRS_ERRORLIMIT_DEFAULT 0x00000022U
/**
* @brief Reset value of the HSI48 Calibration field
* @note The default value is 64, which corresponds to the middle of the trimming interval.
* The trimming step is specified in the product datasheet.
* A higher TRIM value corresponds to a higher output frequency.
*/
#define LL_CRS_HSI48CALIBRATION_DEFAULT 0x00000040U
/**
* @}
*/
/**
* @}
*/
/* Exported macro ------------------------------------------------------------*/
/** @defgroup CRS_LL_Exported_Macros CRS Exported Macros
* @{
*/
/** @defgroup CRS_LL_EM_WRITE_READ Common Write and read registers Macros
* @{
*/
/**
* @brief Write a value in CRS register
* @param __INSTANCE__ CRS Instance
* @param __REG__ Register to be written
* @param __VALUE__ Value to be written in the register
* @retval None
*/
#define LL_CRS_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
/**
* @brief Read a value in CRS register
* @param __INSTANCE__ CRS Instance
* @param __REG__ Register to be read
* @retval Register value
*/
#define LL_CRS_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
/**
* @}
*/
/** @defgroup CRS_LL_EM_Exported_Macros_Calculate_Reload Exported_Macros_Calculate_Reload
* @{
*/
/**
* @brief Macro to calculate reload value to be set in CRS register according to target and sync frequencies
* @note The RELOAD value should be selected according to the ratio between
* the target frequency and the frequency of the synchronization source after
* prescaling. It is then decreased by one in order to reach the expected
* synchronization on the zero value. The formula is the following:
* RELOAD = (fTARGET / fSYNC) -1
* @param __FTARGET__ Target frequency (value in Hz)
* @param __FSYNC__ Synchronization signal frequency (value in Hz)
* @retval Reload value (in Hz)
*/
#define __LL_CRS_CALC_CALCULATE_RELOADVALUE(__FTARGET__, __FSYNC__) (((__FTARGET__) / (__FSYNC__)) - 1U)
/**
* @}
*/
/**
* @}
*/
/* Exported functions --------------------------------------------------------*/
/** @defgroup CRS_LL_Exported_Functions CRS Exported Functions
* @{
*/
/** @defgroup CRS_LL_EF_Configuration Configuration
* @{
*/
/**
* @brief Enable Frequency error counter
* @note When this bit is set, the CRS_CFGR register is write-protected and cannot be modified
* @rmtoll CR CEN LL_CRS_EnableFreqErrorCounter
* @retval None
*/
__STATIC_INLINE void LL_CRS_EnableFreqErrorCounter(void)
{
SET_BIT(CRS->CR, CRS_CR_CEN);
}
/**
* @brief Disable Frequency error counter
* @rmtoll CR CEN LL_CRS_DisableFreqErrorCounter
* @retval None
*/
__STATIC_INLINE void LL_CRS_DisableFreqErrorCounter(void)
{
CLEAR_BIT(CRS->CR, CRS_CR_CEN);
}
/**
* @brief Check if Frequency error counter is enabled or not
* @rmtoll CR CEN LL_CRS_IsEnabledFreqErrorCounter
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_CRS_IsEnabledFreqErrorCounter(void)
{
return ((READ_BIT(CRS->CR, CRS_CR_CEN) == (CRS_CR_CEN)) ? 1UL : 0UL);
}
/**
* @brief Enable Automatic trimming counter
* @rmtoll CR AUTOTRIMEN LL_CRS_EnableAutoTrimming
* @retval None
*/
__STATIC_INLINE void LL_CRS_EnableAutoTrimming(void)
{
SET_BIT(CRS->CR, CRS_CR_AUTOTRIMEN);
}
/**
* @brief Disable Automatic trimming counter
* @rmtoll CR AUTOTRIMEN LL_CRS_DisableAutoTrimming
* @retval None
*/
__STATIC_INLINE void LL_CRS_DisableAutoTrimming(void)
{
CLEAR_BIT(CRS->CR, CRS_CR_AUTOTRIMEN);
}
/**
* @brief Check if Automatic trimming is enabled or not
* @rmtoll CR AUTOTRIMEN LL_CRS_IsEnabledAutoTrimming
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_CRS_IsEnabledAutoTrimming(void)
{
return ((READ_BIT(CRS->CR, CRS_CR_AUTOTRIMEN) == (CRS_CR_AUTOTRIMEN)) ? 1UL : 0UL);
}
/**
* @brief Set HSI48 oscillator smooth trimming
* @note When the AUTOTRIMEN bit is set, this field is controlled by hardware and is read-only
* @rmtoll CR TRIM LL_CRS_SetHSI48SmoothTrimming
* @param Value a number between Min_Data = 0 and Max_Data = 127
* @note Default value can be set thanks to @ref LL_CRS_HSI48CALIBRATION_DEFAULT
* @retval None
*/
__STATIC_INLINE void LL_CRS_SetHSI48SmoothTrimming(uint32_t Value)
{
MODIFY_REG(CRS->CR, CRS_CR_TRIM, Value << CRS_CR_TRIM_Pos);
}
/**
* @brief Get HSI48 oscillator smooth trimming
* @rmtoll CR TRIM LL_CRS_GetHSI48SmoothTrimming
* @retval a number between Min_Data = 0 and Max_Data = 127
*/
__STATIC_INLINE uint32_t LL_CRS_GetHSI48SmoothTrimming(void)
{
return (uint32_t)(READ_BIT(CRS->CR, CRS_CR_TRIM) >> CRS_CR_TRIM_Pos);
}
/**
* @brief Set counter reload value
* @rmtoll CFGR RELOAD LL_CRS_SetReloadCounter
* @param Value a number between Min_Data = 0 and Max_Data = 65535 (0xFFFF)
* @note Default value can be set thanks to @ref LL_CRS_RELOADVALUE_DEFAULT
* Otherwise it can be calculated in using macro @ref __LL_CRS_CALC_CALCULATE_RELOADVALUE (_FTARGET_, _FSYNC_)
* @retval None
*/
__STATIC_INLINE void LL_CRS_SetReloadCounter(uint32_t Value)
{
MODIFY_REG(CRS->CFGR, CRS_CFGR_RELOAD, Value);
}
/**
* @brief Get counter reload value
* @rmtoll CFGR RELOAD LL_CRS_GetReloadCounter
* @retval a number between Min_Data = 0 and Max_Data = 65535 (0xFFFF)
*/
__STATIC_INLINE uint32_t LL_CRS_GetReloadCounter(void)
{
return (uint32_t)(READ_BIT(CRS->CFGR, CRS_CFGR_RELOAD));
}
/**
* @brief Set frequency error limit
* @rmtoll CFGR FELIM LL_CRS_SetFreqErrorLimit
* @param Value a number between Min_Data = 0 and Max_Data = 255
* @note Default value can be set thanks to @ref LL_CRS_ERRORLIMIT_DEFAULT
* @retval None
*/
__STATIC_INLINE void LL_CRS_SetFreqErrorLimit(uint32_t Value)
{
MODIFY_REG(CRS->CFGR, CRS_CFGR_FELIM, Value << CRS_CFGR_FELIM_Pos);
}
/**
* @brief Get frequency error limit
* @rmtoll CFGR FELIM LL_CRS_GetFreqErrorLimit
* @retval A number between Min_Data = 0 and Max_Data = 255
*/
__STATIC_INLINE uint32_t LL_CRS_GetFreqErrorLimit(void)
{
return (uint32_t)(READ_BIT(CRS->CFGR, CRS_CFGR_FELIM) >> CRS_CFGR_FELIM_Pos);
}
/**
* @brief Set division factor for SYNC signal
* @rmtoll CFGR SYNCDIV LL_CRS_SetSyncDivider
* @param Divider This parameter can be one of the following values:
* @arg @ref LL_CRS_SYNC_DIV_1
* @arg @ref LL_CRS_SYNC_DIV_2
* @arg @ref LL_CRS_SYNC_DIV_4
* @arg @ref LL_CRS_SYNC_DIV_8
* @arg @ref LL_CRS_SYNC_DIV_16
* @arg @ref LL_CRS_SYNC_DIV_32
* @arg @ref LL_CRS_SYNC_DIV_64
* @arg @ref LL_CRS_SYNC_DIV_128
* @retval None
*/
__STATIC_INLINE void LL_CRS_SetSyncDivider(uint32_t Divider)
{
MODIFY_REG(CRS->CFGR, CRS_CFGR_SYNCDIV, Divider);
}
/**
* @brief Get division factor for SYNC signal
* @rmtoll CFGR SYNCDIV LL_CRS_GetSyncDivider
* @retval Returned value can be one of the following values:
* @arg @ref LL_CRS_SYNC_DIV_1
* @arg @ref LL_CRS_SYNC_DIV_2
* @arg @ref LL_CRS_SYNC_DIV_4
* @arg @ref LL_CRS_SYNC_DIV_8
* @arg @ref LL_CRS_SYNC_DIV_16
* @arg @ref LL_CRS_SYNC_DIV_32
* @arg @ref LL_CRS_SYNC_DIV_64
* @arg @ref LL_CRS_SYNC_DIV_128
*/
__STATIC_INLINE uint32_t LL_CRS_GetSyncDivider(void)
{
return (uint32_t)(READ_BIT(CRS->CFGR, CRS_CFGR_SYNCDIV));
}
/**
* @brief Set SYNC signal source
* @rmtoll CFGR SYNCSRC LL_CRS_SetSyncSignalSource
* @param Source This parameter can be one of the following values:
* @arg @ref LL_CRS_SYNC_SOURCE_GPIO
* @arg @ref LL_CRS_SYNC_SOURCE_LSE
* @arg @ref LL_CRS_SYNC_SOURCE_USB
* @retval None
*/
__STATIC_INLINE void LL_CRS_SetSyncSignalSource(uint32_t Source)
{
MODIFY_REG(CRS->CFGR, CRS_CFGR_SYNCSRC, Source);
}
/**
* @brief Get SYNC signal source
* @rmtoll CFGR SYNCSRC LL_CRS_GetSyncSignalSource
* @retval Returned value can be one of the following values:
* @arg @ref LL_CRS_SYNC_SOURCE_GPIO
* @arg @ref LL_CRS_SYNC_SOURCE_LSE
* @arg @ref LL_CRS_SYNC_SOURCE_USB
*/
__STATIC_INLINE uint32_t LL_CRS_GetSyncSignalSource(void)
{
return (uint32_t)(READ_BIT(CRS->CFGR, CRS_CFGR_SYNCSRC));
}
/**
* @brief Set input polarity for the SYNC signal source
* @rmtoll CFGR SYNCPOL LL_CRS_SetSyncPolarity
* @param Polarity This parameter can be one of the following values:
* @arg @ref LL_CRS_SYNC_POLARITY_RISING
* @arg @ref LL_CRS_SYNC_POLARITY_FALLING
* @retval None
*/
__STATIC_INLINE void LL_CRS_SetSyncPolarity(uint32_t Polarity)
{
MODIFY_REG(CRS->CFGR, CRS_CFGR_SYNCPOL, Polarity);
}
/**
* @brief Get input polarity for the SYNC signal source
* @rmtoll CFGR SYNCPOL LL_CRS_GetSyncPolarity
* @retval Returned value can be one of the following values:
* @arg @ref LL_CRS_SYNC_POLARITY_RISING
* @arg @ref LL_CRS_SYNC_POLARITY_FALLING
*/
__STATIC_INLINE uint32_t LL_CRS_GetSyncPolarity(void)
{
return (uint32_t)(READ_BIT(CRS->CFGR, CRS_CFGR_SYNCPOL));
}
/**
* @brief Configure CRS for the synchronization
* @rmtoll CR TRIM LL_CRS_ConfigSynchronization\n
* CFGR RELOAD LL_CRS_ConfigSynchronization\n
* CFGR FELIM LL_CRS_ConfigSynchronization\n
* CFGR SYNCDIV LL_CRS_ConfigSynchronization\n
* CFGR SYNCSRC LL_CRS_ConfigSynchronization\n
* CFGR SYNCPOL LL_CRS_ConfigSynchronization
* @param HSI48CalibrationValue a number between Min_Data = 0 and Max_Data = 63
* @param ErrorLimitValue a number between Min_Data = 0 and Max_Data = 255
* @param ReloadValue a number between Min_Data = 0 and Max_Data = 65535 (0xFFFF)
* @param Settings This parameter can be a combination of the following values:
* @arg @ref LL_CRS_SYNC_DIV_1 or @ref LL_CRS_SYNC_DIV_2 or @ref LL_CRS_SYNC_DIV_4
* or @ref LL_CRS_SYNC_DIV_8 or @ref LL_CRS_SYNC_DIV_16 or @ref LL_CRS_SYNC_DIV_32
* or @ref LL_CRS_SYNC_DIV_64 or @ref LL_CRS_SYNC_DIV_128
* @arg @ref LL_CRS_SYNC_SOURCE_GPIO or @ref LL_CRS_SYNC_SOURCE_LSE
* or @ref LL_CRS_SYNC_SOURCE_USB
* @arg @ref LL_CRS_SYNC_POLARITY_RISING or @ref LL_CRS_SYNC_POLARITY_FALLING
* @retval None
*/
__STATIC_INLINE void LL_CRS_ConfigSynchronization(uint32_t HSI48CalibrationValue, uint32_t ErrorLimitValue,
uint32_t ReloadValue, uint32_t Settings)
{
MODIFY_REG(CRS->CR, CRS_CR_TRIM, HSI48CalibrationValue << CRS_CR_TRIM_Pos);
MODIFY_REG(CRS->CFGR,
CRS_CFGR_RELOAD | CRS_CFGR_FELIM | CRS_CFGR_SYNCDIV | CRS_CFGR_SYNCSRC | CRS_CFGR_SYNCPOL,
ReloadValue | (ErrorLimitValue << CRS_CFGR_FELIM_Pos) | Settings);
}
/**
* @}
*/
/** @defgroup CRS_LL_EF_CRS_Management CRS_Management
* @{
*/
/**
* @brief Generate software SYNC event
* @rmtoll CR SWSYNC LL_CRS_GenerateEvent_SWSYNC
* @retval None
*/
__STATIC_INLINE void LL_CRS_GenerateEvent_SWSYNC(void)
{
SET_BIT(CRS->CR, CRS_CR_SWSYNC);
}
/**
* @brief Get the frequency error direction latched in the time of the last
* SYNC event
* @rmtoll ISR FEDIR LL_CRS_GetFreqErrorDirection
* @retval Returned value can be one of the following values:
* @arg @ref LL_CRS_FREQ_ERROR_DIR_UP
* @arg @ref LL_CRS_FREQ_ERROR_DIR_DOWN
*/
__STATIC_INLINE uint32_t LL_CRS_GetFreqErrorDirection(void)
{
return (uint32_t)(READ_BIT(CRS->ISR, CRS_ISR_FEDIR));
}
/**
* @brief Get the frequency error counter value latched in the time of the last SYNC event
* @rmtoll ISR FECAP LL_CRS_GetFreqErrorCapture
* @retval A number between Min_Data = 0x0000 and Max_Data = 0xFFFF
*/
__STATIC_INLINE uint32_t LL_CRS_GetFreqErrorCapture(void)
{
return (uint32_t)(READ_BIT(CRS->ISR, CRS_ISR_FECAP) >> CRS_ISR_FECAP_Pos);
}
/**
* @}
*/
/** @defgroup CRS_LL_EF_FLAG_Management FLAG_Management
* @{
*/
/**
* @brief Check if SYNC event OK signal occurred or not
* @rmtoll ISR SYNCOKF LL_CRS_IsActiveFlag_SYNCOK
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_CRS_IsActiveFlag_SYNCOK(void)
{
return ((READ_BIT(CRS->ISR, CRS_ISR_SYNCOKF) == (CRS_ISR_SYNCOKF)) ? 1UL : 0UL);
}
/**
* @brief Check if SYNC warning signal occurred or not
* @rmtoll ISR SYNCWARNF LL_CRS_IsActiveFlag_SYNCWARN
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_CRS_IsActiveFlag_SYNCWARN(void)
{
return ((READ_BIT(CRS->ISR, CRS_ISR_SYNCWARNF) == (CRS_ISR_SYNCWARNF)) ? 1UL : 0UL);
}
/**
* @brief Check if Synchronization or trimming error signal occurred or not
* @rmtoll ISR ERRF LL_CRS_IsActiveFlag_ERR
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_CRS_IsActiveFlag_ERR(void)
{
return ((READ_BIT(CRS->ISR, CRS_ISR_ERRF) == (CRS_ISR_ERRF)) ? 1UL : 0UL);
}
/**
* @brief Check if Expected SYNC signal occurred or not
* @rmtoll ISR ESYNCF LL_CRS_IsActiveFlag_ESYNC
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_CRS_IsActiveFlag_ESYNC(void)
{
return ((READ_BIT(CRS->ISR, CRS_ISR_ESYNCF) == (CRS_ISR_ESYNCF)) ? 1UL : 0UL);
}
/**
* @brief Check if SYNC error signal occurred or not
* @rmtoll ISR SYNCERR LL_CRS_IsActiveFlag_SYNCERR
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_CRS_IsActiveFlag_SYNCERR(void)
{
return ((READ_BIT(CRS->ISR, CRS_ISR_SYNCERR) == (CRS_ISR_SYNCERR)) ? 1UL : 0UL);
}
/**
* @brief Check if SYNC missed error signal occurred or not
* @rmtoll ISR SYNCMISS LL_CRS_IsActiveFlag_SYNCMISS
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_CRS_IsActiveFlag_SYNCMISS(void)
{
return ((READ_BIT(CRS->ISR, CRS_ISR_SYNCMISS) == (CRS_ISR_SYNCMISS)) ? 1UL : 0UL);
}
/**
* @brief Check if Trimming overflow or underflow occurred or not
* @rmtoll ISR TRIMOVF LL_CRS_IsActiveFlag_TRIMOVF
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_CRS_IsActiveFlag_TRIMOVF(void)
{
return ((READ_BIT(CRS->ISR, CRS_ISR_TRIMOVF) == (CRS_ISR_TRIMOVF)) ? 1UL : 0UL);
}
/**
* @brief Clear the SYNC event OK flag
* @rmtoll ICR SYNCOKC LL_CRS_ClearFlag_SYNCOK
* @retval None
*/
__STATIC_INLINE void LL_CRS_ClearFlag_SYNCOK(void)
{
WRITE_REG(CRS->ICR, CRS_ICR_SYNCOKC);
}
/**
* @brief Clear the SYNC warning flag
* @rmtoll ICR SYNCWARNC LL_CRS_ClearFlag_SYNCWARN
* @retval None
*/
__STATIC_INLINE void LL_CRS_ClearFlag_SYNCWARN(void)
{
WRITE_REG(CRS->ICR, CRS_ICR_SYNCWARNC);
}
/**
* @brief Clear TRIMOVF, SYNCMISS and SYNCERR bits and consequently also
* the ERR flag
* @rmtoll ICR ERRC LL_CRS_ClearFlag_ERR
* @retval None
*/
__STATIC_INLINE void LL_CRS_ClearFlag_ERR(void)
{
WRITE_REG(CRS->ICR, CRS_ICR_ERRC);
}
/**
* @brief Clear Expected SYNC flag
* @rmtoll ICR ESYNCC LL_CRS_ClearFlag_ESYNC
* @retval None
*/
__STATIC_INLINE void LL_CRS_ClearFlag_ESYNC(void)
{
WRITE_REG(CRS->ICR, CRS_ICR_ESYNCC);
}
/**
* @}
*/
/** @defgroup CRS_LL_EF_IT_Management IT_Management
* @{
*/
/**
* @brief Enable SYNC event OK interrupt
* @rmtoll CR SYNCOKIE LL_CRS_EnableIT_SYNCOK
* @retval None
*/
__STATIC_INLINE void LL_CRS_EnableIT_SYNCOK(void)
{
SET_BIT(CRS->CR, CRS_CR_SYNCOKIE);
}
/**
* @brief Disable SYNC event OK interrupt
* @rmtoll CR SYNCOKIE LL_CRS_DisableIT_SYNCOK
* @retval None
*/
__STATIC_INLINE void LL_CRS_DisableIT_SYNCOK(void)
{
CLEAR_BIT(CRS->CR, CRS_CR_SYNCOKIE);
}
/**
* @brief Check if SYNC event OK interrupt is enabled or not
* @rmtoll CR SYNCOKIE LL_CRS_IsEnabledIT_SYNCOK
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_CRS_IsEnabledIT_SYNCOK(void)
{
return ((READ_BIT(CRS->CR, CRS_CR_SYNCOKIE) == (CRS_CR_SYNCOKIE)) ? 1UL : 0UL);
}
/**
* @brief Enable SYNC warning interrupt
* @rmtoll CR SYNCWARNIE LL_CRS_EnableIT_SYNCWARN
* @retval None
*/
__STATIC_INLINE void LL_CRS_EnableIT_SYNCWARN(void)
{
SET_BIT(CRS->CR, CRS_CR_SYNCWARNIE);
}
/**
* @brief Disable SYNC warning interrupt
* @rmtoll CR SYNCWARNIE LL_CRS_DisableIT_SYNCWARN
* @retval None
*/
__STATIC_INLINE void LL_CRS_DisableIT_SYNCWARN(void)
{
CLEAR_BIT(CRS->CR, CRS_CR_SYNCWARNIE);
}
/**
* @brief Check if SYNC warning interrupt is enabled or not
* @rmtoll CR SYNCWARNIE LL_CRS_IsEnabledIT_SYNCWARN
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_CRS_IsEnabledIT_SYNCWARN(void)
{
return ((READ_BIT(CRS->CR, CRS_CR_SYNCWARNIE) == (CRS_CR_SYNCWARNIE)) ? 1UL : 0UL);
}
/**
* @brief Enable Synchronization or trimming error interrupt
* @rmtoll CR ERRIE LL_CRS_EnableIT_ERR
* @retval None
*/
__STATIC_INLINE void LL_CRS_EnableIT_ERR(void)
{
SET_BIT(CRS->CR, CRS_CR_ERRIE);
}
/**
* @brief Disable Synchronization or trimming error interrupt
* @rmtoll CR ERRIE LL_CRS_DisableIT_ERR
* @retval None
*/
__STATIC_INLINE void LL_CRS_DisableIT_ERR(void)
{
CLEAR_BIT(CRS->CR, CRS_CR_ERRIE);
}
/**
* @brief Check if Synchronization or trimming error interrupt is enabled or not
* @rmtoll CR ERRIE LL_CRS_IsEnabledIT_ERR
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_CRS_IsEnabledIT_ERR(void)
{
return ((READ_BIT(CRS->CR, CRS_CR_ERRIE) == (CRS_CR_ERRIE)) ? 1UL : 0UL);
}
/**
* @brief Enable Expected SYNC interrupt
* @rmtoll CR ESYNCIE LL_CRS_EnableIT_ESYNC
* @retval None
*/
__STATIC_INLINE void LL_CRS_EnableIT_ESYNC(void)
{
SET_BIT(CRS->CR, CRS_CR_ESYNCIE);
}
/**
* @brief Disable Expected SYNC interrupt
* @rmtoll CR ESYNCIE LL_CRS_DisableIT_ESYNC
* @retval None
*/
__STATIC_INLINE void LL_CRS_DisableIT_ESYNC(void)
{
CLEAR_BIT(CRS->CR, CRS_CR_ESYNCIE);
}
/**
* @brief Check if Expected SYNC interrupt is enabled or not
* @rmtoll CR ESYNCIE LL_CRS_IsEnabledIT_ESYNC
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_CRS_IsEnabledIT_ESYNC(void)
{
return ((READ_BIT(CRS->CR, CRS_CR_ESYNCIE) == (CRS_CR_ESYNCIE)) ? 1UL : 0UL);
}
/**
* @}
*/
#if defined(USE_FULL_LL_DRIVER)
/** @defgroup CRS_LL_EF_Init Initialization and de-initialization functions
* @{
*/
ErrorStatus LL_CRS_DeInit(void);
/**
* @}
*/
#endif /* USE_FULL_LL_DRIVER */
/**
* @}
*/
/**
* @}
*/
#endif /* defined(CRS) */
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /* STM32U3xx_LL_CRS_H */

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/**
******************************************************************************
* @file stm32u3xx_ll_icache.h
* @author MCD Application Team
* @brief Header file of ICACHE LL module.
******************************************************************************
* @attention
*
* Copyright (c) 2023 STMicroelectronics.
* All rights reserved.
*
* This software is licensed under terms that can be found in the LICENSE file
* in the root directory of this software component.
* If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
/* Define to prevent recursive inclusion ------------------------------------*/
#ifndef STM32U3xx_LL_ICACHE_H
#define STM32U3xx_LL_ICACHE_H
#ifdef __cplusplus
extern "C" {
#endif
/* Includes -----------------------------------------------------------------*/
#include "stm32u3xx.h"
/** @addtogroup STM32U3xx_LL_Driver
* @{
*/
#if defined(ICACHE)
/** @defgroup ICACHE_LL ICACHE
* @{
*/
/* Private types -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private constants ---------------------------------------------------------*/
/* Private macros ------------------------------------------------------------*/
/* Exported types ------------------------------------------------------------*/
/** @defgroup ICACHE_LL_REGION_CONFIG ICACHE Exported Configuration structure
* @{
*/
/**
* @brief LL ICACHE region configuration structure definition
*/
typedef struct
{
uint32_t BaseAddress; /*!< Configures the C-AHB base address to be remapped */
uint32_t RemapAddress; /*!< Configures the remap address to be remapped */
uint32_t Size; /*!< Configures the region size.
This parameter can be a value of @ref ICACHE_LL_EC_Region_Size */
uint32_t TrafficRoute; /*!< Selects the traffic route.
This parameter can be a value of @ref ICACHE_LL_EC_Traffic_Route */
uint32_t OutputBurstType; /*!< Selects the output burst type.
This parameter can be a value of @ref ICACHE_LL_EC_Output_Burst_Type */
} LL_ICACHE_RegionTypeDef;
/**
* @}
*/
/* Exported constants -------------------------------------------------------*/
/** @defgroup ICACHE_LL_Exported_Constants ICACHE Exported Constants
* @{
*/
/** @defgroup ICACHE_LL_EC_WaysSelection Ways selection
* @{
*/
#define LL_ICACHE_1WAY 0U /*!< 1-way cache (direct mapped cache) */
#define LL_ICACHE_2WAYS ICACHE_CR_WAYSEL /*!< 2-ways set associative cache (default) */
/**
* @}
*/
/** @defgroup ICACHE_LL_EC_Monitor_Type Monitor type
* @{
*/
#define LL_ICACHE_MONITOR_HIT ICACHE_CR_HITMEN /*!< Hit monitor counter */
#define LL_ICACHE_MONITOR_MISS ICACHE_CR_MISSMEN /*!< Miss monitor counter */
#define LL_ICACHE_MONITOR_ALL (ICACHE_CR_HITMEN | ICACHE_CR_MISSMEN) /*!< All monitors counters */
/**
* @}
*/
/** @defgroup ICACHE_LL_EC_GET_FLAG Get Flags Defines
* @brief Flags defines which can be used with LL_ICACHE_ReadReg function
* @{
*/
#define LL_ICACHE_SR_BUSYF ICACHE_SR_BUSYF /*!< Busy flag */
#define LL_ICACHE_SR_BSYENDF ICACHE_SR_BSYENDF /*!< Busy end flag */
#define LL_ICACHE_SR_ERRF ICACHE_SR_ERRF /*!< Cache error flag */
/**
* @}
*/
/** @defgroup ICACHE_LL_EC_CLEAR_FLAG Clear Flags Defines
* @brief Flags defines which can be used with LL_ICACHE_WriteReg function
* @{
*/
#define LL_ICACHE_FCR_CBSYENDF ICACHE_FCR_CBSYENDF /*!< Busy end flag */
#define LL_ICACHE_FCR_CERRF ICACHE_FCR_CERRF /*!< Cache error flag */
/**
* @}
*/
/** @defgroup ICACHE_LL_EC_IT IT Defines
* @brief IT defines which can be used with LL_ICACHE_ReadReg and LL_ICACHE_WriteReg functions
* @{
*/
#define LL_ICACHE_IER_BSYENDIE ICACHE_IER_BSYENDIE /*!< Busy end interrupt */
#define LL_ICACHE_IER_ERRIE ICACHE_IER_ERRIE /*!< Cache error interrupt */
/**
* @}
*/
/** @defgroup ICACHE_LL_EC_Region Remapped Region number
* @{
*/
#define LL_ICACHE_REGION_0 0U /*!< Region 0 */
#define LL_ICACHE_REGION_1 1U /*!< Region 1 */
#define LL_ICACHE_REGION_2 2U /*!< Region 2 */
#define LL_ICACHE_REGION_3 3U /*!< Region 3 */
/**
* @}
*/
/** @defgroup ICACHE_LL_EC_Region_Size Remapped Region size
* @{
*/
#define LL_ICACHE_REGIONSIZE_2MB 1U /*!< Region size 2MB */
#define LL_ICACHE_REGIONSIZE_4MB 2U /*!< Region size 4MB */
#define LL_ICACHE_REGIONSIZE_8MB 3U /*!< Region size 8MB */
#define LL_ICACHE_REGIONSIZE_16MB 4U /*!< Region size 16MB */
#define LL_ICACHE_REGIONSIZE_32MB 5U /*!< Region size 32MB */
#define LL_ICACHE_REGIONSIZE_64MB 6U /*!< Region size 64MB */
#define LL_ICACHE_REGIONSIZE_128MB 7U /*!< Region size 128MB */
/**
* @}
*/
/** @defgroup ICACHE_LL_EC_Traffic_Route Remapped Traffic route
* @{
*/
#define LL_ICACHE_MASTER1_PORT 0U /*!< Master1 port */
#define LL_ICACHE_MASTER2_PORT ICACHE_CRRx_MSTSEL /*!< Master2 port */
/**
* @}
*/
/** @defgroup ICACHE_LL_EC_Output_Burst_Type Remapped Output burst type
* @{
*/
#define LL_ICACHE_OUTPUT_BURST_WRAP 0U /*!< WRAP */
#define LL_ICACHE_OUTPUT_BURST_INCR ICACHE_CRRx_HBURST /*!< INCR */
/**
* @}
*/
/**
* @}
*/
/* Exported macros ----------------------------------------------------------*/
/** @defgroup ICACHE_LL_Exported_Macros ICACHE Exported Macros
* @{
*/
/** @defgroup ICACHE_LL_EM_WRITE_READ Common write and read registers Macros
* @{
*/
/**
* @brief Write a value in ICACHE register
* @param __REG__ Register to be written
* @param __VALUE__ Value to be written in the register
* @retval None
*/
#define LL_ICACHE_WriteReg(__REG__, __VALUE__) WRITE_REG(ICACHE->__REG__, (__VALUE__))
/**
* @brief Read a value in ICACHE register
* @param __REG__ Register to be read
* @retval Register value
*/
#define LL_ICACHE_ReadReg(__REG__) READ_REG(ICACHE->__REG__)
/**
* @}
*/
/**
* @}
*/
/* Exported functions --------------------------------------------------------*/
/** @defgroup ICACHE_LL_Exported_Functions ICACHE Exported Functions
* @{
*/
/** @defgroup ICACHE_LL_EF_Configuration Configuration
* @{
*/
/**
* @brief Enable the ICACHE.
* @rmtoll CR EN LL_ICACHE_Enable
* @retval None
*/
__STATIC_INLINE void LL_ICACHE_Enable(void)
{
SET_BIT(ICACHE->CR, ICACHE_CR_EN);
}
/**
* @brief Disable the ICACHE.
* @rmtoll CR EN LL_ICACHE_Disable
* @retval None
*/
__STATIC_INLINE void LL_ICACHE_Disable(void)
{
CLEAR_BIT(ICACHE->CR, ICACHE_CR_EN);
}
/**
* @brief Return if ICACHE is enabled or not.
* @rmtoll CR EN LL_ICACHE_IsEnabled
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_ICACHE_IsEnabled(void)
{
return ((READ_BIT(ICACHE->CR, ICACHE_CR_EN) == (ICACHE_CR_EN)) ? 1UL : 0UL);
}
/**
* @brief Select the ICACHE operating mode.
* @rmtoll CR WAYSEL LL_ICACHE_SetMode
* @param Mode This parameter can be one of the following values:
* @arg @ref LL_ICACHE_1WAY
* @arg @ref LL_ICACHE_2WAYS
* @retval None
*/
__STATIC_INLINE void LL_ICACHE_SetMode(uint32_t Mode)
{
MODIFY_REG(ICACHE->CR, ICACHE_CR_WAYSEL, Mode);
}
/**
* @brief Get the selected ICACHE operating mode.
* @rmtoll CR WAYSEL LL_ICACHE_GetMode
* @retval Returned value can be one of the following values:
* @arg @ref LL_ICACHE_1WAY
* @arg @ref LL_ICACHE_2WAYS
*/
__STATIC_INLINE uint32_t LL_ICACHE_GetMode(void)
{
return (READ_BIT(ICACHE->CR, ICACHE_CR_WAYSEL));
}
/**
* @brief Invalidate the ICACHE.
* @note Until the BSYEND flag is set, the cache is bypassed.
* @rmtoll CR CACHEINV LL_ICACHE_Invalidate
* @retval None
*/
__STATIC_INLINE void LL_ICACHE_Invalidate(void)
{
SET_BIT(ICACHE->CR, ICACHE_CR_CACHEINV);
}
/**
* @}
*/
/** @defgroup ICACHE_LL_EF_Monitors Monitors
* @{
*/
/**
* @brief Enable the hit/miss monitor(s).
* @rmtoll CR HITMEN LL_ICACHE_EnableMonitors
* @rmtoll CR MISSMEN LL_ICACHE_EnableMonitors
* @param Monitors This parameter can be one or a combination of the following values:
* @arg @ref LL_ICACHE_MONITOR_HIT
* @arg @ref LL_ICACHE_MONITOR_MISS
* @arg @ref LL_ICACHE_MONITOR_ALL
* @retval None
*/
__STATIC_INLINE void LL_ICACHE_EnableMonitors(uint32_t Monitors)
{
SET_BIT(ICACHE->CR, Monitors);
}
/**
* @brief Disable the hit/miss monitor(s).
* @rmtoll CR HITMEN LL_ICACHE_DisableMonitors
* @rmtoll CR MISSMEN LL_ICACHE_DisableMonitors
* @param Monitors This parameter can be one or a combination of the following values:
* @arg @ref LL_ICACHE_MONITOR_HIT
* @arg @ref LL_ICACHE_MONITOR_MISS
* @arg @ref LL_ICACHE_MONITOR_ALL
* @retval None
*/
__STATIC_INLINE void LL_ICACHE_DisableMonitors(uint32_t Monitors)
{
CLEAR_BIT(ICACHE->CR, Monitors);
}
/**
* @brief Check if the monitor(s) is(are) enabled or disabled.
* @rmtoll CR HITMEN LL_ICACHE_IsEnabledMonitors
* @rmtoll CR MISSMEN LL_ICACHE_IsEnabledMonitors
* @param Monitors This parameter can be one or a combination of the following values:
* @arg @ref LL_ICACHE_MONITOR_HIT
* @arg @ref LL_ICACHE_MONITOR_MISS
* @arg @ref LL_ICACHE_MONITOR_ALL
* @retval State of parameter value (1 or 0).
*/
__STATIC_INLINE uint32_t LL_ICACHE_IsEnabledMonitors(uint32_t Monitors)
{
return ((READ_BIT(ICACHE->CR, Monitors) == (Monitors)) ? 1UL : 0UL);
}
/**
* @brief Reset the hit/miss monitor(s).
* @rmtoll CR HITMRST LL_ICACHE_ResetMonitors
* @rmtoll CR MISSMRST LL_ICACHE_ResetMonitors
* @param Monitors This parameter can be one or a combination of the following values:
* @arg @ref LL_ICACHE_MONITOR_HIT
* @arg @ref LL_ICACHE_MONITOR_MISS
* @arg @ref LL_ICACHE_MONITOR_ALL
* @retval None
*/
__STATIC_INLINE void LL_ICACHE_ResetMonitors(uint32_t Monitors)
{
/* Reset */
SET_BIT(ICACHE->CR, (Monitors << 2U));
/* Release reset */
CLEAR_BIT(ICACHE->CR, (Monitors << 2U));
}
/**
* @brief Get the Hit monitor.
* @note Upon reaching the 32-bit maximum value, hit monitor does not wrap.
* @rmtoll HMONR HITMON LL_ICACHE_GetHitMonitor
* @retval Value between Min_Data=0 and Max_Data=0xFFFFFFFF
*/
__STATIC_INLINE uint32_t LL_ICACHE_GetHitMonitor(void)
{
return (ICACHE->HMONR);
}
/**
* @brief Get the Miss monitor.
* @note Upon reaching the 16-bit maximum value, miss monitor does not wrap.
* @rmtoll MMONR MISSMON LL_ICACHE_GetMissMonitor
* @retval Value between Min_Data=0 and Max_Data=0xFFFF
*/
__STATIC_INLINE uint32_t LL_ICACHE_GetMissMonitor(void)
{
return (ICACHE->MMONR);
}
/**
* @}
*/
/** @defgroup ICACHE_LL_EF_IT_Management IT_Management
* @{
*/
/**
* @brief Enable BSYEND interrupt.
* @rmtoll IER BSYENDIE LL_ICACHE_EnableIT_BSYEND
* @retval None
*/
__STATIC_INLINE void LL_ICACHE_EnableIT_BSYEND(void)
{
SET_BIT(ICACHE->IER, ICACHE_IER_BSYENDIE);
}
/**
* @brief Disable BSYEND interrupt.
* @rmtoll IER BSYENDIE LL_ICACHE_DisableIT_BSYEND
* @retval None
*/
__STATIC_INLINE void LL_ICACHE_DisableIT_BSYEND(void)
{
CLEAR_BIT(ICACHE->IER, ICACHE_IER_BSYENDIE);
}
/**
* @brief Check if the BSYEND Interrupt is enabled or disabled.
* @rmtoll IER BSYENDIE LL_ICACHE_IsEnabledIT_BSYEND
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_ICACHE_IsEnabledIT_BSYEND(void)
{
return ((READ_BIT(ICACHE->IER, ICACHE_IER_BSYENDIE) == (ICACHE_IER_BSYENDIE)) ? 1UL : 0UL);
}
/**
* @brief Enable ERR interrupt.
* @rmtoll IER ERRIE LL_ICACHE_EnableIT_ERR
* @retval None
*/
__STATIC_INLINE void LL_ICACHE_EnableIT_ERR(void)
{
SET_BIT(ICACHE->IER, ICACHE_IER_ERRIE);
}
/**
* @brief Disable ERR interrupt.
* @rmtoll IER ERRIE LL_ICACHE_DisableIT_ERR
* @retval None
*/
__STATIC_INLINE void LL_ICACHE_DisableIT_ERR(void)
{
CLEAR_BIT(ICACHE->IER, ICACHE_IER_ERRIE);
}
/**
* @brief Check if the ERR Interrupt is enabled or disabled.
* @rmtoll IER ERRIE LL_ICACHE_IsEnabledIT_ERR
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_ICACHE_IsEnabledIT_ERR(void)
{
return ((READ_BIT(ICACHE->IER, ICACHE_IER_ERRIE) == (ICACHE_IER_ERRIE)) ? 1UL : 0UL);
}
/**
* @}
*/
/** @defgroup ICACHE_LL_EF_FLAG_Management FLAG_Management
* @{
*/
/**
* @brief Indicate the status of an ongoing operation flag.
* @rmtoll SR BUSYF LL_ICACHE_IsActiveFlag_BUSY
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_ICACHE_IsActiveFlag_BUSY(void)
{
return ((READ_BIT(ICACHE->SR, ICACHE_SR_BUSYF) == (ICACHE_SR_BUSYF)) ? 1UL : 0UL);
}
/**
* @brief Indicate the status of an operation end flag.
* @rmtoll SR BSYEND LL_ICACHE_IsActiveFlag_BSYEND
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_ICACHE_IsActiveFlag_BSYEND(void)
{
return ((READ_BIT(ICACHE->SR, ICACHE_SR_BSYENDF) == (ICACHE_SR_BSYENDF)) ? 1UL : 0UL);
}
/**
* @brief Indicate the status of an error flag.
* @rmtoll SR ERRF LL_ICACHE_IsActiveFlag_ERR
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_ICACHE_IsActiveFlag_ERR(void)
{
return ((READ_BIT(ICACHE->SR, ICACHE_SR_ERRF) == (ICACHE_SR_ERRF)) ? 1UL : 0UL);
}
/**
* @brief Clear busy end of operation flag.
* @rmtoll FCR CBSYENDF LL_ICACHE_ClearFlag_BSYEND
* @retval None
*/
__STATIC_INLINE void LL_ICACHE_ClearFlag_BSYEND(void)
{
WRITE_REG(ICACHE->FCR, ICACHE_FCR_CBSYENDF);
}
/**
* @brief Clear error flag.
* @rmtoll FCR ERRF LL_ICACHE_ClearFlag_ERR
* @retval None
*/
__STATIC_INLINE void LL_ICACHE_ClearFlag_ERR(void)
{
WRITE_REG(ICACHE->FCR, ICACHE_FCR_CERRF);
}
/**
* @}
*/
/** @defgroup ICACHE_LL_EF_REGION_Management REGION_Management
* @{
*/
/**
* @brief Enable the remapped memory region.
* @note The region must have been already configured.
* @rmtoll CRRx REN LL_ICACHE_EnableRegion
* @param Region This parameter can be one of the following values:
* @arg @ref LL_ICACHE_REGION_0
* @arg @ref LL_ICACHE_REGION_1
* @arg @ref LL_ICACHE_REGION_2
* @arg @ref LL_ICACHE_REGION_3
* @retval None
*/
__STATIC_INLINE void LL_ICACHE_EnableRegion(uint32_t Region)
{
SET_BIT(*((__IO uint32_t *)(&(ICACHE->CRR0) + (1U * Region))), \
ICACHE_CRRx_REN);
}
/**
* @brief Disable the remapped memory region.
* @rmtoll CRRx REN LL_ICACHE_DisableRegion
* @param Region This parameter can be one of the following values:
* @arg @ref LL_ICACHE_REGION_0
* @arg @ref LL_ICACHE_REGION_1
* @arg @ref LL_ICACHE_REGION_2
* @arg @ref LL_ICACHE_REGION_3
* @retval None
*/
__STATIC_INLINE void LL_ICACHE_DisableRegion(uint32_t Region)
{
CLEAR_BIT(*((__IO uint32_t *)(&(ICACHE->CRR0) + (1U * Region))), \
ICACHE_CRRx_REN);
}
/**
* @brief Return if remapped memory region is enabled or not.
* @rmtoll CRRx REN LL_ICACHE_IsEnabledRegion
* @param Region This parameter can be one of the following values:
* @arg @ref LL_ICACHE_REGION_0
* @arg @ref LL_ICACHE_REGION_1
* @arg @ref LL_ICACHE_REGION_2
* @arg @ref LL_ICACHE_REGION_3
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_ICACHE_IsEnabledRegion(uint32_t Region)
{
return ((READ_BIT(*((__IO uint32_t *)(&(ICACHE->CRR0) + (1U * Region))), \
ICACHE_CRRx_REN) == (ICACHE_CRRx_REN)) ? 1UL : 0UL);
}
/**
* @brief Select the memory remapped region base address.
* @note The useful bits depends on RSIZE as described in the Reference Manual.
* @rmtoll CRRx BASEADDR LL_ICACHE_SetRegionBaseAddress
* @param Region This parameter can be one of the following values:
* @arg @ref LL_ICACHE_REGION_0
* @arg @ref LL_ICACHE_REGION_1
* @arg @ref LL_ICACHE_REGION_2
* @arg @ref LL_ICACHE_REGION_3
* @param Address Alias address in the Code region
* @retval None
*/
__STATIC_INLINE void LL_ICACHE_SetRegionBaseAddress(uint32_t Region, uint32_t Address)
{
MODIFY_REG(*((__IO uint32_t *)(&(ICACHE->CRR0) + (1U * Region))), \
ICACHE_CRRx_BASEADDR, ((Address & 0x1FFFFFFFU) >> 21U));
}
/**
* @brief Get the memory remapped region base address.
* @note The base address is the alias in the Code region.
* @note The useful bits depends on RSIZE as described in the Reference Manual.
* @rmtoll CRRx BASEADDR LL_ICACHE_GetRegionBaseAddress
* @param Region This parameter can be one of the following values:
* @arg @ref LL_ICACHE_REGION_0
* @arg @ref LL_ICACHE_REGION_1
* @arg @ref LL_ICACHE_REGION_2
* @arg @ref LL_ICACHE_REGION_3
* @retval Address Alias address in the Code region
*/
__STATIC_INLINE uint32_t LL_ICACHE_GetRegionBaseAddress(uint32_t Region)
{
return (READ_BIT(*((__IO uint32_t *)(&(ICACHE->CRR0) + (1U * Region))), \
ICACHE_CRRx_BASEADDR) << 21U);
}
/**
* @brief Select the memory remapped region address.
* @note The useful bits depends on RSIZE as described in the Reference Manual.
* @rmtoll CRRx REMAPADDR LL_ICACHE_SetRegionRemapAddress
* @param Region This parameter can be one of the following values:
* @arg @ref LL_ICACHE_REGION_0
* @arg @ref LL_ICACHE_REGION_1
* @arg @ref LL_ICACHE_REGION_2
* @arg @ref LL_ICACHE_REGION_3
* @param Address Memory address to remap
* @retval None
*/
__STATIC_INLINE void LL_ICACHE_SetRegionRemapAddress(uint32_t Region, uint32_t Address)
{
MODIFY_REG(*((__IO uint32_t *)(&(ICACHE->CRR0) + (1U * Region))), \
ICACHE_CRRx_REMAPADDR, ((Address >> 21U) << ICACHE_CRRx_REMAPADDR_Pos));
}
/**
* @brief Get the memory remapped region address.
* @note The useful bits depends on RSIZE as described in the Reference Manual.
* @rmtoll CRRx REMAPADDR LL_ICACHE_GetRegionRemapAddress
* @param Region This parameter can be one of the following values:
* @arg @ref LL_ICACHE_REGION_0
* @arg @ref LL_ICACHE_REGION_1
* @arg @ref LL_ICACHE_REGION_2
* @arg @ref LL_ICACHE_REGION_3
* @retval Address Remapped memory address
*/
__STATIC_INLINE uint32_t LL_ICACHE_GetRegionRemapAddress(uint32_t Region)
{
return ((READ_BIT(*((__IO uint32_t *)(&(ICACHE->CRR0) + (1U * Region))), \
ICACHE_CRRx_REMAPADDR) >> ICACHE_CRRx_REMAPADDR_Pos) << 21U);
}
/**
* @brief Select the memory remapped region size.
* @rmtoll CRRx RSIZE LL_ICACHE_SetRegionSize
* @param Region This parameter can be one of the following values:
* @arg @ref LL_ICACHE_REGION_0
* @arg @ref LL_ICACHE_REGION_1
* @arg @ref LL_ICACHE_REGION_2
* @arg @ref LL_ICACHE_REGION_3
* @param Size This parameter can be one of the following values:
* @arg @ref LL_ICACHE_REGIONSIZE_2MB
* @arg @ref LL_ICACHE_REGIONSIZE_4MB
* @arg @ref LL_ICACHE_REGIONSIZE_8MB
* @arg @ref LL_ICACHE_REGIONSIZE_16MB
* @arg @ref LL_ICACHE_REGIONSIZE_32MB
* @arg @ref LL_ICACHE_REGIONSIZE_64MB
* @arg @ref LL_ICACHE_REGIONSIZE_128MB
* @retval None
*/
__STATIC_INLINE void LL_ICACHE_SetRegionSize(uint32_t Region, uint32_t Size)
{
MODIFY_REG(*((__IO uint32_t *)(&(ICACHE->CRR0) + (1U * Region))), \
ICACHE_CRRx_RSIZE, (Size << ICACHE_CRRx_RSIZE_Pos));
}
/**
* @brief Get the selected the memory remapped region size.
* @rmtoll CRRx RSIZE LL_ICACHE_GetRegionSize
* @param Region This parameter can be one of the following values:
* @arg @ref LL_ICACHE_REGION_0
* @arg @ref LL_ICACHE_REGION_1
* @arg @ref LL_ICACHE_REGION_2
* @arg @ref LL_ICACHE_REGION_3
* @retval Returned value can be one of the following values:
* @arg @ref LL_ICACHE_REGIONSIZE_2MB
* @arg @ref LL_ICACHE_REGIONSIZE_4MB
* @arg @ref LL_ICACHE_REGIONSIZE_8MB
* @arg @ref LL_ICACHE_REGIONSIZE_16MB
* @arg @ref LL_ICACHE_REGIONSIZE_32MB
* @arg @ref LL_ICACHE_REGIONSIZE_64MB
* @arg @ref LL_ICACHE_REGIONSIZE_128MB
*/
__STATIC_INLINE uint32_t LL_ICACHE_GetRegionSize(uint32_t Region)
{
return (READ_BIT(*((__IO uint32_t *)(&(ICACHE->CRR0) + (1U * Region))), \
ICACHE_CRRx_RSIZE) >> ICACHE_CRRx_RSIZE_Pos);
}
/**
* @brief Select the memory remapped region output burst type.
* @rmtoll CRRx HBURST LL_ICACHE_SetRegionOutputBurstType
* @param Region This parameter can be one of the following values:
* @arg @ref LL_ICACHE_REGION_0
* @arg @ref LL_ICACHE_REGION_1
* @arg @ref LL_ICACHE_REGION_2
* @arg @ref LL_ICACHE_REGION_3
* @param Type This parameter can be one of the following values:
* @arg @ref LL_ICACHE_OUTPUT_BURST_WRAP
* @arg @ref LL_ICACHE_OUTPUT_BURST_INCR
* @retval None
*/
__STATIC_INLINE void LL_ICACHE_SetRegionOutputBurstType(uint32_t Region, uint32_t Type)
{
MODIFY_REG(*((__IO uint32_t *)(&(ICACHE->CRR0) + (1U * Region))), \
ICACHE_CRRx_HBURST, Type);
}
/**
* @brief Get the selected the memory remapped region output burst type.
* @rmtoll CRRx HBURST LL_ICACHE_GetRegionOutputBurstType
* @param Region This parameter can be one of the following values:
* @arg @ref LL_ICACHE_REGION_0
* @arg @ref LL_ICACHE_REGION_1
* @arg @ref LL_ICACHE_REGION_2
* @arg @ref LL_ICACHE_REGION_3
* @retval Returned value can be one of the following values:
* @arg @ref LL_ICACHE_OUTPUT_BURST_WRAP
* @arg @ref LL_ICACHE_OUTPUT_BURST_INCR
*/
__STATIC_INLINE uint32_t LL_ICACHE_GetRegionOutputBurstType(uint32_t Region)
{
return (READ_BIT(*((__IO uint32_t *)(&(ICACHE->CRR0) + (1U * Region))), \
ICACHE_CRRx_HBURST));
}
/**
* @brief Select the memory remapped region cache master port.
* @rmtoll CRRx MSTSEL LL_ICACHE_SetRegionMasterPort
* @param Region This parameter can be one of the following values:
* @arg @ref LL_ICACHE_REGION_0
* @arg @ref LL_ICACHE_REGION_1
* @arg @ref LL_ICACHE_REGION_2
* @arg @ref LL_ICACHE_REGION_3
* @param Port This parameter can be one of the following values:
* @arg @ref LL_ICACHE_MASTER1_PORT
* @arg @ref LL_ICACHE_MASTER2_PORT
* @retval None
*/
__STATIC_INLINE void LL_ICACHE_SetRegionMasterPort(uint32_t Region, uint32_t Port)
{
MODIFY_REG(*((__IO uint32_t *)(&(ICACHE->CRR0) + (1U * Region))), \
ICACHE_CRRx_MSTSEL, Port);
}
/**
* @brief Get the selected the memory remapped region cache master port.
* @rmtoll CRRx MSTSEL LL_ICACHE_GetRegionMasterPort
* @param Region This parameter can be one of the following values:
* @arg @ref LL_ICACHE_REGION_0
* @arg @ref LL_ICACHE_REGION_1
* @arg @ref LL_ICACHE_REGION_2
* @arg @ref LL_ICACHE_REGION_3
* @retval Returned value can be one of the following values:
* @arg @ref LL_ICACHE_MASTER1_PORT
* @arg @ref LL_ICACHE_MASTER2_PORT
*/
__STATIC_INLINE uint32_t LL_ICACHE_GetRegionMasterPort(uint32_t Region)
{
return (READ_BIT(*((__IO uint32_t *)(&(ICACHE->CRR0) + (1U * Region))), \
ICACHE_CRRx_MSTSEL));
}
/**
* @}
*/
#if defined(USE_FULL_LL_DRIVER)
/** @defgroup ICACHE_LL_EF_REGION_Init Region Initialization functions
* @{
*/
void LL_ICACHE_ConfigRegion(uint32_t Region, const LL_ICACHE_RegionTypeDef *const pICACHE_RegionStruct);
/**
* @}
*/
#endif /* USE_FULL_LL_DRIVER */
/**
* @}
*/
/**
* @}
*/
#endif /* ICACHE */
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /* STM32U3xx_LL_ICACHE_H */

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/**
******************************************************************************
* @file stm32u3xx_ll_utils.h
* @author MCD Application Team
* @brief Header file of UTILS LL module.
******************************************************************************
* @attention
*
* Copyright (c) 2023 STMicroelectronics.
* All rights reserved.
*
* This software is licensed under terms that can be found in the LICENSE file
* in the root directory of this software component.
* If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
@verbatim
==============================================================================
##### How to use this driver #####
==============================================================================
[..]
The LL UTILS driver contains a set of generic APIs that can be
used by user:
(+) Device electronic signature
(+) Timing functions
(+) PLL configuration functions
@endverbatim
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __STM32U3xx_LL_UTILS_H
#define __STM32U3xx_LL_UTILS_H
#ifdef __cplusplus
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include "stm32u3xx.h"
/** @addtogroup STM32U3xx_LL_Driver
* @{
*/
/** @defgroup UTILS_LL UTILS
* @{
*/
/* Private types -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private constants ---------------------------------------------------------*/
/** @defgroup UTILS_LL_Private_Constants UTILS Private Constants
* @{
*/
/* Max delay can be used in LL_mDelay */
#define LL_MAX_DELAY 0xFFFFFFFFU
/**
* @brief Unique device ID register base address
*/
#define UID_BASE_ADDRESS UID_BASE
/**
* @brief Flash size data register base address
*/
#define FLASHSIZE_BASE_ADDRESS FLASHSIZE_BASE
/**
* @brief Package data register base address
*/
#define PACKAGE_BASE_ADDRESS PACKAGE_BASE
/**
* @}
*/
/* Private macros ------------------------------------------------------------*/
/** @defgroup UTILS_LL_Private_Macros UTILS Private Macros
* @{
*/
/**
* @}
*/
/* Exported types ------------------------------------------------------------*/
/** @defgroup UTILS_LL_ES_INIT UTILS Exported structures
* @{
*/
/**
* @brief UTILS System, AHB and APB buses clock configuration structure definition
*/
typedef struct
{
uint32_t AHBCLKDivider; /*!< The AHB clock (HCLK) divider. This clock is derived from the system clock (SYSCLK).
This parameter can be a value of @ref RCC_LL_EC_SYSCLK_DIV
This feature can be modified afterwards using unitary function
@ref LL_RCC_SetAHBPrescaler(). */
uint32_t APB1CLKDivider; /*!< The APB1 clock (PCLK1) divider. This clock is derived from the AHB clock (HCLK).
This parameter can be a value of @ref RCC_LL_EC_APB1_DIV
This feature can be modified afterwards using unitary function
@ref LL_RCC_SetAPB1Prescaler(). */
uint32_t APB2CLKDivider; /*!< The APB2 clock (PCLK2) divider. This clock is derived from the AHB clock (HCLK).
This parameter can be a value of @ref RCC_LL_EC_APB2_DIV
This feature can be modified afterwards using unitary function
@ref LL_RCC_SetAPB2Prescaler(). */
uint32_t APB3CLKDivider; /*!< The APB3 clock (PCLK3) divider. This clock is derived from the AHB clock (HCLK).
This parameter can be a value of @ref RCC_LL_EC_APB3_DIV
This feature can be modified afterwards using unitary function
@ref LL_RCC_SetAPB3Prescaler(). */
} LL_UTILS_ClkInitTypeDef;
/**
* @}
*/
/* Exported constants --------------------------------------------------------*/
/** @defgroup UTILS_LL_Exported_Constants UTILS Exported Constants
* @{
*/
/** @defgroup UTILS_EC_PACKAGETYPE PACKAGE TYPE
* @{
*/
#define LL_UTILS_PACKAGETYPE_UQFN32 0x00000000U /*!< UQFN32 package type */
#define LL_UTILS_PACKAGETYPE_UQFN48 0x00000001U /*!< UQFN48 package type */
#define LL_UTILS_PACKAGETYPE_BGA59 0x00000002U /*!< BGA59 package type */
#define LL_UTILS_PACKAGETYPE_UQFN32_SMPS 0x00000003U /*!< UQFN32 with internal SMPS package type */
#define LL_UTILS_PACKAGETYPE_UQFN48_SMPS 0x00000004U /*!< UQFN48 with internal SMPS package type */
#define LL_UTILS_PACKAGETYPE_BGA59_SMPS 0x00000005U /*!< BGA59 with internal SMPS package type */
/**
* @}
*/
/**
* @}
*/
/* Exported macro ------------------------------------------------------------*/
/* Exported functions --------------------------------------------------------*/
/** @defgroup UTILS_LL_Exported_Functions UTILS Exported Functions
* @{
*/
/** @defgroup UTILS_EF_DEVICE_ELECTRONIC_SIGNATURE DEVICE ELECTRONIC SIGNATURE
* @{
*/
/**
* @brief Get Word0 of the unique device identifier (UID based on 96 bits)
* @retval UID[31:0]: X and Y coordinates on the wafer expressed in BCD format
*/
__STATIC_INLINE uint32_t LL_GetUID_Word0(void)
{
return (uint32_t)(READ_REG(*((uint32_t *)UID_BASE_ADDRESS)));
}
/**
* @brief Get Word1 of the unique device identifier (UID based on 96 bits)
* @retval UID[63:32]: Wafer number (UID[39:32]) & LOT_NUM[23:0] (UID[63:40])
*/
__STATIC_INLINE uint32_t LL_GetUID_Word1(void)
{
return (uint32_t)(READ_REG(*((uint32_t *)(UID_BASE_ADDRESS + 4U))));
}
/**
* @brief Get Word2 of the unique device identifier (UID based on 96 bits)
* @retval UID[95:64]: Lot number (ASCII encoded) - LOT_NUM[55:24]
*/
__STATIC_INLINE uint32_t LL_GetUID_Word2(void)
{
return (uint32_t)(READ_REG(*((uint32_t *)(UID_BASE_ADDRESS + 8U))));
}
/**
* @brief Get Flash memory size
* @note This bitfield indicates the size of the device Flash memory expressed in
* Kbytes. As an example, 0x040 corresponds to 64 Kbytes.
* @retval FLASH_SIZE[15:0]: Flash memory size in Kbytes
*/
__STATIC_INLINE uint32_t LL_GetFlashSize(void)
{
return (uint32_t)(READ_REG(*((uint32_t *)FLASHSIZE_BASE_ADDRESS)) & 0xFFFFU);
}
/**
* @brief Get Package type
* @retval Returned value can be one of the following values:
* @arg @ref LL_UTILS_PACKAGETYPE_UQFN32
* @arg @ref LL_UTILS_PACKAGETYPE_UQFN48
* @arg @ref LL_UTILS_PACKAGETYPE_BGA59
* @arg @ref LL_UTILS_PACKAGETYPE_UQFN32_SMPS
* @arg @ref LL_UTILS_PACKAGETYPE_UQFN48_SMPS
* @arg @ref LL_UTILS_PACKAGETYPE_BGA59_SMPS
*/
__STATIC_INLINE uint32_t LL_GetPackageType(void)
{
return (uint32_t)(READ_REG(*((uint32_t *)PACKAGE_BASE_ADDRESS)) & 0x1FU);
}
/**
* @}
*/
/** @defgroup UTILS_LL_EF_DELAY DELAY
* @{
*/
/**
* @brief This function configures the Cortex-M SysTick source of the time base.
* @param HCLKFrequency HCLK frequency in Hz (can be calculated thanks to RCC helper macro)
* @note When a RTOS is used, it is recommended to avoid changing the SysTick
* configuration by calling this function, for a delay use rather osDelay RTOS service.
* @param Ticks Number of ticks
* @retval None
*/
__STATIC_INLINE void LL_InitTick(uint32_t HCLKFrequency, uint32_t Ticks)
{
/* Configure the SysTick to have interrupt in 1ms time base */
SysTick->LOAD = (uint32_t)((HCLKFrequency / Ticks) - 1UL); /* set reload register */
SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
SysTick_CTRL_ENABLE_Msk; /* Enable the Systick Timer */
}
void LL_Init1msTick(uint32_t HCLKFrequency);
void LL_Init1msTick_HCLK_Div8(uint32_t HCLKFrequency);
void LL_Init1msTick_LSE(void);
void LL_Init1msTick_LSI(void);
void LL_mDelay(uint32_t Delay);
/**
* @}
*/
/** @defgroup UTILS_EF_SYSTEM SYSTEM
* @{
*/
void LL_SetSystemCoreClock(uint32_t HCLKFrequency);
ErrorStatus LL_ConfigSystemClock_HSI16(LL_UTILS_ClkInitTypeDef *UTILS_ClkInitStruct);
ErrorStatus LL_ConfigSystemClock_HSE(uint32_t HSEFrequency,
LL_UTILS_ClkInitTypeDef *UTILS_ClkInitStruct);
ErrorStatus LL_SetFlashLatency(uint32_t HCLK_Frequency);
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /* __STM32U3xx_LL_UTILS_H */

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This software component is provided to you as part of a software package and
applicable license terms are in the Package_license file. If you received this
software component outside of a package or without applicable license terms,
the terms of the BSD-3-Clause license shall apply.
You may obtain a copy of the BSD-3-Clause at:
https://opensource.org/licenses/BSD-3-Clause

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/**
******************************************************************************
* @file stm32u3xx_hal_cortex.c
* @author MCD Application Team
* @brief CORTEX HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of the CORTEX:
* + Initialization and Configuration functions
* + Peripheral Control functions
*
******************************************************************************
* @attention
*
* Copyright (c) 2023 STMicroelectronics.
* All rights reserved.
*
* This software is licensed under terms that can be found in the LICENSE file
* in the root directory of this software component.
* If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
@verbatim
==============================================================================
##### How to use this driver #####
==============================================================================
[..]
*** How to configure Interrupts using CORTEX HAL driver ***
===========================================================
[..]
This section provides functions allowing to configure the NVIC interrupts (IRQ).
The Cortex-M33 exceptions are managed by CMSIS functions.
(#) Configure the NVIC Priority Grouping using HAL_NVIC_SetPriorityGrouping() function.
(#) Configure the priority of the selected IRQ Channels using HAL_NVIC_SetPriority().
(#) Enable the selected IRQ Channels using HAL_NVIC_EnableIRQ().
-@- When the NVIC_PRIORITYGROUP_0 is selected, IRQ pre-emption is no more possible.
The pending IRQ priority will be managed only by the sub priority.
-@- IRQ priority order (sorted by highest to lowest priority):
(+@) Lowest pre-emption priority
(+@) Lowest sub priority
(+@) Lowest hardware priority (IRQ number)
[..]
*** How to configure SysTick using CORTEX HAL driver ***
========================================================
[..]
Setup SysTick Timer for time base.
(+) The HAL_SYSTICK_Config() function calls the SysTick_Config() function which
is a CMSIS function that:
(++) Configures the SysTick Reload register with value passed as function parameter.
(++) Configures the SysTick IRQ priority to the lowest value (0x0F).
(++) Resets the SysTick Counter register.
(++) Configures the SysTick Counter clock source to be Core Clock Source (HCLK).
(++) Enables the SysTick Interrupt.
(++) Starts the SysTick Counter.
(+) You can change the SysTick Clock source to be HCLK_Div8 by calling the macro
__HAL_CORTEX_SYSTICKCLK_CONFIG(SYSTICK_CLKSOURCE_HCLK_DIV8) just after the
HAL_SYSTICK_Config() function call. The __HAL_CORTEX_SYSTICKCLK_CONFIG() macro is defined
inside the stm32u3xx_hal_cortex.h file.
(+) You can change the SysTick IRQ priority by calling the
HAL_NVIC_SetPriority(SysTick_IRQn,...) function just after the HAL_SYSTICK_Config() function
call. The HAL_NVIC_SetPriority() call the NVIC_SetPriority() function which is a CMSIS function.
(+) To adjust the SysTick time base, use the following formula:
Reload Value = SysTick Counter Clock (Hz) x Desired Time base (s)
(++) Reload Value is the parameter to be passed for HAL_SYSTICK_Config() function
(++) Reload Value should not exceed 0xFFFFFF
[..]
*** How to configure MPU using CORTEX HAL driver ***
========================================================
[..]
This section provides functions allowing to configure the MPU.
The Cortex-M33 includes a memory protection unit (MPU) that can restrict the read and write accesses to
memory regions (including regions mapped to peripherals).
In Armv8-M architecture, memory types are divided into:
(#) normal memory
(#) device memory
A normal memory has the following attributes:
(#) cacheability: memories cacheable or non-cacheable
(#) shareability: normal memory shareable or non-shareable
(#) execute never: memories marked as executable or execute never (XN)
A device memory has the following attributes:
(#) G or nG: gathering or non-gathering. (multiple accesses to a device can be merged into a single
transaction except for operations with memory ordering semantics, for example, memory barrier
instructions, load acquire/store release).
(#) R or nR: reordering
(#) E or nE: early write acknowledge (similar to bufferable)
Only four combinations of these attributes are valid:
(#) device-nGnRnE: equivalent to Armv7-M strongly ordered memory type
(#) device-nGnRE: equivalent to Armv7-M device memory
(#) device-nGRE: new to Armv8-M
(#) device-GRE: new to Armv8-M
A normal memory has the following attributes:
(#) Cache Allocation attribute : set when a cache line is allocated (no allocation, read/write/read-write allocation)
(#) Cache write policy : write through (write to cache AND memory), write back (memory is written when the cache line is evicted)
(#) Transient : indicates that the region will be used for a short period of time
For normal memory, attributes can be set for inner and outer caches separately.
Note that outer attributes set to 0 change the memory to device mode. Both inner and outer attributes should be set for normal memory.
Sample configurations
(#) Inner-outer cacheable, write back, read-write allocate INNER_OUTER(MPU_RW_ALLOCATE | MPU_WRITE_BACK)
(#) Inner write back, read allocation, outer non-cacheable (MPU_R_ALLOCATE | MPU_WRITE_BACK) | OUTER(MPU_NOT_CACHEABLE)
For detail on memory attributes, refer to the ARMv8-m MPU documentation.
On STM32U3xx, the MPUs are split memory into regions (up to eight for the non-secure MPU,
and up to twelve for the secure MPU).
The secure MPU is only available when TrustZone is activated.
(#) Enable the MPU using HAL_MPU_Enable() function or HAL_MPU_Enable_NS function for non-secure MPU.
(#) Disable the MPU using HAL_MPU_Disable() function or HAL_MPU_Disable_NS function for non-secure MPU.
(#) Enable the MPU region using HAL_MPU_EnableRegion() function or HAL_MPU_EnableRegion_NS function for non-secure MPU region.
(#) Disable the MPU region using HAL_MPU_DisableRegion() function or HAL_MPU_DisableRegion_NS function for non-secure MPU region.
(#) Configure the MPU region using HAL_MPU_ConfigRegion() function or HAL_MPU_ConfigRegion_NS function
for non-secure MPU.
(#) Configure the MPU memory attributes using HAL_MPU_ConfigMemoryAttributes() function or
HAL_MPU_ConfigMemoryAttributes_NS function for non-secure MPU.
(#) The HAL_MPU_XXX_NS functions are only available when TrustZone is activated and CPU in secure state.
_NS functions are targeting non secure MPU, in any other cases APIs without NS shall be used.
@endverbatim
******************************************************************************
The table below gives the allowed values of the pre-emption priority and subpriority according
to the Priority Grouping configuration performed by HAL_NVIC_SetPriorityGrouping() function.
=================================================================================================================
NVIC_PriorityGroup | NVIC_IRQChannelPreemptionPrio | NVIC_IRQChannelSubPrio | Description
=================================================================================================================
NVIC_PRIORITYGROUP_0 | 0 | 0-15 | 0 bit for pre-emption priority
| | | 4 bits for subpriority
-----------------------------------------------------------------------------------------------------------------
NVIC_PRIORITYGROUP_1 | 0-1 | 0-7 | 1 bit for pre-emption priority
| | | 3 bits for subpriority
-----------------------------------------------------------------------------------------------------------------
NVIC_PRIORITYGROUP_2 | 0-3 | 0-3 | 2 bits for pre-emption priority
| | | 2 bits for subpriority
-----------------------------------------------------------------------------------------------------------------
NVIC_PRIORITYGROUP_3 | 0-7 | 0-1 | 3 bits for pre-emption priority
| | | 1 bit for subpriority
-----------------------------------------------------------------------------------------------------------------
NVIC_PRIORITYGROUP_4 | 0-15 | 0 | 4 bits for pre-emption priority
| | | 0 bit for subpriority
=================================================================================================================
******************************************************************************
*/
/* Includes ------------------------------------------------------------------*/
#include "stm32u3xx_hal.h"
/** @addtogroup STM32U3xx_HAL_Driver
* @{
*/
/** @addtogroup CORTEX
* @brief CORTEX HAL module driver
* @{
*/
#ifdef HAL_CORTEX_MODULE_ENABLED
/* Private types -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private constants ---------------------------------------------------------*/
/* Private macros ------------------------------------------------------------*/
/* Private functions ---------------------------------------------------------*/
/** @defgroup CORTEX_Private_Functions CORTEX Private Functions
* @{
*/
static void MPU_ConfigRegion(MPU_Type *MPUx, const MPU_Region_InitTypeDef *pMPU_RegionInit);
static void MPU_ConfigMemoryAttributes(MPU_Type *MPUx, const MPU_Attributes_InitTypeDef *pMPU_AttributesInit);
/**
* @}
*/
/* Exported functions --------------------------------------------------------*/
/** @addtogroup CORTEX_Exported_Functions
* @{
*/
/** @addtogroup CORTEX_Exported_Functions_Group1
* @brief Initialization and Configuration functions
*
@verbatim
==============================================================================
##### Initialization and Configuration functions #####
==============================================================================
[..]
This section provides the CORTEX HAL driver functions allowing to configure Interrupts
SysTick functionalities
@endverbatim
* @{
*/
/**
* @brief Set the priority grouping field (pre-emption priority and subpriority)
* using the required unlock sequence.
* @param PriorityGroup The priority grouping bits length.
* This parameter can be one of the following values:
* @arg NVIC_PRIORITYGROUP_0 0 bit for pre-emption priority,
* 4 bits for subpriority
* @arg NVIC_PRIORITYGROUP_1 1 bit for pre-emption priority,
* 3 bits for subpriority
* @arg NVIC_PRIORITYGROUP_2 2 bits for pre-emption priority,
* 2 bits for subpriority
* @arg NVIC_PRIORITYGROUP_3 3 bits for pre-emption priority,
* 1 bit for subpriority
* @arg NVIC_PRIORITYGROUP_4 4 bits for pre-emption priority,
* 0 bit for subpriority
* @note When the NVIC_PriorityGroup_0 is selected, IRQ pre-emption is no more possible.
* The pending IRQ priority will be managed only by the subpriority.
* @retval None
*/
void HAL_NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
{
/* Check the parameters */
assert_param(IS_NVIC_PRIORITY_GROUP(PriorityGroup));
/* Set the PRIGROUP[10:8] bits according to the PriorityGroup parameter value */
NVIC_SetPriorityGrouping(PriorityGroup);
}
/**
* @brief Set the priority of an interrupt.
* @param IRQn External interrupt number.
* This parameter can be an enumerator of IRQn_Type enumeration
* (For the complete STM32 Devices IRQ Channels list, please refer
* to the appropriate CMSIS device file (stm32u3xxxx.h))
* @param PreemptPriority The pre-emption priority for the IRQn channel.
* This parameter can be a value between 0 and 15
* A lower priority value indicates a higher priority
* @param SubPriority the subpriority level for the IRQ channel.
* This parameter can be a value between 0 and 15
* A lower priority value indicates a higher priority.
* @retval None
*/
void HAL_NVIC_SetPriority(IRQn_Type IRQn, uint32_t PreemptPriority, uint32_t SubPriority)
{
uint32_t prioritygroup;
/* Check the parameters */
assert_param(IS_NVIC_PRIO_INTERRUPT(IRQn));
prioritygroup = NVIC_GetPriorityGrouping();
assert_param(IS_NVIC_SUB_PRIORITY(SubPriority, prioritygroup));
assert_param(IS_NVIC_PREEMPTION_PRIORITY(PreemptPriority, prioritygroup));
NVIC_SetPriority(IRQn, NVIC_EncodePriority(prioritygroup, PreemptPriority, SubPriority));
}
/**
* @brief Enable a device specific interrupt in the NVIC interrupt controller.
* @note To configure interrupts priority correctly, the NVIC_PriorityGroupConfig()
* function should be called before.
* @param IRQn External interrupt number.
* This parameter can be an enumerator of IRQn_Type enumeration
* (For the complete STM32 Devices IRQ Channels list, please refer
* to the appropriate CMSIS device file (stm32u3xxxx.h))
* @retval None
*/
void HAL_NVIC_EnableIRQ(IRQn_Type IRQn)
{
/* Check the parameters */
assert_param(IS_NVIC_DEVICE_IRQ(IRQn));
/* Enable interrupt */
NVIC_EnableIRQ(IRQn);
}
/**
* @brief Disable a device specific interrupt in the NVIC interrupt controller.
* @param IRQn External interrupt number.
* This parameter can be an enumerator of IRQn_Type enumeration
* (For the complete STM32 Devices IRQ Channels list, please refer
* to the appropriate CMSIS device file (stm32u3xxxx.h))
* @retval None
*/
void HAL_NVIC_DisableIRQ(IRQn_Type IRQn)
{
/* Check the parameters */
assert_param(IS_NVIC_DEVICE_IRQ(IRQn));
/* Disable interrupt */
NVIC_DisableIRQ(IRQn);
}
/**
* @brief Initiate a system reset request to reset the MCU.
* @retval None
*/
void HAL_NVIC_SystemReset(void)
{
/* System Reset */
NVIC_SystemReset();
}
/**
* @brief Initialize the System Timer with interrupt enabled and start the System Tick Timer (SysTick):
* Counter is in free running mode to generate periodic interrupts.
* @param TicksNumb Specifies the ticks Number of ticks between two interrupts.
* @retval status: - 0 Function succeeded.
* - 1 Function failed.
*/
uint32_t HAL_SYSTICK_Config(uint32_t TicksNumb)
{
if ((TicksNumb - 1UL) > SysTick_LOAD_RELOAD_Msk)
{
/* Reload value impossible */
return (1UL);
}
/* Set reload register */
WRITE_REG(SysTick->LOAD, (uint32_t)(TicksNumb - 1UL));
/* Load the SysTick Counter Value */
WRITE_REG(SysTick->VAL, 0UL);
/* Enable SysTick IRQ and SysTick Timer */
SET_BIT(SysTick->CTRL, (SysTick_CTRL_TICKINT_Msk | SysTick_CTRL_ENABLE_Msk));
/* Function successful */
return (0UL);
}
/**
* @}
*/
/** @addtogroup CORTEX_Exported_Functions_Group2
* @brief Cortex control functions
*
@verbatim
==============================================================================
##### Peripheral Control functions #####
==============================================================================
[..]
This subsection provides a set of functions allowing to control the CORTEX
(NVIC, SYSTICK, MPU) functionalities.
@endverbatim
* @{
*/
/**
* @brief Get the priority grouping field from the NVIC Interrupt Controller.
* @retval Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field)
*/
uint32_t HAL_NVIC_GetPriorityGrouping(void)
{
/* Get the PRIGROUP[10:8] field value */
return NVIC_GetPriorityGrouping();
}
/**
* @brief Get the priority of an interrupt.
* @param IRQn External interrupt number.
* This parameter can be an enumerator of IRQn_Type enumeration
* (For the complete STM32 Devices IRQ Channels list, please refer
* to the appropriate CMSIS device file (stm32u3xxxx.h))
* @param PriorityGroup the priority grouping bits length.
* This parameter can be one of the following values:
* @arg NVIC_PRIORITYGROUP_0 0 bit for pre-emption priority,
* 4 bits for subpriority
* @arg NVIC_PRIORITYGROUP_1 1 bit for pre-emption priority,
* 3 bits for subpriority
* @arg NVIC_PRIORITYGROUP_2 2 bits for pre-emption priority,
* 2 bits for subpriority
* @arg NVIC_PRIORITYGROUP_3 3 bits for pre-emption priority,
* 1 bit for subpriority
* @arg NVIC_PRIORITYGROUP_4 4 bits for pre-emption priority,
* 0 bit for subpriority
* @param pPreemptPriority Pointer on the Preemptive priority value (starting from 0).
* @param pSubPriority Pointer on the Subpriority value (starting from 0).
* @retval None
*/
void HAL_NVIC_GetPriority(IRQn_Type IRQn, uint32_t PriorityGroup, uint32_t *pPreemptPriority, uint32_t *pSubPriority)
{
/* Check the parameters */
assert_param(IS_NVIC_PRIO_INTERRUPT(IRQn));
assert_param(IS_NVIC_PRIORITY_GROUP(PriorityGroup));
/* Get priority for Cortex-M system or device specific interrupts */
NVIC_DecodePriority(NVIC_GetPriority(IRQn), PriorityGroup, pPreemptPriority, pSubPriority);
}
/**
* @brief Set Pending bit of an external interrupt.
* @param IRQn External interrupt number
* This parameter can be an enumerator of IRQn_Type enumeration
* (For the complete STM32 Devices IRQ Channels list, please refer
* to the appropriate CMSIS device file (stm32u3xxxx.h))
* @retval None
*/
void HAL_NVIC_SetPendingIRQ(IRQn_Type IRQn)
{
/* Check the parameters */
assert_param(IS_NVIC_DEVICE_IRQ(IRQn));
/* Set interrupt pending */
NVIC_SetPendingIRQ(IRQn);
}
/**
* @brief Get Pending Interrupt (read the pending register in the NVIC
* and return the pending bit for the specified interrupt).
* @param IRQn External interrupt number.
* This parameter can be an enumerator of IRQn_Type enumeration
* (For the complete STM32 Devices IRQ Channels list, please refer
* to the appropriate CMSIS device file (stm32u3xxxx.h))
* @retval status: - 0 Interrupt status is not pending.
* - 1 Interrupt status is pending.
*/
uint32_t HAL_NVIC_GetPendingIRQ(IRQn_Type IRQn)
{
/* Check the parameters */
assert_param(IS_NVIC_DEVICE_IRQ(IRQn));
/* Return 1 if pending else 0 */
return NVIC_GetPendingIRQ(IRQn);
}
/**
* @brief Clear the pending bit of an external interrupt.
* @param IRQn External interrupt number.
* This parameter can be an enumerator of IRQn_Type enumeration
* (For the complete STM32 Devices IRQ Channels list, please refer
* to the appropriate CMSIS device file (stm32u3xxxx.h))
* @retval None
*/
void HAL_NVIC_ClearPendingIRQ(IRQn_Type IRQn)
{
/* Check the parameters */
assert_param(IS_NVIC_DEVICE_IRQ(IRQn));
/* Clear pending interrupt */
NVIC_ClearPendingIRQ(IRQn);
}
/**
* @brief Get active interrupt (read the active register in NVIC and return the active bit).
* @param IRQn External interrupt number
* This parameter can be an enumerator of IRQn_Type enumeration
* (For the complete STM32 Devices IRQ Channels list, please refer
* to the appropriate CMSIS device file (stm32u3xxxx.h))
* @retval status: - 0 Interrupt status is not pending.
* - 1 Interrupt status is pending.
*/
uint32_t HAL_NVIC_GetActive(IRQn_Type IRQn)
{
/* Return 1 if active else 0 */
return NVIC_GetActive(IRQn);
}
/**
* @brief Configure the SysTick clock source.
* @param CLKSource specifies the SysTick clock source.
* This parameter can be one of the following values:
* @arg SYSTICK_CLKSOURCE_LSI LSI clock selected as SysTick clock source.
* @arg SYSTICK_CLKSOURCE_LSE LSE clock selected as SysTick clock source.
* @arg SYSTICK_CLKSOURCE_HCLK AHB clock selected as SysTick clock source.
* @arg SYSTICK_CLKSOURCE_HCLK_DIV8 AHB clock divided by 8 selected as SysTick clock source.
* @retval None
*/
void HAL_SYSTICK_CLKSourceConfig(uint32_t CLKSource)
{
/* Check the parameters */
assert_param(IS_SYSTICK_CLK_SOURCE(CLKSource));
switch (CLKSource)
{
/* Select HCLK as Systick clock source */
case SYSTICK_CLKSOURCE_HCLK:
SET_BIT(SysTick->CTRL, SysTick_CTRL_CLKSOURCE_Msk);
break;
/* Select HCLK_DIV8 as Systick clock source */
case SYSTICK_CLKSOURCE_HCLK_DIV8:
CLEAR_BIT(SysTick->CTRL, SysTick_CTRL_CLKSOURCE_Msk);
MODIFY_REG(RCC->CCIPR1, RCC_CCIPR1_SYSTICKSEL, (0x00000000U));
break;
/* Select LSI as Systick clock source */
case SYSTICK_CLKSOURCE_LSI:
CLEAR_BIT(SysTick->CTRL, SysTick_CTRL_CLKSOURCE_Msk);
MODIFY_REG(RCC->CCIPR1, RCC_CCIPR1_SYSTICKSEL, RCC_CCIPR1_SYSTICKSEL_0);
break;
/* Select LSE as Systick clock source */
case SYSTICK_CLKSOURCE_LSE:
CLEAR_BIT(SysTick->CTRL, SysTick_CTRL_CLKSOURCE_Msk);
MODIFY_REG(RCC->CCIPR1, RCC_CCIPR1_SYSTICKSEL, RCC_CCIPR1_SYSTICKSEL_1);
break;
default:
/* Nothing to do */
break;
}
}
/**
* @brief Get the SysTick clock source configuration.
* @retval SysTick clock source that can be one of the following values:
* @arg SYSTICK_CLKSOURCE_LSI: LSI clock selected as SysTick clock source.
* @arg SYSTICK_CLKSOURCE_LSE: LSE clock selected as SysTick clock source.
* @arg SYSTICK_CLKSOURCE_HCLK: AHB clock selected as SysTick clock source.
* @arg SYSTICK_CLKSOURCE_HCLK_DIV8: AHB clock divided by 8 selected as SysTick clock source.
*/
uint32_t HAL_SYSTICK_GetCLKSourceConfig(void)
{
uint32_t systick_source;
/* Read SysTick->CTRL register for internal or external clock source */
if (READ_BIT(SysTick->CTRL, SysTick_CTRL_CLKSOURCE_Msk) != 0U)
{
/* Internal clock source */
systick_source = SYSTICK_CLKSOURCE_HCLK;
}
else
{
/* External clock source, check the selected one in RCC */
switch (__HAL_RCC_GET_SYSTICK_SOURCE())
{
case RCC_SYSTICKCLKSOURCE_LSI:
systick_source = SYSTICK_CLKSOURCE_LSI;
break;
case RCC_SYSTICKCLKSOURCE_LSE:
systick_source = SYSTICK_CLKSOURCE_LSE;
break;
default: /* RCC_SYSTICKCLKSOURCE_HCLK_DIV8 */
systick_source = SYSTICK_CLKSOURCE_HCLK_DIV8;
break;
}
}
return systick_source;
}
/**
* @brief Handle SYSTICK interrupt request.
* @retval None
*/
void HAL_SYSTICK_IRQHandler(void)
{
HAL_SYSTICK_Callback();
}
/**
* @brief SYSTICK callback.
* @retval None
*/
__weak void HAL_SYSTICK_Callback(void)
{
/* NOTE : This function should not be modified, when the callback is needed,
the HAL_SYSTICK_Callback could be implemented in the user file
*/
}
/**
* @brief Clear pending event(s).
* @retval None
*/
void HAL_CORTEX_ClearEvent(void)
{
__SEV();
__WFE();
}
/**
* @brief Enable the MPU.
* @param MPU_Control Specifies the control mode of the MPU during hard fault,
* NMI, FAULTMASK and privileged access to the default memory
* This parameter can be one of the following values:
* @arg MPU_HFNMI_PRIVDEF_NONE
* @arg MPU_HARDFAULT_NMI
* @arg MPU_PRIVILEGED_DEFAULT
* @arg MPU_HFNMI_PRIVDEF
* @retval None
*/
void HAL_MPU_Enable(uint32_t MPU_Control)
{
/* Force any outstanding transfers to complete before enabling MPU */
__DMB();
/* Enable the MPU */
MPU->CTRL = (MPU_Control | MPU_CTRL_ENABLE_Msk);
/* Enable fault exceptions */
SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk;
/* Ensure MPU setting take effects */
__DSB();
__ISB();
}
#if defined (CPU_IN_SECURE_STATE)
/**
* @brief Enable the non-secure MPU.
* @param MPU_Control: Specifies the control mode of the MPU during hard fault,
* NMI, FAULTMASK and privileged access to the default memory
* This parameter can be one of the following values:
* @arg MPU_HFNMI_PRIVDEF_NONE
* @arg MPU_HARDFAULT_NMI
* @arg MPU_PRIVILEGED_DEFAULT
* @arg MPU_HFNMI_PRIVDEF
* @retval None
*/
void HAL_MPU_Enable_NS(uint32_t MPU_Control)
{
__DMB(); /* Data Memory Barrier operation to force any outstanding writes to memory before enabling the MPU */
/* Enable the MPU */
MPU_NS->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk;
/* Enable fault exceptions */
SCB_NS->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk;
/* Follow ARM recommendation with */
/* Data Synchronization and Instruction Synchronization Barriers to ensure MPU configuration */
__DSB(); /* Ensure that the subsequent instruction is executed only after the write to memory */
__ISB(); /* Flush and refill pipeline with updated MPU configuration settings */
}
#endif /* defined (CPU_IN_SECURE_STATE) */
/**
* @brief Disable the MPU.
* @retval None
*/
void HAL_MPU_Disable(void)
{
/* Force any outstanding transfers to complete before disabling MPU */
__DMB();
/* Disable fault exceptions */
SCB->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk;
/* Disable the MPU */
MPU->CTRL &= ~MPU_CTRL_ENABLE_Msk;
/* Ensure MPU setting take effects */
__DSB();
__ISB();
}
#if defined (CPU_IN_SECURE_STATE)
/**
* @brief Disable the non-secure MPU.
* @retval None
*/
void HAL_MPU_Disable_NS(void)
{
/* Force any outstanding transfers to complete before disabling MPU */
__DMB();
/* Disable fault exceptions */
SCB_NS->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk;
/* Disable the MPU */
MPU_NS->CTRL &= ~MPU_CTRL_ENABLE_Msk;
/* Ensure MPU setting take effects */
__DSB();
__ISB();
}
#endif /* defined (CPU_IN_SECURE_STATE) */
/**
* @brief Enable the MPU Region.
* @retval None
*/
void HAL_MPU_EnableRegion(uint32_t RegionNumber)
{
/* Check the parameters */
assert_param(IS_MPU_REGION_NUMBER(RegionNumber));
/* Set the Region number */
MPU->RNR = RegionNumber;
/* Enable the Region */
SET_BIT(MPU->RLAR, MPU_RLAR_EN_Msk);
}
#if defined (CPU_IN_SECURE_STATE)
/**
* @brief Enable the non-secure MPU Region.
* @retval None
*/
void HAL_MPU_EnableRegion_NS(uint32_t RegionNumber)
{
assert_param(IS_MPU_REGION_NUMBER(RegionNumber));
/* Set the Region number */
MPU_NS->RNR = RegionNumber;
/* Enable the Region */
SET_BIT(MPU_NS->RLAR, MPU_RLAR_EN_Msk);
}
#endif /* defined (CPU_IN_SECURE_STATE) */
/**
* @brief Disable the MPU Region.
* @retval None
*/
void HAL_MPU_DisableRegion(uint32_t RegionNumber)
{
/* Check the parameters */
assert_param(IS_MPU_REGION_NUMBER(RegionNumber));
/* Set the Region number */
MPU->RNR = RegionNumber;
/* Disable the Region */
CLEAR_BIT(MPU->RLAR, MPU_RLAR_EN_Msk);
}
#if defined (CPU_IN_SECURE_STATE)
/**
* @brief Disable the non-secure MPU Region.
* @retval None
*/
void HAL_MPU_DisableRegion_NS(uint32_t RegionNumber)
{
/* Check the parameters */
assert_param(IS_MPU_REGION_NUMBER(RegionNumber));
/* Set the Region number */
MPU_NS->RNR = RegionNumber;
/* Disable the Region */
CLEAR_BIT(MPU_NS->RLAR, MPU_RLAR_EN_Msk);
}
#endif /* defined (CPU_IN_SECURE_STATE) */
/**
* @brief Initialize and configure the Region and the memory to be protected.
* @param pMPU_RegionInit Pointer to a MPU_Region_InitTypeDef structure that contains
* the initialization and configuration information.
* @retval None
* @note STM32U3xx supports 12 secure and 8 non secure MPU regions.
*/
void HAL_MPU_ConfigRegion(const MPU_Region_InitTypeDef *pMPU_RegionInit)
{
MPU_ConfigRegion(MPU, pMPU_RegionInit);
}
#if defined (CPU_IN_SECURE_STATE)
/**
* @brief Initialize and configure the Region and the memory to be protected for non-secure MPU.
* @param pMPU_RegionInit Pointer to a MPU_Region_InitTypeDef structure that contains
* the initialization and configuration information.
* @note STM32U3xx supports 8 non secure MPU regions.
* @retval None
*/
void HAL_MPU_ConfigRegion_NS(const MPU_Region_InitTypeDef *pMPU_RegionInit)
{
MPU_ConfigRegion(MPU_NS, pMPU_RegionInit);
}
#endif /* defined (CPU_IN_SECURE_STATE) */
/**
* @brief Initialize and configure the memory attributes.
* @param pMPU_AttributesInit Pointer to a MPU_Attributes_InitTypeDef structure that contains
* the initialization and configuration information.
* @retval None
*/
void HAL_MPU_ConfigMemoryAttributes(const MPU_Attributes_InitTypeDef *pMPU_AttributesInit)
{
MPU_ConfigMemoryAttributes(MPU, pMPU_AttributesInit);
}
#if defined (CPU_IN_SECURE_STATE)
/**
* @brief Initialize and configure the memory attributes for non-secure MPU.
* @param pMPU_AttributesInit Pointer to a MPU_Attributes_InitTypeDef structure that contains
* the initialization and configuration information.
* @retval None
*/
void HAL_MPU_ConfigMemoryAttributes_NS(const MPU_Attributes_InitTypeDef *pMPU_AttributesInit)
{
MPU_ConfigMemoryAttributes(MPU_NS, pMPU_AttributesInit);
}
#endif /* defined (CPU_IN_SECURE_STATE) */
/**
* @}
*/
/**
* @}
*/
/** @addtogroup CORTEX_Private_Functions
* @{
*/
static void MPU_ConfigRegion(MPU_Type *MPUx, const MPU_Region_InitTypeDef *pMPU_RegionInit)
{
/* Check the parameters */
assert_param(IS_MPU_REGION_NUMBER(pMPU_RegionInit->Number));
assert_param(IS_MPU_REGION_ENABLE(pMPU_RegionInit->Enable));
/* Set the Region number */
MPUx->RNR = pMPU_RegionInit->Number;
/* Disable the Region */
CLEAR_BIT(MPUx->RLAR, MPU_RLAR_EN_Msk);
/* Check the parameters */
assert_param(IS_MPU_INSTRUCTION_ACCESS(pMPU_RegionInit->DisableExec));
assert_param(IS_MPU_REGION_PERMISSION_ATTRIBUTE(pMPU_RegionInit->AccessPermission));
assert_param(IS_MPU_ACCESS_SHAREABLE(pMPU_RegionInit->IsShareable));
assert_param(IS_MPU_ATTRIBUTES_NUMBER(pMPU_RegionInit->AttributesIndex));
MPUx->RBAR = (((uint32_t)pMPU_RegionInit->BaseAddress & 0xFFFFFFE0UL) |
((uint32_t)pMPU_RegionInit->IsShareable << MPU_RBAR_SH_Pos) |
((uint32_t)pMPU_RegionInit->AccessPermission << MPU_RBAR_AP_Pos) |
((uint32_t)pMPU_RegionInit->DisableExec << MPU_RBAR_XN_Pos));
MPUx->RLAR = (((uint32_t)pMPU_RegionInit->LimitAddress & 0xFFFFFFE0UL) |
((uint32_t)pMPU_RegionInit->AttributesIndex << MPU_RLAR_AttrIndx_Pos) |
((uint32_t)pMPU_RegionInit->Enable << MPU_RLAR_EN_Pos));
}
static void MPU_ConfigMemoryAttributes(MPU_Type *MPUx, const MPU_Attributes_InitTypeDef *pMPU_AttributesInit)
{
__IO uint32_t *p_mair;
uint32_t attr_values;
uint32_t attr_number;
/* Check the parameters */
assert_param(IS_MPU_ATTRIBUTES_NUMBER(pMPU_AttributesInit->Number));
/* No need to check Attributes value as all 0x0..0xFF possible */
if (pMPU_AttributesInit->Number < MPU_ATTRIBUTES_NUMBER4)
{
/* Program MPU_MAIR0 */
p_mair = &(MPUx->MAIR0);
attr_number = pMPU_AttributesInit->Number;
}
else
{
/* Program MPU_MAIR1 */
p_mair = &(MPUx->MAIR1);
attr_number = (uint32_t)pMPU_AttributesInit->Number - 4U;
}
attr_values = *(p_mair);
attr_values &= ~(0xFFU << (attr_number * 8U));
*(p_mair) = attr_values | ((uint32_t)pMPU_AttributesInit->Attributes << (attr_number * 8U));
}
/**
* @}
*/
#endif /* HAL_CORTEX_MODULE_ENABLED */
/**
* @}
*/
/**
* @}
*/

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/**
******************************************************************************
* @file stm32u3xx_hal_exti.c
* @author MCD Application Team
* @brief EXTI HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of the General Purpose Input/Output (EXTI) peripheral:
* + Initialization and de-initialization functions
* + IO operation functions
*
******************************************************************************
* @attention
*
* Copyright (c) 2023 STMicroelectronics.
* All rights reserved.
*
* This software is licensed under terms that can be found in the LICENSE file
* in the root directory of this software component.
* If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
@verbatim
==============================================================================
##### EXTI Peripheral features #####
==============================================================================
[..]
(+) Each Exti line can be configured within this driver.
(+) Exti line can be configured in 3 different modes
(++) Interrupt
(++) Event
(++) Both of them
(+) Configurable Exti lines can be configured with 3 different triggers
(++) Rising
(++) Falling
(++) Both of them
(+) When set in interrupt mode, configurable Exti lines have two diffenrents
interrupt pending registers which allow to distinguish which transition
occurs:
(++) Rising edge pending interrupt
(++) Falling
(+) Exti lines 0 to 15 are linked to gpio pin number 0 to 15. Gpio port can
be selected through multiplexer.
##### How to use this driver #####
==============================================================================
[..]
(#) Configure the EXTI line using HAL_EXTI_SetConfigLine().
(++) Choose the interrupt line number by setting "Line" member from
EXTI_ConfigTypeDef structure.
(++) Configure the interrupt and/or event mode using "Mode" member from
EXTI_ConfigTypeDef structure.
(++) For configurable lines, configure rising and/or falling trigger
"Trigger" member from EXTI_ConfigTypeDef structure.
(++) For Exti lines linked to gpio, choose gpio port using "GPIOSel"
member from GPIO_InitTypeDef structure.
(#) Get current Exti configuration of a dedicated line using
HAL_EXTI_GetConfigLine().
(++) Provide exiting handle as parameter.
(++) Provide pointer on EXTI_ConfigTypeDef structure as second parameter.
(#) Clear Exti configuration of a dedicated line using HAL_EXTI_GetConfigLine().
(++) Provide exiting handle as parameter.
(#) Register callback to treat Exti interrupts using HAL_EXTI_RegisterCallback().
(++) Provide exiting handle as first parameter.
(++) Provide which callback will be registered using one value from
EXTI_CallbackIDTypeDef.
(++) Provide callback function pointer.
(#) Get interrupt pending bit using HAL_EXTI_GetPending().
(#) Clear interrupt pending bit using HAL_EXTI_GetPending().
(#) Generate software interrupt using HAL_EXTI_GenerateSWI().
@endverbatim
******************************************************************************
*/
/* Includes ------------------------------------------------------------------*/
#include "stm32u3xx_hal.h"
/** @addtogroup STM32U3xx_HAL_Driver
* @{
*/
/** @addtogroup EXTI
* @{
*/
#ifdef HAL_EXTI_MODULE_ENABLED
/* Private typedef -----------------------------------------------------------*/
/* Private defines ------------------------------------------------------------*/
/** @defgroup EXTI_Private_Constants EXTI Private Constants
* @{
*/
#define EXTI_MODE_OFFSET 0x04U /* byte offset between IMR/EMR registers */
#define EXTI_CONFIG_OFFSET 0x08U /* byte offset between Rising/Falling configuration registers */
#define EXTI_PRIVCFGR_OFFSET 0x04U /* byte offset between PRIVCFGR1/PRIVCFGR2 registers */
#define EXTI_SECCFGR_OFFSET 0x04U /* byte offset between SECCFGR1/SECCFGR2 registers */
/**
* @}
*/
/* Private macros ------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private function prototypes -----------------------------------------------*/
/* Exported functions --------------------------------------------------------*/
/** @addtogroup EXTI_Exported_Functions
* @{
*/
/** @addtogroup EXTI_Exported_Functions_Group1
* @brief Configuration functions
*
@verbatim
===============================================================================
##### Configuration functions #####
===============================================================================
@endverbatim
* @{
*/
/**
* @brief Set configuration of a dedicated Exti line.
* @param hexti Exti handle.
* @param pExtiConfig Pointer on EXTI configuration to be set.
* @retval HAL Status.
*/
HAL_StatusTypeDef HAL_EXTI_SetConfigLine(EXTI_HandleTypeDef *hexti, EXTI_ConfigTypeDef *pExtiConfig)
{
__IO uint32_t *regaddr;
uint32_t regval;
uint32_t linepos;
uint32_t maskline;
uint32_t offset;
/* Check null pointer */
if ((hexti == NULL) || (pExtiConfig == NULL))
{
return HAL_ERROR;
}
/* Check the parameters */
assert_param(IS_EXTI_LINE(pExtiConfig->Line));
assert_param(IS_EXTI_MODE(pExtiConfig->Mode));
/* Assign line number to handle */
hexti->Line = pExtiConfig->Line;
/* compute line register offset and line mask */
offset = ((pExtiConfig->Line & EXTI_REG_MASK) >> EXTI_REG_SHIFT);
linepos = (pExtiConfig->Line & EXTI_PIN_MASK);
maskline = (1UL << linepos);
/* Configure triggers for configurable lines */
if ((pExtiConfig->Line & EXTI_CONFIG) != 0U)
{
assert_param(IS_EXTI_TRIGGER(pExtiConfig->Trigger));
/* Configure rising trigger */
regaddr = (__IO uint32_t *)(&EXTI->RTSR1 + (EXTI_CONFIG_OFFSET * offset));
regval = *regaddr;
/* Mask or set line */
if ((pExtiConfig->Trigger & EXTI_TRIGGER_RISING) != 0U)
{
regval |= maskline;
}
else
{
regval &= ~maskline;
}
/* Store rising trigger mode */
*regaddr = regval;
/* Configure falling trigger */
regaddr = (__IO uint32_t *)(&EXTI->FTSR1 + (EXTI_CONFIG_OFFSET * offset));
regval = *regaddr;
/* Mask or set line */
if ((pExtiConfig->Trigger & EXTI_TRIGGER_FALLING) != 0U)
{
regval |= maskline;
}
else
{
regval &= ~maskline;
}
/* Store falling trigger mode */
*regaddr = regval;
/* Configure gpio port selection in case of gpio exti line */
if ((pExtiConfig->Line & EXTI_GPIO) == EXTI_GPIO)
{
assert_param(IS_EXTI_GPIO_PORT(pExtiConfig->GPIOSel));
assert_param(IS_EXTI_GPIO_PIN(linepos));
regval = EXTI->EXTICR[(linepos >> 2U) & 0x03UL];
regval &= ~(EXTI_EXTICR1_EXTI0 << (EXTI_EXTICR1_EXTI1_Pos * (linepos & 0x03U)));
regval |= (pExtiConfig->GPIOSel << (EXTI_EXTICR1_EXTI1_Pos * (linepos & 0x03U)));
EXTI->EXTICR[(linepos >> 2U) & 0x03UL] = regval;
}
}
/* Configure interrupt mode : read current mode */
regaddr = (__IO uint32_t *)(&EXTI->IMR1 + (EXTI_MODE_OFFSET * offset));
regval = *regaddr;
/* Mask or set line */
if ((pExtiConfig->Mode & EXTI_MODE_INTERRUPT) != 0U)
{
regval |= maskline;
}
else
{
regval &= ~maskline;
}
/* Store interrupt mode */
*regaddr = regval;
/* Configure event mode : read current mode */
regaddr = (__IO uint32_t *)(&EXTI->EMR1 + (EXTI_MODE_OFFSET * offset));
regval = *regaddr;
/* Mask or set line */
if ((pExtiConfig->Mode & EXTI_MODE_EVENT) != 0U)
{
regval |= maskline;
}
else
{
regval &= ~maskline;
}
/* Store event mode */
*regaddr = regval;
return HAL_OK;
}
/**
* @brief Get configuration of a dedicated Exti line.
* @param hexti Exti handle.
* @param pExtiConfig Pointer on structure to store Exti configuration.
* @retval HAL Status.
*/
HAL_StatusTypeDef HAL_EXTI_GetConfigLine(const EXTI_HandleTypeDef *hexti, EXTI_ConfigTypeDef *pExtiConfig)
{
const __IO uint32_t *regaddr;
uint32_t regval;
uint32_t linepos;
uint32_t maskline;
uint32_t offset;
/* Check null pointer */
if ((hexti == NULL) || (pExtiConfig == NULL))
{
return HAL_ERROR;
}
/* Check the parameter */
assert_param(IS_EXTI_LINE(hexti->Line));
/* Store handle line number to configiguration structure */
pExtiConfig->Line = hexti->Line;
/* compute line register offset and line mask */
offset = ((pExtiConfig->Line & EXTI_REG_MASK) >> EXTI_REG_SHIFT);
linepos = (pExtiConfig->Line & EXTI_PIN_MASK);
maskline = (1UL << linepos);
/* 1] Get core mode : interrupt */
regaddr = (__IO uint32_t *)(&EXTI->IMR1 + (EXTI_MODE_OFFSET * offset));
regval = *regaddr;
/* Check if selected line is enable */
if ((regval & maskline) != 0U)
{
pExtiConfig->Mode = EXTI_MODE_INTERRUPT;
}
else
{
pExtiConfig->Mode = EXTI_MODE_NONE;
}
/* Get event mode */
regaddr = (__IO uint32_t *)(&EXTI->EMR1 + (EXTI_MODE_OFFSET * offset));
regval = *regaddr;
/* Check if selected line is enable */
if ((regval & maskline) != 0U)
{
pExtiConfig->Mode |= EXTI_MODE_EVENT;
}
/* 2] Get trigger for configurable lines : rising */
if ((pExtiConfig->Line & EXTI_CONFIG) != 0U)
{
regaddr = (__IO uint32_t *)(&EXTI->RTSR1 + (EXTI_CONFIG_OFFSET * offset));
regval = *regaddr;
/* Check if configuration of selected line is enable */
if ((regval & maskline) != 0U)
{
pExtiConfig->Trigger = EXTI_TRIGGER_RISING;
}
else
{
pExtiConfig->Trigger = EXTI_TRIGGER_NONE;
}
/* Get falling configuration */
regaddr = (__IO uint32_t *)(&EXTI->FTSR1 + (EXTI_CONFIG_OFFSET * offset));
regval = *regaddr;
/* Check if configuration of selected line is enable */
if ((regval & maskline) != 0U)
{
pExtiConfig->Trigger |= EXTI_TRIGGER_FALLING;
}
/* Get Gpio port selection for gpio lines */
if ((pExtiConfig->Line & EXTI_GPIO) == EXTI_GPIO)
{
assert_param(IS_EXTI_GPIO_PIN(linepos));
regval = EXTI->EXTICR[(linepos >> 2U) & 0x03UL];
pExtiConfig->GPIOSel = (regval >> (EXTI_EXTICR1_EXTI1_Pos * (linepos & 0x03U))) & EXTI_EXTICR1_EXTI0;
}
else
{
pExtiConfig->GPIOSel = 0U;
}
}
else
{
pExtiConfig->Trigger = EXTI_TRIGGER_NONE;
pExtiConfig->GPIOSel = 0U;
}
return HAL_OK;
}
/**
* @brief Clear whole configuration of a dedicated Exti line.
* @param hexti Exti handle.
* @retval HAL Status.
*/
HAL_StatusTypeDef HAL_EXTI_ClearConfigLine(const EXTI_HandleTypeDef *hexti)
{
__IO uint32_t *regaddr;
uint32_t regval;
uint32_t linepos;
uint32_t maskline;
uint32_t offset;
/* Check null pointer */
if (hexti == NULL)
{
return HAL_ERROR;
}
/* Check the parameter */
assert_param(IS_EXTI_LINE(hexti->Line));
/* compute line register offset and line mask */
offset = ((hexti->Line & EXTI_REG_MASK) >> EXTI_REG_SHIFT);
linepos = (hexti->Line & EXTI_PIN_MASK);
maskline = (1UL << linepos);
/* 1] Clear interrupt mode */
regaddr = (__IO uint32_t *)(&EXTI->IMR1 + (EXTI_MODE_OFFSET * offset));
regval = (*regaddr & ~maskline);
*regaddr = regval;
/* 2] Clear event mode */
regaddr = (__IO uint32_t *)(&EXTI->EMR1 + (EXTI_MODE_OFFSET * offset));
regval = (*regaddr & ~maskline);
*regaddr = regval;
/* 3] Clear triggers in case of configurable lines */
if ((hexti->Line & EXTI_CONFIG) != 0U)
{
regaddr = (__IO uint32_t *)(&EXTI->RTSR1 + (EXTI_CONFIG_OFFSET * offset));
regval = (*regaddr & ~maskline);
*regaddr = regval;
regaddr = (__IO uint32_t *)(&EXTI->FTSR1 + (EXTI_CONFIG_OFFSET * offset));
regval = (*regaddr & ~maskline);
*regaddr = regval;
/* Get Gpio port selection for gpio lines */
if ((hexti->Line & EXTI_GPIO) == EXTI_GPIO)
{
assert_param(IS_EXTI_GPIO_PIN(linepos));
regval = EXTI->EXTICR[(linepos >> 2U) & 0x03UL];
regval &= ~(EXTI_EXTICR1_EXTI0 << (EXTI_EXTICR1_EXTI1_Pos * (linepos & 0x03U)));
EXTI->EXTICR[(linepos >> 2U) & 0x03UL] = regval;
}
}
return HAL_OK;
}
/**
* @brief Register callback for a dedicaated Exti line.
* @param hexti Exti handle.
* @param CallbackID User callback identifier.
* This parameter can be one of @arg @ref EXTI_CallbackIDTypeDef values.
* @param pPendingCbfn function pointer to be stored as callback.
* @retval HAL Status.
*/
HAL_StatusTypeDef HAL_EXTI_RegisterCallback(EXTI_HandleTypeDef *hexti,
EXTI_CallbackIDTypeDef CallbackID,
void (*pPendingCbfn)(void))
{
HAL_StatusTypeDef status = HAL_OK;
switch (CallbackID)
{
case HAL_EXTI_COMMON_CB_ID:
hexti->RisingCallback = pPendingCbfn;
hexti->FallingCallback = pPendingCbfn;
break;
case HAL_EXTI_RISING_CB_ID:
hexti->RisingCallback = pPendingCbfn;
break;
case HAL_EXTI_FALLING_CB_ID:
hexti->FallingCallback = pPendingCbfn;
break;
default:
status = HAL_ERROR;
break;
}
return status;
}
/**
* @brief Store line number as handle private field.
* @param hexti Exti handle.
* @param ExtiLine Exti line number.
* This parameter can be from 0 to @ref EXTI_LINE_NB.
* @retval HAL Status.
*/
HAL_StatusTypeDef HAL_EXTI_GetHandle(EXTI_HandleTypeDef *hexti, uint32_t ExtiLine)
{
/* Check the parameters */
assert_param(IS_EXTI_LINE(ExtiLine));
/* Check null pointer */
if (hexti == NULL)
{
return HAL_ERROR;
}
else
{
/* Store line number as handle private field */
hexti->Line = ExtiLine;
return HAL_OK;
}
}
/**
* @}
*/
/** @addtogroup EXTI_Exported_Functions_Group2
* @brief EXTI IO functions.
*
@verbatim
===============================================================================
##### IO operation functions #####
===============================================================================
@endverbatim
* @{
*/
/**
* @brief Handle EXTI interrupt request.
* @param hexti Exti handle.
* @retval none.
*/
void HAL_EXTI_IRQHandler(const EXTI_HandleTypeDef *hexti)
{
__IO uint32_t *regaddr;
uint32_t regval;
uint32_t maskline;
uint32_t offset;
/* Compute line register offset and line mask */
offset = ((hexti->Line & EXTI_REG_MASK) >> EXTI_REG_SHIFT);
maskline = (1UL << (hexti->Line & EXTI_PIN_MASK));
/* Get rising edge pending bit */
regaddr = (__IO uint32_t *)(&EXTI->RPR1 + (EXTI_CONFIG_OFFSET * offset));
regval = (*regaddr & maskline);
if (regval != 0U)
{
/* Clear pending bit */
*regaddr = maskline;
/* Call rising callback */
if (hexti->RisingCallback != NULL)
{
hexti->RisingCallback();
}
}
/* Get falling edge pending bit */
regaddr = (__IO uint32_t *)(&EXTI->FPR1 + (EXTI_CONFIG_OFFSET * offset));
regval = (*regaddr & maskline);
if (regval != 0U)
{
/* Clear pending bit */
*regaddr = maskline;
/* Call rising callback */
if (hexti->FallingCallback != NULL)
{
hexti->FallingCallback();
}
}
}
/**
* @brief Get interrupt pending bit of a dedicated line.
* @param hexti Exti handle.
* @param Edge Specify which pending edge as to be checked.
* This parameter can be one of the following values:
* @arg @ref EXTI_TRIGGER_RISING
* @arg @ref EXTI_TRIGGER_FALLING
* @retval 1 if interrupt is pending else 0.
*/
uint32_t HAL_EXTI_GetPending(const EXTI_HandleTypeDef *hexti, uint32_t Edge)
{
const __IO uint32_t *regaddr;
uint32_t regval;
uint32_t linepos;
uint32_t maskline;
uint32_t offset;
/* Check the parameters */
assert_param(IS_EXTI_LINE(hexti->Line));
assert_param(IS_EXTI_CONFIG_LINE(hexti->Line));
assert_param(IS_EXTI_PENDING_EDGE(Edge));
/* compute line register offset and line mask */
offset = ((hexti->Line & EXTI_REG_MASK) >> EXTI_REG_SHIFT);
linepos = (hexti->Line & EXTI_PIN_MASK);
maskline = (1UL << linepos);
if (Edge != EXTI_TRIGGER_RISING)
{
/* Get falling edge pending bit */
regaddr = (__IO uint32_t *)(&EXTI->FPR1 + (EXTI_CONFIG_OFFSET * offset));
}
else
{
/* Get rising edge pending bit */
regaddr = (__IO uint32_t *)(&EXTI->RPR1 + (EXTI_CONFIG_OFFSET * offset));
}
/* return 1 if bit is set else 0 */
regval = ((*regaddr & maskline) >> linepos);
return regval;
}
/**
* @brief Clear interrupt pending bit of a dedicated line.
* @param hexti Exti handle.
* @param Edge Specify which pending edge as to be clear.
* This parameter can be one of the following values:
* @arg @ref EXTI_TRIGGER_RISING
* @arg @ref EXTI_TRIGGER_FALLING
* @retval None.
*/
void HAL_EXTI_ClearPending(const EXTI_HandleTypeDef *hexti, uint32_t Edge)
{
__IO uint32_t *regaddr;
uint32_t maskline;
uint32_t offset;
/* Check the parameters */
assert_param(IS_EXTI_LINE(hexti->Line));
assert_param(IS_EXTI_CONFIG_LINE(hexti->Line));
assert_param(IS_EXTI_PENDING_EDGE(Edge));
/* compute line register offset and line mask */
offset = ((hexti->Line & EXTI_REG_MASK) >> EXTI_REG_SHIFT);
maskline = (1UL << (hexti->Line & EXTI_PIN_MASK));
if (Edge != EXTI_TRIGGER_RISING)
{
/* Get falling edge pending register address */
regaddr = (__IO uint32_t *)(&EXTI->FPR1 + (EXTI_CONFIG_OFFSET * offset));
}
else
{
/* Get falling edge pending register address */
regaddr = (__IO uint32_t *)(&EXTI->RPR1 + (EXTI_CONFIG_OFFSET * offset));
}
/* Clear Pending bit */
*regaddr = maskline;
}
/**
* @brief Generate a software interrupt for a dedicated line.
* @param hexti Exti handle.
* @retval None.
*/
void HAL_EXTI_GenerateSWI(const EXTI_HandleTypeDef *hexti)
{
__IO uint32_t *regaddr;
uint32_t maskline;
uint32_t offset;
/* Check the parameters */
assert_param(IS_EXTI_LINE(hexti->Line));
assert_param(IS_EXTI_CONFIG_LINE(hexti->Line));
/* compute line register offset and line mask */
offset = ((hexti->Line & EXTI_REG_MASK) >> EXTI_REG_SHIFT);
maskline = (1UL << (hexti->Line & EXTI_PIN_MASK));
regaddr = (__IO uint32_t *)(&EXTI->SWIER1 + (EXTI_CONFIG_OFFSET * offset));
*regaddr = maskline;
}
/**
* @}
*/
/** @defgroup EXTI_Exported_Functions_Group3 EXTI line attributes management functions
* @brief EXTI attributes management functions.
*
@verbatim
===============================================================================
##### EXTI attributes functions #####
===============================================================================
@endverbatim
* @{
*/
/**
* @brief Configure the EXTI line attribute(s).
* @note Available attributes are to secure EXTI line and set EXT line as privileged.
* Default state is not secure and unprivileged access allowed.
* @note Secure and non-secure attributes can only be set from the secure
* state when the system implements the security (TZEN=1).
* @note Security and privilege attributes can be set independently.
* @param ExtiLine Exti line number.
* This parameter can be from 0 to @ref EXTI_LINE_NB.
* @param LineAttributes can be one or a combination of the following values:
* @arg @ref EXTI_LINE_PRIV Privileged-only access
* @arg @ref EXTI_LINE_NPRIV Privileged/Non-privileged access
* @arg @ref EXTI_LINE_SEC Secure-only access
* @arg @ref EXTI_LINE_NSEC Secure/Non-secure access
* @retval None
*/
void HAL_EXTI_ConfigLineAttributes(uint32_t ExtiLine, uint32_t LineAttributes)
{
__IO uint32_t *regaddr;
uint32_t regval;
uint32_t linepos;
uint32_t maskline;
uint32_t offset;
/* Check the parameters */
assert_param(IS_EXTI_LINE(ExtiLine));
assert_param(IS_EXTI_LINE_ATTRIBUTES(LineAttributes));
/* compute line register offset and line mask */
offset = ((ExtiLine & EXTI_REG_MASK) >> EXTI_REG_SHIFT);
linepos = (ExtiLine & EXTI_PIN_MASK);
maskline = (1UL << linepos);
/* Configure privilege or non-privilege attributes */
regaddr = (__IO uint32_t *)(&EXTI->PRIVCFGR1 + (EXTI_PRIVCFGR_OFFSET * offset));
regval = *regaddr;
/* Mask or set line */
if ((LineAttributes & EXTI_LINE_PRIV) == EXTI_LINE_PRIV)
{
regval |= maskline;
}
else if ((LineAttributes & EXTI_LINE_NPRIV) == EXTI_LINE_NPRIV)
{
regval &= ~maskline;
}
else
{
/* do nothing */
}
/* Store privilege or non-privilege attribute */
*regaddr = regval;
#if defined (CPU_IN_SECURE_STATE)
/* Configure secure or non-secure attributes */
regaddr = (uint32_t *)(&EXTI->SECCFGR1 + (EXTI_SECCFGR_OFFSET * offset));
regval = *regaddr;
/* Mask or set line */
if ((LineAttributes & EXTI_LINE_SEC) == EXTI_LINE_SEC)
{
regval |= maskline;
}
else if ((LineAttributes & EXTI_LINE_NSEC) == EXTI_LINE_NSEC)
{
regval &= ~maskline;
}
else
{
/* do nothing */
}
/* Store secure or non-secure attribute */
*regaddr = regval;
#endif /* CPU_IN_SECURE_STATE */
}
/**
* @brief Get the EXTI line attribute(s).
* @note Secure and non-secure attributes are only available from secure state
* when the system implements the security (TZEN=1)
* @param ExtiLine Exti line number.
* This parameter can be from 0 to @ref EXTI_LINE_NB.
* @param pLineAttributes: pointer to return line attributes.
* @retval HAL Status.
*/
HAL_StatusTypeDef HAL_EXTI_GetConfigLineAttributes(uint32_t ExtiLine, uint32_t *pLineAttributes)
{
const __IO uint32_t *regaddr;
uint32_t linepos;
uint32_t maskline;
uint32_t offset;
uint32_t attributes;
/* Check null pointer */
if (pLineAttributes == NULL)
{
return HAL_ERROR;
}
/* Check the parameters */
assert_param(IS_EXTI_LINE(ExtiLine));
/* Compute line register offset and line mask */
offset = ((ExtiLine & EXTI_REG_MASK) >> EXTI_REG_SHIFT);
linepos = (ExtiLine & EXTI_PIN_MASK);
maskline = (1UL << linepos);
/* Get privilege or non-privilege attribute */
regaddr = (__IO uint32_t *)(&EXTI->PRIVCFGR1 + (EXTI_PRIVCFGR_OFFSET * offset));
if ((*regaddr & maskline) != 0U)
{
attributes = EXTI_LINE_PRIV;
}
else
{
attributes = EXTI_LINE_NPRIV;
}
/* Get secure or non-secure attribute */
regaddr = (__IO uint32_t *)(&EXTI->SECCFGR1 + (EXTI_SECCFGR_OFFSET * offset));
if ((*regaddr & maskline) != 0U)
{
attributes |= EXTI_LINE_SEC;
}
else
{
attributes |= EXTI_LINE_NSEC;
}
/* return value */
*pLineAttributes = attributes;
return HAL_OK;
}
#if defined (CPU_IN_SECURE_STATE)
/**
* @brief Lock the secure and privilege configuration registers.
* @note Once security and privilege configuration locked, it can no longer be modified
* until next system reset
* @retval None
*/
void HAL_EXTI_LockAttributes(void)
{
SET_BIT(EXTI->LOCKR, EXTI_LOCKR_LOCK);
}
/**
* @brief Return the secure and privilege configuration registers LOCK status
* @retval 1 if the secure and privilege configuration registers have been locked else 0.
*/
uint32_t HAL_EXTI_GetLockAttributes(void)
{
return READ_BIT(EXTI->LOCKR, EXTI_LOCKR_LOCK);
}
#endif /* CPU_IN_SECURE_STATE */
/**
* @}
*/
/**
* @}
*/
#endif /* HAL_EXTI_MODULE_ENABLED */
/**
* @}
*/
/**
* @}
*/

806
Software/Station_SW/Drivers/STM32U3xx_HAL_Driver/Src/stm32u3xx_hal_flash.c Normal file
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/**
******************************************************************************
* @file stm32u3xx_hal_flash.c
* @author MCD Application Team
* @brief FLASH HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of the internal FLASH memory:
* + Program operations functions
* + Memory Control functions
* + Peripheral Errors functions
*
******************************************************************************
* @attention
*
* Copyright (c) 2023 STMicroelectronics.
* All rights reserved.
*
* This software is licensed under terms that can be found in the LICENSE file
* in the root directory of this software component.
* If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
@verbatim
==============================================================================
##### Flash peripheral features #####
==============================================================================
[..] The Flash memory interface manages CPU AHB C-Bus accesses to the Flash memory.
It implements the erase and program Flash memory operations and the read
and write protection mechanisms.
[..] The Flash memory interface implements the TrustZone security features (TZ) supported
by ARM Cortex-M33 core (CM33).
[..] The FLASH main features are:
(+) Flash memory read operations
(+) Flash memory program/erase operations
(+) Read / write protections
(+) Option bytes programming
(+) TrustZone aware
(+) Watermark-based area protection including the secure hide area
(+) Block-based page protection
(+) Error code correction (ECC) : Data in flash are 72-bits word
(8 bits added per double-word)
##### How to use this driver #####
==============================================================================
[..]
This driver provides functions and macros to configure and program the FLASH
memory of all STM32U3xx devices.
(#) Flash Memory IO Programming functions:
(++) Lock and Unlock the FLASH interface using HAL_FLASH_Unlock() and
HAL_FLASH_Lock() functions
(++) Program functions: double-words and burst program (16 double-words)
(++) There are two modes of programming:
(+++) Polling mode using HAL_FLASH_Program() function
(+++) Interrupt mode using HAL_FLASH_Program_IT() function
(#) Interrupts and flags management functions:
(++) Handle FLASH interrupts by calling HAL_FLASH_IRQHandler()
(++) Callback functions are called when the flash operations are finished :
HAL_FLASH_EndOfOperationCallback() when everything is ok, otherwise
HAL_FLASH_OperationErrorCallback()
(++) Get error flag status by calling HAL_GetError()
(#) Option bytes management functions :
(++) Lock and Unlock the option bytes using HAL_FLASH_OB_Unlock() and
HAL_FLASH_OB_Lock() functions
(++) Launch the reload of the option bytes using HAL_FLASH_OB_Launch() function.
In this case, a reset is generated
[..]
In addition to these functions, this driver includes a set of macros allowing
to handle the following operations:
(+) Set the latency
(+) Enable/Disable the Flash power-down during low-power run and sleep modes
(+) Enable/Disable the Flash interrupts
(+) Monitor the Flash flags status
@endverbatim
******************************************************************************
*/
/* Includes ------------------------------------------------------------------*/
#include "stm32u3xx_hal.h"
/** @addtogroup STM32U3xx_HAL_Driver
* @{
*/
/** @defgroup FLASH FLASH
* @brief FLASH HAL module driver
* @{
*/
#ifdef HAL_FLASH_MODULE_ENABLED
/* Private typedef -----------------------------------------------------------*/
/* Private defines -----------------------------------------------------------*/
/** @addtogroup FLASH_Private_Constants
* @{
*/
#define FLASH_NB_WORDS_IN_BURST 32
/**
* @}
*/
/* Private macros ------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/** @defgroup FLASH_Private_Variables FLASH Private Variables
* @{
*/
/**
* @brief Variable used for Program/Erase sectors under interruption
*/
FLASH_ProcessTypeDef pFlash = {.Lock = HAL_UNLOCKED, \
.ErrorCode = HAL_FLASH_ERROR_NONE, \
.ProcedureOnGoing = 0U, \
.Address = 0U, \
.Page = 0U, \
.NbPagesToErase = 0U
};
/**
* @}
*/
/* Private function prototypes -----------------------------------------------*/
/** @defgroup FLASH_Private_Functions FLASH Private Functions
* @{
*/
static void FLASH_Program_DoubleWord(uint32_t Address, uint32_t DataAddress);
static void FLASH_Program_Burst(uint32_t Address, uint32_t DataAddress);
/**
* @}
*/
/* Exported functions --------------------------------------------------------*/
/** @defgroup FLASH_Exported_Functions FLASH Exported Functions
* @{
*/
/** @defgroup FLASH_Exported_Functions_Group1 Programming operation functions
* @brief Programming operation functions
*
@verbatim
===============================================================================
##### Programming operation functions #####
===============================================================================
[..]
This subsection provides a set of functions allowing to manage the FLASH
program operations.
@endverbatim
* @{
*/
/**
* @brief Program a double-word or a burst of 16 double-words at a specified address.
*
* @param TypeProgram Indicate the way to program at a specified address
* This parameter can be a value of @ref FLASH_Type_Program
* @param Address Specifies the address to be programmed.
* This parameter shall be aligned to the Flash word (64 bits)
* @param DataAddress Specifies the address of data to be programmed.
* This parameter shall be 32-bit aligned
*
* @retval HAL_StatusTypeDef HAL Status
*/
HAL_StatusTypeDef HAL_FLASH_Program(uint32_t TypeProgram, uint32_t Address, uint32_t DataAddress)
{
HAL_StatusTypeDef status;
__IO uint32_t *reg_cr;
/* Check the parameters */
assert_param(IS_FLASH_TYPEPROGRAM(TypeProgram));
/* Process Locked */
__HAL_LOCK(&pFlash);
/* Reset error code */
pFlash.ErrorCode = HAL_FLASH_ERROR_NONE;
/* Verify that next operation can be proceed */
status = FLASH_WaitForLastOperation(FLASH_TIMEOUT_VALUE);
if (status == HAL_OK)
{
/* Set current operation type */
pFlash.ProcedureOnGoing = TypeProgram;
/* Access to SCR or CR depends on operation type */
reg_cr = (IS_FLASH_SECURE_OPERATION() != 0U) ? &(FLASH->SCR) : &(FLASH_NS->CR);
if ((TypeProgram & (~FLASH_NON_SECURE_MASK)) == FLASH_TYPEPROGRAM_DOUBLEWORD)
{
/* Program a double-word (64-bit) at a specified address */
FLASH_Program_DoubleWord(Address, DataAddress);
}
else
{
/* Program a burst of 16 double-words at a specified address */
FLASH_Program_Burst(Address, DataAddress);
}
/* Wait for last operation to be completed */
status = FLASH_WaitForLastOperation(FLASH_TIMEOUT_VALUE);
/* If the program operation is completed, disable the PG (and BWR Bit in Burst programming mode) */
CLEAR_BIT((*reg_cr), (TypeProgram & ~(FLASH_NON_SECURE_MASK)));
}
/* Process Unlocked */
__HAL_UNLOCK(&pFlash);
/* return status */
return status;
}
/**
* @brief Program a double-word or a burst of 16 double-words at a specified address with interrupt enabled.
*
* @param TypeProgram Indicate the way to program at a specified address.
* This parameter can be a value of @ref FLASH_Type_Program
* @param Address Specifies the address to be programmed.
* This parameter shall be aligned to the Flash word (64 bits)
* @param DataAddress Specifies the address of data to be programmed.
* This parameter shall be 32-bit aligned
*
* @retval HAL Status
*/
HAL_StatusTypeDef HAL_FLASH_Program_IT(uint32_t TypeProgram, uint32_t Address, uint32_t DataAddress)
{
HAL_StatusTypeDef status;
__IO uint32_t *reg_cr;
/* Check the parameters */
assert_param(IS_FLASH_TYPEPROGRAM(TypeProgram));
assert_param(IS_FLASH_PROGRAM_ADDRESS(Address));
/* Process Locked */
__HAL_LOCK(&pFlash);
/* Reset error code */
pFlash.ErrorCode = HAL_FLASH_ERROR_NONE;
/* Verify that next operation can be proceed */
status = FLASH_WaitForLastOperation(FLASH_TIMEOUT_VALUE);
if (status != HAL_OK)
{
/* Process Unlocked */
__HAL_UNLOCK(&pFlash);
}
else
{
/* Set internal variables used by the IRQ handler */
pFlash.ProcedureOnGoing = TypeProgram;
pFlash.Address = Address;
/* Access to SCR or CR depends on operation type */
reg_cr = (IS_FLASH_SECURE_OPERATION() != 0U) ? &(FLASH->SCR) : &(FLASH_NS->CR);
/* Enable End of Operation and Error interrupts */
(*reg_cr) |= (FLASH_IT_EOP | FLASH_IT_OPERR);
if ((TypeProgram & (~FLASH_NON_SECURE_MASK)) == FLASH_TYPEPROGRAM_DOUBLEWORD)
{
/* Program a double-word (64-bit) at a specified address */
FLASH_Program_DoubleWord(Address, DataAddress);
}
else
{
/* Program a burst of 16 double-words at a specified address */
FLASH_Program_Burst(Address, DataAddress);
}
}
/* return status */
return status;
}
/**
* @brief Handle FLASH interrupt request.
*
* @retval None
*/
void HAL_FLASH_IRQHandler(void)
{
uint32_t param = 0U;
uint32_t error;
__IO uint32_t *reg_cr;
__IO uint32_t *reg_sr;
uint32_t type;
type = (pFlash.ProcedureOnGoing & ~(FLASH_NON_SECURE_MASK));
/* Access to CR and SR registers depends on operation type */
reg_cr = (IS_FLASH_SECURE_OPERATION() != 0U) ? &(FLASH->SCR) : &(FLASH_NS->CR);
reg_sr = (IS_FLASH_SECURE_OPERATION() != 0U) ? &(FLASH->SSR) : &(FLASH_NS->SR);
/* Save Flash errors */
error = (*reg_sr) & FLASH_FLAG_SR_ERRORS;
#if defined (CPU_IN_SECURE_STATE)
error |= (FLASH->SR & FLASH_FLAG_OPTWERR);
#endif /* CPU_IN_SECURE_STATE */
/* Set parameter of the callback */
if (type == FLASH_TYPEERASE_PAGES)
{
param = pFlash.Page;
}
else if (type == FLASH_TYPEERASE_MASSERASE)
{
param = pFlash.Bank;
}
else if (type == FLASH_TYPEPROGRAM_DOUBLEWORD)
{
param = pFlash.Address;
}
else if (type == FLASH_TYPEPROGRAM_BURST)
{
param = pFlash.Address;
}
else
{
/* Empty statement (to be compliant MISRA 15.7) */
}
/* Clear operation bit on the on-going procedure */
CLEAR_BIT((*reg_cr), (type | FLASH_CR_BKER | FLASH_CR_PNB));
/* Check FLASH operation error flags */
if (error != 0U)
{
/* Save the error code */
pFlash.ErrorCode |= error;
/* Clear error programming flags */
(*reg_sr) = error;
#if defined (CPU_IN_SECURE_STATE)
if ((error & FLASH_FLAG_OPTWERR) != 0U)
{
FLASH->SR = FLASH_FLAG_OPTWERR;
}
#endif /* CPU_IN_SECURE_STATE */
/* Stop the procedure ongoing */
pFlash.ProcedureOnGoing = 0U;
/* FLASH error interrupt user callback */
HAL_FLASH_OperationErrorCallback(param);
}
/* Check FLASH End of Operation flag */
if (((*reg_sr) & FLASH_FLAG_EOP) != 0U)
{
/* Clear FLASH End of Operation pending bit */
(*reg_sr) = FLASH_FLAG_EOP;
if (type == FLASH_TYPEERASE_PAGES)
{
/* Nb of pages to erase can be decreased */
pFlash.NbPagesToErase--;
/* Check if there are still pages to erase */
if (pFlash.NbPagesToErase != 0U)
{
/* Increment page number */
pFlash.Page++;
FLASH_PageErase(pFlash.Page, pFlash.Bank);
}
else
{
/* No more pages to Erase */
pFlash.ProcedureOnGoing = 0U;
param = 0xFFFFFFFFU;
}
}
else
{
/*Clear the procedure ongoing*/
pFlash.ProcedureOnGoing = 0U;
}
/* FLASH EOP interrupt user callback */
HAL_FLASH_EndOfOperationCallback(param);
}
if (pFlash.ProcedureOnGoing == 0U)
{
/* Disable End of Operation and Error interrupts */
(*reg_cr) &= ~(FLASH_IT_EOP | FLASH_IT_OPERR);
/* Process Unlocked */
__HAL_UNLOCK(&pFlash);
}
/* Check ECC Correction Error */
if ((FLASH->ECCCR & (FLASH_IT_ECCC | FLASH_FLAG_ECCC)) == (FLASH_IT_ECCC | FLASH_FLAG_ECCC))
{
/* Call User callback */
HAL_FLASHEx_EccCorrectionCallback();
/* Clear ECC correction flag in order to allow new ECC error record */
SET_BIT(FLASH->ECCCR, FLASH_ECCCR_ECCC);
}
}
/**
* @brief FLASH end of operation interrupt callback.
*
* @param ReturnValue The value saved in this parameter depends on the ongoing procedure :
* @arg Mass Erase: 0
* @arg Page Erase: Page which has been erased
* (if 0xFFFFFFFF, it means that all the selected pages have been erased)
* @arg Program: Address which was selected for data program
*
* @retval None
*/
__weak void HAL_FLASH_EndOfOperationCallback(uint32_t ReturnValue)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(ReturnValue);
/* NOTE : This function should not be modified, when the callback is needed,
the HAL_FLASH_EndOfOperationCallback could be implemented in the user file
*/
}
/**
* @brief FLASH operation error interrupt callback.
*
* @param ReturnValue The value saved in this parameter depends on the ongoing procedure :
* @arg Mass Erase: 0
* @arg Page Erase: Page number which returned an error
* @arg Program: Address which was selected for data program
*
* @retval None
*/
__weak void HAL_FLASH_OperationErrorCallback(uint32_t ReturnValue)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(ReturnValue);
/* NOTE : This function should not be modified, when the callback is needed,
the HAL_FLASH_OperationErrorCallback could be implemented in the user file
*/
}
/**
* @}
*/
/** @defgroup FLASH_Exported_Functions_Group2 Peripheral Control functions
* @brief Management functions
*
@verbatim
===============================================================================
##### Peripheral Control functions #####
===============================================================================
[..]
This subsection provides a set of functions allowing to control the FLASH
memory operations.
@endverbatim
* @{
*/
/**
* @brief Unlock the FLASH control register access.
*
* @retval HAL Status
*/
HAL_StatusTypeDef HAL_FLASH_Unlock(void)
{
HAL_StatusTypeDef status = HAL_OK;
if (READ_BIT(FLASH->CR, FLASH_CR_LOCK) != 0U)
{
/* Authorize the FLASH Registers access */
WRITE_REG(FLASH->KEYR, FLASH_KEY1);
WRITE_REG(FLASH->KEYR, FLASH_KEY2);
/* verify Flash is unlocked */
if (READ_BIT(FLASH->CR, FLASH_CR_LOCK) != 0U)
{
status = HAL_ERROR;
}
}
#if defined (CPU_IN_SECURE_STATE)
if (status == HAL_OK)
{
if (READ_BIT(FLASH->SCR, FLASH_SCR_LOCK) != 0U)
{
/* Authorize the FLASH Registers access */
WRITE_REG(FLASH->SKEYR, FLASH_KEY1);
WRITE_REG(FLASH->SKEYR, FLASH_KEY2);
/* verify Flash is unlocked */
if (READ_BIT(FLASH->SCR, FLASH_SCR_LOCK) != 0U)
{
status = HAL_ERROR;
}
}
}
#endif /* CPU_IN_SECURE_STATE */
return status;
}
/**
* @brief Lock the FLASH control register access.
*
* @retval HAL Status
*/
HAL_StatusTypeDef HAL_FLASH_Lock(void)
{
HAL_StatusTypeDef status = HAL_ERROR;
/* Set the LOCK Bit to lock the FLASH Registers access */
SET_BIT(FLASH->CR, FLASH_CR_LOCK);
/* verify Flash is locked */
if (READ_BIT(FLASH->CR, FLASH_CR_LOCK) != 0U)
{
status = HAL_OK;
}
#if defined (CPU_IN_SECURE_STATE)
if (status == HAL_OK)
{
SET_BIT(FLASH->SCR, FLASH_SCR_LOCK);
/* verify Flash is locked */
if (READ_BIT(FLASH->SCR, FLASH_SCR_LOCK) != 0U)
{
status = HAL_OK;
}
}
#endif /* CPU_IN_SECURE_STATE */
return status;
}
/**
* @brief Unlock the FLASH Option Bytes Registers access.
*
* @retval HAL Status
*/
HAL_StatusTypeDef HAL_FLASH_OB_Unlock(void)
{
if (READ_BIT(FLASH->CR, FLASH_CR_OPTLOCK) != 0U)
{
/* Authorizes the Option Byte register programming */
WRITE_REG(FLASH->OPTKEYR, FLASH_OPTKEY1);
WRITE_REG(FLASH->OPTKEYR, FLASH_OPTKEY2);
/* Verify that the Option Bytes are unlocked */
if (READ_BIT(FLASH->CR, FLASH_CR_OPTLOCK) != 0U)
{
return HAL_ERROR;
}
}
return HAL_OK;
}
/**
* @brief Lock the FLASH Option Bytes Registers access.
*
* @retval HAL Status
*/
HAL_StatusTypeDef HAL_FLASH_OB_Lock(void)
{
/* Set the OPTLOCK Bit to lock the FLASH Option Byte Registers access */
SET_BIT(FLASH->CR, FLASH_CR_OPTLOCK);
/* Verify that the Option Bytes are locked */
if (READ_BIT(FLASH->CR, FLASH_CR_OPTLOCK) != 0U)
{
return HAL_OK;
}
return HAL_ERROR;
}
/**
* @brief Launch the option byte loading.
*
* @retval HAL Status
*/
HAL_StatusTypeDef HAL_FLASH_OB_Launch(void)
{
/* Set the bit to force the option byte reloading */
SET_BIT(FLASH->CR, FLASH_CR_OBL_LAUNCH);
/* We should not reach here : Option byte launch generates Option byte reset
so return error */
return HAL_ERROR;
}
/**
* @}
*/
/** @defgroup FLASH_Exported_Functions_Group3 Peripheral State and Errors functions
* @brief Peripheral Errors functions
*
@verbatim
===============================================================================
##### Peripheral Errors functions #####
===============================================================================
[..]
This subsection permits to get in run-time Errors of the FLASH peripheral.
@endverbatim
* @{
*/
/**
* @brief Get the specific FLASH error flag.
*
* @retval FLASH_ErrorCode The returned value can be
* @arg @ref HAL_FLASH_ERROR_NONE No error set
* @arg @ref HAL_FLASH_ERROR_OP FLASH Operation error
* @arg @ref HAL_FLASH_ERROR_PROG FLASH Programming error
* @arg @ref HAL_FLASH_ERROR_WRP FLASH Write protection error
* @arg @ref HAL_FLASH_ERROR_PGA FLASH Programming alignment error
* @arg @ref HAL_FLASH_ERROR_SIZ FLASH Size error
* @arg @ref HAL_FLASH_ERROR_PGS FLASH Programming sequence error
* @arg @ref HAL_FLASH_ERROR_OPTW FLASH Option modification error
*/
uint32_t HAL_FLASH_GetError(void)
{
return pFlash.ErrorCode;
}
/**
* @}
*/
/**
* @}
*/
/* Private functions ---------------------------------------------------------*/
/** @addtogroup FLASH_Private_Functions
* @{
*/
/**
* @brief Wait for a FLASH operation to complete.
* @param Timeout Maximum flash operation timeout
* @retval HAL_StatusTypeDef HAL Status
*/
HAL_StatusTypeDef FLASH_WaitForLastOperation(uint32_t Timeout)
{
/* Wait for the FLASH operation to complete by polling on BUSY and WDW flags to be reset.
Even if the FLASH operation fails, the BUSY & WDW flags will be reset, and an error flag will be set */
uint32_t timeout = HAL_GetTick();
uint32_t error;
__IO uint32_t *reg_sr;
/* Access to SECSR or NSSR registers depends on operation type */
reg_sr = (IS_FLASH_SECURE_OPERATION() != 0U) ? &(FLASH->SSR) : &(FLASH_NS->SR);
while (((*reg_sr) & (FLASH_FLAG_BSY | FLASH_FLAG_WDW)) != 0U)
{
if (Timeout != HAL_MAX_DELAY)
{
if ((HAL_GetTick() - timeout) >= Timeout)
{
return HAL_TIMEOUT;
}
}
}
/* Check FLASH operation error flags */
error = ((*reg_sr) & FLASH_FLAG_SR_ERRORS);
#if defined (CPU_IN_SECURE_STATE)
error |= (FLASH->SR & FLASH_FLAG_OPTWERR);
#endif /* CPU_IN_SECURE_STATE */
if (error != 0U)
{
/*Save the error code*/
pFlash.ErrorCode |= error;
/* Clear error programming flags */
(*reg_sr) = error;
#if defined (CPU_IN_SECURE_STATE)
if ((error & FLASH_FLAG_OPTWERR) != 0U)
{
FLASH->SR = FLASH_FLAG_OPTWERR;
}
#endif /* CPU_IN_SECURE_STATE */
return HAL_ERROR;
}
/* Check FLASH End of Operation flag */
if (((*reg_sr) & FLASH_FLAG_EOP) != 0U)
{
/* Clear FLASH End of Operation pending bit */
(*reg_sr) = FLASH_FLAG_EOP;
}
return HAL_OK;
}
/**
* @brief Program a double-word (64-bit) at a specified address.
* @param Address Specifies the address to be programmed.
* @param DataAddress Specifies the address of data to be programmed.
* @retval None
*/
static void FLASH_Program_DoubleWord(uint32_t Address, uint32_t DataAddress)
{
uint8_t index = 2;
uint32_t *dest_addr = (uint32_t *)Address;
uint32_t *src_addr = (uint32_t *)DataAddress;
uint32_t primask_bit;
__IO uint32_t *reg_cr;
/* Check the parameters */
assert_param(IS_FLASH_PROGRAM_ADDRESS(Address));
/* Access to SCR or CR registers depends on operation type */
reg_cr = (IS_FLASH_SECURE_OPERATION() != 0U) ? &(FLASH->SCR) : &(FLASH_NS->CR);
/* Set PG bit */
SET_BIT((*reg_cr), FLASH_CR_PG);
/* Enter critical section: Disable interrupts to avoid any interruption during the loop */
primask_bit = __get_PRIMASK();
__disable_irq();
/* Program the double-word */
do
{
*dest_addr = *src_addr;
dest_addr++;
src_addr++;
index--;
} while (index != 0U);
/* Exit critical section: restore previous priority mask */
__set_PRIMASK(primask_bit);
}
/**
* @brief Program a burst of 16x double-words at a specified address.
* @param Address Specifies the address to be programmed.
* @param DataAddress Specifies the address where the data are stored.
* @retval None
*/
static void FLASH_Program_Burst(uint32_t Address, uint32_t DataAddress)
{
uint8_t burst_index = FLASH_NB_WORDS_IN_BURST;
uint32_t *dest_addr = (uint32_t *)Address;
uint32_t *src_addr = (uint32_t *)DataAddress;
uint32_t primask_bit;
__IO uint32_t *reg_cr;
/* Check the parameters */
assert_param(IS_FLASH_MAIN_MEM_ADDRESS(Address));
/* Access to SCR or CR registers depends on operation type */
reg_cr = (IS_FLASH_SECURE_OPERATION() != 0U) ? &(FLASH->SCR) : &(FLASH_NS->CR);
/* Set PG and BWR bits */
SET_BIT((*reg_cr), (FLASH_CR_PG | FLASH_CR_BWR));
/* Enter critical section: Disable interrupts to avoid any interruption during the loop */
primask_bit = __get_PRIMASK();
__disable_irq();
/* Program the burst */
do
{
*dest_addr = *src_addr;
dest_addr++;
src_addr++;
burst_index--;
} while (burst_index != 0U);
/* Exit critical section: restore previous priority mask */
__set_PRIMASK(primask_bit);
}
/**
* @}
*/
#endif /* HAL_FLASH_MODULE_ENABLED */
/**
* @}
*/
/**
* @}
*/

1964
Software/Station_SW/Drivers/STM32U3xx_HAL_Driver/Src/stm32u3xx_hal_flash_ex.c Normal file
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708
Software/Station_SW/Drivers/STM32U3xx_HAL_Driver/Src/stm32u3xx_hal_gpio.c Normal file
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/**
******************************************************************************
* @file stm32u3xx_hal_gpio.c
* @author GPM Application Team
* @brief GPIO HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of the General Purpose Input/Output (GPIO) peripheral:
* + Initialization and de-initialization functions
* + IO operation functions
*
******************************************************************************
* @attention
*
* Copyright (c) 2023 STMicroelectronics.
* All rights reserved.
*
* This software is licensed under terms that can be found in the LICENSE file
* in the root directory of this software component.
* If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
@verbatim
==============================================================================
##### GPIO Peripheral features #####
==============================================================================
[..]
(+) Each port bit of the general-purpose I/O (GPIO) ports can be individually
configured by software in several modes:
(++) Input mode
(++) Analog mode
(++) Output mode
(++) Alternate function mode
(++) External interrupt/event lines
(+) During and just after reset, the alternate functions and external interrupt
lines are not active and the I/O ports are configured in analog mode.
(+) All GPIO pins have weak internal pull-up and pull-down resistors, which can be
activated or not.
(+) In Output or Alternate mode, each IO can be configured on open-drain or push-pull
type and the IO speed can be selected depending on the VDD value.
(+) The microcontroller IO pins are connected to onboard peripherals/modules through a
multiplexer that allows only one peripheral alternate function (AF) connected
to an IO pin at a time. In this way, there can be no conflict between peripherals
sharing the same IO pin.
(+) All ports have external interrupt/event capability. To use external interrupt
lines, the port must be configured in input mode. All available GPIO pins are
connected to the 16 external interrupt/event lines from EXTI0 to EXTI15.
(+) The external interrupt/event controller consists of up to 23 edge detectors
(16 lines are connected to GPIO) for generating event/interrupt requests (each
input line can be independently configured to select the type (interrupt or event)
and the corresponding trigger event (rising or falling or both). Each line can
also be masked independently.
##### How to use this driver #####
==============================================================================
[..]
(#) Enable the GPIO AHB clock using the following function: __HAL_RCC_GPIOx_CLK_ENABLE().
(#) Configure the GPIO pin(s) using HAL_GPIO_Init().
(++) Configure the IO mode using "Mode" member from GPIO_InitTypeDef structure
(++) Activate Pull-up, Pull-down resistor using "Pull" member from GPIO_InitTypeDef
structure.
(++) In case of Output or alternate function mode selection: the speed is
configured through "Speed" member from GPIO_InitTypeDef structure.
(++) In alternate mode is selection, the alternate function connected to the IO
is configured through "Alternate" member from GPIO_InitTypeDef structure.
(++) Analog mode is required when a pin is to be used as ADC channel
or DAC output.
(++) In case of external interrupt/event selection the "Mode" member from
GPIO_InitTypeDef structure select the type (interrupt or event) and
the corresponding trigger event (rising or falling or both).
(#) In case of external interrupt/event mode selection, configure NVIC IRQ priority
mapped to the EXTI line using HAL_NVIC_SetPriority() and enable it using
HAL_NVIC_EnableIRQ().
(#) To get the level of a pin configured in input mode use HAL_GPIO_ReadPin().
(#) To set/reset the level of a pin configured in output mode use
HAL_GPIO_WritePin()/HAL_GPIO_TogglePin().
(#) To set the level of several pins and reset level of several other pins in
same cycle, use HAL_GPIO_WriteMultipleStatePin().
(#) To lock pin configuration until next reset use HAL_GPIO_LockPin().
(#) During and just after reset, the alternate functions are not
active and the GPIO pins are configured in analog mode (except JTAG
pins).
(#) The LSE oscillator pins OSC32_IN and OSC32_OUT can be used as general purpose
(PC14 and PC15, respectively) when the LSE oscillator is off. The LSE has
priority over the GPIO function.
(#) The HSE oscillator pins OSC_IN/OSC_OUT can be used as
general purpose PH0 and PH1, respectively, when the HSE oscillator is off.
The HSE has priority over the GPIO function.
@endverbatim
*/
/* Includes ------------------------------------------------------------------*/
#include "stm32u3xx_hal.h"
/** @addtogroup STM32U3xx_HAL_Driver
* @{
*/
/** @addtogroup GPIO
* @{
*/
/** MISRA C:2012 deviation rule has been granted for following rules:
* Rule-12.2 - Medium: RHS argument is in interval [0,INF] which is out of
* range of the shift operator in following API :
* HAL_GPIO_Init
* HAL_GPIO_DeInit
*/
#ifdef HAL_GPIO_MODULE_ENABLED
/* Private typedef -----------------------------------------------------------*/
/* Private defines ------------------------------------------------------------*/
/** @addtogroup GPIO_Private_Constants
* @{
*/
#define GPIO_NUMBER (16U)
/**
* @}
*/
/* Private macros ------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private function prototypes -----------------------------------------------*/
/* Exported functions --------------------------------------------------------*/
/** @addtogroup GPIO_Exported_Functions
* @{
*/
/** @addtogroup GPIO_Exported_Functions_Group1
* @brief Initialization and Configuration functions
*
@verbatim
===============================================================================
##### Initialization and de-initialization functions #####
===============================================================================
@endverbatim
* @{
*/
/**
* @brief Initialize the GPIOx peripheral according to the specified parameters in the GPIO_Init.
* @note If GPIOx peripheral pin is used in EXTI_MODE and the pin is secure/privilege, it is up
* to the application to insure that the corresponding EXTI line is set secure/privilege.
* insure that the corresponding EXTI line is set secure.
* @param GPIOx where x can be (A..E, G, H).
* @param GPIO_Init pointer to a GPIO_InitTypeDef structure that contains
* the configuration information for the specified GPIO peripheral.
* @retval None
*/
void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, const GPIO_InitTypeDef *GPIO_Init)
{
uint32_t position = 0x00U;
uint32_t iocurrent;
uint32_t temp;
/* Check the parameters */
assert_param(IS_GPIO_ALL_INSTANCE(GPIOx));
assert_param(IS_GPIO_PIN(GPIO_Init->Pin));
assert_param(IS_GPIO_MODE(GPIO_Init->Mode));
/* Configure the port pins */
while (((GPIO_Init->Pin) >> position) != 0x00U)
{
/* Get current io position */
iocurrent = (GPIO_Init->Pin) & (1UL << position);
if (iocurrent != 0x00U)
{
/*--------------------- GPIO Mode Configuration ------------------------*/
/* In case of Output or Alternate function mode selection */
if (((GPIO_Init->Mode & GPIO_MODE) == MODE_OUTPUT) || ((GPIO_Init->Mode & GPIO_MODE) == MODE_AF))
{
/* Check the Speed parameter */
assert_param(IS_GPIO_SPEED(GPIO_Init->Speed));
/* Configure the IO Speed */
temp = GPIOx->OSPEEDR;
temp &= ~(GPIO_OSPEEDR_OSPEED0 << (position * GPIO_OSPEEDR_OSPEED1_Pos));
temp |= (GPIO_Init->Speed << (position * GPIO_OSPEEDR_OSPEED1_Pos));
GPIOx->OSPEEDR = temp;
/* Configure the IO Output Type */
temp = GPIOx->OTYPER;
temp &= ~(GPIO_OTYPER_OT0 << position) ;
temp |= (((GPIO_Init->Mode & OUTPUT_TYPE) >> OUTPUT_TYPE_Pos) << position);
GPIOx->OTYPER = temp;
}
if (((GPIO_Init->Mode & GPIO_MODE) != MODE_ANALOG) ||
(((GPIO_Init->Mode & GPIO_MODE) == MODE_ANALOG) && (GPIO_Init->Pull != GPIO_PULLUP)))
{
/* Check the Pull parameter */
assert_param(IS_GPIO_PULL(GPIO_Init->Pull));
/* Activate the Pull-up or Pull down resistor for the current IO */
temp = GPIOx->PUPDR;
temp &= ~(GPIO_PUPDR_PUPD0 << (position * GPIO_PUPDR_PUPD1_Pos));
temp |= ((GPIO_Init->Pull) << (position * GPIO_PUPDR_PUPD1_Pos));
GPIOx->PUPDR = temp;
}
/* In case of Alternate function mode selection */
if ((GPIO_Init->Mode & GPIO_MODE) == MODE_AF)
{
/* Check the Alternate function parameters */
assert_param(IS_GPIO_AF_INSTANCE(GPIOx));
assert_param(IS_GPIO_AF(GPIO_Init->Alternate));
/* Configure Alternate function mapped with the current IO */
temp = GPIOx->AFR[position >> 3U];
temp &= ~(0xFu << ((position & 0x07U) * GPIO_AFRL_AFSEL1_Pos));
temp |= ((GPIO_Init->Alternate) << ((position & 0x07U) * GPIO_AFRL_AFSEL1_Pos));
GPIOx->AFR[position >> 3U] = temp;
}
/* Configure IO Direction mode (Input, Output, Alternate or Analog) */
temp = GPIOx->MODER;
temp &= ~(GPIO_MODER_MODE0 << (position * GPIO_MODER_MODE1_Pos));
temp |= ((GPIO_Init->Mode & GPIO_MODE) << (position * GPIO_MODER_MODE1_Pos));
GPIOx->MODER = temp;
/*--------------------- EXTI Mode Configuration ------------------------*/
/* Configure the External Interrupt or event for the current IO */
if ((GPIO_Init->Mode & EXTI_MODE) != 0x00U)
{
temp = EXTI->EXTICR[position >> 2U];
temp &= ~(0x0FuL << ((position & 0x03U) * EXTI_EXTICR1_EXTI1_Pos));
temp |= (GPIO_GET_INDEX(GPIOx) << ((position & 0x03U) * EXTI_EXTICR1_EXTI1_Pos));
EXTI->EXTICR[position >> 2U] = temp;
/* Clear EXTI line configuration */
temp = EXTI->IMR1;
temp &= ~(iocurrent);
if ((GPIO_Init->Mode & EXTI_IT) != 0x00U)
{
temp |= iocurrent;
}
EXTI->IMR1 = temp;
temp = EXTI->EMR1;
temp &= ~(iocurrent);
if ((GPIO_Init->Mode & EXTI_EVT) != 0x00U)
{
temp |= iocurrent;
}
EXTI->EMR1 = temp;
/* Clear Rising Falling edge configuration */
temp = EXTI->RTSR1;
temp &= ~(iocurrent);
if ((GPIO_Init->Mode & TRIGGER_RISING) != 0x00U)
{
temp |= iocurrent;
}
EXTI->RTSR1 = temp;
temp = EXTI->FTSR1;
temp &= ~(iocurrent);
if ((GPIO_Init->Mode & TRIGGER_FALLING) != 0x00U)
{
temp |= iocurrent;
}
EXTI->FTSR1 = temp;
}
}
position++;
}
}
/**
* @brief De-initialize the GPIOx peripheral registers to their default reset values.
* @param GPIOx where x can be (A..E, G, H).
* @param GPIO_Pin specifies the port bit to be written.
* This parameter can be any combination of GPIO_Pin_x where x can be (0..15).
* @retval None
*/
void HAL_GPIO_DeInit(GPIO_TypeDef *GPIOx, uint32_t GPIO_Pin)
{
uint32_t position = 0x00U;
uint32_t iocurrent;
uint32_t tmp;
/* Check the parameters */
assert_param(IS_GPIO_ALL_INSTANCE(GPIOx));
assert_param(IS_GPIO_PIN(GPIO_Pin));
/* Configure the port pins */
while ((GPIO_Pin >> position) != 0x00U)
{
/* Get current io position */
iocurrent = (GPIO_Pin) & (1UL << position);
if (iocurrent != 0x00U)
{
/*------------------------- EXTI Mode Configuration --------------------*/
/* Clear the External Interrupt or Event for the current IO */
tmp = EXTI->EXTICR[position >> 2U];
tmp &= (0x0FUL << ((position & 0x03U) * EXTI_EXTICR1_EXTI1_Pos));
if (tmp == (GPIO_GET_INDEX(GPIOx) << ((position & 0x03U) * EXTI_EXTICR1_EXTI1_Pos)))
{
/* Clear EXTI line configuration */
EXTI->IMR1 &= ~(iocurrent);
EXTI->EMR1 &= ~(iocurrent);
/* Clear Rising Falling edge configuration */
EXTI->RTSR1 &= ~(iocurrent);
EXTI->FTSR1 &= ~(iocurrent);
tmp = 0x0FuL << ((position & 0x03U) * EXTI_EXTICR1_EXTI1_Pos);
EXTI->EXTICR[position >> 2U] &= ~tmp;
}
/*------------------------- GPIO Mode Configuration --------------------*/
/* Configure IO in Analog Mode */
GPIOx->MODER |= (GPIO_MODER_MODE0 << (position * GPIO_MODER_MODE1_Pos));
/* Configure the default Alternate Function in current IO */
GPIOx->AFR[position >> 3U] &= ~(0xFu << ((position & 0x07U) * GPIO_AFRL_AFSEL1_Pos)) ;
/* Configure the default value for IO Speed */
GPIOx->OSPEEDR &= ~(GPIO_OSPEEDR_OSPEED0 << (position * GPIO_OSPEEDR_OSPEED1_Pos));
/* Configure the default value IO Output Type */
GPIOx->OTYPER &= ~(GPIO_OTYPER_OT0 << position) ;
/* Deactivate the Pull-up and Pull-down resistor for the current IO */
GPIOx->PUPDR &= ~(GPIO_PUPDR_PUPD0 << (position * GPIO_PUPDR_PUPD1_Pos));
}
position++;
}
}
/**
* @}
*/
/** @addtogroup GPIO_Exported_Functions_Group2
* @brief GPIO Read, Write, Toggle, Lock and EXTI management functions.
*
@verbatim
===============================================================================
##### IO operation functions #####
===============================================================================
@endverbatim
* @{
*/
/**
* @brief Read the specified input port pin.
* @param GPIOx where x can be (A..E, G, H).
* @param GPIO_Pin specifies the port bit to read.
* This parameter can be any combination of GPIO_Pin_x where x can be (0..15).
* @retval The input port pin value.
*/
GPIO_PinState HAL_GPIO_ReadPin(const GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin)
{
GPIO_PinState bitstatus;
/* Check the parameters */
assert_param(IS_GPIO_PIN(GPIO_Pin));
if ((GPIOx->IDR & GPIO_Pin) != 0x00U)
{
bitstatus = GPIO_PIN_SET;
}
else
{
bitstatus = GPIO_PIN_RESET;
}
return bitstatus;
}
/**
* @brief Set or clear the selected data port bit.
* @note This function uses GPIOx_BSRR and GPIOx_BRR registers to allow atomic read/modify
* accesses. In this way, there is no risk of an IRQ occurring between
* the read and the modify access.
* @param GPIOx where x can be (A..E, G, H).
* @param GPIO_Pin specifies the port bit to be written.
* This parameter can be any combination of GPIO_Pin_x where x can be (0..15).
* @param PinState specifies the value to be written to the selected bit.
* This parameter can be one of the GPIO_PinState enum values:
* @arg GPIO_PIN_RESET: to clear the port pin
* @arg GPIO_PIN_SET: to set the port pin
* @retval None
*/
void HAL_GPIO_WritePin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin, GPIO_PinState PinState)
{
/* Check the parameters */
assert_param(IS_GPIO_PIN(GPIO_Pin));
assert_param(IS_GPIO_PIN_ACTION(PinState));
if (PinState != GPIO_PIN_RESET)
{
GPIOx->BSRR = (uint32_t)GPIO_Pin;
}
else
{
GPIOx->BRR = (uint32_t)GPIO_Pin;
}
}
/**
* @brief Toggle the specified GPIO pin.
* @param GPIOx where x can be (A..E, G, H).
* @param GPIO_Pin specifies the pin to be toggled.
* This parameter can be any combination of GPIO_Pin_x where x can be (0..15).
* @retval None
*/
void HAL_GPIO_TogglePin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin)
{
uint32_t odr;
/* Check the parameters */
assert_param(IS_GPIO_PIN(GPIO_Pin));
/* get current Output Data Register value */
odr = GPIOx->ODR;
/* Set selected pins that were at low level, and reset ones that were high */
GPIOx->BSRR = ((odr & GPIO_Pin) << GPIO_NUMBER) | (~odr & GPIO_Pin);
}
/**
* @brief Set and clear several pins of a dedicated port in same cycle.
* @param GPIOx where x can be (A..E, G, H).
* @param PinReset specifies the port bits to be reset
* This parameter can be any combination of GPIO_Pin_x where x can be (0..15) or zero.
* @param PinSet specifies the port bits to be set
* This parameter can be any combination of GPIO_Pin_x where x can be (0..15) or zero.
* @note Both PinReset and PinSet combinations shall not get any common bit, else
* assert would be triggered.
* @note At least one of the two parameters used to set or reset shall be different from zero.
* @retval None
*/
void HAL_GPIO_WriteMultipleStatePin(GPIO_TypeDef *GPIOx, uint16_t PinReset, uint16_t PinSet)
{
uint32_t tmp;
/* Check the parameters */
/* Make sure at least one parameter is different from zero and that there is no common pin */
assert_param(IS_GPIO_PIN((uint32_t)PinReset | (uint32_t)PinSet));
assert_param(IS_GPIO_COMMON_PIN(PinReset, PinSet));
tmp = (((uint32_t)PinReset << 16) | PinSet);
GPIOx->BSRR = tmp;
}
/**
* @brief Lock GPIO Pins configuration registers.
* @note The locked registers are GPIOx_MODER, GPIOx_OTYPER, GPIOx_OSPEEDR,
* GPIOx_PUPDR, GPIOx_AFRL and GPIOx_AFRH.
* @note The configuration of the locked GPIO pins can no longer be modified
* until the next reset.
* @param GPIOx where x can be (A..E, G, H).
* @param GPIO_Pin specifies the port bits to be locked.
* This parameter can be any combination of GPIO_Pin_x where x can be (0..15).
* @retval HAL_OK if success, HAL_ERROR otherwise
*/
HAL_StatusTypeDef HAL_GPIO_LockPin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin)
{
__IO uint32_t tmp = GPIO_LCKR_LCKK;
/* Check the parameters */
assert_param(IS_GPIO_LOCK_INSTANCE(GPIOx));
assert_param(IS_GPIO_PIN(GPIO_Pin));
/* Apply lock key write sequence */
tmp |= GPIO_Pin;
/* Set LCKx bit(s): LCKK='1' + LCK[15-0] */
GPIOx->LCKR = tmp;
/* Reset LCKx bit(s): LCKK='0' + LCK[15-0] */
GPIOx->LCKR = GPIO_Pin;
/* Set LCKx bit(s): LCKK='1' + LCK[15-0] */
GPIOx->LCKR = tmp;
/* Read LCKK register. This read is mandatory to complete key lock sequence */
tmp = GPIOx->LCKR;
/* read again in order to confirm lock is active */
if ((GPIOx->LCKR & GPIO_LCKR_LCKK) != 0x00U)
{
return HAL_OK;
}
else
{
return HAL_ERROR;
}
}
/**
* @brief Enable speed optimization for several pin of dedicated port.
* @note It must be used only if the I/O supply voltage is below 2.7 V.
* @note Not all I/Os support the HSLV mode. Refer to the I/O structure in the corresponding
* datasheet for the list of I/Os supporting this feature. Other I/Os HSLV configuration must
* be kept at reset value.
* @param GPIOx where x can be (A..E, G, H).
* @param GPIO_Pin: specifies the port bit to be optimized.
* This parameter can be any combination of GPIO_Pin_x where x can be (0..15).
* @retval None
*/
void HAL_GPIO_EnableHighSpeedLowVoltage(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin)
{
/* Check the parameters */
assert_param(IS_GPIO_PIN(GPIO_Pin));
assert_param(IS_GPIO_ALL_INSTANCE(GPIOx));
/* Set HSLVR gpio pin */
GPIOx->HSLVR |= GPIO_Pin;
}
/**
* @brief Disable speed optimization for several pin of dedicated port.
* @note Not all I/Os support the HSLV mode. Refer to the I/O structure in the corresponding
* datasheet for the list of I/Os supporting this feature. Other I/Os HSLV configuration must
* be kept at reset value.
* @note It must be used only if the I/O supply voltage is below 2.7 V.
* @param GPIOx where x can be (A..E, G, H).
* @param GPIO_Pin: specifies the port bit to be unoptimized.
* This parameter can be any combination of GPIO_Pin_x where x can be (0..15).
* @retval None
*/
void HAL_GPIO_DisableHighSpeedLowVoltage(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin)
{
/* Check the parameters */
assert_param(IS_GPIO_PIN(GPIO_Pin));
assert_param(IS_GPIO_ALL_INSTANCE(GPIOx));
/* Set HSLVR gpio pin */
GPIOx->HSLVR &= ~(GPIO_Pin);
}
/**
* @brief Handle EXTI interrupt request.
* @param GPIO_Pin Specifies the port pin connected to corresponding EXTI line.
* @retval None
*/
void HAL_GPIO_EXTI_IRQHandler(uint16_t GPIO_Pin)
{
/* EXTI line interrupt detected */
if (__HAL_GPIO_EXTI_GET_RISING_IT(GPIO_Pin) != 0x00U)
{
__HAL_GPIO_EXTI_CLEAR_RISING_IT(GPIO_Pin);
HAL_GPIO_EXTI_Rising_Callback(GPIO_Pin);
}
if (__HAL_GPIO_EXTI_GET_FALLING_IT(GPIO_Pin) != 0x00U)
{
__HAL_GPIO_EXTI_CLEAR_FALLING_IT(GPIO_Pin);
HAL_GPIO_EXTI_Falling_Callback(GPIO_Pin);
}
}
/**
* @brief EXTI line rising detection callback.
* @param GPIO_Pin Specifies the port pin connected to corresponding EXTI line.
* @retval None
*/
__weak void HAL_GPIO_EXTI_Rising_Callback(uint16_t GPIO_Pin)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(GPIO_Pin);
/* NOTE: This function should not be modified, when the callback is needed,
the HAL_GPIO_EXTI_Rising_Callback could be implemented in the user file
*/
}
/**
* @brief EXTI line falling detection callback.
* @param GPIO_Pin Specifies the port pin connected to corresponding EXTI line.
* @retval None
*/
__weak void HAL_GPIO_EXTI_Falling_Callback(uint16_t GPIO_Pin)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(GPIO_Pin);
/* NOTE: This function should not be modified, when the callback is needed,
the HAL_GPIO_EXTI_Falling_Callback could be implemented in the user file
*/
}
/**
* @}
*/
/** @defgroup GPIO_Exported_Functions_Group3 IO attributes management functions
* @brief GPIO attributes management functions.
*
@verbatim
===============================================================================
##### IO attributes functions #####
===============================================================================
@endverbatim
* @{
*/
#if defined (CPU_IN_SECURE_STATE)
/**
* @brief Configure the GPIO pins attributes.
* @note Available attributes are to secure GPIO pin(s), so this function is
* only available in secure
* @param GPIOx: where x can be (A..E, G, H).
* @param GPIO_Pin: specifies the port bit to be written.
* This parameter can be one of GPIO_PIN_x where x can be (0..15).
* @param PinAttributes: specifies the pin(s) to be set in secure mode, other being set non secured.
* @note Refer to the product datasheet to know which bits are available for each port.
* @retval None
*/
void HAL_GPIO_ConfigPinAttributes(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin, uint32_t PinAttributes)
{
uint32_t sec;
/* Check the parameters */
assert_param(IS_GPIO_ALL_INSTANCE(GPIOx));
assert_param(IS_GPIO_PIN(GPIO_Pin));
assert_param(IS_GPIO_PIN_ATTRIBUTES(PinAttributes));
/* Configure the port pins */
sec = GPIOx->SECCFGR;
if (PinAttributes != GPIO_PIN_NSEC)
{
sec |= (uint32_t)GPIO_Pin;
}
else
{
sec &= ~((uint32_t)GPIO_Pin);
}
GPIOx->SECCFGR = sec;
}
#endif /* CPU_IN_SECURE_STATE */
/**
* @brief Get the GPIO pins attributes.
* @param GPIOx: where x can be (A..E, G, H).
* @param GPIO_Pin: specifies the port bit to be written.
* This parameter can be one of GPIO_PIN_x where x can be (0..15).
* @param pPinAttributes: pointer to return the pin attributes.
* @note Refer to the product datasheet to know which bits are available for each port.
* @retval HAL Status.
*/
HAL_StatusTypeDef HAL_GPIO_GetConfigPinAttributes(const GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin,
uint32_t *pPinAttributes)
{
/* Check the parameters */
assert_param(IS_GPIO_ALL_INSTANCE(GPIOx));
assert_param(IS_GPIO_SINGLE_PIN(GPIO_Pin));
/* Check null pointer */
if (pPinAttributes == NULL)
{
return HAL_ERROR;
}
if ((GPIOx->SECCFGR & GPIO_Pin) != 0x00U)
{
*pPinAttributes = GPIO_PIN_SEC;
}
else
{
*pPinAttributes = GPIO_PIN_NSEC;
}
return HAL_OK;
}
/**
* @}
*/
/**
* @}
*/
#endif /* HAL_GPIO_MODULE_ENABLED */
/**
* @}
*/
/**
* @}
*/

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/**
******************************************************************************
* @file stm32u3xx_hal_i2c_ex.c
* @author MCD Application Team
* @brief I2C Extended HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of I2C Extended peripheral:
* + Filter Mode Functions
* + WakeUp Mode Functions
* + FastModePlus Functions
* + Autonomous Mode Functions
*
******************************************************************************
* @attention
*
* Copyright (c) 2023 STMicroelectronics.
* All rights reserved.
*
* This software is licensed under terms that can be found in the LICENSE file
* in the root directory of this software component.
* If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
@verbatim
==============================================================================
##### I2C peripheral Extended features #####
==============================================================================
[..] Comparing to other previous devices, the I2C interface for STM32U3xx
devices contains the following additional features
(+) Possibility to disable or enable Analog Noise Filter
(+) Use of a configured Digital Noise Filter
(+) Disable or enable wakeup from Stop mode(s)
(+) Disable or enable Fast Mode Plus
(+) Configure Autonomous mode
##### How to use this driver #####
==============================================================================
[..] This driver provides functions to configure Noise Filter and Wake Up Feature
(#) Configure I2C Analog noise filter using the function HAL_I2CEx_ConfigAnalogFilter()
(#) Configure I2C Digital noise filter using the function HAL_I2CEx_ConfigDigitalFilter()
(#) Configure the enable or disable of I2C Wake Up Mode using the functions :
(++) HAL_I2CEx_EnableWakeUp()
(++) HAL_I2CEx_DisableWakeUp()
(#) Configure the enable or disable of fast mode plus driving capability using the functions :
(++) HAL_I2CEx_ConfigFastModePlus()
(#) Set or get or clear the autonomous mode configuration using these functions :
(++) HAL_I2CEx_SetConfigAutonomousMode()
(++) HAL_I2CEx_GetConfigAutonomousMode()
(++) HAL_I2CEx_ClearConfigAutonomousMode()
@endverbatim
*/
/* Includes ------------------------------------------------------------------*/
#include "stm32u3xx_hal.h"
/** @addtogroup STM32U3xx_HAL_Driver
* @{
*/
/** @defgroup I2CEx I2CEx
* @brief I2C Extended HAL module driver
* @{
*/
#ifdef HAL_I2C_MODULE_ENABLED
/* Private typedef -----------------------------------------------------------*/
/* Private define ------------------------------------------------------------*/
/* Private macro -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private function prototypes -----------------------------------------------*/
/* Private functions ---------------------------------------------------------*/
/** @defgroup I2CEx_Exported_Functions I2C Extended Exported Functions
* @{
*/
/** @defgroup I2CEx_Exported_Functions_Group1 Filter Mode Functions
* @brief Filter Mode Functions
*
@verbatim
===============================================================================
##### Filter Mode Functions #####
===============================================================================
[..] This section provides functions allowing to:
(+) Configure Noise Filters
@endverbatim
* @{
*/
/**
* @brief Configure I2C Analog noise filter.
* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
* the configuration information for the specified I2Cx peripheral.
* @param AnalogFilter New state of the Analog filter.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_I2CEx_ConfigAnalogFilter(I2C_HandleTypeDef *hi2c, uint32_t AnalogFilter)
{
/* Check the parameters */
assert_param(IS_I2C_ALL_INSTANCE(hi2c->Instance));
assert_param(IS_I2C_ANALOG_FILTER(AnalogFilter));
if (hi2c->State == HAL_I2C_STATE_READY)
{
/* Process Locked */
__HAL_LOCK(hi2c);
hi2c->State = HAL_I2C_STATE_BUSY;
/* Disable the selected I2C peripheral */
__HAL_I2C_DISABLE(hi2c);
/* Reset I2Cx ANOFF bit */
hi2c->Instance->CR1 &= ~(I2C_CR1_ANFOFF);
/* Set analog filter bit*/
hi2c->Instance->CR1 |= AnalogFilter;
__HAL_I2C_ENABLE(hi2c);
hi2c->State = HAL_I2C_STATE_READY;
/* Process Unlocked */
__HAL_UNLOCK(hi2c);
return HAL_OK;
}
else
{
return HAL_BUSY;
}
}
/**
* @brief Configure I2C Digital noise filter.
* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
* the configuration information for the specified I2Cx peripheral.
* @param DigitalFilter Coefficient of digital noise filter between Min_Data=0x00 and Max_Data=0x0F.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_I2CEx_ConfigDigitalFilter(I2C_HandleTypeDef *hi2c, uint32_t DigitalFilter)
{
uint32_t tmpreg;
/* Check the parameters */
assert_param(IS_I2C_ALL_INSTANCE(hi2c->Instance));
assert_param(IS_I2C_DIGITAL_FILTER(DigitalFilter));
if (hi2c->State == HAL_I2C_STATE_READY)
{
/* Process Locked */
__HAL_LOCK(hi2c);
hi2c->State = HAL_I2C_STATE_BUSY;
/* Disable the selected I2C peripheral */
__HAL_I2C_DISABLE(hi2c);
/* Get the old register value */
tmpreg = hi2c->Instance->CR1;
/* Reset I2Cx DNF bits [11:8] */
tmpreg &= ~(I2C_CR1_DNF);
/* Set I2Cx DNF coefficient */
tmpreg |= DigitalFilter << 8U;
/* Store the new register value */
hi2c->Instance->CR1 = tmpreg;
__HAL_I2C_ENABLE(hi2c);
hi2c->State = HAL_I2C_STATE_READY;
/* Process Unlocked */
__HAL_UNLOCK(hi2c);
return HAL_OK;
}
else
{
return HAL_BUSY;
}
}
/**
* @}
*/
/** @defgroup I2CEx_Exported_Functions_Group2 WakeUp Mode Functions
* @brief WakeUp Mode Functions
*
@verbatim
===============================================================================
##### WakeUp Mode Functions #####
===============================================================================
[..] This section provides functions allowing to:
(+) Configure Wake Up Feature
@endverbatim
* @{
*/
/**
* @brief Enable I2C wakeup from Stop mode(s).
* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
* the configuration information for the specified I2Cx peripheral.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_I2CEx_EnableWakeUp(I2C_HandleTypeDef *hi2c)
{
/* Check the parameters */
assert_param(IS_I2C_WAKEUP_FROMSTOP_INSTANCE(hi2c->Instance));
if (hi2c->State == HAL_I2C_STATE_READY)
{
/* Process Locked */
__HAL_LOCK(hi2c);
hi2c->State = HAL_I2C_STATE_BUSY;
/* Disable the selected I2C peripheral */
__HAL_I2C_DISABLE(hi2c);
/* Enable wakeup from stop mode */
hi2c->Instance->CR1 |= I2C_CR1_WUPEN;
__HAL_I2C_ENABLE(hi2c);
hi2c->State = HAL_I2C_STATE_READY;
/* Process Unlocked */
__HAL_UNLOCK(hi2c);
return HAL_OK;
}
else
{
return HAL_BUSY;
}
}
/**
* @brief Disable I2C wakeup from Stop mode(s).
* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
* the configuration information for the specified I2Cx peripheral.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_I2CEx_DisableWakeUp(I2C_HandleTypeDef *hi2c)
{
/* Check the parameters */
assert_param(IS_I2C_WAKEUP_FROMSTOP_INSTANCE(hi2c->Instance));
if (hi2c->State == HAL_I2C_STATE_READY)
{
/* Process Locked */
__HAL_LOCK(hi2c);
hi2c->State = HAL_I2C_STATE_BUSY;
/* Disable the selected I2C peripheral */
__HAL_I2C_DISABLE(hi2c);
/* Enable wakeup from stop mode */
hi2c->Instance->CR1 &= ~(I2C_CR1_WUPEN);
__HAL_I2C_ENABLE(hi2c);
hi2c->State = HAL_I2C_STATE_READY;
/* Process Unlocked */
__HAL_UNLOCK(hi2c);
return HAL_OK;
}
else
{
return HAL_BUSY;
}
}
/**
* @}
*/
/** @defgroup I2CEx_Exported_Functions_Group3 Fast Mode Plus Functions
* @brief Fast Mode Plus Functions
*
@verbatim
===============================================================================
##### Fast Mode Plus Functions #####
===============================================================================
[..] This section provides functions allowing to:
(+) Configure Fast Mode Plus
@endverbatim
* @{
*/
/**
* @brief Configure I2C Fast Mode Plus.
* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
* the configuration information for the specified I2Cx peripheral.
* @param FastModePlus New state of the Fast Mode Plus.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_I2CEx_ConfigFastModePlus(I2C_HandleTypeDef *hi2c, uint32_t FastModePlus)
{
/* Check the parameters */
assert_param(IS_I2C_ALL_INSTANCE(hi2c->Instance));
assert_param(IS_I2C_FASTMODEPLUS(FastModePlus));
if (hi2c->State == HAL_I2C_STATE_READY)
{
/* Process Locked */
__HAL_LOCK(hi2c);
hi2c->State = HAL_I2C_STATE_BUSY;
/* Disable the selected I2C peripheral */
__HAL_I2C_DISABLE(hi2c);
if (FastModePlus == I2C_FASTMODEPLUS_ENABLE)
{
/* Set I2Cx FMP bit */
hi2c->Instance->CR1 |= (I2C_CR1_FMP);
}
else
{
/* Reset I2Cx FMP bit */
hi2c->Instance->CR1 &= ~(I2C_CR1_FMP);
}
__HAL_I2C_ENABLE(hi2c);
hi2c->State = HAL_I2C_STATE_READY;
/* Process Unlocked */
__HAL_UNLOCK(hi2c);
return HAL_OK;
}
else
{
return HAL_BUSY;
}
}
/**
* @}
*/
/** @defgroup I2CEx_Exported_Functions_Group4 Autonomous Mode Functions
* @brief Autonomous Mode Functions
*
@verbatim
===============================================================================
##### Autonomous Mode functions #####
===============================================================================
[..] This section provides functions allowing to:
(+) Configure Autonomous Mode
@endverbatim
* @{
*/
/**
* @brief Set Autonomous Mode configuration
* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
* the configuration information for the specified I2Cx peripheral.
* @param sConfig Pointer to a I2C_AutonomousModeConfTypeDef structure that contains
* the configuration information of the autonomous mode for the specified I2Cx peripheral.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_I2CEx_SetConfigAutonomousMode(I2C_HandleTypeDef *hi2c,
const I2C_AutonomousModeConfTypeDef *sConfig)
{
if (hi2c->State == HAL_I2C_STATE_READY)
{
/* Process Locked */
__HAL_LOCK(hi2c);
hi2c->State = HAL_I2C_STATE_BUSY;
/* Check the parameters */
assert_param(IS_I2C_TRIG_INPUT_INSTANCE(hi2c->Instance));
assert_param(IS_I2C_TRIG_SOURCE(hi2c->Instance, sConfig->TriggerSelection));
assert_param(IS_I2C_AUTO_MODE_TRG_POL(sConfig->TriggerPolarity));
/* Disable the selected I2C peripheral to be able to configure AUTOCR */
__HAL_I2C_DISABLE(hi2c);
/* I2Cx AUTOCR Configuration */
WRITE_REG(hi2c->Instance->AUTOCR,
(sConfig->TriggerState | \
((sConfig->TriggerSelection) & I2C_AUTOCR_TRIGSEL_Msk) | \
sConfig->TriggerPolarity));
/* Enable the selected I2C peripheral */
__HAL_I2C_ENABLE(hi2c);
hi2c->State = HAL_I2C_STATE_READY;
/* Process Unlocked */
__HAL_UNLOCK(hi2c);
return HAL_OK;
}
else
{
return HAL_ERROR;
}
}
/**
* @brief Get Autonomous Mode configuration
* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
* the configuration information for the specified I2Cx peripheral.
* @param sConfig Pointer to a I2C_AutonomousModeConfTypeDef structure that contains
* the configuration information of the autonomous mode for the specified I2Cx peripheral.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_I2CEx_GetConfigAutonomousMode(const I2C_HandleTypeDef *hi2c,
I2C_AutonomousModeConfTypeDef *sConfig)
{
uint32_t autocr_tmp;
/* Check the parameters */
assert_param(IS_I2C_TRIG_INPUT_INSTANCE(hi2c->Instance));
autocr_tmp = hi2c->Instance->AUTOCR;
sConfig->TriggerState = (autocr_tmp & I2C_AUTOCR_TRIGEN);
if (IS_I2C_GRP2_INSTANCE(hi2c->Instance))
{
sConfig->TriggerSelection = ((autocr_tmp & I2C_AUTOCR_TRIGSEL) | I2C_TRIG_GRP2);
}
else
{
sConfig->TriggerSelection = ((autocr_tmp & I2C_AUTOCR_TRIGSEL) | I2C_TRIG_GRP1);
}
sConfig->TriggerPolarity = (autocr_tmp & I2C_AUTOCR_TRIGPOL);
return HAL_OK;
}
/**
* @brief Clear Autonomous Mode configuration
* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
* the configuration information for the specified I2Cx peripheral.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_I2CEx_ClearConfigAutonomousMode(I2C_HandleTypeDef *hi2c)
{
if (hi2c->State == HAL_I2C_STATE_READY)
{
/* Process Locked */
__HAL_LOCK(hi2c);
hi2c->State = HAL_I2C_STATE_BUSY;
/* Check the parameters */
assert_param(IS_I2C_TRIG_INPUT_INSTANCE(hi2c->Instance));
/* Disable the selected I2C peripheral to be able to clear AUTOCR */
__HAL_I2C_DISABLE(hi2c);
CLEAR_REG(hi2c->Instance->AUTOCR);
/* Enable the selected I2C peripheral */
__HAL_I2C_ENABLE(hi2c);
hi2c->State = HAL_I2C_STATE_READY;
/* Process Unlocked */
__HAL_UNLOCK(hi2c);
return HAL_OK;
}
else
{
return HAL_ERROR;
}
}
/**
* @}
*/
/**
* @}
*/
#endif /* HAL_I2C_MODULE_ENABLED */
/**
* @}
*/
/**
* @}
*/

651
Software/Station_SW/Drivers/STM32U3xx_HAL_Driver/Src/stm32u3xx_hal_icache.c Normal file
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@@ -0,0 +1,651 @@
/**
******************************************************************************
* @file stm32u3xx_hal_icache.c
* @author MCD Application Team
* @brief ICACHE HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of the Instruction Cache (ICACHE).
* + Initialization and Configuration
* + Invalidate functions
* + Monitoring management
* + Memory address remap management
******************************************************************************
* @attention
*
* Copyright (c) 2023 STMicroelectronics.
* All rights reserved.
*
* This software is licensed under terms that can be found in the LICENSE file
* in the root directory of this software component.
* If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
@verbatim
==============================================================================
##### ICACHE main features #####
==============================================================================
[..]
The Instruction Cache (ICACHE) is introduced on C-AHB code bus of
Cortex-M33 processor to improve performance when fetching instruction
and data from both internal and external memories. It allows close to
zero wait states performance.
(+) The ICACHE provides two performance counters (Hit and Miss),
cache invalidate maintenance operation, error management and TrustZone
security support.
(+) The ICACHE provides additionally the possibility to remap input address
falling into up to four memory regions (used to remap aliased code in
external memories to the internal Code region, for execution)
===============================================================================
##### How to use this driver #####
===============================================================================
[..]
The ICACHE HAL driver can be used as follows:
(#) Optionally configure the Instruction Cache mode with
HAL_ICACHE_ConfigAssociativityMode() if the default configuration
does not suit the application requirements.
(#) Enable and disable the Instruction Cache with respectively
HAL_ICACHE_Enable() and HAL_ICACHE_Disable().
Use HAL_ICACHE_IsEnabled() to get the Instruction Cache status.
To ensure a deterministic cache behavior after power on, system reset or after
a call to @ref HAL_ICACHE_Disable(), the application must call
@ref HAL_ICACHE_WaitForInvalidateComplete(). Indeed on power on, system reset
or cache disable, an automatic cache invalidation procedure is launched and the
cache is bypassed until the operation completes.
(#) Initiate the cache maintenance invalidation procedure with either
HAL_ICACHE_Invalidate() (blocking mode) or HAL_ICACHE_Invalidate_IT()
(interrupt mode). When interrupt mode is used, the callback function
HAL_ICACHE_InvalidateCompleteCallback() is called when the invalidate
procedure is complete. The function HAL_ICACHE_WaitForInvalidateComplete()
may be called to wait for the end of the invalidate procedure automatically
initiated when disabling the Instruction Cache with HAL_ICACHE_Disable().
The cache operation is bypassed during the invalidation procedure.
(#) Use the performance monitoring counters for Hit and Miss with the following
functions: HAL_ICACHE_Monitor_Start(), HAL_ICACHE_Monitor_Stop(),
HAL_ICACHE_Monitor_Reset(), HAL_ICACHE_Monitor_GetHitValue() and
HAL_ICACHE_Monitor_GetMissValue()
(#) Enable and disable up to four regions to remap input address from external
memories to the internal Code region for execution with
HAL_ICACHE_EnableRemapRegion() and HAL_ICACHE_DisableRemapRegion()
@endverbatim
*/
/* Includes ------------------------------------------------------------------*/
#include "stm32u3xx_hal.h"
/** @addtogroup STM32U3xx_HAL_Driver
* @{
*/
/** @defgroup ICACHE ICACHE
* @brief HAL ICACHE module driver
* @{
*/
#if defined(ICACHE) && defined (HAL_ICACHE_MODULE_ENABLED)
/* Private typedef -----------------------------------------------------------*/
/* Private constants ---------------------------------------------------------*/
/** @addtogroup ICACHE_Private_Constants ICACHE Private Constants
* @{
*/
#define ICACHE_INVALIDATE_TIMEOUT_VALUE 1U /* 1ms */
#define ICACHE_DISABLE_TIMEOUT_VALUE 1U /* 1ms */
/**
* @}
*/
/* Private macros ------------------------------------------------------------*/
/** @defgroup ICACHE_Private_Macros ICACHE Private Macros
* @{
*/
#define IS_ICACHE_ASSOCIATIVITY_MODE(__MODE__) (((__MODE__) == ICACHE_1WAY) || \
((__MODE__) == ICACHE_2WAYS))
#define IS_ICACHE_MONITOR_TYPE(__TYPE__) (((__TYPE__) == ICACHE_MONITOR_HIT_MISS) || \
((__TYPE__) == ICACHE_MONITOR_HIT) || \
((__TYPE__) == ICACHE_MONITOR_MISS))
#define IS_ICACHE_REGION_NUMBER(__NUMBER__) ((__NUMBER__) < 4U)
#define IS_ICACHE_REGION_SIZE(__SIZE__) (((__SIZE__) == ICACHE_REGIONSIZE_2MB) || \
((__SIZE__) == ICACHE_REGIONSIZE_4MB) || \
((__SIZE__) == ICACHE_REGIONSIZE_8MB) || \
((__SIZE__) == ICACHE_REGIONSIZE_16MB) || \
((__SIZE__) == ICACHE_REGIONSIZE_32MB) || \
((__SIZE__) == ICACHE_REGIONSIZE_64MB) || \
((__SIZE__) == ICACHE_REGIONSIZE_128MB))
#define IS_ICACHE_REGION_TRAFFIC_ROUTE(__TRAFFICROUTE__) (((__TRAFFICROUTE__) == ICACHE_MASTER1_PORT) || \
((__TRAFFICROUTE__) == ICACHE_MASTER2_PORT))
#define IS_ICACHE_REGION_OUTPUT_BURST_TYPE(__OUTPUTBURSTTYPE_) (((__OUTPUTBURSTTYPE_) == ICACHE_OUTPUT_BURST_WRAP) || \
((__OUTPUTBURSTTYPE_) == ICACHE_OUTPUT_BURST_INCR))
/**
* @}
*/
/* Private variables ---------------------------------------------------------*/
/* Private function prototypes -----------------------------------------------*/
/* Exported functions --------------------------------------------------------*/
/** @defgroup ICACHE_Exported_Functions ICACHE Exported Functions
* @{
*/
/** @defgroup ICACHE_Exported_Functions_Group1 Initialization and control functions
* @brief Initialization and control functions
*
@verbatim
==============================================================================
##### Initialization and control functions #####
==============================================================================
[..]
This section provides functions allowing to initialize and control the
Instruction Cache (mode, invalidate procedure, performance counters).
@endverbatim
* @{
*/
/**
* @brief Configure the Instruction Cache cache associativity mode selection.
* @param AssociativityMode Associativity mode selection
* This parameter can be one of the following values:
* @arg ICACHE_1WAY 1-way cache (direct mapped cache)
* @arg ICACHE_2WAYS 2-ways set associative cache (default)
* @retval HAL status (HAL_OK/HAL_ERROR)
*/
HAL_StatusTypeDef HAL_ICACHE_ConfigAssociativityMode(uint32_t AssociativityMode)
{
HAL_StatusTypeDef status = HAL_OK;
/* Check the parameters */
assert_param(IS_ICACHE_ASSOCIATIVITY_MODE(AssociativityMode));
/* Check cache is not enabled */
if (READ_BIT(ICACHE->CR, ICACHE_CR_EN) != 0U)
{
status = HAL_ERROR;
}
else
{
MODIFY_REG(ICACHE->CR, ICACHE_CR_WAYSEL, AssociativityMode);
}
return status;
}
/**
* @brief DeInitialize the Instruction Cache.
* @retval HAL status (HAL_OK)
*/
HAL_StatusTypeDef HAL_ICACHE_DeInit(void)
{
/* Reset interrupt enable value */
WRITE_REG(ICACHE->IER, 0U);
/* Clear any pending flags */
WRITE_REG(ICACHE->FCR, ICACHE_FCR_CBSYENDF | ICACHE_FCR_CERRF);
/* Disable cache then set default associative mode value */
CLEAR_BIT(ICACHE->CR, ICACHE_CR_EN);
WRITE_REG(ICACHE->CR, ICACHE_CR_WAYSEL);
/* Stop monitor and reset monitor values */
CLEAR_BIT(ICACHE->CR, ICACHE_MONITOR_HIT_MISS);
SET_BIT(ICACHE->CR, (ICACHE_MONITOR_HIT_MISS << 2U));
CLEAR_BIT(ICACHE->CR, (ICACHE_MONITOR_HIT_MISS << 2U));
/* Reset regions configuration values */
WRITE_REG(ICACHE->CRR0, ICACHE_REGIONSIZE_2MB << ICACHE_CRRx_RSIZE_Pos);
WRITE_REG(ICACHE->CRR1, ICACHE_REGIONSIZE_2MB << ICACHE_CRRx_RSIZE_Pos);
WRITE_REG(ICACHE->CRR2, ICACHE_REGIONSIZE_2MB << ICACHE_CRRx_RSIZE_Pos);
WRITE_REG(ICACHE->CRR3, ICACHE_REGIONSIZE_2MB << ICACHE_CRRx_RSIZE_Pos);
return HAL_OK;
}
/**
* @brief Enable the Instruction Cache.
* @note This function always returns HAL_OK even if there is any ongoing
* cache operation. The Instruction Cache is bypassed until the
* cache operation completes.
* @retval HAL status (HAL_OK)
*/
HAL_StatusTypeDef HAL_ICACHE_Enable(void)
{
SET_BIT(ICACHE->CR, ICACHE_CR_EN);
return HAL_OK;
}
/**
* @brief Disable the Instruction Cache.
* @note This function waits for the cache being disabled but
* not for the end of the automatic cache invalidation procedure.
* @retval HAL status (HAL_OK/HAL_TIMEOUT)
*/
HAL_StatusTypeDef HAL_ICACHE_Disable(void)
{
HAL_StatusTypeDef status = HAL_OK;
uint32_t tickstart;
/* Make sure BSYENDF is reset before to disable the instruction cache */
/* as it automatically starts a cache invalidation procedure */
WRITE_REG(ICACHE->FCR, ICACHE_FCR_CBSYENDF);
CLEAR_BIT(ICACHE->CR, ICACHE_CR_EN);
/* Get tick */
tickstart = HAL_GetTick();
/* Wait for instruction cache being disabled */
while (READ_BIT(ICACHE->CR, ICACHE_CR_EN) != 0U)
{
if ((HAL_GetTick() - tickstart) > ICACHE_DISABLE_TIMEOUT_VALUE)
{
/* New check to avoid false timeout detection in case of preemption */
if (READ_BIT(ICACHE->CR, ICACHE_CR_EN) != 0U)
{
status = HAL_TIMEOUT;
break;
}
}
}
return status;
}
/**
* @brief Check whether the Instruction Cache is enabled or not.
* @retval Status (0: disabled, 1: enabled)
*/
uint32_t HAL_ICACHE_IsEnabled(void)
{
return ((READ_BIT(ICACHE->CR, ICACHE_CR_EN) != 0U) ? 1UL : 0UL);
}
/**
* @brief Invalidate the Instruction Cache.
* @note This function waits for the end of cache invalidation procedure
* and clears the associated BSYENDF flag.
* @retval HAL status (HAL_OK/HAL_ERROR/HAL_TIMEOUT)
*/
HAL_StatusTypeDef HAL_ICACHE_Invalidate(void)
{
HAL_StatusTypeDef status;
/* Check if no ongoing operation */
if (READ_BIT(ICACHE->SR, ICACHE_SR_BUSYF) == 0U)
{
/* Launch cache invalidation */
SET_BIT(ICACHE->CR, ICACHE_CR_CACHEINV);
}
status = HAL_ICACHE_WaitForInvalidateComplete();
return status;
}
/**
* @brief Invalidate the Instruction Cache with interrupt.
* @note This function launches cache invalidation and returns.
* User application shall resort to interrupt generation to check
* the end of the cache invalidation with the BSYENDF flag and the
* HAL_ICACHE_InvalidateCompleteCallback() callback.
* @retval HAL status (HAL_OK/HAL_ERROR)
*/
HAL_StatusTypeDef HAL_ICACHE_Invalidate_IT(void)
{
HAL_StatusTypeDef status = HAL_OK;
/* Check no ongoing operation */
if (READ_BIT(ICACHE->SR, ICACHE_SR_BUSYF) != 0U)
{
status = HAL_ERROR;
}
else
{
/* Make sure BSYENDF is reset before to start cache invalidation */
WRITE_REG(ICACHE->FCR, ICACHE_FCR_CBSYENDF);
/* Enable end of cache invalidation interrupt */
SET_BIT(ICACHE->IER, ICACHE_IER_BSYENDIE);
/* Launch cache invalidation */
SET_BIT(ICACHE->CR, ICACHE_CR_CACHEINV);
}
return status;
}
/**
* @brief Wait for the end of the Instruction Cache invalidate procedure.
* @note This function checks and clears the BSYENDF flag when set.
* @retval HAL status (HAL_OK/HAL_TIMEOUT)
*/
HAL_StatusTypeDef HAL_ICACHE_WaitForInvalidateComplete(void)
{
HAL_StatusTypeDef status = HAL_OK;
uint32_t tickstart;
/* Check if ongoing invalidation operation */
if (READ_BIT(ICACHE->SR, ICACHE_SR_BUSYF) != 0U)
{
/* Get tick */
tickstart = HAL_GetTick();
/* Wait for end of cache invalidation */
while (READ_BIT(ICACHE->SR, ICACHE_SR_BSYENDF) == 0U)
{
if ((HAL_GetTick() - tickstart) > ICACHE_INVALIDATE_TIMEOUT_VALUE)
{
/* New check to avoid false timeout detection in case of preemption */
if (READ_BIT(ICACHE->SR, ICACHE_SR_BSYENDF) == 0U)
{
status = HAL_TIMEOUT;
break;
}
}
}
}
/* Clear BSYENDF */
WRITE_REG(ICACHE->FCR, ICACHE_FCR_CBSYENDF);
return status;
}
/**
* @brief Start the Instruction Cache performance monitoring.
* @param MonitorType Monitoring type
* This parameter can be one of the following values:
* @arg ICACHE_MONITOR_HIT_MISS Hit & Miss monitoring
* @arg ICACHE_MONITOR_HIT Hit monitoring
* @arg ICACHE_MONITOR_MISS Miss monitoring
* @retval HAL status (HAL_OK)
*/
HAL_StatusTypeDef HAL_ICACHE_Monitor_Start(uint32_t MonitorType)
{
/* Check the parameters */
assert_param(IS_ICACHE_MONITOR_TYPE(MonitorType));
SET_BIT(ICACHE->CR, MonitorType);
return HAL_OK;
}
/**
* @brief Stop the Instruction Cache performance monitoring.
* @note Stopping the monitoring does not reset the values.
* @param MonitorType Monitoring type
* This parameter can be one of the following values:
* @arg ICACHE_MONITOR_HIT_MISS Hit & Miss monitoring
* @arg ICACHE_MONITOR_HIT Hit monitoring
* @arg ICACHE_MONITOR_MISS Miss monitoring
* @retval HAL status (HAL_OK)
*/
HAL_StatusTypeDef HAL_ICACHE_Monitor_Stop(uint32_t MonitorType)
{
/* Check the parameters */
assert_param(IS_ICACHE_MONITOR_TYPE(MonitorType));
CLEAR_BIT(ICACHE->CR, MonitorType);
return HAL_OK;
}
/**
* @brief Reset the Instruction Cache performance monitoring values.
* @param MonitorType Monitoring type
* This parameter can be one of the following values:
* @arg ICACHE_MONITOR_HIT_MISS Hit & Miss monitoring
* @arg ICACHE_MONITOR_HIT Hit monitoring
* @arg ICACHE_MONITOR_MISS Miss monitoring
* @retval HAL status (HAL_OK)
*/
HAL_StatusTypeDef HAL_ICACHE_Monitor_Reset(uint32_t MonitorType)
{
/* Check the parameters */
assert_param(IS_ICACHE_MONITOR_TYPE(MonitorType));
/* Force/Release reset */
SET_BIT(ICACHE->CR, (MonitorType << 2U));
CLEAR_BIT(ICACHE->CR, (MonitorType << 2U));
return HAL_OK;
}
/**
* @brief Get the Instruction Cache performance Hit monitoring value.
* @note Upon reaching the 32-bit maximum value, monitor does not wrap.
* @retval Hit monitoring value
*/
uint32_t HAL_ICACHE_Monitor_GetHitValue(void)
{
return (ICACHE->HMONR);
}
/**
* @brief Get the Instruction Cache performance Miss monitoring value.
* @note Upon reaching the 32-bit maximum value, monitor does not wrap.
* @retval Miss monitoring value
*/
uint32_t HAL_ICACHE_Monitor_GetMissValue(void)
{
return (ICACHE->MMONR);
}
/**
* @}
*/
/** @defgroup ICACHE_Exported_Functions_Group2 IRQ and callback functions
* @brief IRQ and callback functions
*
@verbatim
==============================================================================
##### IRQ and callback functions #####
==============================================================================
[..]
This section provides functions allowing to handle ICACHE global interrupt
and the associated callback functions.
@endverbatim
* @{
*/
/**
* @brief Handle the Instruction Cache interrupt request.
* @note This function should be called under the ICACHE_IRQHandler().
* @note This function respectively disables the interrupt and clears the
* flag of any pending flag before calling the associated user callback.
* @retval None
*/
void HAL_ICACHE_IRQHandler(void)
{
/* Get current interrupt flags and interrupt sources value */
uint32_t itflags = READ_REG(ICACHE->SR);
uint32_t itsources = READ_REG(ICACHE->IER);
/* Check Instruction cache Error interrupt flag */
if (((itflags & itsources) & ICACHE_FLAG_ERROR) != 0U)
{
/* Disable error interrupt */
CLEAR_BIT(ICACHE->IER, ICACHE_IER_ERRIE);
/* Clear ERR pending flag */
WRITE_REG(ICACHE->FCR, ICACHE_FCR_CERRF);
/* Instruction cache error interrupt user callback */
HAL_ICACHE_ErrorCallback();
}
/* Check Instruction cache BusyEnd interrupt flag */
if (((itflags & itsources) & ICACHE_FLAG_BUSYEND) != 0U)
{
/* Disable end of cache invalidation interrupt */
CLEAR_BIT(ICACHE->IER, ICACHE_IER_BSYENDIE);
/* Clear BSYENDF pending flag */
WRITE_REG(ICACHE->FCR, ICACHE_FCR_CBSYENDF);
/* Instruction cache busyend interrupt user callback */
HAL_ICACHE_InvalidateCompleteCallback();
}
}
/**
* @brief Cache invalidation complete callback.
*/
__weak void HAL_ICACHE_InvalidateCompleteCallback(void)
{
/* NOTE : This function should not be modified, when the callback is needed,
the HAL_ICACHE_InvalidateCompleteCallback() should be implemented in the user file
*/
}
/**
* @brief Error callback.
*/
__weak void HAL_ICACHE_ErrorCallback(void)
{
/* NOTE : This function should not be modified, when the callback is needed,
the HAL_ICACHE_ErrorCallback() should be implemented in the user file
*/
}
/**
* @}
*/
/** @defgroup ICACHE_Exported_Functions_Group3 Memory remapped regions functions
* @brief Memory remapped regions functions
*
@verbatim
==============================================================================
##### Memory remapped regions functions #####
==============================================================================
[..]
This section provides functions allowing to manage the remapping of
external memories to internal Code for execution.
@endverbatim
* @{
*/
/**
* @brief Configure and enable a region for memory remapping.
* @note The Instruction Cache and the region must be disabled.
* @param Region Region number
This parameter can be a value of @arg @ref ICACHE_Region
* @param pRegionConfig Pointer to structure of ICACHE region configuration parameters
* @retval HAL status (HAL_OK/HAL_ERROR)
*/
HAL_StatusTypeDef HAL_ICACHE_EnableRemapRegion(uint32_t Region, const ICACHE_RegionConfigTypeDef *const pRegionConfig)
{
HAL_StatusTypeDef status = HAL_OK;
__IO uint32_t *p_reg;
uint32_t value;
/* Check the parameters */
assert_param(IS_ICACHE_REGION_NUMBER(Region));
assert_param(IS_ICACHE_REGION_SIZE(pRegionConfig->Size));
assert_param(IS_ICACHE_REGION_TRAFFIC_ROUTE(pRegionConfig->TrafficRoute));
assert_param(IS_ICACHE_REGION_OUTPUT_BURST_TYPE(pRegionConfig->OutputBurstType));
/* Check cache is not enabled */
if (READ_BIT(ICACHE->CR, ICACHE_CR_EN) != 0U)
{
status = HAL_ERROR;
}
else
{
/* Get region control register address */
p_reg = &(ICACHE->CRR0) + (1U * Region);
/* Check region is not already enabled */
if ((*p_reg & ICACHE_CRRx_REN) != 0U)
{
status = HAL_ERROR;
}
else
{
/* Region 2MB: BaseAddress size 8 bits, RemapAddress size 11 bits */
/* Region 4MB: BaseAddress size 7 bits, RemapAddress size 10 bits */
/* Region 8MB: BaseAddress size 6 bits, RemapAddress size 9 bits */
/* Region 16MB: BaseAddress size 5 bits, RemapAddress size 8 bits */
/* Region 32MB: BaseAddress size 4 bits, RemapAddress size 7 bits */
/* Region 64MB: BaseAddress size 3 bits, RemapAddress size 6 bits */
/* Region 128MB: BaseAddress size 2 bits, RemapAddress size 5 bits */
value = ((pRegionConfig->BaseAddress & 0x1FFFFFFFU) >> 21U) & \
(0xFFU & ~(pRegionConfig->Size - 1U));
value |= ((pRegionConfig->RemapAddress >> 5U) & \
((uint32_t)(0x7FFU & ~(pRegionConfig->Size - 1U)) << ICACHE_CRRx_REMAPADDR_Pos));
value |= (pRegionConfig->Size << ICACHE_CRRx_RSIZE_Pos) | pRegionConfig->TrafficRoute | \
pRegionConfig->OutputBurstType;
*p_reg = (value | ICACHE_CRRx_REN);
}
}
return status;
}
/**
* @brief Disable the memory remapping for a predefined region.
* @param Region Region number
This parameter can be a value of @arg @ref ICACHE_Region
* @retval HAL status (HAL_OK/HAL_ERROR)
*/
HAL_StatusTypeDef HAL_ICACHE_DisableRemapRegion(uint32_t Region)
{
HAL_StatusTypeDef status = HAL_OK;
__IO uint32_t *p_reg;
/* Check the parameters */
assert_param(IS_ICACHE_REGION_NUMBER(Region));
/* Check cache is not enabled */
if (READ_BIT(ICACHE->CR, ICACHE_CR_EN) != 0U)
{
status = HAL_ERROR;
}
else
{
/* Get region control register address */
p_reg = &(ICACHE->CRR0) + (1U * Region);
*p_reg &= ~ICACHE_CRRx_REN;
}
return status;
}
/**
* @}
*/
/**
* @}
*/
#endif /* ICACHE && HAL_ICACHE_MODULE_ENABLED */
/**
* @}
*/
/**
* @}
*/

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/**
******************************************************************************
* @file stm32u3xx_hal_spi_ex.c
* @author MCD Application Team
* @brief Extended SPI HAL module driver.
* This file provides firmware functions to manage the following
* SPI peripheral extended functionalities :
* + IO operation functions
* + Peripheral Control functions
*
******************************************************************************
* @attention
*
* Copyright (c) 2023 STMicroelectronics.
* All rights reserved.
*
* This software is licensed under terms that can be found in the LICENSE file
* in the root directory of this software component.
* If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
/* Includes ------------------------------------------------------------------*/
#include "stm32u3xx_hal.h"
/** @addtogroup STM32U3xx_HAL_Driver
* @{
*/
/** @defgroup SPIEx SPIEx
* @brief SPI Extended HAL module driver
* @{
*/
#ifdef HAL_SPI_MODULE_ENABLED
/* Private typedef -----------------------------------------------------------*/
/* Private defines -----------------------------------------------------------*/
/* Private macros ------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private function prototypes -----------------------------------------------*/
/* Exported functions --------------------------------------------------------*/
/** @defgroup SPIEx_Exported_Functions SPIEx Exported Functions
* @{
*/
/** @defgroup SPIEx_Exported_Functions_Group1 IO operation functions
* @brief Data transfers functions
*
@verbatim
==============================================================================
##### IO operation functions #####
===============================================================================
[..]
This subsection provides a set of extended functions to manage the SPI
data transfers.
(#) SPIEx function:
(++) HAL_SPIEx_FlushRxFifo()
(++) HAL_SPIEx_EnableLockConfiguration()
(++) HAL_SPIEx_ConfigureUnderrun()
@endverbatim
* @{
*/
/**
* @brief Flush the RX fifo.
* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
* the configuration information for the specified SPI module.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_SPIEx_FlushRxFifo(const SPI_HandleTypeDef *hspi)
{
uint8_t count = 0;
uint32_t itflag = hspi->Instance->SR;
__IO uint32_t tmpreg;
while (((hspi->Instance->SR & SPI_FLAG_FRLVL) != SPI_RX_FIFO_0PACKET) || ((itflag & SPI_FLAG_RXWNE) != 0UL))
{
count += (uint8_t)4UL;
tmpreg = hspi->Instance->RXDR;
UNUSED(tmpreg); /* To avoid GCC warning */
if (IS_SPI_FULL_INSTANCE(hspi->Instance))
{
if (count > SPI_HIGHEND_FIFO_SIZE)
{
return HAL_TIMEOUT;
}
}
else
{
if (count > SPI_LOWEND_FIFO_SIZE)
{
return HAL_TIMEOUT;
}
}
}
return HAL_OK;
}
/**
* @brief Enable the Lock for the AF configuration of associated IOs
* and write protect the Content of Configuration register 2
* when SPI is enabled
* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
* the configuration information for SPI module.
* @retval None
*/
HAL_StatusTypeDef HAL_SPIEx_EnableLockConfiguration(SPI_HandleTypeDef *hspi)
{
HAL_StatusTypeDef errorcode = HAL_OK;
/* Process Locked */
__HAL_LOCK(hspi);
if (hspi->State != HAL_SPI_STATE_READY)
{
errorcode = HAL_BUSY;
hspi->State = HAL_SPI_STATE_READY;
/* Process Unlocked */
__HAL_UNLOCK(hspi);
return errorcode;
}
/* Check if the SPI is disabled to edit IOLOCK bit */
if ((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE)
{
SET_BIT(hspi->Instance->CR1, SPI_CR1_IOLOCK);
}
else
{
/* Disable SPI peripheral */
__HAL_SPI_DISABLE(hspi);
SET_BIT(hspi->Instance->CR1, SPI_CR1_IOLOCK);
/* Enable SPI peripheral */
__HAL_SPI_ENABLE(hspi);
}
hspi->State = HAL_SPI_STATE_READY;
/* Process Unlocked */
__HAL_UNLOCK(hspi);
return errorcode;
}
/**
* @brief Configure the UNDERRUN condition and behavior of slave transmitter.
* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
* the configuration information for SPI module.
* @param UnderrunDetection : Detection of underrun condition at slave transmitter
* This parameter is not supported in this SPI version.
* It is kept in order to not break the compatibility.
* @param UnderrunBehaviour : Behavior of slave transmitter at underrun condition
* This parameter can be a value of @ref SPI_Underrun_Behaviour.
* @retval None
*/
HAL_StatusTypeDef HAL_SPIEx_ConfigureUnderrun(SPI_HandleTypeDef *hspi, uint32_t UnderrunDetection,
uint32_t UnderrunBehaviour)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(UnderrunDetection);
HAL_StatusTypeDef errorcode = HAL_OK;
/* Process Locked */
__HAL_LOCK(hspi);
/* Check State and Insure that Underrun configuration is managed only by Salve */
if ((hspi->State != HAL_SPI_STATE_READY) || (hspi->Init.Mode != SPI_MODE_SLAVE))
{
errorcode = HAL_BUSY;
hspi->State = HAL_SPI_STATE_READY;
/* Process Unlocked */
__HAL_UNLOCK(hspi);
return errorcode;
}
/* Check the parameters */
assert_param(IS_SPI_UNDERRUN_BEHAVIOUR(UnderrunBehaviour));
/* Check if the SPI is disabled to edit CFG1 register */
if ((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE)
{
/* Configure Underrun fields */
MODIFY_REG(hspi->Instance->CFG1, SPI_CFG1_UDRCFG, UnderrunBehaviour);
}
else
{
/* Disable SPI peripheral */
__HAL_SPI_DISABLE(hspi);
/* Configure Underrun fields */
MODIFY_REG(hspi->Instance->CFG1, SPI_CFG1_UDRCFG, UnderrunBehaviour);
/* Enable SPI peripheral */
__HAL_SPI_ENABLE(hspi);
}
hspi->State = HAL_SPI_STATE_READY;
/* Process Unlocked */
__HAL_UNLOCK(hspi);
return errorcode;
}
/**
* @brief Set Autonomous Mode configuration
* @param hspi Pointer to a SPI_HandleTypeDef structure that contains
* the configuration information for the specified SPIx peripheral.
* @param sConfig Pointer to a SPI_HandleTypeDef structure that contains
* the configuration information of the autonomous mode for the specified SPIx peripheral.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_SPIEx_SetConfigAutonomousMode(SPI_HandleTypeDef *hspi,
const SPI_AutonomousModeConfTypeDef *sConfig)
{
if (hspi->State == HAL_SPI_STATE_READY)
{
/* Process Locked */
__HAL_LOCK(hspi);
hspi->State = HAL_SPI_STATE_BUSY;
/* Check the parameters */
assert_param(IS_SPI_AUTONOMOUS_INSTANCE(hspi->Instance));
assert_param(IS_SPI_TRIG_SOURCE(hspi->Instance, sConfig->TriggerSelection));
assert_param(IS_SPI_AUTO_MODE_TRG_POL(sConfig->TriggerPolarity));
/* Disable the selected SPI peripheral to be able to configure AUTOCR */
__HAL_SPI_DISABLE(hspi);
/* SPIx AUTOCR Configuration */
WRITE_REG(hspi->Instance->AUTOCR, (sConfig->TriggerState | ((sConfig->TriggerSelection) & SPI_AUTOCR_TRIGSEL_Msk) |
sConfig->TriggerPolarity));
hspi->State = HAL_SPI_STATE_READY;
/* Process Unlocked */
__HAL_UNLOCK(hspi);
return HAL_OK;
}
else
{
return HAL_ERROR;
}
}
/**
* @brief Get Autonomous Mode configuration
* @param hspi Pointer to a SPI_HandleTypeDef structure that contains
* the configuration information for the specified SPIx peripheral.
* @param sConfig Pointer to a SPI_HandleTypeDef structure that contains
* the configuration information of the autonomous mode for the specified SPIx peripheral.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_SPIEx_GetConfigAutonomousMode(const SPI_HandleTypeDef *hspi,
SPI_AutonomousModeConfTypeDef *sConfig)
{
uint32_t autocr_tmp;
/* Check the parameters */
assert_param(IS_SPI_AUTONOMOUS_INSTANCE(hspi->Instance));
autocr_tmp = hspi->Instance->AUTOCR;
sConfig->TriggerState = (autocr_tmp & SPI_AUTOCR_TRIGEN);
if (IS_SPI_GRP2_INSTANCE(hspi->Instance))
{
sConfig->TriggerSelection = ((autocr_tmp & SPI_AUTOCR_TRIGSEL) | SPI_TRIG_GRP2);
}
else
{
sConfig->TriggerSelection = ((autocr_tmp & SPI_AUTOCR_TRIGSEL) | SPI_TRIG_GRP1);
}
sConfig->TriggerPolarity = (autocr_tmp & SPI_AUTOCR_TRIGPOL);
return HAL_OK;
}
/**
* @brief Clear Autonomous Mode configuration
* @param hspi Pointer to a SPI_HandleTypeDef structure that contains
* the configuration information for the specified SPIx peripheral.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_SPIEx_ClearConfigAutonomousMode(SPI_HandleTypeDef *hspi)
{
if (hspi->State == HAL_SPI_STATE_READY)
{
/* Process Locked */
__HAL_LOCK(hspi);
hspi->State = HAL_SPI_STATE_BUSY;
/* Check the parameters */
assert_param(IS_SPI_AUTONOMOUS_INSTANCE(hspi->Instance));
/* Disable the selected SPI peripheral to be able to clear AUTOCR */
__HAL_SPI_DISABLE(hspi);
CLEAR_REG(hspi->Instance->AUTOCR);
/* Enable the selected SPI peripheral */
__HAL_SPI_ENABLE(hspi);
hspi->State = HAL_SPI_STATE_READY;
/* Process Unlocked */
__HAL_UNLOCK(hspi);
return HAL_OK;
}
else
{
return HAL_ERROR;
}
}
/**
* @}
*/
/**
* @}
*/
#endif /* HAL_SPI_MODULE_ENABLED */
/**
* @}
*/
/**
* @}
*/

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