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ADS124S08 Bibliothek hinzugefügt, erste möglichkeit wie auswertung funktionieren könnte hinzugefügt, sollte aber noch weniger blockierend gemacht werden

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raphael stade
2026-01-09 23:00:37 +01:00
parent 3f9dd014de
commit c7e27f2219
134 changed files with 197450 additions and 0 deletions
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404
Software/Station_SW/Drivers/SmartBeeHive/ADS124S08/Inc/ADS124S08_Defines.h Normal file
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/*
* ADS124S08_defines.h
*
* Created on: Nov 10, 2024
* Author: zafst
*/
#ifndef INC_ADS124S08_DEFINES_H_
#define INC_ADS124S08_DEFINES_H_
#if defined ( __GNUC__ )
#ifndef __weak
#define __weak __attribute__((weak))
#endif /* __weak */
#endif
#define UNUSED(X) (void)X
#define ADS124S08_DATA_MIN_SIZE 3
#define ADS124S08_RESET_COMMAND 0x06
#define ADS124S08_READ_DATA_COMMAND 0x12
#define ADS124S08_START_CONVERSION_COMMAND 0x09
#define ADS124S08_STOP_CONVERSION_COMMAND 0x0B
#define ADS124S08_SFOCAL_COMMAND 0x19
#define ADS124S08_SYOCAL_COMMAND 0x16
typedef enum ADS124S08_State
{
ADS124S08_OK,
ADS124S08_ERROR,
}e_ADS124S08_State;
typedef enum ADS124S08_ChipID
{
ADS124S08_ID0,
ADS124S08_ID1,
ADS124S08_ID2,
ADS124S08_ID3,
ADS124S08_MAX_NUM_CHIPS,
}e_ADS124S08_ChipID;
typedef enum ADS124S08_CS_State
{
CS_SELECTED,
CS_NOT_SELECTED,
}e_ADS124S08_CS_State;
enum ADS124S08_RegisterMap
{
REG_ADS124S08_DEVICE_ID,
REG_ADS124S08_DEVICE_STATUS,
REG_ADS124S08_INPUT_MUX,
REG_ADS124S08_GAIN_SETTINGS,
REG_ADS124S08_DATA_RATE,
REG_ADS124S08_REFERENCE_CONTROL,
REG_ADS124S08_EXCITATION_CURRENT_1,
REG_ADS124S08_EXCITATION_CURRENT_2,
REG_ADS124S08_SENSOR_BIASING,
REG_ADS124S08_SYSTEM_CONTROL,
REG_ADS124S08_OFFSET_CALIBRATION_1,
REG_ADS124S08_OFFSET_CALIBRATION_2,
REG_ADS124S08_OFFSET_CALIBRATION_3,
REG_ADS124S08_GAIN_CALIBRATION_1,
REG_ADS124S08_GAIN_CALIBRATION_2,
REG_ADS124S08_GAIN_CALIBRATION_3,
REG_ADS124S08_GPIO_DATA,
REG_ADS124S08_GPIO_CONFIGURATION,
};
#define ADS124S08_DEVICE_ID_MASK 0b00000111
enum ADS124S08_DEVICE_ID
{
ADS124S08_DEVICE_ID_S08,
ADS124S08_DEVICE_ID_S06,
};
enum ADS124S08_DEVICE_STATUS_FLAGS
{
ADS124S08_FLAG_REF_MON_LVL_0,
ADS124S08_FLAG_REF_MON_LVL_1,
ADS124S08_FLAG_NEG_PGA_OUT_NEG_RAIL,
ADS124S08_FLAG_NEG_PGA_OUT_POS_RAIL,
ADS124S08_FLAG_POS_PGA_OUT_NEG_RAIL,
ADS124S08_FLAG_POS_PGA_OUT_POS_RAIL,
ADS124S08_FLAG_NOT_RDY,
ADS124S08_FLAG_POR,
};
#define ADS124S08_NEGATIVE_IN_SEL_CLEAR_MASK 0b11110000
#define ADS124S08_NEGATIVE_IN_SEL_BASE_SHIFT 0
typedef enum ADS124S08_NEG_IN_SEL
{
ADS124S08_NEG_IN_AIN_0,
ADS124S08_NEG_IN_AIN_1,
ADS124S08_NEG_IN_AIN_2,
ADS124S08_NEG_IN_AIN_3,
ADS124S08_NEG_IN_AIN_4,
ADS124S08_NEG_IN_AIN_5,
ADS124S08_NEG_IN_AIN_6,
ADS124S08_NEG_IN_AIN_7,
ADS124S08_NEG_IN_AIN_8,
ADS124S08_NEG_IN_AIN_9,
ADS124S08_NEG_IN_AIN_10,
ADS124S08_NEG_IN_AIN_11,
ADS124S08_NEG_IN_AIN_COM,
}e_ADS124S08_NEG_IN_SEL;
#define ADS124S08_POSITIVE_IN_SEL_CLEAR_MASK 0b00001111
#define ADS124S08_POSITIVE_IN_SEL_BASE_SHIFT 4
typedef enum ADS124S08_POSITIVE_IN_SEL
{
ADS124S08_POS_IN_AIN_0,
ADS124S08_POS_IN_AIN_1,
ADS124S08_POS_IN_AIN_2,
ADS124S08_POS_IN_AIN_3,
ADS124S08_POS_IN_AIN_4,
ADS124S08_POS_IN_AIN_5,
ADS124S08_POS_IN_AIN_6,
ADS124S08_POS_IN_AIN_7,
ADS124S08_POS_IN_AIN_8,
ADS124S08_POS_IN_AIN_9,
ADS124S08_POS_IN_AIN_10,
ADS124S08_POS_IN_AIN_11,
ADS124S08_POS_IN_AIN_COM,
}e_ADS124S08_POS_IN_SEL;
#define ADS124S08_PGA_GAIN_CLEAR_MASK 0b11111000
#define ADS124S08_PGA_GAIN_BASE_SHIFT 0
typedef enum ADS124S08_GAIN_SETTING
{
ADS124S08_GAIN_1,
ADS124S08_GAIN_2,
ADS124S08_GAIN_4,
ADS124S08_GAIN_8,
ADS124S08_GAIN_16,
ADS124S08_GAIN_32,
ADS124S08_GAIN_64,
ADS124S08_GAIN_128,
}e_ADS124S08_GAIN_SETTING;
#define ADS124S08_PGA_MODE_CLEAR_MASK 0b11110111
#define ADS124S08_PGA_MODE_BASE_SHIFT 3
typedef enum ADS124S08_PGA_MODE
{
ADS124S08_PGA_DISABLED,
ADS124S08_PGA_ENABLED,
}e_ADS124S08_PGA_MODE;
#define ADS124S08_PROG_CONV_DELAY_CLEAR_MASK 0b00011111
#define ADS124S08_PROG_CONV_DELAY_BASE_SHIFT 5
typedef enum ADS124S08_PROG_CONV_DELAY
{
ADS124S08_PROG_CONV_DELAY_14_x_tMOD,
ADS124S08_PROG_CONV_DELAY_25_x_tMOD,
ADS124S08_PROG_CONV_DELAY_64_x_tMOD,
ADS124S08_PROG_CONV_DELAY_256_x_tMOD,
ADS124S08_PROG_CONV_DELAY_1024_x_tMOD,
ADS124S08_PROG_CONV_DELAY_2048_x_tMOD,
ADS124S08_PROG_CONV_DELAY_4096_x_tMOD,
ADS124S08_PROG_CONV_DELAY_1_x_tMOD,
}e_ADS124S08_PROG_CONV_DELAY;
#define ADS124S08_DATA_RATE_CLEAR_MASK 0b11110000
#define ADS124S08_DATA_RATE_BASE_SHIFT 0
typedef enum ADS124S08_DATA_RATE
{
ADS124S08_DATA_RATE_2_5SPS,
ADS124S08_DATA_RATE_5SPS,
ADS124S08_DATA_RATE_10SPS,
ADS124S08_DATA_RATE_16_6SPS,
ADS124S08_DATA_RATE_20SPS,
ADS124S08_DATA_RATE_50SPS,
ADS124S08_DATA_RATE_60SPS,
ADS124S08_DATA_RATE_100SPS,
ADS124S08_DATA_RATE_200SPS,
ADS124S08_DATA_RATE_400SPS,
ADS124S08_DATA_RATE_800SPS,
ADS124S08_DATA_RATE_1000SPS,
ADS124S08_DATA_RATE_2000SPS,
ADS124S08_DATA_RATE_4000SPS,
}e_ADS124S08_DATA_RATE;
#define ADS124S08_SEL_FILTER_CLEAR_MASK 0b11101111
#define ADS124S08_SEL_FILTER_MODE_BASE_SHIFT 4
typedef enum ADS124S08_FILTER_MODE
{
ADS124S08_FILTER_MODE_SINC3,
ADS124S08_FILTER_MODE_LOW_LATENCY,
}ADS124S08_FILTER_MODE;
#define ADS124S08_CONV_MODE_CLEAR_MASK 0b11011111
#define ADS124S08_CONV_MODE_BASE_SHIFT 5
typedef enum ADS124S08_CONV_MODE
{
ADS124S08_CONV_MODE_CONTINOUS,
ADS124S08_CONV_MODE_SINGLE,
}e_ADS124S08_CONV_MODE;
#define ADS124S08_SEL_CLOCK_CLEAR_MASK 0b10111111
#define ADS124S08_SEL_CLOCK_BASE_SHIFT 6
typedef enum ADS124S08_CLOCK_MODE
{
ADS124S08_CLOCK_MODE_INTERNAL,
ADS124S08_CLOCK_MODE_EXTERNAL,
}e_ADS124S08_CLOCK_MODE;
#define ADS124S08_GLOBAL_CHOP_MODE_CLEAR_MASK 0b01111111
#define ADS124S08_GLOBAL_CHOP_MODE_BASE_SHIFT 7
typedef enum ADS124S08_GLOBAL_CHOP_MODE
{
ADS124S08_GLOBAL_CHOP_MODE_DISABLED,
ADS124S08_GLOBAL_CHOP_MODE_ENABLED,
}e_ADS124S08_GLOBAL_CHOP_MODE;
#define ADS124S08_INTERNAL_REFERENCE_CONF_CLEAR_MASK 0b11111100
#define ADS124S08_INTERNAL_REFERENCE_CONF_BASE_SHIFT 0
typedef enum ADS124S08_INTERNAL_REFERENCE_CONFIGURATION
{
ADS124S08_INTERNAL_REFERENCE_OFF,
ADS124S08_INTERNAL_REFERENCE_ON_OFF_IN_POWERDOWN,
ADS124S08_INTERNAL_REFERENCE_ALWAYS_ON,
}e_ADS124S08_INTERNAL_REFERENCE_CONFIGURATION;
#define ADS124S08_REFERENCE_IN_SEL_CLEAR_MASK 0b11110011
#define ADS124S08_REFERENCE_IN_SEL_BASE_SHIFT 2
typedef enum ADS124S08_REFERENCE_IN_SEL
{
ADS124S08_REFERENCE_IN_REFP0_REFN0,
ADS124S08_REFERENCE_IN_REFP1_REFN1,
ADS124S08_REFERENCE_IN_INTERNAL_2_5,
}e_ADS124S08_REFERENCE_IN_SEL;
#define ADS124S08_REFN_BUFFER_BYPASS_CLEAR_MASK 0b11101111
#define ADS124S08_REFN_BUFFER_BYPASS_BASE_SHIFT 4
typedef enum ADS124S08_REFN_BUFFER_MODE
{
ADS124S08_REFN_BUFFER_BYPASSED,
ADS124S08_REFN_BUFFER_NOT_BYPASSED,
}e_ADS124S08_REFN_BUFFER_MODE;
#define ADS124S08_REFP_BUFFER_BYPASS_CLEAR_MASK 0b11011111
#define ADS124S08_REFP_BUFFER_BYPASS_BASE_SHIFT 5
typedef enum ADS124S08_REFP_BUFFER_MODE
{
ADS124S08_REFP_BUFFER_BYPASSED,
ADS124S08_REFP_BUFFER_NOT_BYPASSED,
}e_ADS124S08_REFP_BUFFER_MODE;
#define ADS124S08_REFERENCE_MON_MODE_CLEAR_MASK 0b00111111
#define ADS124S08_REFERENCE_MON_MODE_BASE_SHIFT 6
typedef enum ADS124S08_REFERENCE_MONITOR_MODE
{
ADS124S08_REFERENCE_MONITOR_DISABLED,
ADS124S08_REFERENCE_MONITOR_L0_ENABLED,
ADS124S08_REFERENCE_MONITOR_L0_L1_ENABLED,
}e_ADS124S08_REFERENCE_MONITOR_MODE;
#define ADS124S08_SET_EXCITATION_CURRENT_CLEAR_MASK 0b11110000
#define ADS124S08_SET_EXCITATION_CURRENT_BASE_SHIFT 0
typedef enum ADS124S08_EXCITATION_CURRENT
{
ADS124S08_EXCITATION_CURRENT_OFF,
ADS124S08_EXCITATION_CURRENT_10_µA,
ADS124S08_EXCITATION_CURRENT_50_µA,
ADS124S08_EXCITATION_CURRENT_100_µA,
ADS124S08_EXCITATION_CURRENT_250_µA,
ADS124S08_EXCITATION_CURRENT_500_µA,
ADS124S08_EXCITATION_CURRENT_750_µA,
ADS124S08_EXCITATION_CURRENT_1000_µA,
ADS124S08_EXCITATION_CURRENT_1500_µA,
ADS124S08_EXCITATION_CURRENT_2000_µA,
}e_ADS124S08_EXCITATION_CURRENT;
#define ADS124S08_IDAC_1_OUTPUT_CLEAR_MASK 0b11110000
#define ADS124S08_IDAC_1_OUTPUT_BASE_SHIFT 0
#define ADS124S08_IDAC_2_OUTPUT_CLEAR_MASK 0b00001111
#define ADS124S08_IDAC_2_OUTPUT_BASE_SHIFT 4
typedef enum ADS124S08_IDAC_CHANNEL
{
ADS124S08_IDAC_CHANNEL_1,
ADS124S08_IDAC_CHANNEL_2
}e_ADS124S08_IDAC_CHANNEL;
typedef enum ADS124S08_IDAC_OUTPUT
{
ADS124S08_IDAC_OUTPUT_AIN_0,
ADS124S08_IDAC_OUTPUT_AIN_1,
ADS124S08_IDAC_OUTPUT_AIN_2,
ADS124S08_IDAC_OUTPUT_AIN_3,
ADS124S08_IDAC_OUTPUT_AIN_4,
ADS124S08_IDAC_OUTPUT_AIN_5,
ADS124S08_IDAC_OUTPUT_AIN_6,
ADS124S08_IDAC_OUTPUT_AIN_7,
ADS124S08_IDAC_OUTPUT_AIN_8,
ADS124S08_IDAC_OUTPUT_AIN_9,
ADS124S08_IDAC_OUTPUT_AIN_10,
ADS124S08_IDAC_OUTPUT_AIN_11,
ADS124S08_IDAC_OUTPUT_AINCOM,
ADS124S08_IDAC_OUTPUT_DISCONNECTED,
}e_ADS124S08_IDAC_OUTPUT;
#define ADS124S08_VBIAS_LEVEL_CLEAR_MASK 0b10000000
#define ADS124S08_VBIAS_LEVEL_BASE_SHIFT 7
typedef enum ADS124S08_VBIAS_LEVEL
{
ADS124S08_VBIAS_LEVEL_AVDD_AVSS_2,
ADS124S08_VBIAS_LEVEL_AVDD_AVSS_12,
}e_ADS124S08_VBIAS_LEVEL;
typedef enum ADS124S08_VBIAS_ENABLE_ON_CHANNEL
{
ADS124S08_ENABLED_ON_CHANNEL,
ADS124S08_DISABLED_ON_CHANNEL,
}e_ADS124S08_VBIAS_ENABLE_ON_CHANNEL;
typedef enum ADS124S08_VBIAS_CHANNEL
{
ADS124S08_VBIAS_CHANNEL_AIN_0,
ADS124S08_VBIAS_CHANNEL_AIN_1,
ADS124S08_VBIAS_CHANNEL_AIN_2,
ADS124S08_VBIAS_CHANNEL_AIN_3,
ADS124S08_VBIAS_CHANNEL_AIN_4,
ADS124S08_VBIAS_CHANNEL_AIN_5,
ADS124S08_VBIAS_CHANNEL_AINCOM,
}e_ADS124S08_VBIAS_CHANNEL;
#define ADS124S08_ENABLE_SEND_STAT_CLEAR_MASK 0b11111110
#define ADS124S08_ENABLE_SEND_STAT_BASE_SHIFT 0
typedef enum ADS124S08_SEND_STAT
{
ADS124S08_SEND_STAT_DISABLED,
ADS124S08_SEND_STAT_ENABLED,
}e_ADS124S08_SEND_STAT;
#define ADS124S08_ENABLE_CRC_CLEAR_MASK 0b11111101
#define ADS124S08_ENABLE_CRC_BASE_SHIFT 1
typedef enum ADS124S08_SEND_CRC
{
ADS124S08_SEND_CRC_DISABLED,
ADS124S08_SEND_CRC_ENABLED,
}e_ADS124S08_SEND_CRC;
#define ADS124S08_SPI_TIMEOUT_ENABLE_CLEAR_MASK 0b11111011
#define ADS124S08_SPI_TIMEOUT_ENABLE_BASE_SHIFT 2
typedef enum ADS124S08_ENABLED_SPI_TIMEOUT
{
ADS124S08_SPI_TIMEOUT_DISABLED,
ADS124S08_SPI_TIMEOUT_ENABLED,
}e_ADS124S08_ENABLE_SPI_TIMEOUT;
#define ADS124S08_CAL_SAMPLES_CLEAR_MASK 0b00011000
#define ADS124S08_CAL_SAMPLES_BASE_SHIFT 3
typedef enum ADS124S08_CAL_SAMPLES
{
ADS124S08_CAL_SAMPLES_1,
ADS124S08_CAL_SAMPLES_4,
ADS124S08_CAL_SAMPLES_8,
ADS124S08_CAL_SAMPLES_16,
}e_ADS124S08_CAL_SAMPLES;
/*SYS_MON tbd*/
#endif /* INC_ADS124S08_DEFINES_H_ */

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Software/Station_SW/Drivers/SmartBeeHive/ADS124S08/Inc/ADS124S08_LIB.h Normal file
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/*
* ADS124S08_LIB.h
*
* Created on: Nov 10, 2024
* Author: zafst
*/
#ifndef INC_ADS124S08_LIB_H_
#define INC_ADS124S08_LIB_H_
#include "ADS124S08_Defines.h"
#include <stdint.h>
e_ADS124S08_State ADS124S08_INIT(e_ADS124S08_ChipID ChipID);
e_ADS124S08_State ADS124S08_RESET(e_ADS124S08_ChipID ChipID);
e_ADS124S08_State ADS124S08_START_CONVERSION(e_ADS124S08_ChipID ChipID);
e_ADS124S08_State ADS124S08_STOP_CONVERSION(e_ADS124S08_ChipID ChipID);
e_ADS124S08_State ADS124S08_PERFORM_SFOCAL(e_ADS124S08_ChipID ChipID);
e_ADS124S08_State ADS124S08_PERFORM_SYOCAL(e_ADS124S08_ChipID ChipID);
e_ADS124S08_State ADS124S08_SET_POSITIVE_ANALOG_INPUT_CHANNEL(e_ADS124S08_ChipID ChipID,e_ADS124S08_POS_IN_SEL POS_IN);
e_ADS124S08_State ADS124S08_SET_NEGATIVE_ANALOG_INPUT_CHANNEL(e_ADS124S08_ChipID ChipID,e_ADS124S08_NEG_IN_SEL NEG_IN);
e_ADS124S08_State ADS124S08_SET_PGA_SETTINGS(e_ADS124S08_ChipID ChipID,e_ADS124S08_PROG_CONV_DELAY Delay,e_ADS124S08_PGA_MODE Mode,e_ADS124S08_GAIN_SETTING Gain);
e_ADS124S08_State ADS124S08_SET_DATA_RATE(e_ADS124S08_ChipID ChipID,e_ADS124S08_DATA_RATE DataRate);
e_ADS124S08_State ADS124S08_SET_FILTER_MODE(e_ADS124S08_ChipID ChipID,ADS124S08_FILTER_MODE Mode);
e_ADS124S08_State ADS124S08_SET_CONV_MODE(e_ADS124S08_ChipID ChipID,e_ADS124S08_CONV_MODE Mode);
e_ADS124S08_State ADS124S08_SET_CLOCK_MODE(e_ADS124S08_ChipID ChipID,e_ADS124S08_CLOCK_MODE Mode);
e_ADS124S08_State ADS124S08_SET_CHOP_MODE(e_ADS124S08_ChipID ChipID,e_ADS124S08_GLOBAL_CHOP_MODE Mode);
e_ADS124S08_State ADS124S08_SET_REFERENCE_SETTINGS(e_ADS124S08_ChipID ChipID,e_ADS124S08_INTERNAL_REFERENCE_CONFIGURATION Int_Ref_Conv,e_ADS124S08_REFERENCE_IN_SEL Ref_In_Sel,e_ADS124S08_REFN_BUFFER_MODE Ref_N_Buf_Mode,e_ADS124S08_REFP_BUFFER_MODE Ref_P_Buf_Mode,e_ADS124S08_REFERENCE_MONITOR_MODE Ref_Mon_Mode);
e_ADS124S08_State ADS124S08_SET_EXCITATION_CURRENT(e_ADS124S08_ChipID ChipID, e_ADS124S08_EXCITATION_CURRENT Current);
e_ADS124S08_State ADS124S08_SET_IDAC_OUTPUT(e_ADS124S08_ChipID ChipID,e_ADS124S08_IDAC_CHANNEL Channel, e_ADS124S08_IDAC_OUTPUT Output);
e_ADS124S08_State ADS124S08_SYSTEM_CONTROL(e_ADS124S08_ChipID ChipID,e_ADS124S08_SEND_STAT SendStat,e_ADS124S08_SEND_CRC SendCRC, e_ADS124S08_ENABLE_SPI_TIMEOUT SpiTimeout,e_ADS124S08_CAL_SAMPLES CalSamples);
e_ADS124S08_State ADS124S08_DRDY_CALLBACK(e_ADS124S08_ChipID ChipID);
e_ADS124S08_State ADS124S08_DATA_READY_INTERRUPT(e_ADS124S08_ChipID ChipID); //extern aufrufen wenn Interrupt kommt
e_ADS124S08_State ADS124S08_DATA_READ_CALLBACK(e_ADS124S08_ChipID ChipID,int32_t Data,uint8_t Status);
#endif /* INC_ADS124S08_LIB_H_ */

20
Software/Station_SW/Drivers/SmartBeeHive/ADS124S08/Inc/ADS124S08_Port.h Normal file
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/*
* ADS124S08_port.h
*
* Created on: Nov 10, 2024
* Author: zafst
*/
#ifndef INC_ADS124S08_PORT_H_
#define INC_ADS124S08_PORT_H_
#include <stdint.h>
#include "ADS124S08_Defines.h"
e_ADS124S08_State ADS124S08_PORT_Read_Register(e_ADS124S08_ChipID ChipID, uint8_t* CommandData,uint8_t NumRegs,uint8_t* Data);
e_ADS124S08_State ADS124S08_PORT_Read_Data(e_ADS124S08_ChipID ChipID, uint8_t Command, uint8_t* Data, uint8_t size);
e_ADS124S08_State ADS124S08_PORT_Write_Register(e_ADS124S08_ChipID ChipID, uint8_t *CommandData, uint8_t NumRegs,uint8_t* Data);
e_ADS124S08_State ADS124S08_PORT_CHECK_CRC(uint8_t* Data,uint8_t size,uint8_t CRC_DATA);
e_ADS124S08_State ADS124S08_PORT_SEND_COMMAND(e_ADS124S08_ChipID ChipID, uint8_t Command);
#endif /* INC_ADS124S08_PORT_H_ */

926
Software/Station_SW/Drivers/SmartBeeHive/ADS124S08/Src/ADS124S08_LIB.c Normal file
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/*
* ADS124S08_LIB.c
*
* Created on: Nov 10, 2024
* Author: zafst
*/
#include "ADS124S08_LIB.h"
#include "ADS124S08_Port.h"
typedef enum ADS124S08_INIT_STATE
{
ADS124S08_NOT_INITIALIZED,
ADS124S08_INITIALIZED,
}e_ADS124S08_INIT_STATE;
e_ADS124S08_INIT_STATE InitStates[ADS124S08_MAX_NUM_CHIPS] = {ADS124S08_NOT_INITIALIZED};
e_ADS124S08_SEND_CRC SendCRCEnabled[ADS124S08_MAX_NUM_CHIPS] = {ADS124S08_SEND_CRC_DISABLED};
e_ADS124S08_SEND_STAT SendStatEnabled[ADS124S08_MAX_NUM_CHIPS] = {ADS124S08_SEND_STAT_DISABLED};
/* Data Handling Functions*/
e_ADS124S08_State ADS124S08_Read_Data(e_ADS124S08_ChipID ChipID,uint8_t* Data,uint8_t size)
{
uint8_t Command = ADS124S08_READ_DATA_COMMAND;
if(ADS124S08_PORT_Read_Data(ChipID, Command, Data, size) == ADS124S08_OK)
{
return ADS124S08_OK;
}
else
{
return ADS124S08_ERROR;
}
}
e_ADS124S08_State ADS124S08_Read_Register(e_ADS124S08_ChipID ChipID,uint8_t RegAddres,uint8_t NumRegs,uint8_t* Data)
{
uint8_t CommandData[2] = {0};
CommandData[0] = (RegAddres | 0b00100000);
CommandData[1] = (NumRegs) & 0b00011111; // mit und verknüpfen um auf max Register zu Begrenzen
if(ADS124S08_PORT_Read_Register(ChipID, CommandData, NumRegs, Data) == ADS124S08_OK)
{
return ADS124S08_OK;
}
else
{
return ADS124S08_ERROR;
}
}
e_ADS124S08_State ADS124S08_Write_Register(e_ADS124S08_ChipID ChipID,uint8_t RegAddres,uint8_t NumRegs,uint8_t* Data)
{
uint8_t CommandData[2] = {0};
CommandData[0] = (RegAddres | 0b01000000);
CommandData[1] = (NumRegs) & 0b00011111; // mit und verknüpfen um auf max Register zu Begrenzen
if(ADS124S08_PORT_Write_Register(ChipID, CommandData, NumRegs, Data) == ADS124S08_OK)
{
return ADS124S08_OK;
}
else
{
return ADS124S08_ERROR;
}
}
e_ADS124S08_State ADS124S08_DATA_READY_INTERRUPT(e_ADS124S08_ChipID ChipID)
{
if(ChipID < ADS124S08_MAX_NUM_CHIPS)
{
if(InitStates[ChipID] == ADS124S08_INITIALIZED)
{
uint8_t ADC_DATA_SIZE = ADS124S08_DATA_MIN_SIZE;
int32_t ADC_RAW_DATA = 0;
uint8_t ADC_STATUS = 0;
uint8_t ADC_CRC = 0;
switch(SendStatEnabled[ChipID])
{
case ADS124S08_SEND_STAT_DISABLED:
{
break;
}
case ADS124S08_SEND_STAT_ENABLED:
{
ADC_DATA_SIZE++;
break;
}
}
switch(SendCRCEnabled[ChipID])
{
case ADS124S08_SEND_CRC_DISABLED:
{
break;
}
case ADS124S08_SEND_CRC_ENABLED:
{
ADC_DATA_SIZE++;
break;
}
}
uint8_t ADC_DATA[ADC_DATA_SIZE];
for(uint_fast8_t i = 0; i< ADC_DATA_SIZE;i++) // Sicherheitshalber mit 0 initialisieren
{
ADC_DATA[i] = 0;
}
if(ADS124S08_Read_Data(ChipID, ADC_DATA,ADC_DATA_SIZE) == ADS124S08_OK)
{
if(SendCRCEnabled[ChipID] == ADS124S08_SEND_CRC_ENABLED)
{
if(ADS124S08_PORT_CHECK_CRC(ADC_DATA, ADC_DATA_SIZE-1,ADC_CRC) == ADS124S08_OK)
{
if(SendStatEnabled[ChipID] == ADS124S08_SEND_STAT_ENABLED)
{
ADC_STATUS = ADC_DATA[0];
ADC_RAW_DATA = ADC_DATA[1]<<16 | ADC_DATA[2]<<8 | ADC_DATA[3];
if(ADC_RAW_DATA & 0x800000)
{
ADC_RAW_DATA = ADC_RAW_DATA | 0xFF000000;
}
else
{
ADC_RAW_DATA = ADC_RAW_DATA;
}
ADS124S08_DATA_READ_CALLBACK(ChipID, ADC_RAW_DATA, ADC_STATUS);
return ADS124S08_OK;
}
else
{
ADC_RAW_DATA = ADC_DATA[0]<<16 | ADC_DATA[1]<<8 | ADC_DATA[2];
if(ADC_RAW_DATA & 0x800000)
{
ADC_RAW_DATA = ADC_RAW_DATA | 0xFF000000;
}
else
{
ADC_RAW_DATA = ADC_RAW_DATA;
}
ADS124S08_DATA_READ_CALLBACK(ChipID, ADC_RAW_DATA, ADC_STATUS);
return ADS124S08_OK;
}
}
else
{
return ADS124S08_ERROR;
}
}
else
{
if(SendStatEnabled[ChipID] == ADS124S08_SEND_STAT_ENABLED)
{
ADC_STATUS = ADC_DATA[0];
ADC_RAW_DATA = ADC_DATA[1]<<16 | ADC_DATA[2]<<8 | ADC_DATA[3];
if(ADC_RAW_DATA & 0x800000)
{
ADC_RAW_DATA = ADC_RAW_DATA | 0xFF000000;
}
else
{
ADC_RAW_DATA = ADC_RAW_DATA;
}
ADS124S08_DATA_READ_CALLBACK(ChipID, ADC_RAW_DATA, ADC_STATUS);
return ADS124S08_OK;
}
else
{
ADC_RAW_DATA = ADC_DATA[0]<<16 | ADC_DATA[1]<<8 | ADC_DATA[2];
if(ADC_RAW_DATA & 0x800000)
{
ADC_RAW_DATA = ADC_RAW_DATA | 0xFF000000;
}
else
{
ADC_RAW_DATA = ADC_RAW_DATA;
}
ADS124S08_DATA_READ_CALLBACK(ChipID, ADC_RAW_DATA, ADC_STATUS);
return ADS124S08_OK;
}
}
}
else
{
return ADS124S08_ERROR;
}
}
else
{
return ADS124S08_ERROR;
}
}
else
{
return ADS124S08_ERROR;
}
}
__weak e_ADS124S08_State ADS124S08_DATA_READ_CALLBACK(e_ADS124S08_ChipID ChipID,int32_t Data,uint8_t Status)
{
UNUSED(ChipID);
UNUSED(Data);
return ADS124S08_OK;
}
e_ADS124S08_State ADS124S08_SET_POSITIVE_ANALOG_INPUT_CHANNEL(e_ADS124S08_ChipID ChipID,e_ADS124S08_POS_IN_SEL POS_IN)
{
if(ChipID < ADS124S08_MAX_NUM_CHIPS)
{
if(InitStates[ChipID] == ADS124S08_INITIALIZED)
{
if(POS_IN <= ADS124S08_POS_IN_AIN_COM)
{
uint8_t tempReg = 0;
if(ADS124S08_Read_Register(ChipID, REG_ADS124S08_INPUT_MUX, 1, &tempReg) == ADS124S08_OK)
{
tempReg = tempReg & ADS124S08_POSITIVE_IN_SEL_CLEAR_MASK; //Positiv IN Einstellung loeschen
tempReg = tempReg | (POS_IN << ADS124S08_POSITIVE_IN_SEL_BASE_SHIFT); //Neuen Kanal Wählen
if(ADS124S08_Write_Register(ChipID, REG_ADS124S08_INPUT_MUX, 1, &tempReg) == ADS124S08_OK)
{
return ADS124S08_OK;
}
else
{
return ADS124S08_ERROR; // Fehler Register schreiben
}
}
else
{
return ADS124S08_ERROR; //Fehler inputmux Register Lesen
}
}
else
{
return ADS124S08_ERROR; // Fehler Eingang auserhalb erlaubten Berich
}
}
else
{
return ADS124S08_ERROR; //Fehler ADC nicht Initialisiert
}
}
else
{
return ADS124S08_ERROR; //Fehler ChipID auserhalb erlaubten Bereich
}
}
e_ADS124S08_State ADS124S08_SET_NEGATIVE_ANALOG_INPUT_CHANNEL(e_ADS124S08_ChipID ChipID,e_ADS124S08_NEG_IN_SEL NEG_IN)
{
if(ChipID < ADS124S08_MAX_NUM_CHIPS)
{
if(InitStates[ChipID] == ADS124S08_INITIALIZED)
{
if(NEG_IN <= ADS124S08_NEG_IN_AIN_COM)
{
uint8_t tempReg = 0;
if(ADS124S08_Read_Register(ChipID, REG_ADS124S08_INPUT_MUX, 1, &tempReg) == ADS124S08_OK)
{
tempReg = tempReg & ADS124S08_NEGATIVE_IN_SEL_CLEAR_MASK; //Negativ IN Einstellung loeschen
tempReg = tempReg | (NEG_IN << ADS124S08_NEGATIVE_IN_SEL_BASE_SHIFT); //Neuen Kanal Wählen
if(ADS124S08_Write_Register(ChipID, REG_ADS124S08_INPUT_MUX, 1, &tempReg) == ADS124S08_OK)
{
return ADS124S08_OK;
}
else
{
return ADS124S08_ERROR; // Fehler Register schreiben
}
}
else
{
return ADS124S08_ERROR; //Fehler inputmux Register Lesen
}
}
else
{
return ADS124S08_ERROR; // Fehler Eingang auserhalb erlaubten Berich
}
}
else
{
return ADS124S08_ERROR; //Fehler ADC nicht Initialisiert
}
}
else
{
return ADS124S08_ERROR; //Fehler ChipID auserhalb erlaubten Bereich
}
}
e_ADS124S08_State ADS124S08_SET_PGA_SETTINGS(e_ADS124S08_ChipID ChipID,e_ADS124S08_PROG_CONV_DELAY Delay,e_ADS124S08_PGA_MODE Mode,e_ADS124S08_GAIN_SETTING Gain)
{
if(ChipID < ADS124S08_MAX_NUM_CHIPS)
{
if(InitStates[ChipID] == ADS124S08_INITIALIZED)
{
uint8_t tempReg = 0;
tempReg = tempReg | Delay << ADS124S08_PROG_CONV_DELAY_BASE_SHIFT;
tempReg = tempReg | Mode << ADS124S08_PGA_MODE_BASE_SHIFT;
tempReg = tempReg | Gain << ADS124S08_PGA_GAIN_BASE_SHIFT;
if(ADS124S08_Write_Register(ChipID, REG_ADS124S08_GAIN_SETTINGS, 1, &tempReg) == ADS124S08_OK)
{
return ADS124S08_OK;
}
else
{
return ADS124S08_ERROR;
}
}
else
{
return ADS124S08_ERROR;
}
}
else
{
return ADS124S08_ERROR;
}
}
e_ADS124S08_State ADS124S08_SET_DATA_RATE(e_ADS124S08_ChipID ChipID,e_ADS124S08_DATA_RATE DataRate)
{
if(ChipID < ADS124S08_MAX_NUM_CHIPS)
{
if(InitStates[ChipID] == ADS124S08_INITIALIZED)
{
uint8_t tempReg = 0;
if(ADS124S08_Read_Register(ChipID, REG_ADS124S08_DATA_RATE, 1, &tempReg) == ADS124S08_OK)
{
tempReg = tempReg & ADS124S08_DATA_RATE_CLEAR_MASK;
tempReg = tempReg | DataRate << ADS124S08_DATA_RATE_BASE_SHIFT;
if(ADS124S08_Write_Register(ChipID, REG_ADS124S08_DATA_RATE, 1, &tempReg) == ADS124S08_OK)
{
return ADS124S08_OK;
}
else
{
return ADS124S08_ERROR;
}
}
else
{
return ADS124S08_ERROR;
}
}
else
{
return ADS124S08_ERROR;
}
}
else
{
return ADS124S08_ERROR;
}
}
e_ADS124S08_State ADS124S08_SET_FILTER_MODE(e_ADS124S08_ChipID ChipID,ADS124S08_FILTER_MODE Mode)
{
if(ChipID < ADS124S08_MAX_NUM_CHIPS)
{
if(InitStates[ChipID] == ADS124S08_INITIALIZED)
{
uint8_t tempReg = 0;
if(ADS124S08_Read_Register(ChipID, REG_ADS124S08_DATA_RATE, 1, &tempReg) == ADS124S08_OK)
{
tempReg = tempReg & ADS124S08_SEL_FILTER_CLEAR_MASK;
tempReg = tempReg | Mode << ADS124S08_SEL_FILTER_MODE_BASE_SHIFT;
if(ADS124S08_Write_Register(ChipID, REG_ADS124S08_DATA_RATE, 1, &tempReg) == ADS124S08_OK)
{
return ADS124S08_OK;
}
else
{
return ADS124S08_ERROR;
}
}
else
{
return ADS124S08_ERROR;
}
}
else
{
return ADS124S08_ERROR;
}
}
else
{
return ADS124S08_ERROR;
}
}
e_ADS124S08_State ADS124S08_SET_CONV_MODE(e_ADS124S08_ChipID ChipID,e_ADS124S08_CONV_MODE Mode)
{
if(ChipID < ADS124S08_MAX_NUM_CHIPS)
{
if(InitStates[ChipID] == ADS124S08_INITIALIZED)
{
uint8_t tempReg = 0;
if(ADS124S08_Read_Register(ChipID, REG_ADS124S08_DATA_RATE, 1, &tempReg) == ADS124S08_OK)
{
tempReg = tempReg & ADS124S08_CONV_MODE_CLEAR_MASK;
tempReg = tempReg | Mode << ADS124S08_CONV_MODE_BASE_SHIFT;
if(ADS124S08_Write_Register(ChipID, REG_ADS124S08_DATA_RATE, 1, &tempReg) == ADS124S08_OK)
{
return ADS124S08_OK;
}
else
{
return ADS124S08_ERROR;
}
}
else
{
return ADS124S08_ERROR;
}
}
else
{
return ADS124S08_ERROR;
}
}
else
{
return ADS124S08_ERROR;
}
}
e_ADS124S08_State ADS124S08_SET_CLOCK_MODE(e_ADS124S08_ChipID ChipID,e_ADS124S08_CLOCK_MODE Mode)
{
if(ChipID < ADS124S08_MAX_NUM_CHIPS)
{
if(InitStates[ChipID] == ADS124S08_INITIALIZED)
{
uint8_t tempReg = 0;
if(ADS124S08_Read_Register(ChipID, REG_ADS124S08_DATA_RATE, 1, &tempReg) == ADS124S08_OK)
{
tempReg = tempReg & ADS124S08_SEL_CLOCK_CLEAR_MASK;
tempReg = tempReg | Mode << ADS124S08_SEL_CLOCK_BASE_SHIFT;
if(ADS124S08_Write_Register(ChipID, REG_ADS124S08_DATA_RATE, 1, &tempReg) == ADS124S08_OK)
{
return ADS124S08_OK;
}
else
{
return ADS124S08_ERROR;
}
}
else
{
return ADS124S08_ERROR;
}
}
else
{
return ADS124S08_ERROR;
}
}
else
{
return ADS124S08_ERROR;
}
}
e_ADS124S08_State ADS124S08_SET_CHOP_MODE(e_ADS124S08_ChipID ChipID,e_ADS124S08_GLOBAL_CHOP_MODE Mode)
{
if(ChipID < ADS124S08_MAX_NUM_CHIPS)
{
if(InitStates[ChipID] == ADS124S08_INITIALIZED)
{
uint8_t tempReg = 0;
if(ADS124S08_Read_Register(ChipID, REG_ADS124S08_DATA_RATE, 1, &tempReg) == ADS124S08_OK)
{
tempReg = tempReg & ADS124S08_GLOBAL_CHOP_MODE_CLEAR_MASK;
tempReg = tempReg | Mode << ADS124S08_GLOBAL_CHOP_MODE_BASE_SHIFT;
if(ADS124S08_Write_Register(ChipID, REG_ADS124S08_DATA_RATE, 1, &tempReg) == ADS124S08_OK)
{
return ADS124S08_OK;
}
else
{
return ADS124S08_ERROR;
}
}
else
{
return ADS124S08_ERROR;
}
}
else
{
return ADS124S08_ERROR;
}
}
else
{
return ADS124S08_ERROR;
}
}
e_ADS124S08_State ADS124S08_SET_REFERENCE_SETTINGS(e_ADS124S08_ChipID ChipID,e_ADS124S08_INTERNAL_REFERENCE_CONFIGURATION Int_Ref_Conv,e_ADS124S08_REFERENCE_IN_SEL Ref_In_Sel,e_ADS124S08_REFN_BUFFER_MODE Ref_N_Buf_Mode,e_ADS124S08_REFP_BUFFER_MODE Ref_P_Buf_Mode,e_ADS124S08_REFERENCE_MONITOR_MODE Ref_Mon_Mode)
{
if(ChipID < ADS124S08_MAX_NUM_CHIPS)
{
if(InitStates[ChipID] == ADS124S08_INITIALIZED)
{
uint8_t tempReg = 0;
tempReg = tempReg | Int_Ref_Conv << ADS124S08_INTERNAL_REFERENCE_CONF_BASE_SHIFT;
tempReg = tempReg | Ref_In_Sel << ADS124S08_REFERENCE_IN_SEL_BASE_SHIFT;
tempReg = tempReg | Ref_N_Buf_Mode << ADS124S08_REFN_BUFFER_BYPASS_BASE_SHIFT;
tempReg = tempReg | Ref_P_Buf_Mode << ADS124S08_REFP_BUFFER_BYPASS_BASE_SHIFT;
tempReg = tempReg | Ref_Mon_Mode << ADS124S08_REFERENCE_MON_MODE_BASE_SHIFT;
if(ADS124S08_Write_Register(ChipID, REG_ADS124S08_REFERENCE_CONTROL, 1, &tempReg) == ADS124S08_OK)
{
return ADS124S08_OK;
}
else
{
return ADS124S08_ERROR;
}
}
else
{
return ADS124S08_ERROR;
}
}
else
{
return ADS124S08_ERROR;
}
}
e_ADS124S08_State ADS124S08_SET_EXCITATION_CURRENT(e_ADS124S08_ChipID ChipID, e_ADS124S08_EXCITATION_CURRENT Current)
{
if(ChipID < ADS124S08_MAX_NUM_CHIPS)
{
if(InitStates[ChipID] == ADS124S08_INITIALIZED)
{
uint8_t tempReg = 0;
tempReg = tempReg | Current << ADS124S08_SET_EXCITATION_CURRENT_BASE_SHIFT;
if(ADS124S08_Write_Register(ChipID, REG_ADS124S08_EXCITATION_CURRENT_1, 1, &tempReg) == ADS124S08_OK)
{
return ADS124S08_OK;
}
else
{
return ADS124S08_ERROR;
}
}
else
{
return ADS124S08_ERROR;
}
}
else
{
return ADS124S08_ERROR;
}
}
e_ADS124S08_State ADS124S08_SET_IDAC_OUTPUT(e_ADS124S08_ChipID ChipID,e_ADS124S08_IDAC_CHANNEL Channel, e_ADS124S08_IDAC_OUTPUT Output)
{
if(ChipID <ADS124S08_MAX_NUM_CHIPS)
{
if(InitStates[ChipID] == ADS124S08_INITIALIZED)
{
uint8_t tempReg = 0;
if(ADS124S08_Read_Register(ChipID, REG_ADS124S08_EXCITATION_CURRENT_2, 1, &tempReg) == ADS124S08_OK)
{
switch(Channel)
{
case ADS124S08_IDAC_CHANNEL_1:
{
tempReg = tempReg & ADS124S08_IDAC_1_OUTPUT_CLEAR_MASK;
tempReg = tempReg | Output << ADS124S08_IDAC_1_OUTPUT_BASE_SHIFT;
break;
}
case ADS124S08_IDAC_CHANNEL_2:
{
tempReg = tempReg & ADS124S08_IDAC_2_OUTPUT_CLEAR_MASK;
tempReg = tempReg | Output << ADS124S08_IDAC_2_OUTPUT_BASE_SHIFT;
break;
}
default:
{
return ADS124S08_ERROR;
}
}
if(ADS124S08_Write_Register(ChipID, REG_ADS124S08_EXCITATION_CURRENT_2, 1, &tempReg) == ADS124S08_OK)
{
return ADS124S08_OK;
}
else
{
return ADS124S08_ERROR;
}
}
else
{
return ADS124S08_ERROR;
}
}
else
{
return ADS124S08_ERROR;
}
}
else
{
return ADS124S08_ERROR;
}
}
e_ADS124S08_State ADS124S08_SYSTEM_CONTROL(e_ADS124S08_ChipID ChipID,e_ADS124S08_SEND_STAT SendStat,e_ADS124S08_SEND_CRC SendCRC, e_ADS124S08_ENABLE_SPI_TIMEOUT SpiTimeout,e_ADS124S08_CAL_SAMPLES CalSamples)
{
if(ChipID < ADS124S08_MAX_NUM_CHIPS)
{
uint8_t tempReg = 0;
if(ADS124S08_Read_Register(ChipID, REG_ADS124S08_SYSTEM_CONTROL, 1, &tempReg) == ADS124S08_OK)
{
if(SendStat == ADS124S08_SEND_STAT_ENABLED)
{
SendStatEnabled[ChipID] = ADS124S08_SEND_STAT_ENABLED;
tempReg = tempReg & ADS124S08_ENABLE_SEND_STAT_CLEAR_MASK;
tempReg = tempReg | ADS124S08_SEND_STAT_ENABLED << ADS124S08_ENABLE_SEND_STAT_BASE_SHIFT;
}
else if(SendStat == ADS124S08_SEND_STAT_DISABLED)
{
SendStatEnabled[ChipID] = ADS124S08_SEND_STAT_DISABLED;
tempReg = tempReg & ADS124S08_ENABLE_SEND_STAT_CLEAR_MASK;
tempReg = tempReg | ADS124S08_SEND_STAT_DISABLED << ADS124S08_ENABLE_SEND_STAT_BASE_SHIFT;
}
else
{
return ADS124S08_ERROR;
}
if(SendCRC == ADS124S08_SEND_CRC_ENABLED)
{
SendCRCEnabled[ChipID] = ADS124S08_SEND_CRC_ENABLED;
tempReg = tempReg & ADS124S08_ENABLE_CRC_CLEAR_MASK;
tempReg = tempReg | ADS124S08_SEND_CRC_ENABLED << ADS124S08_ENABLE_CRC_BASE_SHIFT;
}
else if(SendCRC == ADS124S08_SEND_CRC_DISABLED)
{
SendCRCEnabled[ChipID] = ADS124S08_SEND_CRC_DISABLED;
tempReg = tempReg & ADS124S08_ENABLE_CRC_CLEAR_MASK;
tempReg = tempReg | ADS124S08_SEND_CRC_DISABLED << ADS124S08_ENABLE_CRC_BASE_SHIFT;
}
else
{
return ADS124S08_ERROR;
}
if(SpiTimeout == ADS124S08_SPI_TIMEOUT_ENABLED)
{
tempReg = tempReg & ADS124S08_SPI_TIMEOUT_ENABLE_CLEAR_MASK;
tempReg = tempReg | ADS124S08_SPI_TIMEOUT_ENABLED << ADS124S08_SPI_TIMEOUT_ENABLE_BASE_SHIFT;
}
else if(SpiTimeout == ADS124S08_SPI_TIMEOUT_DISABLED)
{
tempReg = tempReg & ADS124S08_SPI_TIMEOUT_ENABLE_CLEAR_MASK;
tempReg = tempReg | ADS124S08_SPI_TIMEOUT_DISABLED << ADS124S08_SPI_TIMEOUT_ENABLE_BASE_SHIFT;
}
else
{
return ADS124S08_ERROR;
}
if(ADS124S08_Write_Register(ChipID, REG_ADS124S08_SYSTEM_CONTROL, 1, &tempReg) == ADS124S08_OK)
{
return ADS124S08_OK;
}
else
{
return ADS124S08_ERROR;
}
}
else
{
return ADS124S08_ERROR;
}
}
else
{
return ADS124S08_ERROR;
}
}
e_ADS124S08_State ADS124S08_INIT(e_ADS124S08_ChipID ChipID)
{
if(ChipID < ADS124S08_MAX_NUM_CHIPS)
{
if(ADS124S08_RESET(ChipID) != ADS124S08_OK)
{
return ADS124S08_ERROR;
}
if(ADS124S08_SET_DATA_RATE(ChipID, ADS124S08_DATA_RATE_2_5SPS) != ADS124S08_OK)
{
return ADS124S08_ERROR;
}
if(ADS124S08_SET_FILTER_MODE(ChipID, ADS124S08_FILTER_MODE_SINC3) != ADS124S08_OK)
{
return ADS124S08_ERROR;
}
if(ADS124S08_SET_CONV_MODE(ChipID, ADS124S08_CONV_MODE_CONTINOUS) != ADS124S08_OK)
{
return ADS124S08_ERROR;
}
if(ADS124S08_SET_CLOCK_MODE(ChipID, ADS124S08_CLOCK_MODE_INTERNAL) != ADS124S08_OK)
{
return ADS124S08_ERROR;
}
if(ADS124S08_SET_CHOP_MODE(ChipID, ADS124S08_GLOBAL_CHOP_MODE_DISABLED) != ADS124S08_OK)
{
return ADS124S08_ERROR;
}
if(ADS124S08_SET_REFERENCE_SETTINGS(ChipID, ADS124S08_INTERNAL_REFERENCE_ALWAYS_ON, ADS124S08_REFERENCE_IN_REFP0_REFN0, ADS124S08_REFN_BUFFER_NOT_BYPASSED, ADS124S08_REFP_BUFFER_NOT_BYPASSED, ADS124S08_REFERENCE_MONITOR_DISABLED) != ADS124S08_OK)
{
return ADS124S08_ERROR;
}
if(ADS124S08_SET_PGA_SETTINGS(ChipID, ADS124S08_PROG_CONV_DELAY_14_x_tMOD, ADS124S08_PGA_ENABLED, ADS124S08_GAIN_1) != ADS124S08_OK)
{
return ADS124S08_ERROR;
}
InitStates[ChipID] = ADS124S08_INITIALIZED;
return ADS124S08_OK;
}
else
{
return ADS124S08_ERROR;
}
}
e_ADS124S08_State ADS124S08_START_CONVERSION(e_ADS124S08_ChipID ChipID)
{
if(ChipID < ADS124S08_MAX_NUM_CHIPS)
{
if(InitStates[ChipID] == ADS124S08_INITIALIZED)
{
if(ADS124S08_PORT_SEND_COMMAND(ChipID, ADS124S08_START_CONVERSION_COMMAND) == ADS124S08_OK)
{
return ADS124S08_OK;
}
else
{
return ADS124S08_ERROR;
}
}
else
{
return ADS124S08_ERROR;
}
}
else
{
return ADS124S08_ERROR;
}
}
e_ADS124S08_State ADS124S08_STOP_CONVERSION(e_ADS124S08_ChipID ChipID)
{
if(ChipID < ADS124S08_MAX_NUM_CHIPS)
{
if(InitStates[ChipID] == ADS124S08_INITIALIZED)
{
if(ADS124S08_PORT_SEND_COMMAND(ChipID, ADS124S08_STOP_CONVERSION_COMMAND) == ADS124S08_OK)
{
return ADS124S08_OK;
}
else
{
return ADS124S08_ERROR;
}
}
else
{
return ADS124S08_ERROR;
}
}
else
{
return ADS124S08_ERROR;
}
}
e_ADS124S08_State ADS124S08_RESET(e_ADS124S08_ChipID ChipID)
{
if(ChipID < ADS124S08_MAX_NUM_CHIPS)
{
if(ADS124S08_PORT_SEND_COMMAND(ChipID, ADS124S08_RESET_COMMAND) == ADS124S08_OK)
{
uint8_t tempStatus = 0;
uint8_t returnStatus = 0;
uint8_t Wait_Counter = 0;
do
{
Wait_Counter++;
if(ADS124S08_Read_Register(ChipID, REG_ADS124S08_DEVICE_STATUS, 1, &tempStatus) == ADS124S08_OK)
{
returnStatus = 0;
}
else
{
returnStatus = 1;
break;
}
if(Wait_Counter > 200)
{
returnStatus = 1;
break;
}
}while ((tempStatus & (0x01<< ADS124S08_FLAG_NOT_RDY)) != 0);
if(returnStatus == 0)
{
InitStates[ChipID] = ADS124S08_INITIALIZED;
return ADS124S08_OK;
}
else
{
return ADS124S08_ERROR;
}
}
else
{
return ADS124S08_ERROR;
}
}
else
{
return ADS124S08_ERROR;
}
}
e_ADS124S08_State ADS124S08_PERFORM_SFOCAL(e_ADS124S08_ChipID ChipID)
{
if(ChipID < ADS124S08_MAX_NUM_CHIPS)
{
if(InitStates[ChipID] == ADS124S08_INITIALIZED)
{
if(ADS124S08_PORT_SEND_COMMAND(ChipID, ADS124S08_SFOCAL_COMMAND) == ADS124S08_OK)
{
return ADS124S08_OK;
}
else
{
return ADS124S08_ERROR;
}
}
else
{
return ADS124S08_ERROR;
}
}
else
{
return ADS124S08_ERROR;
}
}
e_ADS124S08_State ADS124S08_PERFORM_SYOCAL(e_ADS124S08_ChipID ChipID)
{
if(ChipID < ADS124S08_MAX_NUM_CHIPS)
{
if(InitStates[ChipID] == ADS124S08_INITIALIZED)
{
if(ADS124S08_PORT_SEND_COMMAND(ChipID, ADS124S08_SYOCAL_COMMAND) == ADS124S08_OK)
{
return ADS124S08_OK;
}
else
{
return ADS124S08_ERROR;
}
}
else
{
return ADS124S08_ERROR;
}
}
else
{
return ADS124S08_ERROR;
}
}

180
Software/Station_SW/Drivers/SmartBeeHive/ADS124S08/Src/ADS124S08_Port.c Normal file
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@@ -0,0 +1,180 @@
/*
* ADS124S08_Port.c
*
* Created on: Nov 10, 2024
* Author: zafst
*/
#include "ADS124S08_Port.h"
/*MCU specific includes */
#include "stm32u3xx_hal.h"
#include "spi.h"
/*Function Prototypes*/
e_ADS124S08_State ADS124S08_PORT_Write_ChipSelect(e_ADS124S08_ChipID ChipID, e_ADS124S08_CS_State State);
/* Portable Functions*/
e_ADS124S08_State ADS124S08_PORT_Read_Register(e_ADS124S08_ChipID ChipID, uint8_t* CommandData,uint8_t NumRegs,uint8_t* Data)
{
if(ADS124S08_PORT_Write_ChipSelect(ChipID, CS_SELECTED) != ADS124S08_OK)
{
return ADS124S08_ERROR;
}
if(HAL_SPI_Transmit(&hspi2, CommandData, 2, HAL_MAX_DELAY) != HAL_OK)
{
return ADS124S08_ERROR;
}
if(HAL_SPI_Receive(&hspi2, Data, NumRegs, HAL_MAX_DELAY) != HAL_OK)
{
return ADS124S08_ERROR;
}
if(ADS124S08_PORT_Write_ChipSelect(ChipID, CS_NOT_SELECTED) != ADS124S08_OK)
{
return ADS124S08_ERROR;
}
return ADS124S08_OK;
}
e_ADS124S08_State ADS124S08_PORT_Write_Register(e_ADS124S08_ChipID ChipID, uint8_t *CommandData, uint8_t NumRegs,uint8_t* Data)
{
if(ADS124S08_PORT_Write_ChipSelect(ChipID, CS_SELECTED) != ADS124S08_OK)
{
return ADS124S08_ERROR;
}
if(HAL_SPI_Transmit(&hspi2, CommandData, 2, HAL_MAX_DELAY) != HAL_OK)
{
return ADS124S08_ERROR;
}
if(HAL_SPI_Transmit(&hspi2, Data, NumRegs, HAL_MAX_DELAY) != HAL_OK)
{
return ADS124S08_ERROR;
}
if(ADS124S08_PORT_Write_ChipSelect(ChipID, CS_NOT_SELECTED) != ADS124S08_OK)
{
return ADS124S08_ERROR;
}
return ADS124S08_OK;
}
e_ADS124S08_State ADS124S08_PORT_Read_Data(e_ADS124S08_ChipID ChipID, uint8_t Command, uint8_t* Data, uint8_t size)
{
if(ADS124S08_PORT_Write_ChipSelect(ChipID, CS_SELECTED) != ADS124S08_OK)
{
return ADS124S08_ERROR;
}
if(HAL_SPI_Transmit(&hspi2, &Command, 1, HAL_MAX_DELAY) != HAL_OK)
{
return ADS124S08_ERROR;
}
if(HAL_SPI_Receive(&hspi2, Data, size, HAL_MAX_DELAY) != HAL_OK)
{
return ADS124S08_ERROR;
}
if(ADS124S08_PORT_Write_ChipSelect(ChipID, CS_NOT_SELECTED) != ADS124S08_OK)
{
return ADS124S08_ERROR;
}
return ADS124S08_OK;
}
e_ADS124S08_State ADS124S08_PORT_SEND_COMMAND(e_ADS124S08_ChipID ChipID, uint8_t Command)
{
if(ADS124S08_PORT_Write_ChipSelect(ChipID, CS_SELECTED) != ADS124S08_OK)
{
return ADS124S08_ERROR;
}
if(HAL_SPI_Transmit(&hspi2, &Command, 1, HAL_MAX_DELAY) != HAL_OK)
{
return ADS124S08_ERROR;
}
if(ADS124S08_PORT_Write_ChipSelect(ChipID, CS_NOT_SELECTED) != ADS124S08_OK)
{
return ADS124S08_ERROR;
}
return ADS124S08_OK;
}
e_ADS124S08_State ADS124S08_PORT_Write_ChipSelect(e_ADS124S08_ChipID ChipID, e_ADS124S08_CS_State State)
{
switch(ChipID)
{
case ADS124S08_ID0:
{
if(State == CS_NOT_SELECTED)
{
HAL_GPIO_WritePin(ADC_CS_GPIO_Port, ADC_CS_Pin, GPIO_PIN_SET);
}
else if(State == CS_SELECTED)
{
HAL_GPIO_WritePin(ADC_CS_GPIO_Port, ADC_CS_Pin, GPIO_PIN_RESET);
}
else
{
return ADS124S08_ERROR;
}
return ADS124S08_OK;
break;
}
case ADS124S08_ID1:
{
if(State == CS_NOT_SELECTED)
{
HAL_GPIO_WritePin(ADC_TEMP_CS_GPIO_Port, ADC_TEMP_CS_Pin, GPIO_PIN_SET);
}
else if(State == CS_SELECTED)
{
HAL_GPIO_WritePin(ADC_TEMP_CS_GPIO_Port, ADC_TEMP_CS_Pin, GPIO_PIN_RESET);
}
else
{
return ADS124S08_ERROR;
}
return ADS124S08_OK;
break;
}
case ADS124S08_ID2:
{
return ADS124S08_ERROR;
break;
}
case ADS124S08_ID3:
{
return ADS124S08_ERROR;
break;
}
default:
{
return ADS124S08_ERROR;
}
}
}
e_ADS124S08_State ADS124S08_PORT_CHECK_CRC(uint8_t* Data,uint8_t size,uint8_t CRC_DATA)
{
uint8_t CRC_OK = 1;
if(CRC_OK)
{
return ADS124S08_OK;
}
else
{
return ADS124S08_ERROR;
}
}